Semiconductor structure and forming method

Abstract

The invention provides a semiconductor structure and a forming method. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a first compound semiconductor layer, a second compound semiconductor layer, a gate electrode, a conductive portion, a source electrode, and a drain electrode. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the first compound semiconductor layer. The conductive portion is disposed on the second compound semiconductor layer. The source electrode and the drain electrode are respectively arranged on the barrier layer and are respectively arranged on opposite sides of the gate electrode. Wherein the drain electrode is electrically connected with the conductive part.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a forming method thereof, and in particular to a semiconductor structure including a conductive portion connected to a drain electrode and a forming method thereof. Background Art

[0002] Due to its wide bandgap and strong polarization effect, GaN materials are widely used. For example, GaN-based semiconductors are currently widely used in power devices, such as high electron mobility transistors (HEMTs) with heterojunction structures.

[0003] However, high electron mobility transistors (HEMTs) can suffer from issues such as excessive leakage current, insufficient breakdown voltage, degraded dynamic resistance characteristics, the need for a turn-on voltage to achieve conduction, and complex processes and structures. Consequently, while existing semiconductor structures and their formation methods have gradually met their intended uses, they still do not fully meet all requirements. Consequently, several challenges remain to be overcome regarding semiconductor structures and their formation methods. Summary of the Invention

[0004] The present disclosure provides adjacently arranged Schottky contacts and ohmic contacts to form a hybrid drain structure. The conductive portion forms a Schottky contact with the second compound semiconductor layer, and the drain electrode forms an ohmic contact with the third compound semiconductor layer. Accordingly, the Schottky contact can be compared to a reverse diode to reduce leakage current and / or increase breakdown voltage. The ohmic contact can be compared to a resistor to turn on the semiconductor structure without applying a turn-on voltage. In addition, the ohmic contact can provide more holes to neutralize the trapped charge captured by defects in each layer, thereby making the electric field distribution uniform, increasing the turn-on current and / or improving the dynamic resistance characteristics. Improving the dynamic resistance characteristics may include maintaining the dynamic on-resistance to avoid the problem of the on-resistance increasing with increasing voltage stress. Furthermore, by arranging the island-shaped second compound semiconductor layer and the third compound semiconductor layer on the barrier layer, the regrowth process can be omitted, thereby reducing the process and structural complexity.

[0005] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a first compound semiconductor layer, a second compound semiconductor layer, a gate electrode, a conductive portion, and source and drain electrodes. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the first compound semiconductor layer. The conductive portion is disposed on the second compound semiconductor layer. The source electrode and the drain electrode are respectively disposed on the barrier layer and on opposite sides of the gate electrode. The drain electrode is electrically connected to the conductive portion.

[0006] In some embodiments, a method for forming a semiconductor structure is provided. The method includes providing a substrate, providing a channel layer on the substrate, forming a barrier layer on the channel layer, forming a first compound semiconductor layer on the barrier layer, forming a second compound semiconductor layer on the barrier layer, forming a gate electrode on the first compound semiconductor layer, and forming a conductive portion on the second compound semiconductor layer. A source electrode and a drain electrode are formed on the barrier layer, with the source electrode and the drain electrode being disposed on opposite sides of the gate electrode, respectively. The drain electrode is electrically connected to the conductive portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily enlarged or reduced for clarity.

[0008] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 The figures are cross-sectional schematic diagrams of different stages of a method for forming a semiconductor structure according to an embodiment of the present disclosure.

[0009] Figure 5 FIG. 4 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure.

[0010] Figure 6 FIG. 4 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.

[0011] Figure 7 FIG. 4 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure.

[0012] Figure 8 FIG. 4 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure.

[0013] Explanation of symbols

[0014] 1,2,3: Semiconductor structure

[0015] 100:Substrate

[0016] 200: buffer layer

[0017] 300: Channel layer

[0018] 310: Two-dimensional electron gas

[0019] 400: barrier layer

[0020] 510: first compound semiconductor layer

[0021] 520: Second compound semiconductor layer

[0022] 520a, 520b, 520c: Part 1

[0023] 530: third compound semiconductor layer

[0024] 530a, 530b, 530c: Part 2

[0025] 530S: Side surface

[0026] 530T: Top surface

[0027] 600: Gate electrode

[0028] 610: conductive part

[0029] 620: Source electrode

[0030] 640: drain electrode

[0031] 640E: Edge

[0032] 700: first dielectric layer

[0033] 800: second dielectric layer

[0034] 810,820,840: Connectors

[0035] 822: Source field plate

[0036] 842: Drain field plate

[0037] D1: First direction

[0038] D2: Second direction

[0039] D3: Third direction

[0040] G: Gap

[0041] I-I',II-II': Section DETAILED DESCRIPTION

[0042] The following is a detailed description of the semiconductor structure of each embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only for a simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and are not limitations on the present disclosure. In addition, similar and / or corresponding element symbols may be used in different embodiments to indicate similar and / or corresponding elements in order to clearly describe the present disclosure. However, the use of these similar and / or corresponding element symbols is only for a simple and clear description of some embodiments of the present disclosure and does not represent any correlation between the different embodiments and / or structures discussed.

[0043] It should be understood that relative terms, such as "lower," "bottom," "upper," or "top," may be used in various embodiments to describe the relative relationship of one element to another element in the drawings. It should be understood that if the device in the drawings is flipped upside down, the element described as being on the "lower" side would become the element on the "upper" side. The embodiments of the present disclosure should be understood in conjunction with the drawings, which are also considered part of the disclosure.

[0044] Furthermore, when a first material layer is described as being on or over a second material layer, this may include situations where the first material layer is in direct contact with the second material layer, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where one or more other material layers may be interposed between the first material layer and the second material layer. However, if the first material layer is directly on the second material layer, this means that the first material layer and the second material layer are in direct contact.

[0045] Furthermore, it should be understood that the use of ordinal numbers such as "first," "second," and the like in the specification and claims to modify an element is not intended to imply any prior ordinal number for the element(s), nor does it indicate the order of one element relative to another, or the order of manufacturing methods. These ordinal numbers are used solely to clearly distinguish a named element from another element with the same name. The claims and the specification may not use the same terms; for example, the first element in the specification may be the second element in the claims.

[0046] In some embodiments of the present disclosure, terms related to joining and connecting, such as "connect," "interconnect," and "bond," unless otherwise specified, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with another structure disposed between the two structures. Furthermore, such terms related to joining and bonding may include situations where both structures are movable or both structures are fixed. Furthermore, the terms "electrically connected" or "electrically coupled" include any direct and indirect electrical connection means.

[0047] In the text, the terms "approximate", "about", and "substantially" generally mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, in the absence of specific instructions for "about", "approximately", or "substantially", the meanings of "about", "approximately", or "substantially" may still be implied. The term "range is between a first value and a second value" or "first value to second value" means that the range includes the first value, the second value, and other values ​​therebetween. Furthermore, there may be a certain error between any two values ​​or directions used for comparison. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value.

[0048] Throughout the specification and claims of this disclosure, certain words will be used to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, words such as "comprise", "contain", and "have" are open-ended words and should therefore be interpreted as meaning "including but not limited to..." Therefore, when the terms "comprise", "contain" and / or "have" are used in the description of this disclosure, they specify the presence of corresponding parts, areas, steps, operations and / or elements, but do not exclude the presence of one or more corresponding parts, areas, steps, operations and / or elements.

[0049] It should be understood that the following embodiments may be implemented by replacing, reorganizing, or combining components from various different embodiments without departing from the spirit of the present disclosure. Components from various embodiments may be combined and used in any manner as long as they do not violate the spirit of the invention or conflict with it.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this disclosure.

[0051] In the present disclosure, the directions are not limited to the three axes of the rectangular coordinate system such as the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, hereinafter, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the top view schematic diagram described herein is a schematic diagram for observing the XY plane (the plane formed by the first direction D1 and the second direction D2), and the cross-sectional schematic diagram described herein is a schematic diagram for observing the XZ plane (the plane formed by the first direction D1 and the third direction D3).

[0052] In the following, the current-voltage characteristic curve (I-V curve) of the "Schottky contact" presents a nonlinear relationship and is unidirectional with rectification characteristics; while the current-voltage characteristic curve of the "Ohmic contact" presents a linear relationship and is bidirectional with no rectification characteristics.

[0053] Reference Figure 1 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor structure 1 according to an embodiment of the present disclosure. Figure 1 As shown, in some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. A SOI substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, polysilicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like.

[0054] In some embodiments, substrate 100 may be an undoped or doped substrate, such as a substrate doped with p-type or n-type dopants. In some embodiments, substrate 100 may include a multi-layered substrate or a gradient substrate. In some embodiments, substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, substrate 100 may be a silicon substrate.

[0055] like Figure 1 As shown, in some embodiments, a buffer layer 200 may be formed on the substrate 100 to improve the compatibility between the substrate 100 and other components disposed on the substrate 100, such as reducing differences in thermal expansion coefficients and / or reducing differences in lattice constants. In some embodiments, the buffer layer 200 may include a III-V compound semiconductor material, such as a III-V nitride. For example, the buffer layer 200 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the buffer layer 200 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), the like, or a combination thereof, but the present disclosure is not limited thereto.

[0056] In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 200 to reduce the lattice difference between the substrate 100 and other layers disposed thereon, thereby improving epitaxial growth quality and reliability. In some embodiments, the nucleation layer may comprise aluminum nitride (AlN), aluminum gallium nitride (AlGaN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the nucleation layer may be formed by a deposition process. In other embodiments, the buffer layer 200 may be omitted.

[0057] like Figure 1As shown, in some embodiments, a channel layer 300 may be formed on the substrate 100. Specifically, the channel layer 300 may be formed on the buffer layer 200. In some embodiments, the channel layer 300 may include a III-V compound semiconductor material, such as a III-V nitride, but the present disclosure is not limited thereto. For example, the channel layer 300 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the channel layer 300 may be gallium nitride. In some embodiments, the channel layer 300 may be formed by a deposition process.

[0058] like Figure 1 As shown, in some embodiments, a barrier layer 400 may be formed on the channel layer 300. In some embodiments, the barrier layer 400 may include a III-V compound semiconductor material, such as a III-V nitride, but the present disclosure is not limited thereto. For example, the barrier layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium aluminum gallium nitride (InAlGaN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the barrier layer 400 may be aluminum gallium nitride. In some embodiments, the barrier layer 400 may be formed by a deposition process. Due to the presence of a heterogeneous interface between the channel layer 300 and the barrier layer 400, and the difference in lattice constants between the channel layer 300 and the barrier layer 400, a two-dimensional electron gas (2DEG) 310 may be formed near the top surface of the channel layer 300, serving as a current path.

[0059] Reference Figure 2 , which is a cross-sectional schematic diagram of different stages of a method for forming a semiconductor structure 1 according to an embodiment of the present disclosure. Figure 2 As shown, in some embodiments, a first compound semiconductor layer 510 may be formed on the barrier layer 400. In some embodiments, the first compound semiconductor layer 510 may be formed by a deposition process. In some embodiments, the first compound semiconductor layer 510 may be a semiconductor material doped with a p-type dopant.

[0060] In some embodiments, a second compound semiconductor layer 520 may be formed on the barrier layer 400. In some embodiments, the material and formation method of the second compound semiconductor layer 520 may be the same as or different from the material and formation method of the first compound semiconductor layer 510. In some embodiments, the second compound semiconductor layer 520 may be formed in the same process as the first compound semiconductor layer 510. For example, the first compound semiconductor layer 510 and the second compound semiconductor layer 520 may include p-type doped gallium nitride (p-GaN). Because the first compound semiconductor layer 510 and the second compound semiconductor layer 520 include p-GaN, the formation of the two-dimensional electron gas 310 below the first compound semiconductor layer 510 and the second compound semiconductor layer 520 may be suppressed, resulting in the two-dimensional electron gas 310 being depleted and discontinuous.

[0061] Reference Figure 3 , which is a schematic cross-sectional view of different stages of a method for forming a semiconductor structure 1 according to an embodiment of the present disclosure. In some embodiments, a gate electrode 600 may be formed on the first compound semiconductor layer 510 to provide the semiconductor structure 1 with a normally-off structure. In some embodiments, the gate electrode 600 may comprise a conductive material. In some embodiments, the conductive material may comprise a metal, a metal nitride, a semiconductor material, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the metal may comprise gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like, or a combination thereof. In some embodiments, the metal nitride may comprise titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof. In some embodiments, the semiconductor material may comprise polycrystalline silicon or polycrystalline germanium, the like, or a combination thereof. In some embodiments, the conductive material may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the gate electrode 600 and the first compound semiconductor layer 510 may form a Schottky contact.

[0062] like Figure 3 As shown, in some embodiments, a conductive portion 610 may be formed on the second compound semiconductor layer 520. In some embodiments, the material and formation method of the conductive portion 610 may be the same as or different from the material and formation method of the gate electrode 600. In some embodiments, the conductive portion 610 may be formed in the same process as the gate electrode 600. In some embodiments, the conductive portion 610 and the second compound semiconductor layer 520 may form a Schottky contact.

[0063] like Figure 3 As shown, in some embodiments, a source electrode 620 and a drain electrode 640 may be formed on the barrier layer 400. In some embodiments, the source electrode 620 and the drain electrode 640 may be disposed on opposite sides of the gate electrode 600. In some embodiments, the source electrode 620 and the drain electrode 640 may each be in contact with the barrier layer 400. In some embodiments, the materials and formation methods of the source electrode 620 and the drain electrode 640 may be the same as or different from those of the gate electrode 600. In some embodiments, the source electrode 620 may form an ohmic contact with the barrier layer 400, and the drain electrode 640 may form an ohmic contact with the barrier layer 400.

[0064] like Figure 3 As shown, in some embodiments, in the first direction D1, the second compound semiconductor layer 520 is spaced a distance from the drain electrode 640. In some embodiments, the conductive portion 610 may be closer to the drain electrode 640 than to the gate electrode 600 or the source electrode 620. Accordingly, the conductive portion 610 may make the electric field distribution near the drain electrode 640 more uniform.

[0065] Reference Figure 4 , which is a schematic cross-sectional view of different stages of a method for forming a semiconductor structure 1 according to an embodiment of the present disclosure. In some embodiments, a first dielectric layer 700 may be formed on the barrier layer 400. In some embodiments, the first dielectric layer 700 may be between the source electrode 620 and the gate electrode 600, between the gate electrode 600 and the conductive portion 610, and between the conductive portion 610 and the drain electrode 640. In some embodiments, the first dielectric layer 700 may be formed by a deposition process. In some embodiments, the first dielectric layer 700 may serve as a passivation layer or a planarization layer. In some embodiments, the first dielectric layer 700 may include an oxide such as silicon oxide, a nitride such as silicon nitride, an oxynitride such as silicon oxynitride, the like, or a combination thereof, but the present disclosure is not limited thereto.

[0066] like Figure 4As shown, in some embodiments, a second dielectric layer 800 may be formed on the gate electrode 600, the conductive portion 610, the source electrode 620, the drain electrode 640, and the first dielectric layer 700. In some embodiments, the material and formation method of the second dielectric layer 800 may be the same as or different from those of the first dielectric layer 700. In some embodiments, the second dielectric layer 800 may serve as an interlayer dielectric layer. In some embodiments, connectors 810, 820, and 840 may be formed in the second dielectric layer 800. In some embodiments, the connectors 810, 820, and 840 may penetrate the second dielectric layer 800. In some embodiments, the connectors 810, 820, and 840 may include a conductive material. In some embodiments, the connector 810 may be electrically connected to the conductive portion 610, the connector 820 may be electrically connected to the source electrode 620, and the connector 840 may be electrically connected to the drain electrode 640. In some embodiments, the connectors 810 , 820 , and 840 may be formed by forming openings (not shown) through the second dielectric layer 800 and then depositing a conductive material in the openings.

[0067] like Figure 4 As shown, in some embodiments, a source field plate 822 and a drain field plate 842 can be formed on the second dielectric layer 800 to obtain the semiconductor structure 1. In some embodiments, the source field plate 822 can be electrically connected to the source electrode 620 via a connector 820. In some embodiments, the drain field plate 842 can be electrically connected to the conductive portion 610 and the drain electrode 640 via connectors 810 and 840, respectively, so that the conductive portion 610 and the drain electrode 640 can be substantially electrically connected to each other. In other words, in the present disclosure, the conductive portion 610 and the drain electrode 640 that are substantially electrically connected to each other can form a hybrid drain structure.

[0068] In some embodiments, the source field plate 822 and the drain field plate 842 can be used to adjust the electric field distribution. In some embodiments, the source field plate 822 and the drain field plate 842 can include a conductive material. In some embodiments, the projection of the source electrode 620 onto the substrate 100 can be located within the projection of the source field plate 822 onto the substrate 100. In some embodiments, the projection of the gate electrode 600 onto the substrate 100 can be located within the projection of the source field plate 822 onto the substrate 100. Thus, the source field plate 822 can uniformly distribute the electric field adjacent to the source electrode 620 and the gate electrode 600. In some embodiments, the projection of the drain electrode 640 onto the substrate 100 can be located within the projection of the drain field plate 842 onto the substrate 100. In some embodiments, the projection of the conductive portion 610 onto the substrate 100 can be located within the projection of the drain field plate 842 onto the substrate 100. Thus, the drain field plate 842 can uniformly distribute the electric field adjacent to the drain electrode 640.

[0069] Reference Figure 5, which is a schematic top view of a semiconductor structure 1 according to an embodiment of the present disclosure. For ease of explanation, Figure 5 Some components are omitted. Figure 5 The structure shown in the cross section I-I' is shown in Figure 4 In, and Figure 5 The structure shown in the cross section II-II' is shown in the subsequent Figure 6 In. Reference Figure 5 And match with reference Figure 6 ,in Figure 6 FIG. 1 is a schematic top view of a semiconductor structure 1 according to an embodiment of the present disclosure.

[0070] like Figure 5 and Figure 6 As shown, in some embodiments, a third compound semiconductor layer 530 may be formed on the barrier layer 400. In some embodiments, the material and formation method of the third compound semiconductor layer 530 may be the same as or different from the material and formation method of the first compound semiconductor layer 510. In some embodiments, the third compound semiconductor layer 530 may include p-type doped gallium nitride (p-GaN), and the third compound semiconductor layer 530 may suppress the formation of the two-dimensional electron gas 310 below the third compound semiconductor layer 530, thereby causing the two-dimensional electron gas 310 to be depleted and discontinuous. Because the two-dimensional electron gas 310 is controlled by the second compound semiconductor layer 520 and the third compound semiconductor layer 530, and the second compound semiconductor layer 520 and the third compound semiconductor layer 530 are disposed on the top surface of the barrier layer 400 away from the substrate 100, a regrowth process can be omitted, thereby reducing process and structural complexity.

[0071] like Figure 5 and Figure 6 As shown, in some embodiments, the drain electrode 640 may be disposed on the third compound semiconductor layer 530, and the drain electrode 640 may contact the third compound semiconductor layer 530. In some embodiments, the drain electrode 640 and the third compound semiconductor layer 530 may form an ohmic contact. In some embodiments, the drain electrode 640 may cover the top surface 530T and side surfaces 530S of the third compound semiconductor layer 530. In some embodiments, the drain electrode 640 may expose the top surface 530T of the third compound semiconductor layer 530 and cover the side surfaces 530S of the third compound semiconductor layer 530.

[0072] In some embodiments, the drain electrode 640 may have a protruding portion extending toward the gate electrode 600 in the first direction D1. In some embodiments, the protruding portion of the drain electrode 640 may have a rectangular, triangular, polygonal, semicircular, semi-elliptical, bullet-shaped, teardrop-shaped, or other suitable shapes or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the protruding portion of the drain electrode 640 may include curved edges to disperse the electric field, thereby making the electric field distribution more uniform.

[0073] like Figure 5 As shown, in some embodiments, the ratio of the Schottky contact to the ohmic contact can be adjusted by adjusting the ratio of the contact area between the conductive portion 610 and the second compound semiconductor layer 520 to the contact area between the drain electrode 640 and the third compound semiconductor layer 530. In some embodiments, when the area of ​​the second compound semiconductor layer 520 and the area of ​​the third compound semiconductor layer 530 are both constant, the ratio of the Schottky contact to the ohmic contact can be adjusted by adjusting the contact area between the drain electrode 640 and the third compound semiconductor layer 530. This can achieve a more uniform electric field distribution and / or adjust the ratio of the Schottky contact to the ohmic contact based on power requirements.

[0074] like Figure 5 As shown, in some embodiments, the second compound semiconductor layer 520 and the third compound semiconductor layer 530 may expose the top surface of the barrier layer 400 between the gate electrode 600 and the drain electrode 640. In some embodiments, the second compound semiconductor layer 520 and the third compound semiconductor layer 530 may be arranged along the extension direction of the gate electrode 600, i.e., the second direction D2. In some embodiments, the second compound semiconductor layer 520 and the third compound semiconductor layer 530 are separated by a distance in the second direction D2. Accordingly, when no voltage is applied (e.g., when the turn-on voltage is approximately 0), a portion of the two-dimensional electron gas 310 remains continuous, thereby preserving a current path. For example, when the turn-on voltage is approximately 0, the two-dimensional electron gas 310 located in the gap G between the second compound semiconductor layer 520 and the third compound semiconductor layer 530 remains continuous, so that a current path still exists between the source electrode 620 and the drain electrode 640. In some embodiments, the second compound semiconductor layer 520 and the third compound semiconductor layer 530 may not be disposed on a virtual connection line between the source electrode 620 and the drain electrode 640 to maintain a current path.

[0075] like Figure 5 As shown, in some embodiments, the second compound semiconductor layer 520 may include a plurality of first portions, and the third compound semiconductor layer 530 may include a plurality of second portions. Figure 5The plurality of first portions may include three first portions 520a, 520b, and 520c, and the plurality of second portions may include three second portions 530a, 530b, and 530c, but the disclosure is not limited thereto. For example, the number of the plurality of first portions and the number of the plurality of first portions may be 2, 3, 4, 5, 10, 20, 50, or any number between or including any range of numbers, but the disclosure is not limited thereto.

[0076] In some embodiments, the plurality of first portions 520a, 520b, 520c and the plurality of second portions 530a, 530b, 530c may be alternately arranged along the extension direction (i.e., the second direction D2) of the gate electrode 600. In some embodiments, in a top view, the Schottky contacts and the ohmic contacts may be alternately arranged along the extension direction (i.e., the second direction D2) of the gate electrode 600.

[0077] In some embodiments, each of the plurality of first portions 520a, 520b, 520c and each of the plurality of second portions 530a, 530b, 530c are isolated from each other. In some embodiments, at least one second portion may be disposed between adjacent first portions. In other embodiments, at least one first portion may be disposed between adjacent second portions. In some embodiments, the first portion and the second portion may each have an island shape. In some embodiments, the drain electrode 640 may have a plurality of protruding portions, and the plurality of protruding portions of the drain electrode 640 are respectively disposed on the plurality of second portions 530a, 530b, 530c, so that the plurality of protruding portions of the drain electrode 640 contact the plurality of second portions 530a, 530b, 530c.

[0078] Hereinafter, the same or similar element numbers and descriptions may be omitted.

[0079] Reference Figure 7 , which is a schematic top view of a semiconductor structure 2 according to an embodiment of the present disclosure. In some embodiments, the third compound semiconductor layer 530 may be closer to the gate electrode 600 than the second compound semiconductor layer 520 .

[0080] Reference Figure 8, which is a schematic top view of a semiconductor structure 3 according to an embodiment of the present disclosure. In some embodiments, the plurality of first portions 520a, 520b, and 520c of the second compound semiconductor layer 520 may be disposed adjacent to a portion of the edge 640E of the drain electrode 640, and the plurality of second portions 530a, 530b, and 530c of the third compound semiconductor layer 530 may be disposed adjacent to the remaining portion of the edge 640E of the drain electrode 640. In other words, along the extension direction of the gate electrode 600 (i.e., the second direction D2), the plurality of first portions 520a, 520b, and 520c and the plurality of second portions 530a, 530b, and 530c may be sequentially arranged. In some embodiments, in a top view, a Schottky contact and an ohmic contact may be sequentially disposed along the extension direction of the gate electrode 600 (i.e., the second direction D2).

[0081] In some embodiments, the semiconductor structures 1-3 disclosed herein can be used in any combination and can serve as a high electron mobility transistor. In other embodiments, any of the semiconductor structures 1-3 can be further processed to form a high electron mobility transistor.

[0082] Accordingly, the present disclosure forms a Schottky contact by disposing a conductive portion on the second compound semiconductor layer, and forms an ohmic contact by disposing a drain electrode on the third compound semiconductor layer. Thus, the conductive portion is electrically connected to the drain electrode to form a hybrid drain structure. Therefore, in the present disclosure, the conductive portion that is a Schottky contact can reduce leakage current and / or increase breakdown voltage. In the present disclosure, the drain electrode that is an ohmic contact can provide holes to improve dynamic resistance characteristics and / or can be turned on when the on-voltage is approximately 0. Furthermore, in the present disclosure, the hybrid drain structure can reduce process and structural complexity.

[0083] The scope of protection of this disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods, and steps described in the specific embodiments within this specification. Any skilled artisan will understand from this disclosure that any processes, machines, manufactures, compositions of matter, devices, methods, and steps currently or in the future that can perform substantially the same functions or achieve substantially the same results as those described herein may be used in accordance with this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufactures, compositions of matter, devices, methods, and steps. It is not necessary for any embodiment or claim of this disclosure to achieve all of the objects, advantages, and / or features described herein.

[0084] The above summarizes several embodiments so that those skilled in the art can better understand the concepts of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a first compound semiconductor layer disposed on the barrier layer; a second compound semiconductor layer disposed on the barrier layer; a gate electrode disposed on the first compound semiconductor layer; a conductive portion disposed on the second compound semiconductor layer; and A source electrode and a drain electrode are respectively disposed on the barrier layer and on opposite sides of the gate electrode. Wherein, the drain electrode is electrically connected to the conductive part.

2. The semiconductor structure according to claim 1, wherein Also includes: a third compound semiconductor layer disposed on the barrier layer; Wherein, the drain electrode is arranged on the third compound semiconductor layer.

3. The semiconductor structure according to claim 2, wherein: The conductive portion is in Schottky contact with the second compound semiconductor layer, and the drain electrode is in ohmic contact with the third compound semiconductor layer.

4. The semiconductor structure according to claim 2, wherein: The second compound semiconductor layer is spaced apart from the drain electrode by a distance.

5. The semiconductor structure according to claim 2, wherein: The second compound semiconductor layer and the third compound semiconductor layer are arranged along an extending direction of the gate electrode, and the second compound semiconductor layer is spaced apart from the third compound semiconductor layer by a distance.

6. The semiconductor structure according to claim 5, wherein: The second compound semiconductor layer includes a plurality of first portions, the third compound semiconductor layer includes a plurality of second portions, and the plurality of first portions and the plurality of second portions are alternately arranged along the extending direction of the gate electrode.

7. The semiconductor structure according to claim 5, wherein: The second compound semiconductor layer includes a plurality of first portions, the third compound semiconductor layer includes a plurality of second portions, the plurality of first portions are disposed adjacent to a portion of an edge of the drain electrode, and the plurality of second portions are disposed adjacent to a remaining portion of the edge of the drain electrode.

8. The semiconductor structure according to claim 2, wherein: Compared with the gate electrode, the conductive portion is closer to the drain electrode.

9. The semiconductor structure according to claim 2, wherein: The second compound semiconductor layer and the third compound semiconductor layer expose a top surface of the barrier layer between the gate electrode and the drain electrode.

10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; forming a first compound semiconductor layer on the barrier layer; forming a second compound semiconductor layer on the barrier layer; forming a gate electrode on the first compound semiconductor layer; forming a conductive portion on the second compound semiconductor layer; and forming a source electrode and a drain electrode on the barrier layer, wherein the source electrode and the drain electrode are respectively disposed on opposite sides of the gate electrode; Wherein, the drain electrode is electrically connected to the conductive part.

Images