In-stack nanobelt thickness adjustment for improved gate-all-around transistor performance

Abstract

Devices, transistor structures, systems, and techniques are described herein that relate to gate-all-around field effect transistors having a stack of nanobelts (i.e., semiconductor structures) having a thickness adjusted to vary across the stack. The nanobelt source-to-drain length is from a source interface with the source structure to a drain interface with the drain structure, respectively, and the thickness is orthogonal to the source-to-drain length aligned with the vertical stack of nanobelts. The nanobelts have different thicknesses across the stack of nanobelts of the field effect transistor.

Description

Background Art

[0001] Higher performance, lower cost, increased miniaturization, and higher density integrated circuits (ICs) are ongoing goals of the electronics industry. To maintain the pace of increasing transistor performance, for example, multi-gate transistors, such as gate-all-around (GAA) or nanoribbon transistors, are being deployed. In such devices, the gate structure surrounds the channel region on all sides of each nanoribbon or strip of semiconductor material to improve drive current, device control, and other advantages. Currently, multi-gate transistors have difficulties, including non-uniformity in the nanoribbons from which the transistor devices are manufactured. It is precisely because of these and other factors that the current improvements are needed. As the desire to deploy multi-gate transistor structures becomes more prevalent, such improvements may become critical. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The material described herein is illustrated in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Furthermore, where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or similar elements. In the drawings:

[0003] Figure 1A provides an isometric view of selected components of an example transistor structure having an adjusted semiconductor structure thickness;

[0004] Figure 1B Provides a cutout along the source to drain Figure 1A A cross-sectional side view of a transistor structure;

[0005] Figure 2 Shown with Figure 1A and Figure 1B a cross-sectional side view of a transistor structure similar to a transistor structure of wherein a lowermost semiconductor structure has an increased thickness relative to other semiconductor structures in a stack of semiconductor structures;

[0006] Figure 3 shows a cross-sectional side view of a transistor structure in which a second-to-lower-most semiconductor structure has an increased thickness relative to other semiconductor structures in a stack of semiconductor structures;

[0007] Figure 4 shows a cross-sectional side view of a transistor structure in which two topmost semiconductor structures have increased thickness relative to other semiconductor structures of a stack of semiconductor structures;

[0008] Figure 5shows a cross-sectional side view of a transistor structure wherein a semiconductor structure having a longer source-to-drain length has an increased thickness relative to other semiconductor structures in a stack of transistor structures;

[0009] Figure 6 showing a cross-sectional side view of a transistor structure wherein a semiconductor structure having a shorter source-to-drain length has an increased thickness relative to other semiconductor structures of a stack of transistor structures;

[0010] Figure 7 shows a cross-sectional side view of another transistor structure in which a lowermost semiconductor structure has an increased thickness relative to other semiconductor structures of a stack of semiconductor structures;

[0011] Figure 8 shows a cross-sectional side view of a transistor structure in which two lowermost semiconductor structures have increased thickness relative to other semiconductor structures of a stack of semiconductor structures;

[0012] Figure 9 is a flow chart illustrating an exemplary method for forming a transistor structure having a stack of semiconductor structures having an adjusted thickness;

[0013] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15 When executing Figure 9 a cross-sectional side view of an example transistor structure during a particular fabrication operation of the method;

[0014] Figure 16 showing a cross-sectional side view of a transistor structure having a stack of semiconductor structures having adjusted thicknesses incorporated into an integrated circuit die;

[0015] Figure 17 An exemplary system employing an integrated circuit assembly including an integrated circuit die having a transistor structure including a stack of semiconductor structures having a modified thickness is shown; and

[0016] Figure 18 is a functional block diagram of an electronic computing device, all in accordance with at least some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] One or more embodiments or implementations will now be described with reference to the accompanying drawings. Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be employed without departing from the spirit and scope of the specification. It will be apparent to those skilled in the relevant art that the techniques and / or arrangements described herein may also be employed in various other systems and applications in addition to the systems and applications described herein.

[0018] In the following detailed description, reference is made to the accompanying drawings forming a part thereof, wherein similar reference numerals may always represent similar parts to indicate corresponding or similar elements. It should be understood that, for the sake of simplicity and / or clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, for the sake of clarity, the sizes of some elements may be exaggerated relative to other elements. In addition, it should be understood that other embodiments can be utilized, and structural and / or logical changes can be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., upward, downward, top, bottom, above, below, etc.) can be used to promote discussion of the drawings and embodiments, and are not intended to limit the application of the claimed subject matter. Therefore, the following detailed description should not be understood as limiting the meaning and scope of the claimed subject matter as defined by the appended claims and their equivalents.

[0019] In the following description, many details are set forth. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some cases, well-known methods and apparatus are shown in block diagram form rather than in detail to avoid obscuring the present invention. References throughout this specification to "an embodiment" or "one embodiment" mean that the specific features, structures, functions, or characteristics described in conjunction with that embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in an embodiment" or "in one embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment of the present invention. In addition, in one or more embodiments, specific features, structures, functions, or characteristics may be combined in any suitable manner. For example, the first embodiment may be combined with the second embodiment as long as the specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0020] As used in the description of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or," as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items. As used herein, the term "predominantly" indicates not less than 50% of a particular material or component, while the term "substantially pure" indicates not less than 99% of a particular material or component, and the term "pure" indicates not less than 99.9% of a particular material or component. Unless otherwise indicated, such material percentages are based on atomic percentages. As used herein, the terms concentration and material percentage are used interchangeably and also indicate atomic percentages, unless otherwise indicated.

[0021] The terms "coupled" and "connected" and their derivatives may be used herein to describe the structural relationship between components. It should be understood that these terms are not intended to be synonymous with each other. On the contrary, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediate elements between them), and / or that two or more elements cooperate or interact with each other (e.g., such as a causal relationship, an electrical relationship, a functional relationship, etc.).

[0022] As used herein, the terms "above," "below," "between," "on," and the like refer to the relative position of one material layer or component relative to other layers or components. For example, a layer positioned above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Additionally, a layer positioned between two layers may be in direct contact with both layers or may have one or more intervening layers. Conversely, a first layer "above" a second layer may be in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature positioned between two features may be in direct contact with the adjacent feature or may have one or more intervening features. The term "directly adjacent" indicates that such features are in direct contact. Furthermore, the terms "substantially," "close," "approximately," "near," and "approximately" generally refer to within + / - 10% of a target value. As used herein, the term layer may include a single material or multiple materials. As used throughout this specification and claims, a list of items linked by the terms "at least one of" or "one or more of" may refer to any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. The terms "lateral," "laterally adjacent," and similar terms indicate that two or more components are aligned along a plane orthogonal to the vertical direction of the overall structure. As used herein, the terms "monolithic," "monolithically integrated," and similar terms indicate that the components of a monolithic, unitary structure form an inseparable whole that cannot be reasonably separated.

[0023] Described herein are devices, transistor structures, integrated circuit dies, apparatus, systems, and techniques related to gate-all-around field-effect transistors (GAA-FETs) containing stacks of semiconductor structures with tailored thicknesses.

[0024] As discussed, multi-gate transistors such as gate-all-around (GAA) or nanoribbon transistors are deployed in advanced integrated circuit devices. As used herein, the terms nanowire, nanoribbon, stacked semiconductor structure and similar terms are used essentially interchangeably to indicate a semiconductor material extending from a source to a drain, such that the semiconductor material is one of two or more such materials that are separated and vertically aligned. The multiple semiconductor materials are each coupled to the same source and drain and separated by a gate structure that may include a gate dielectric and a gate electrode. Thus, a field effect transistor or device includes a source, a drain, and a stack of semiconductor structures extending between the source and the drain. The stack of semiconductor structures (e.g., two to approximately eight semiconductor structures) is controlled by the same gate electrode and works in conjunction with the channel of the device. As used herein, the term channel region of a semiconductor structure indicates a region of a material layer adjacent to the gate dielectric and the gate electrode that will be controlled by the gate electrode to switch the transistor structure during operation. It is noteworthy that the region of the material layer does not need to be characterized as a channel region, a channel material, etc. during operation. The term semiconductor structure is used broadly to include nanowires, nanoribbons, and similar terms.

[0025] Current GAA-FETs have difficulties, including non-uniformity in the semiconductor structure of the transistor device when it is manufactured. It is worth noting that in a stack of semiconductor structures, the distance from the source to the drain along the semiconductor structure (i.e., the source to drain length) may be non-uniform. That is, when patterned (e.g., using photolithography and one or more etching processes), the resulting semiconductor structure has different lengths in the xy plane perpendicular to the vertical line of the stack (i.e., the z dimension). This defines the source to drain length because the source and drain structures are then formed by epitaxial growth from the patterned semiconductor structure. Due to the non-uniform source to drain length of the semiconductor structure, assuming that the thickness and other properties of the semiconductor structure are the same, there are differences in the channel resistance and other electrical properties of the semiconductor structure (e.g., nanoribbon). The technology discussed herein optimizes the performance of the GAA-FET by changing the thickness of the semiconductor structure across the stack of semiconductor structures. In some embodiments, this can be a response to the source to drain length change discussed. However, thickness variation can be used in devices containing semiconductor structures with the same source to drain length. In some embodiments, the non-uniformity of the source-to-drain length of the discussed semiconductor structures is predictable and repeatable based on the process used to form them. By pre-defining the thickness of the semiconductor structures and subsequent patterning, the thickness and corresponding source-to-drain length can then be predictably and repeatably formed to adjust the resulting device. In some embodiments, the thickness is adjusted to reduce the channel resistance of the device by, for example, providing a greater thickness for one or more semiconductor structures with a longer source-to-drain length. However, as further discussed herein, any combination of thicknesses can be used to advantageously adjust the GAA-FET to improve electrical performance.

[0026] In some embodiments, a superlattice of alternating layers of silicon (i.e., nanoribbon material) and silicon germanium (i.e., sacrificial layer) is formed. The thickness of the silicon layer can be adjusted based on the expected source-to-drain length of the final nanoribbon being fabricated and / or based on the desired electrical characteristics of the final transistor device. The silicon layer thickness can be adjusted using any suitable technique or techniques, such as adjusting the deposition time and conditions used when forming the silicon layer. The superlattice is then patterned with the resulting source-to-drain length being defined and advantageously corresponding to the predefined silicon layer thickness. Processing continues to form a GAA-FET by, for example, epitaxial growth of the source and drain, nanoribbon release by removal of the silicon germanium sacrificial layer, and formation of the gate structure. During such processing, the source-to-drain length and thickness are substantially maintained, and the resulting device has the advantageous electrical characteristics discussed due to the silicon layer thickness adjustment established during superlattice growth. Although discussed herein with respect to alternating layers of silicon and silicon germanium, any suitable channel semiconductor material and sacrificial material may be used.

[0027] Figure 1Aand Figure 1B Components of an exemplary transistor structure 100 having an adjusted semiconductor structure thickness are shown, in accordance with at least some embodiments of the present disclosure. Figure 1A An isometric view of selected components of an example transistor structure 100 having an adjusted semiconductor structure thickness is provided, and Figure 1B A cross-sectional side view of the transistor structure 100 is provided, taken along a source-to-drain cut (also characterized as a fin cut because it extends along a fin formed during fabrication of the transistor structure 100). As shown, Figure 1B The source to drain cutout shown in the Figure 1A The transistor structure 100 may be part of a device layer of a monolithic integrated circuit die 150 that is incorporated into an electronic device as further discussed herein.

[0028] As shown, transistor structure 100 includes source structure 122, drain structure 123, and gate structure 141, which may be formed on substrate 171 and partially within dielectric material 144. Note that the illustration of transistor structure 100 provides exemplary components and partial fabrication for clarity of presentation. Figure 1B As shown in the cross-sectional view of FIG, the gate structure 141 may include an isolation material 181, a gate structure 183, and a gate contact including a material 180 such as polysilicon. In some embodiments, the material 180 may be removed or not used. Figure 1B As further shown in the cross-section of , the gate structure 183 can surround the gate contact, including a gate dielectric layer 184 adjacent to the stack 124 of semiconductor structures 131, 132, 133, 134 (e.g., surrounding adjacent semiconductor structures 131, 132, 133, 134) and a gate electrode 185 on the gate dielectric layer 184.

[0029] For clarity and convenience, each of the semiconductor structures 131, 132, 133, 134 of the stack 124 may be labeled using nanowire abbreviations from the top of the stack 124 toward the bottom of the stack 124, as shown with respect to the labels nr1, nr2, nr3, nr4. As shown with respect to the semiconductor structure 134, each of the semiconductor structures 131, 132, 133, 134 of the stack 124 has a source-to-drain length (LnrX) and a thickness (TnrX). The source-to-drain length (LnrX) and thickness (TnrX) of each of the semiconductor structures 131, 132, 133, 134 of the stack 124 are further shown and discussed below, but are not shown in the figures for clarity of presentation. Figure 1BIn some embodiments, each source-to-drain length (LnrX) is the same, and one or more of the thicknesses (TnrX) is varied (e.g., by deltas of three angstroms or more) to tune the transistor structure 100. In some embodiments, one or more of the source-to-drain lengths (LnrX) are different, and one or more of the thicknesses (TnrX) is varied (e.g., by deltas of three angstroms or more) to tune the transistor structure 100 based in part on the different source-to-drain lengths (LnrX).

[0030] In some embodiments, the source structure 122 and the drain structure 123 are epitaxial with respect to the stack 124 of semiconductor structures 131, 132, 133, 134. However, the source structure 122 and the drain structure 123 can be formed using any suitable technique or techniques and can include any suitable materials. In any case, each of the semiconductor structures 131, 132, 133, 134 has a source-to-drain length extending from an interface 111 with the source structure 122 to an interface 112 with the drain structure 123, as shown with respect to semiconductor structure 134. As used herein, the term interface indicates the location of a transition from one material or structure to another. As shown with respect to semiconductor structure 134, the source-to-drain length extends from the interface 111 to the interface 112 in a source-to-drain direction 113 that is orthogonal to the vertical dimension 114 of the device.

[0031] 10. In this document, the vertical dimension 114 and the source-to-drain direction 113 are used in their ordinary sense, such that the vertical dimension 114 is orthogonal to the xy plane of the working surface of the substrate 171 (e.g., wafer) and in the front build direction of the transistor structure 100. The source-to-drain direction 113 is in the xy plane and is therefore orthogonal to the vertical dimension 114. Furthermore, in the context shown, the source-to-drain direction 113 extends in the x dimension from the source structure 122 to the drain structure 123. In some embodiments, the source-to-drain direction 113 extends along a fin structure of the transistor structure 100, along a centerline of a channel of the transistor structure 100, etc., as is known in the art. In some embodiments, the source-to-drain direction 113 extends in a direction from the center of mass of the source structure 122 to the drain structure 123. The source-to-drain length LnrX is defined by the distance between the source structure 122 and the drain structure 123 through the channel of each of the semiconductor structures 131 , 132 , 133 , 134 .

[0032] In addition, each of the semiconductor structures 131, 132, 133, 134 of the stack 124 has a thickness (TnrX), again shown with respect to the semiconductor structure 134 (Tnr4). Thickness Tnr4 is in the vertical dimension 114, and thickness Tnr4 (along with each of thicknesses TnrX) can be determined using any suitable technique or techniques. In some embodiments, thickness TnrX is determined by measuring at a center point of each of the semiconductor structures 131, 132, 133, 134. In some embodiments, thickness TnrX is determined by measuring at multiple locations of each of the semiconductor structures 131, 132, 133, 134 and taking an average or median of the resulting measurements. In some embodiments, thickness TnrX is taken across multiple instances of each of the semiconductor structures 131, 132, 133, 134 (e.g., at the center point of each of many transistor structures 100 or at multiple points of each nanoribbon), and the resulting average or median value can be used as thickness TnrX. Other techniques may be used.

[0033] As discussed further below, the thickness TnrX is adjusted to improve the performance of the transistor structure. In some embodiments, the thickness TnrX is adjusted to utilize the equal source-to-drain lengths LnrX of the semiconductor structures 131, 132, 133, 134. In some embodiments, the thickness TnrX is adjusted based on a predictable resulting source-to-drain length LnrX of the stack 124 used to manufacture the semiconductor structures 131, 132, 133, 134. As discussed, the source-to-drain lengths LnrX of the semiconductor structures 131, 132, 133, 134 may not be uniform across the stack 124, but may be predictable and reliable (i.e., predictably different based on manufacturing). As Figure 1B As shown, in some embodiments, the thickness of the bottommost semiconductor structure 134 has a greater thickness Tnr4, which is adjusted to be thicker in response to the source-to-drain length Lnr4 of the semiconductor structure 134 being the longest source-to-drain length in the stack 124. That is, the semiconductor structure 134 can be repeatedly manufactured to be longer than the semiconductor structures 131, 132, and 133, and in response thereto, the thickness Tnr4 can be adjusted to be thicker than the thickness of any of the semiconductor structures 131, 132, and 133. As used herein, the terms bottommost and topmost refer to the last semiconductor structure in the stack 124, where the bottommost is adjacent to the substrate, sub-fins, and similar features, and the topmost is adjacent to the front metallization and similar features.

[0034] As shown, transistor structure 100 includes a source (e.g., source structure 122) and a drain (e.g., drain structure 123), and a stack 124 of semiconductor structures 131, 132, 133, and 134 extending between source structure 122 and drain structure 123. The semiconductor structures 131, 132, 133, and 134 have corresponding source-to-drain lengths Lnr1, Lnr2, Lnr3, and Lnr4 and thicknesses Tnr1, Tnr2, Tnr3, and Tnr4. In some embodiments, the thicknesses Tnr1, Tnr2, Tnr3, and Tnr4 are adjusted such that one of the thicknesses Tnr1, Tnr2, Tnr3, and Tnr4 is less than or greater than any other of the thicknesses Tnr1, Tnr2, Tnr3, and Tnr4 by a thickness increment Td of no less than three angstroms. This adjustment can be made for equal source-to-drain lengths Lnr1, Lnr2, Lnr3, and Lnr4. In some embodiments, the source-to-drain lengths Lnr1, Lnr2, Lnr3, and Lnr4 are equal, and the thickness Tnr4 of the semiconductor structure 134 is no less than 3 angstroms (i.e., Td) greater than any of the thicknesses Tnr1, Tnr2, and Tnr3. However, any of the thicknesses Tnr1, Tnr2, Tnr3, and Tnr4 can be greater or less than all or some of the other thicknesses Tnr1, Tnr2, Tnr3, and Tnr4 by any thickness increment Td discussed herein.

[0035] In some embodiments, some source-to-drain lengths are greater than other source-to-drain lengths, and correspondingly, thicknesses Tnr1, Tnr2, Tnr3, and Tnr4 can be increased by a thickness increment Td. In some embodiments, source-to-drain length Lnr4 of semiconductor structure 134 is greater than any of source-to-drain lengths Lnr1, Lnr2, and Lnr3, and thickness Tnr4 of semiconductor structure 134 is no less than 3 angstroms (i.e., Td) greater than any of thicknesses Tnr1, Tnr2, and Tnr3. Transistor structure 100 further includes a gate structure 183 adjacent to and between the semiconductor structures 131, 132, 133, and 134 of stack 124.

[0036] The discussion now turns to various embodiments of the source-to-drain length LnrX and adjusted thickness of the semiconductor structure of the stack 124. Figure 2-8 In the illustration of FIG, for clarity of presentation, only semiconductor structures such as semiconductor structures 131, 132, 133, 134, substrate 171, and intermediate sacrificial layers are shown. However, the invention can be deployed in transistor structure 100 and other transistor structures, devices, and systems discussed herein. Figure 2-8 Any component of the transistor structure under discussion.

[0037] Figure 2 A cross-sectional side view of a transistor structure 200 similar to the transistor structure 100 is shown, in accordance with at least some embodiments of the present disclosure, wherein the lowermost semiconductor structure has an increased thickness relative to the other semiconductor structures of the stack 124 of semiconductor structures 131, 132, 133, 134. Notably, the source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4 and thicknesses Tnr1, Tnr2, Tnr3, Tnr4 of the semiconductor structures 131, 132, 133, 134 of the transistor structure 200 match those of the transistor structure 100. Transistor structure 200 and related Figure 3-8 The transistor structures discussed above show semiconductor structures 131, 132, 133, 134 separated by a sacrificial layer 201. In some embodiments, the semiconductor structures 131, 132, 133, 134 are silicon or include silicon, and the sacrificial layer 201 is silicon germanium or includes silicon and germanium. The transistor structure 200 can be implemented by forming alternating planar layers of the semiconductor structures 131, 132, 133, 134 and the sacrificial layer 201, and patterning and etching the alternating planar layers into a fin structure, as further described below. In some embodiments, the patterning and etching includes at least a fin-defining etch and a recess etch that forms the recess 202. In some embodiments, the fin-defining etch includes multiple etching processes. As discussed, such patterning and etching can predictably form semiconductor structures 131, 132, 133, 134 having different source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4.

[0038] In some embodiments, the source-to-drain lengths Lnr1, Lnr2, Lnr3, and Lnr4 are in a range of 5 nm to 20 nm, however any suitable source-to-drain lengths Lnr1, Lnr2, Lnr3, and Lnr4 may be employed. In some embodiments, the bottommost semiconductor structure 134 has a source-to-drain length Lnr4 that is greater than any of the source-to-drain lengths Lnr1, Lnr2, and Lnr3. In some embodiments, the bottommost semiconductor structure 134 has a maximum source-to-drain length Lnr4 that is no less than 5% greater than any of the source-to-drain lengths Lnr1, Lnr2, and Lnr3. In some embodiments, the bottommost semiconductor structure 134 has a maximum source-to-drain length Lnr4 that is no less than 10% greater than any of the source-to-drain lengths Lnr1, Lnr2, and Lnr3. In some embodiments, the bottommost semiconductor structure 134 has a maximum source-to-drain length Lnr4 that is no less than 20% greater than any of the source-to-drain lengths Lnr1 , Lnr2 , Lnr3 .Other lengths and multiples are contemplated.

[0039] Furthermore, as shown, the discussed patterning and etching can provide a profile of source-to-drain lengths Lnr1, Lnr2, Lnr3, and Lnr4, with the longest source-to-drain length Lnr1, the shortest source-to-drain length Lnr2, and the source-to-drain length Lnr3 increasing to a length similar to the length of the source-to-drain length Lnr1. However, other profiles can be formed depending on the patterning and etching techniques employed.

[0040] In the context of transistor structure 200, source-to-drain length Lnr4 being substantially longer than any of source-to-drain lengths Lnr1, Lnr2, Lnr3 may enable semiconductor structure 134 to have a substantially longer length from source structure 122 to drain structure 123 (refer to FIG. Figure 1B ). Therefore, when the resulting device is turned on, the semiconductor structure 134 may not carry an equal share of current relative to the semiconductor structures 131, 132, 133. Therefore, in order to adjust the performance, the thickness Tnr4 is increased relative to some or all of the semiconductor structures 131, 132, 133. Figure 2 In the example, thickness Tnr4 is increased by a thickness increment Td relative to reference thickness TnrR. For example, each of semiconductor structures 131, 132, and 133 may have a thickness TnrR (i.e., Tnr1 = Tnr2 = Tnr3 = TnrR), and semiconductor structure 134 may have a thickness Tnr4 (i.e., Tnr4 = TnrR + Td), such that thickness Tnr4 is not less than 3 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. However, thicknesses Tnr1, Tnr2, and Tnr3 may also differ from one another.

[0041] In some embodiments, the reference thickness TnrR is in the range of approximately 75 to 100 angstroms. In some embodiments, the reference thickness TnrR is not less than 75 and not more than 100 angstroms. In some embodiments, the reference thickness TnrR is not less than 85 and not more than 95 angstroms. In some embodiments, the reference thickness TnrR is not less than 85 and not more than 90 angstroms. However, other target thicknesses may be used.

[0042] As discussed, in some embodiments, thickness Tnr4 is no less than 3 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. For example, thickness increment Td may be no less than 3 angstroms. In some embodiments, thickness Tnr4 is no less than 5 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. In some embodiments, thickness Tnr4 is no less than 7 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. In some embodiments, thickness Tnr4 is no less than 3 angstroms and no more than 12 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. In some embodiments, thickness Tnr4 is no less than 3 angstroms and no more than 15 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. In some embodiments, thickness Tnr4 is no less than 5 angstroms and no more than 10 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. Other thickness increments Td may be used; however, it should be noted that thickness increments Td less than 3 angstroms are unlikely to significantly affect electrical performance, while thickness increments Td greater than 15 angstroms provide little additional electrical performance impact relative to smaller thickness increments Td.

[0043] In some embodiments, the thickness increment Td, whether added to or subtracted from one or more of the thicknesses Tnr1, Tnr2, Tnr3, and Tnr4 (as shown), can be approximately 3% to 20% of the reference thickness TnrR shown. In some embodiments, the thickness increment Td is no less than 3% of the reference thickness TnrR. In some embodiments, the thickness increment Td is no less than 5% of the reference thickness TnrR. In some embodiments, the thickness increment Td is no less than 10% of the reference thickness TnrR. In some embodiments, the thickness increment Td is no less than 15% of the reference thickness TnrR. In some embodiments, the thickness increment Td is no less than 3% of the reference thickness TnrR and no more than 20% of the reference thickness TnrR.

[0044] Tnr4 is no less than 5 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. In some embodiments, thickness Tnr4 is no less than 7 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. In some embodiments, thickness Tnr4 is no less than 3 angstroms and no more than 12 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. In some embodiments, thickness Tnr4 is no less than 3 angstroms and no more than 15 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. Other thickness increments Td may be used. In some embodiments, thickness Tnr4 is no less than 5 angstroms and no more than 10 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. Other thickness increments Td may be used, however, it should be noted that thickness increments Td less than 3 angstroms are unlikely to significantly affect electrical performance, while thickness increments Td greater than 15 angstroms provide little additional electrical performance impact relative to smaller thickness increments Td.

[0045] As discussed, since the source-to-drain length Lnr4 is greater than the source-to-drain lengths Lnr1, Lnr2, Lnr3, the thickness Tnr4 can be increased relative to the thicknesses Tnr1, Tnr2, Tnr3. However, any adjustments may be implemented herein. In some embodiments, one or more of the longer length semiconductor structures 131, 132, 133, 134 can have an increased thickness. In other embodiments, one or more of the shorter length semiconductor structures 131, 132, 133, 134 can have an increased thickness. This depends on the type of adjustment desired in the transistor structure. For example, while increasing the thickness of one or more of the semiconductor structures 131, 132, 133, 134 can increase device current, such an increase in thickness increases the overall height H, which increases device capacitance (adversely increasing power consumption) and may adversely increase leakage current, and lead to other difficulties. Therefore, device performance adjustment can be achieved by increasing a specific thickness among the thicknesses Tnr1 , Tnr2 , Tnr3 , Tnr4 , or reducing a specific thickness among the thicknesses Tnr1 , Tnr2 , Tnr3 , Tnr4 , or both.

[0046] Figure 3A cross-sectional side view of a transistor structure 300 is shown, in accordance with at least some embodiments of the present disclosure, wherein a second-lowest semiconductor structure has an increased thickness relative to the other semiconductor structures of the stack 124 of semiconductor structures 131, 132, 133, 134. As discussed, components of the transistor structure 300 can be implemented by forming alternating planar layers of semiconductor structures 131, 132, 133, 134 and sacrificial layer 201, and patterning and etching the alternating planar layers into a fin structure, such that the patterning and etching predictably form semiconductor structures 131, 132, 133, 134 having different source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4. The source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4 can be any of the lengths discussed herein. Notably, the source-to-drain lengths Lnr1 , Lnr2 , Lnr3 , Lnr4 may be the same as or similar to those discussed with respect to the transistor structure 200 .

[0047] In the context of transistor structure 300, source-to-drain length Lnr3 being substantially longer than other source-to-drain lengths (e.g., source-to-drain length Lnr2) may enable semiconductor structure 133 to have a substantially greater length from source structure 122 to drain structure 123 (see FIG. Figure 1B ) has a greater resistance than desired. In addition, because semiconductor structure 133 is not the bottommost semiconductor structure, increasing its thickness may not promote device leakage as much as increasing the thickness of semiconductor structure 134. Therefore, in order to adjust performance, thickness Tnr3 is increased relative to some or all of semiconductor structures 131, 132, and 134. In some embodiments, thickness Tnr3 is increased relative to reference thickness TnrR by a thickness increment Td. For example, each of semiconductor structures 131, 132, and 134 can have a thickness TnrR (i.e., Tnr1=Tnr2=Tnr4=TnrR), and semiconductor structure 133 has a thickness Tnr3 (i.e., Tnr3=TnrR+Td), such that thickness Tnr3 is not less than 3 angstroms greater than each of thicknesses Tnr1, Tnr2, and Tnr3. However, thicknesses Tnr1, Tnr2, and Tnr4 can also be different from each other.

[0048] In some embodiments, source-to-drain length Lnr3 is within 3% of source-to-drain length Lnr1, and source-to-drain length Lnr3 is no less than 5% greater than source-to-drain length Lnr2. In some embodiments, source-to-drain length Lnr3 is no less than 10% greater than source-to-drain length Lnr2. In some embodiments, source-to-drain length Lnr4 is the longest source-to-drain length, and source-to-drain length Lnr4 is no less than 5% greater than source-to-drain length Lnr3. As discussed, in some embodiments, source-to-drain lengths Lnr1, Lnr2, Lnr3, and Lnr4 are in a range of 5 nm to 20 nm. Furthermore, the discussed patterning and etching can provide profiles of source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4 with the longest source-to-drain length Lnr1, the shortest source-to-drain length Lnr2, and a source-to-drain length Lnr3 that increases to a length similar to that of the source-to-drain length Lnr1, as described with respect to FIG. Figure 2 discussed.

[0049] The reference thickness TnrR can be any value discussed above, such as the thickness increment Td. Similarly, the ratio of the thickness increment Td to the reference thickness TnrR can be any value discussed above. In some embodiments, the thickness Tnr3 is not less than 3 angstroms greater than each of the thicknesses Tnr1, Tnr2, and Tnr4. In some embodiments, the thickness Tnr3 is not less than 5 angstroms greater than each of the thicknesses Tnr1, Tnr2, and Tnr4. In some embodiments, the thickness Tnr3 is not less than 7 angstroms greater than each of the thicknesses Tnr1, Tnr2, and Tnr4. In some embodiments, the thickness Tnr3 is not less than 3 angstroms greater than each of the thicknesses Tnr1, Tnr2, and Tnr4 and not more than 12 angstroms. In some embodiments, the thickness Tnr3 is not less than 3 angstroms greater than each of the thicknesses Tnr1, Tnr2, and Tnr4 and not more than 15 angstroms greater than each of the thicknesses Tnr1, Tnr2, and Tnr4. In some embodiments, thickness Tnr3 is no less than 5 angstroms and no more than 10 angstroms greater than each of thicknesses Tnr1 , Tnr2 , and Tnr4 .

[0050] Figure 4A cross-sectional side view of a transistor structure 400 is shown, in accordance with at least some embodiments of the present disclosure, wherein the two topmost semiconductor structures have increased thickness relative to the other semiconductor structures of the stack 124 of semiconductor structures 131, 132, 133, 134. As discussed, the components of the transistor structure 400 can be implemented by forming alternating planar layers of the semiconductor structures 131, 132, 133, 134 and the sacrificial layer 201, and patterning and etching the alternating planar layers into a fin structure. The source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4 can be any length discussed herein. Notably, the source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4 can be the same or similar to those discussed with respect to the transistor structures 200, 300. For example, the transistor structures 200, 300, 400 can have the same or similar source-to-drain length profiles.

[0051] In the context of transistor structure 400, source-to-drain lengths Lnr3, Ln4 that are longer than other source-to-drain lengths (such as, for example, source-to-drain length Lnr2) may allow transistor structure 400 as a whole to have a length from source structure 122 to drain structure 123 (refer to FIG. Figure 1B ) has a greater resistance than desired. In addition, because the semiconductor structures 131, 132 are located on top of the stack 124, increasing the thickness of the semiconductor structures 131, 132 may not promote device leakage as much as increasing the thickness of the semiconductor structures 133, 134. Therefore, to adjust performance, the thicknesses Tnr1, Tnr2 are increased relative to the semiconductor structures 133, 134. In some embodiments, the thicknesses Tnr1, Tnr2 are increased relative to the reference thickness TnrR by a thickness increment Td. For example, each of the semiconductor structures 133, 134 can have a thickness TnrR (i.e., Tnr3=Tnr4=TnrR), and the semiconductor structures 131, 132 have thicknesses Tnr1, Tnr2 (i.e., Tnr1=Tnr2=TnrR+Td), such that the thicknesses Tnr1, Tnr2 are no less than 3 angstroms greater than each of the thicknesses Tnr3, Tnr4. In some embodiments, for example, thicknesses Tnr1, Tnr2 may differ from one another such that each is no less than 3 angstroms, 5 angstroms, or 7 angstroms greater than thicknesses Tnr3, Tnr4.

[0052] The reference thickness TnrR, the thickness increment Td, and the ratio of the thickness increment Td to the reference thickness TnrR can be any of the values ​​discussed above. In some embodiments, the thicknesses Tnr1 and Tnr2 are no less than 3 angstroms greater than each of the thicknesses Tnr3 and Tnr4. In some embodiments, the thicknesses Tnr1 and Tnr2 are no less than 5 angstroms greater than each of the thicknesses Tnr3 and Tnr4. In some embodiments, the thicknesses Tnr1 and Tnr2 are no less than 7 angstroms greater than each of the thicknesses Tnr3 and Tnr4. In some embodiments, the thicknesses Tnr1 and Tnr2 are no less than 3 angstroms and no more than 12 angstroms greater than each of the thicknesses Tnr3 and Tnr4. In some embodiments, the thicknesses Tnr1 and Tnr2 are no less than 3 angstroms and no more than 15 angstroms greater than each of the thicknesses Tnr3 and Tnr4. In some embodiments, the thicknesses Tnr1 and Tnr2 are no less than 5 angstroms and no more than 10 angstroms greater than each of the thicknesses Tnr3 and Tnr4.

[0053] Figure 5 A cross-sectional side view of a transistor structure 500 is shown, wherein the semiconductor structure 531 having a longer source-to-drain length has an increased thickness relative to the other semiconductor structures of the stack 124 of semiconductor structures 531 , 532 , according to at least some embodiments of the present disclosure. Figure 1A 、 Figure 1B 、 Figure 2 、 Figure 3 and Figure 4 In the context of FIG, a stack 124 of four semiconductor structures 131, 132, 133, 134 is shown. However, the stack 124 may have any number of semiconductor structures, such as 2, 3, 6, 7, 8, or more.

[0054] As discussed, the components of the transistor structure 500 are formed by patterning alternating planar layers of semiconductor material and sacrificial layers. The source-to-drain lengths Lnr5, Lnr6 can be any of the lengths discussed herein with respect to the source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4. In the context of the transistor structure 500, a source-to-drain length Lnr5 that is longer than other source-to-drain lengths (e.g., source-to-drain length Lnr6) may result in a longer transition from the source structure 122 to the drain structure 123 (see FIG. Figure 1B ) has a greater resistance than desired. Therefore, thickness Tnr5 is increased relative to thickness Tnr6 to increase the current load of semiconductor structure 531. Although semiconductor structure 531 is shown directly above semiconductor structure 532, semiconductor structures 531, 532 can be at any location within stack 124.

[0055] In some embodiments, the semiconductor structure 531 has a source-to-drain length Lnr5 that is greater than the source-to-drain length Lnr6. In some embodiments, the source-to-drain length Lnr5 is no less than 5% greater than the source-to-drain length Lnr6. In some embodiments, the source-to-drain length Lnr5 is no less than 10% greater than the source-to-drain length Lnr6. In some embodiments, the source-to-drain length Lnr5 is no less than 20% greater than the source-to-drain length Lnr6. Other lengths and multiples are contemplated. As discussed, the thickness Tnr5 of the semiconductor structure 531 is increased relative to the thickness Tnr6 of the semiconductor structure 532 to adjust the performance of the transistor structure 500. In some embodiments, the thickness Tnr5 is increased by a thickness increment Td relative to the reference thickness TnrR. For example, the semiconductor structure 532 may have a thickness of TnrR (i.e., Tnr6=TnrR), and the semiconductor structure 531 may have a thickness of TnrR plus a thickness increment (i.e., Tnr5=TnrR+Td), such that the thickness Tnr5 is not less than 3 angstroms greater than the thickness Tnr6. In some embodiments, the thickness Tnr5 is not less than 5 angstroms greater than the thickness Tnr6. In some embodiments, the thickness Tnr5 is not less than 7 angstroms greater than the thickness Tnr6. In some embodiments, the thickness Tnr5 is not less than 3 angstroms greater than the thickness Tnr6 and not more than 12 angstroms. In some embodiments, the thickness Tnr5 is not less than 3 angstroms greater than the thickness Tnr6 and not more than 15 angstroms greater than the thickness Tnr6. In some embodiments, the thickness Tnr5 is not less than 5 angstroms greater than the thickness Tnr6 and not more than 10 angstroms.

[0056] Figure 6 A cross-sectional side view of a transistor structure 600 is shown, in accordance with at least some embodiments of the present disclosure, wherein a semiconductor structure 631 having a shorter source-to-drain length has an increased thickness relative to other semiconductor structures of the stack 124 of semiconductor structures 631, 632. Transistor structure 600 illustrates the opposite relationship with respect to transistor structure 500. In the context of transistor structure 600, the shorter source-to-drain length semiconductor structure 632 can be located at a location in the stack 124 (e.g., not at the bottom of the stack 124, or at or near the middle of the stack 124) such that increased current flows through the semiconductor structure 632. For example, current can be advantageously moved within the stack 124 to a location in the stack, a longer source-to-drain length semiconductor structure, a shorter source-to-drain length semiconductor structure, or any combination thereof to adjust the performance of the transistor structure.

[0057] The source to drain length Lnr5, Lnr6 and thickness Tnr5, Tnr6 can be about Figure 6Any dimensions discussed. Note that the thicknesses Tnr5, Tnr6 are switched such that the shorter source-to-drain length semiconductor structure 632 (i.e., having a shorter source-to-drain length Lnr6) is paired with the larger thickness Tnr5, and the source-to-drain length semiconductor structure 631 (i.e., having a longer source-to-drain length Lnr5) is paired with the smaller thickness Tnr6. Although semiconductor structure 531 is shown directly above semiconductor structure 532, semiconductor structures 531, 532 can be located anywhere within stack 124.

[0058] In some embodiments, semiconductor structure 631 has a source-to-drain length Lnr5 that is greater than source-to-drain length Lnr6 of semiconductor structure 632. In some embodiments, source-to-drain length Lnr5 is no less than 5% greater than source-to-drain length Lnr6. In some embodiments, source-to-drain length Lnr5 is no less than 10% greater than source-to-drain length Lnr6. In some embodiments, source-to-drain length Lnr5 is no less than 20% greater than source-to-drain length Lnr6. Other lengths and multiples are contemplated. As discussed, the thickness Tnr5 of semiconductor structure 632 is increased relative to the thickness Tnr6 of semiconductor structure 631 to adjust the performance of transistor structure 600. In some embodiments, thickness Tnr5 is increased by a thickness increment Td relative to a reference thickness TnrR. For example, the semiconductor structure 631 may have a thickness of TnrR (i.e., Tnr6=TnrR), and the semiconductor structure 632 may have a thickness of TnrR plus a thickness increment Td (i.e., Tnr5=TnrR+Td), such that the thickness Tnr5 is not less than 3 angstroms greater than the thickness Tnr6. In some embodiments, the thickness Tnr5 is not less than 5 angstroms greater than the thickness Tnr6. In some embodiments, the thickness Tnr5 is not less than 7 angstroms greater than the thickness Tnr6. In some embodiments, the thickness Tnr5 is not less than 3 angstroms greater than the thickness Tnr6 and not more than 12 angstroms. In some embodiments, the thickness Tnr5 is not less than 3 angstroms greater than the thickness Tnr6 and not more than 15 angstroms greater than the thickness Tnr6. In some embodiments, the thickness Tnr5 is not less than 5 angstroms greater than the thickness Tnr6 and not more than 10 angstroms.

[0059] Figure 7 A cross-sectional side view of a transistor structure 700 is shown in accordance with at least some embodiments of the present disclosure, wherein a lowermost semiconductor structure has an increased thickness relative to the other semiconductor structures of the stack 124 of semiconductor structures 131, 132, 133, 134, 135, 136. As discussed, the stack 124 may have any number of semiconductor structures, such as 2 to 8 semiconductor structures or more. Figure 7An example is shown with six semiconductor structures 131, 132, 133, 134, 135, 136, wherein semiconductor structure 136 is longer than any other semiconductor structure of semiconductor structures 131, 132, 133, 134, 135 and, correspondingly, semiconductor structure 136 has an increased adjusted thickness. This is similar to Figure 2 .

[0060] The source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4, Lnr5, and Lnr6 can be any of the lengths discussed above. In some embodiments, the bottommost semiconductor structure 136 has a source-to-drain length Lnr6 that is greater than any of the source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4, and Lnr5. In some embodiments, the maximum source-to-drain length Lnr6 of the bottommost semiconductor structure 136 is no less than 5%, no less than 10%, or no less than 20% greater than any of the source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4, and Lnr5. In response to this predictably manufactured length difference, the thickness Tnr6 of the bottommost semiconductor structure 136 is increased by a thickness increment Td, as discussed herein.

[0061] exist Figure 7 In the context of FIG, the thickness Tnr6 of the bottommost semiconductor structure 136 is increased due to it having the longest source-to-drain length Lnr6. However, any of the semiconductor structures 131, 132, 133, 134, 135, 136 may have an increased thickness in response to its length being longer or shorter than the other semiconductor structures 131, 132, 133, 134, 135, 136. As discussed, such electrical adjustments may be based on balancing current flow through the semiconductor structures 131, 132, 133, 134, 135, 136, and / or other issues such as leakage, source / drain to semiconductor resistance differences across the semiconductor structures 131, 132, 133, 134, 135, 136, proximity to source / drain contacts, etc.

[0062] In some embodiments, in any combination, any of the semiconductor structures 131, 132, 133, 134, 135, 136 can have a thickness that is increased or decreased by 3 to 15 angstroms relative to the other semiconductor structures 131, 132, 133, 134, 135, 136, based on, for example, being 5%, 10%, or 20% longer or shorter (i.e., in terms of source-to-drain length) than the other semiconductor structures 131, 132, 133, 134, 135, 136. Furthermore, such an increase or decrease can be performed in any combination across the semiconductor structures 131, 132, 133, 134, 135, 136. It should be noted that due to the limited benefits of thickness differences as discussed above, multiple increases, multiple decreases, or a combination thereof may be limited to two increases, two decreases, or one increase and one decrease throughout the stack 124 for a total 2*Td difference between any two of the semiconductor structures 131, 132, 133, 134, 135, 136. However, with smaller thickness differences Td, three or four times the thickness difference Td may be used between any of the semiconductor structures 131, 132, 133, 134, 135, 136.

[0063] As discussed, any of the semiconductor structures 131, 132, 133, 134, 135, 136, in any combination, can have an increased or decreased thickness relative to the other semiconductor structures 131, 132, 133, 134, 135, 136, based on being longer or shorter than the other semiconductor structures 131, 132, 133, 134, 135, 136. In some embodiments, the topmost semiconductor structure 131 and the bottommost semiconductor structure 136 have a thickness no less than 3 to 15 angstroms greater than any of the semiconductor structures 132, 133, 134, 135. In some embodiments, the intermediate semiconductor structures 133, 134 have a thickness no less than 3 to 15 angstroms greater than any of the semiconductor structures 131, 132, 135, 136. In some embodiments, topmost semiconductor structure 131 and bottommost semiconductor structure 136 have thicknesses no less than 3 to 15 angstroms greater than semiconductor structures 133 and 134, and semiconductor structures 132 and 135 have thicknesses no less than 3 to 15 angstroms less than semiconductor structures 133 and 134. It will be appreciated that combinations of such thickness variations may be used for stack 124.

[0064] Figure 8A cross-sectional side view of a transistor structure 800 is shown in accordance with at least some embodiments of the present disclosure, wherein the two lowermost semiconductor structures have increased thickness relative to the other semiconductor structures of the stack 124 of semiconductor structures 131 , 132 , 133 , 134 , 135 , 136 . Figure 8 An example with six semiconductor structures 131 , 132 , 133 , 134 , 135 , 136 is shown, but any number of semiconductor structures may be used. In the context of the transistor structure 800 , the bottommost semiconductor structures 135 , 136 have an increasing adjusted thickness.

[0065] As discussed, adjusting the thickness of the semiconductor structures 131, 132, 133, 134, 135, 136 may be based on differences in source-to-drain lengths and electrical characteristics of the semiconductor structures 131, 132, 133, 134, 135, 136. Figure 8 In the context of FIG, the bottommost semiconductor structure 136 has a maximum source-to-drain length Lnr6, which is not less than 5%, not less than 10%, or not less than 20% greater than any of the source-to-drain lengths Lnr1, Lnr2, Lnr3, Ln4, and Lnr5. Furthermore, the next-bottommost semiconductor structure 135 has a source-to-drain length Lnr5 that is less than the length of Lnr6 and not greater than any of the source-to-drain lengths Lnr1, Lnr2, Lnr3, and Ln4. For example, the source-to-drain length Lnr5 may be less than or equal to any of the source-to-drain lengths Lnr1, Lnr2, Lnr3, and Ln4, such as the source-to-drain length Lnr1. In this context, the thickness Tnr5 of the semiconductor structure 135 may be increased to unload current from the other semiconductor structures 131, 132, 133, 134 and toward the semiconductor structure 136. Although the semiconductor structures 135, 136 are shown with increased thicknesses, in other examples, the thickness of any one of the semiconductor structures 131, 132, 133, 134 and the semiconductor structure 136 is increased.

[0066] For example, the source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4, Lnr5, and Lnr6 can be any of the lengths discussed above. And in some embodiments, the bottommost semiconductor structure 136 has a source-to-drain length Lnr6 that is greater than any of the source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4, and Lnr5. For example, the bottommost semiconductor structure 136 can have a maximum source-to-drain length Lnr6 that is no less than 5%, no less than 10%, or no less than 20% greater than any of the source-to-drain lengths Lnr1, Lnr2, Lnr3, Lnr4, and Lnr5. Then, as discussed above, the thickness Tnr6 of the bottommost semiconductor structure 136 increases along with the thickness of one of the semiconductor structures 131, 132, 133, 134, and 135.

[0067] exist Figure 7 In the context of FIG, the thickness Tnr6 of the bottommost semiconductor structure 136 is increased due to it having the longest source-to-drain length Lnr6. However, any of the semiconductor structures 131, 132, 133, 134, 135, 136 may have an increased thickness in response to its length being longer or shorter than the other semiconductor structures 131, 132, 133, 134, 135, 136. As discussed, such electrical adjustments may be based on balancing current flow through the semiconductor structures 131, 132, 133, 134, 135, 136, and / or other issues such as leakage, source / drain to semiconductor resistance differences across the semiconductor structures 131, 132, 133, 134, 135, 136, proximity to source / drain contacts, etc.

[0068] The discussion now turns to the fabrication of any of the transistor structures discussed herein. Notably, the adjusted thickness is formed at the beginning of fabrication based on a known etch profile that occurs later in the fabrication process.

[0069] Figure 9 907. The present invention provides a flow chart illustrating an exemplary method 900 for forming a transistor structure having a stack of semiconductor structures having an adjusted thickness, arranged in accordance with at least some embodiments of the present disclosure. For example, the method 900 may be implemented to fabricate the transistor structures 100, 1500, or any transistor structure having any of the adjusted thickness stacks discussed herein. In the illustrated embodiment, the method 900 may include one or more operations as illustrated by operations 901-907. However, the embodiments herein may include additional operations, have certain operations omitted, or perform operations out of the order provided.

[0070] Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15 is a cross-sectional side view of an example transistor structure when performing certain manufacturing operations of method 900, arranged in accordance with at least some embodiments of the present disclosure. For example, method 900 may be deployed to manufacture Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15 The transistor structure fabricated may have any of the characteristics discussed with respect to transistor structures 100, 200, 300, 400, 500, 600, 700, 800.

[0071] Processing begins at operation 901 where a workpiece, such as a substrate, is received for processing. The substrate may include any suitable substrate as discussed herein, such as a silicon wafer, etc. In some embodiments, the substrate includes underlying devices or electrical interconnects. In some embodiments, substrate 171 may be received for processing.

[0072] Processing continues at operation 902 where alternating layers of semiconductor material and sacrificial layers are formed over a workpiece or substrate. The alternating layers of semiconductor material and sacrificial layers may be formed using any suitable one or more techniques such as epitaxial growth techniques, deposition techniques, etc. The semiconductor material and sacrificial layers may have a thickness of about Figure 2-8 In some embodiments, the thickness of the semiconductor material layer is adjusted based on growth or deposition conditions (such as adjusting the growth or deposition time used in forming the semiconductor material layer).

[0073] Now refer to Figure 10 , an example transistor structure 1000 includes a substrate 171 (e.g., a transistor structure workpiece) and a stack 124 of semiconductor material layers 1001, 1002, 1003, 1004 alternating or interleaved with a sacrificial layer 1010. The sacrificial layer 1010 and the stack 124 of semiconductor material layers 1001, 1002, 1003, 1004 can be formed using any suitable one or more techniques, such as those discussed with respect to operation 902. Notably, the semiconductor material layers 1001, 1002, 1003, 1004 and the sacrificial layer 1010 are bulk layers that can subsequently be patterned so that the patterning forms a predictable source-to-drain length as discussed. In some embodiments, the semiconductor material layers 1001, 1002, 1003, 1004 are silicon, such as single crystal silicon, and the sacrificial layer 1010 is silicon germanium, although other material systems may be used.

[0074] It is noted that the thicknesses Tnr1, Tnr2, Tnr3, and Tnr4 of the semiconductor material layers 1001, 1002, 1003, and 1004 are adjusted to produce the transistor structure 200. However, any thickness discussed herein may be employed. As shown, the semiconductor material layers 1001, 1002, 1003, and 1004 and the sacrificial layer 1010 are formed over the substrate 171.

[0075] Substrate 171 can include any suitable material or materials, and in some embodiments, substrate 171 includes one or more materials having the same or similar composition relative to semiconductor material layers 1001, 1002, 1003, 1004. In some embodiments, substrate 171 and semiconductor material layers 1001, 1002, 1003, 1004 include Group IV materials (e.g., silicon). In some embodiments, substrate 171 and semiconductor material layers 1001, 1002, 1003, 1004 include substantially single crystalline materials. In some embodiments, substrate 171 includes a buried insulator layer (e.g., SiO2), such as a semiconductor-on-insulator (SOI) substrate and / or an isolation insulator region. The semiconductor material layers 1001, 1002, 1003, 1004 may include any number of layers used to form a semiconductor structure, channel semiconductor, nanoribbon, or nanowire above the substrate 171, such as two, three, four, five, six, seven, eight, or more layers with a typically deployed even number of semiconductor material layers 1001, 1002, 1003, 1004. The semiconductor material layers 1001, 1002, 1003, 1004 are separated and interleaved with sacrificial layers 1010 that will later be removed and replaced by one or more gate structures including, for example, a gate dielectric material and a gate electrode material.

[0076] Back to Figure 9 , processing continues at operation 903, where alternating layers of semiconductor material layers and sacrificial layers are patterned to form a fin structure. Such patterning can be performed using any suitable one or more techniques, such as photolithography and etching techniques. As discussed, when patterned, the resulting semiconductor structure or nanoribbon has predictably different lengths due, at least in part, to the patterning profile (e.g., the etching profile). In some embodiments, patterning includes multiple etches, such as one or two etches for defining the fin critical dimensions of the semiconductor material layers, and a groove etch for recessing the sacrificial layer to form a dielectric spacer. The dielectric can isolate the source and drain from the gate, which is formed later in the process.

[0077] Figure 11An exemplary transistor structure 1100 similar to transistor structure 1000 is shown after a patterning process to form a stack 124 including semiconductor structures 131, 132, 133, 134 and sacrificial layer 201, which can have any of the characteristics discussed above, including recess 202. As discussed, stack 124 can be patterned from semiconductor material layers 1001, 1002, 1003, 1004 and sacrificial layer 1010 using one or more photolithography and etching patterning operations. Also as shown, the formation of semiconductor material layers 1001, 1002, 1003, 1004 can form a sub-fin portion 1102.

[0078] Back to Figure 9 , processing continues at operation 904 where dielectric spacers are formed adjacent to the sacrificial layer to ultimately isolate the gate structure from the source and drain materials. The dielectric spacers may be formed using any suitable technique or techniques, such as deposition and etching techniques.

[0079] Figure 12 An example transistor structure 1200 similar to transistor structure 1100 is shown after forming isolation material 181. Figure 12-15 , the thickness TnrX and the source-to-drain length LnrX are not shown for clarity, but such dimensions are substantially maintained in the transistor structure 1200 and subsequent transistor structures. The isolation material 181 can also be characterized as a dielectric spacer, spacer, or spacer material because it separates the final gate structure (which will replace the sacrificial layer 201) from the final source structure 122 and drain structure 123. The isolation material 181 can be any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0080] Back to Figure 9 , processing continues at operation 905, where epitaxial source and drain materials are deposited via growth from exposed portions of the patterned semiconductor structure. In some embodiments, an epitaxial nucleation layer may be deposited followed by bulk deposition. The source and drain materials may be any suitable material, such as doped silicon, doped silicon germanium, etc. The epitaxial source and drain materials may be deposited using any suitable technique or techniques, such as chemical vapor deposition including a dopant material.

[0081] Figure 13An example transistor structure 1300 is shown that is similar to transistor structure 1200 after forming source structure 122 and drain structure 123. As discussed, source structure 122 and drain structure 123 can be, for example, epitaxial bodies such as doped epitaxial silicon or doped epitaxial silicon and germanium (SiGe). As discussed, the formation of source structure 122 and drain structure 123 provides an interface between the source-to-drain lengths of semiconductor structures 131, 132, 133, 134 (see FIG. 1 ). Figure 1B ).

[0082] Back to Figure 9 , processing continues at operation 906, where the sacrificial material deposited at operation 902 and patterned at operation 903 is removed and replaced by a gate structure, which may include a gate dielectric material on at least a portion of the semiconductor structure and a gate electrode (e.g., gate metal) on the gate dielectric material. The sacrificial material may be removed using any suitable technique or techniques (e.g., wet etching techniques). The gate dielectric material may be formed using, for example, conformal deposition, and the gate electrode may be formed by conformal deposition (of a work function metal) followed by metal fill. However, other fabrication techniques may be used.

[0083] Figure 14 An exemplary transistor structure 1400 similar to transistor structure 1300 is shown after forming isolation material 1401 and gate structure 183, which includes a gate dielectric layer 184 and a gate electrode 185. Isolation material 1401 can be silicon oxide or other dielectric materials. In some embodiments, gate structure 183 includes gate dielectric layer 184, which is or includes aluminum oxide, hafnium oxide, zirconium oxide, titanium silicon oxide, hafnium silicon oxide, or silicon nitride. In some embodiments, gate electrode 185 includes a work function layer of platinum, nickel, titanium nitride, or tantalum nitride and a fill metal such as tungsten. However, other material systems may be used.

[0084] Back to Figure 9, processing continues at operation 907 where the source and drain materials and the gate structure are contacted by metal contacts using any suitable technique or techniques, such as patterning and metal deposition processes known in the art. Additionally, at operation 907, additional fabrication can be completed and the resulting structure can be output. Such processing can include additional front metallization, back metallization, additional back-end processing, cutting, packaging, assembly, and the like. The resulting device (e.g., an integrated circuit die) can then be implemented in any suitable form factor device, such as a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant, ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, and the like.

[0085] Figure 15 An example transistor structure 1500 similar to transistor structure 1400 is shown after forming isolation material 1504, gate contact 1502, source contact 1501, and drain contact 1503. Isolation material 1504, gate contact 1502, source contact 1501, and drain contact 1503 can be formed using operations known in the art, such as body isolation followed by planarization to form isolation material 1504, and photolithographic patterning of vias and via filling and optional planarization to form gate contact 1502, source contact 1501, and drain contact 1503. Such components can include any suitable material. For example, isolation material 1504 can be silicon oxide, and gate contact 1502, source contact 1501, and drain contact 1503 can include a liner material such as titanium nitride and a fill metal such as tungsten. However, other material systems can be used.

[0086] Figure 16 A cross-sectional side view of a transistor structure 1500 having a stack of semiconductor structures with adjusted thicknesses, incorporating the transistor structure 1500 into an integrated circuit die 1600, is shown in accordance with at least some embodiments of the present disclosure. As shown, the transistor structure 1500, or any other transistor structure discussed herein, can be incorporated into an integrated circuit (IC) die 1600 having a front metallization layer 1601 (or front interconnect layer) and a back metallization layer 1602 (or back interconnect layer). The front metallization layer 1601 and the back metallization layer 1602 can be formed using any suitable technique or techniques, such as a dual damascene technique, a single damascene technique, a subtractive metallization patterning technique, and the like.

[0087] For example, interconnection, signal routing, power delivery, etc. can be provided by the front metallization layer 1601. Adjacent metallization layers (such as metallization interconnect 1610) are interconnected by vias (such as via 1603), which can be characterized as part of a metallization layer or between metallization layers. As shown, in some embodiments, the front metallization layer 1601 is formed above and adjacent to the transistor structure 1500. In the example shown, the front metallization layer 1601 includes M0, V0, M1, M2 / V1, M3 / V2, and M4 / V3. However, the front metallization layer 1601 can include any number of metallization layers, such as six, eight, or more metallization layers.

[0088] Similarly, the back metallization layer 1602 can be used for power delivery and any other suitable electrical connection. In the example shown, the package-level interconnect 1611 is provided on the back side of the device or above the back side of the device as a bump above the passivation layer 1605. However, any suitable interconnect structure such as a bonding pad, a solder bump, etc. can be used to provide the package-level interconnect 1611. As shown, in some embodiments, the back metallization layer 1602 is formed above and adjacent to the transistor structure 1500, such that the device layer 1604 including the transistor structure 1500 is between the front metallization layer 1601 and the back metallization layer 1602. In the example shown, the back metallization layer 1602 includes BM0, BM1 and BM2 with an intermediate via layer. However, the back metallization layer 1602 can include any number of metallization layers, such as three, four or more metallization layers.

[0089] In some embodiments, transistor structure 1500 is implemented in a monolithic integrated circuit (IC) die 1600 including a gate-all-around field-effect transistor structure (e.g., GAA-FET) including any of the components and features discussed. As shown, a power supply 1606 can be coupled to IC die 1600 such that power supply 1606 can include a battery, a voltage converter, power circuitry, and the like.

[0090] Figure 17An exemplary system employing an integrated circuit assembly including an integrated circuit die having a transistor structure having a stack of semiconductor structures with adjusted thicknesses is shown in accordance with some embodiments. For example, the system may be a mobile computing platform 1705 and / or a data server machine 1706. Either may employ a component assembly including an IC die having a transistor structure having a stack of semiconductor structures with adjusted thicknesses as described elsewhere herein. Server machine 1706 may be any commercial server, such as any number of high-performance computing platforms arranged in a rack and networked together for electronic data processing, which in an exemplary embodiment includes an IC die assembly 1750 having an IC die having a transistor structure having a stack of semiconductor structures with adjusted thicknesses as described elsewhere herein. Mobile computing platform 1705 may be any portable device configured for electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1705 may be any of a tablet computer, a smartphone, a laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touch screen), a chip-level or package-level integrated system 1710, and a battery 1715. Although illustrated with respect to the mobile computing platform 1705, in other examples, the chip-level or package-level integrated system 1710 and the battery 1715 may be implemented in a desktop computing platform, an automotive computing platform, an Internet of Things platform, etc. As discussed below, in some examples, the disclosed system may include the subsystem 1760 illustrated with respect to the mobile computing platform 1705, such as a system on a chip (SOC) or an integrated system of multiple ICs.

[0091] Whether provided within the integrated system 1710 shown in the expanded view 1720 or as a standalone packaged device within the data server machine 1706, the subsystem 1760 may include memory circuitry and / or processor circuitry 1740 (e.g., RAM, a microprocessor, a multi-core microprocessor, a graphics processor, etc.), a power management integrated circuit (PMIC) 1730, a controller 1735, and a radio frequency integrated circuit (RFIC) 1725 (e.g., including a broadband RF transmitter and / or receiver (TX / RX)). As shown, one or more IC dies, such as the memory circuitry and / or processor circuitry 1740, may be assembled and implemented such that the one or more IC dies have a transistor structure having a stack of semiconductor structures with adjusted thicknesses as described herein. In some embodiments, the RFIC 1725 includes a digital baseband and an analog front-end module, which also includes a power amplifier in the transmit path and a low-noise amplifier in the receive path. Functionally, the PMIC 1730 may perform battery power conditioning, DC to DC conversion, etc., and thus has an input coupled to the battery 1715 and an output providing current supply to other functional modules. Figure 17 As further shown in FIG, in an exemplary embodiment, RFIC 1725 has an output coupled to an antenna (not shown) to implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. Memory circuitry and / or processor circuitry 1740 can provide memory functions for subsystem 1760, provide high-level control, data processing, etc. for subsystem 1760. In an alternative embodiment, each SOC module can be integrated into a separate IC coupled to a package substrate, interposer, or board.

[0092] Figure 18is a functional block diagram of an electronic computing device 1800 according to some embodiments. For example, the device 1800 can employ, via any suitable component therein, a transistor structure having a stack of semiconductor structures having adjusted thicknesses according to any embodiment described elsewhere herein. The device 1800 further includes a motherboard or packaging substrate 1802 that carries a plurality of components, such as, but not limited to, a processor 1804 (e.g., an application processor). The processor 1804 can be physically and / or electrically coupled to the packaging substrate 1802. In some examples, the processor 1804 is within an IC assembly that includes an IC die having a transistor structure having a stack of semiconductor structures having adjusted thicknesses as described elsewhere herein. In general, the term "processor" or "microprocessor" can refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be further stored in registers and / or memory.

[0093] In various examples, one or more communication chips 1806 may also be physically and / or electrically coupled to the package substrate 1802. In further implementations, the communication chip 1806 may be part of the processor 1804. Depending on its application, the computing device 1800 may include other components that may or may not be physically and electrically coupled to the package substrate 1802. These other components include, but are not limited to, volatile memory (e.g., DRAM 1832), non-volatile memory (e.g., ROM 1835), flash memory (e.g., NAND or NOR), magnetic memory (MRAM 1830), a graphics processor 1822, a digital signal processor, a cryptographic processor, a chipset 1812, an antenna 1825, a touch screen display 1815, a touch screen controller 1865, a battery 1816, an audio codec, a video codec, a power amplifier 1821, a global positioning system (GPS) device 1840, a compass 1845, an accelerometer, a gyroscope, a speaker 1820, a camera 1841, and mass storage devices (such as hard disk drives, solid-state drives (SSDs), compact disks (CDs), digital versatile disks (DVDs), etc.), etc.

[0094] The communication chip 1806 can implement wireless communications for transmitting data to and from the computing device 1800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires. The communication chip 1806 can implement any of a variety of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, the computing device 1800 can include multiple communication chips 1806. For example, a first communication chip can be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip can be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0095] Although certain features set forth herein have been described with reference to various embodiments, this description is not intended to be construed in a limiting sense. Therefore, various modifications to the embodiments described herein, as well as other embodiments obvious to those skilled in the art to which the present disclosure pertains, are deemed to be within the spirit and scope of the present disclosure.

[0096] It will be appreciated that the invention is not limited to the embodiments thus described, but may be practiced with modification and alteration without departing from the scope of the appended claims.For example, the embodiments described above may include specific combinations of features as further provided below.

[0097] The following relates to exemplary embodiments.

[0098] In one or more first embodiments, a device includes: a source and a drain; a stack of semiconductor structures between the source and the drain, such that a first semiconductor structure in the semiconductor structures has a first thickness, a second semiconductor structure in the semiconductor structures has a second thickness, and the first thickness is not less than three angstroms greater than the second thickness; and a gate structure adjacent to and between the stack of semiconductor structures.

[0099] In one or more second embodiments, further to the first embodiment, a first semiconductor structure in the semiconductor structure has a first source-to-drain length, and a second semiconductor structure in the semiconductor structure has a second source-to-drain length, and the first source-to-drain length is greater than the second source-to-drain length.

[0100] In one or more third embodiments, further to the first or second embodiment, the first source-to-drain length is not less than 10% greater than the second source-to-drain length, and the first thickness is not less than five angstroms greater than the second thickness.

[0101] In one or more fourth embodiments, further to the first to third embodiments, the first semiconductor structure in the semiconductor structures is a bottommost semiconductor structure in a stack of semiconductor structures.

[0102] In one or more fifth embodiments, further to the first to fourth embodiments, a first semiconductor structure in the semiconductor structure has a first source-to-drain length, and a second semiconductor structure in the semiconductor structure has a second source-to-drain length, and the second source-to-drain length is greater than the first source-to-drain length.

[0103] In one or more sixth embodiments, further to the first to fifth embodiments, the second source-to-drain length is not less than 10% greater than the first source-to-drain length, and the first thickness is not less than five angstroms greater than the second thickness.

[0104] In one or more seventh embodiments, further to the first to sixth embodiments, the second semiconductor structure in the semiconductor structure is the bottommost semiconductor structure of the stack of semiconductor structures, and the first semiconductor structure in the semiconductor structure is the topmost semiconductor structure of the stack of semiconductor structures.

[0105] In one or more eighth embodiments, further to the first to seventh embodiments, a third semiconductor structure in the semiconductor structure has a third source-to-drain length and a third thickness, the second source-to-drain length is not less than 10% greater than the third source-to-drain length, and the second thickness is not less than three angstroms less than the third thickness, and the third semiconductor structure in the semiconductor structure is immediately below the first semiconductor structure in the semiconductor structure.

[0106] In one or more ninth embodiments, further to the first to eighth embodiments, each of the semiconductor structures comprises silicon, and the source and the drain are epitaxial to the semiconductor structures.

[0107] In one or more tenth embodiments, further to the first to ninth embodiments, the apparatus further comprises an integrated circuit (IC) die and a power supply coupled to the IC die, wherein the IC die comprises a source, a drain, a stack of semiconductor structures, and a gate structure.

[0108] In one or more eleventh embodiments, a device includes: a source structure and a drain structure; a stack of semiconductor structures aligned in a vertical direction and extending between an interface with the source structure and an interface with the drain structure, a first semiconductor structure in the semiconductor structure having a first source-to-drain length that is not less than 10% greater than a second source-to-drain length of a second semiconductor structure in the semiconductor structure, such that the first semiconductor structure in the semiconductor structure has a first thickness that is not less than five angstroms greater than a second thickness of the second semiconductor structure in the semiconductor structure; and a gate structure adjacent to the stack of semiconductor structures.

[0109] In one or more twelfth embodiments, further to the eleventh embodiment, the first semiconductor structure in the semiconductor structures is a bottommost semiconductor structure in a stack of semiconductor structures.

[0110] In one or more thirteenth embodiments, further to the eleventh or twelfth embodiment, the first thickness is not less than seven angstroms greater than the second thickness.

[0111] In one or more fourteenth embodiments, further to the eleventh to thirteenth embodiments, the second thickness is not less than 75 angstroms and not more than 100 angstroms.

[0112] In one or more fifteenth embodiments, further to the eleventh to fourteenth embodiments, a first semiconductor structure in the semiconductor structure is above a second semiconductor structure in the semiconductor structure in the stack of semiconductor structures.

[0113] In one or more sixteenth embodiments, further to the eleventh to fifteenth embodiments, the device also includes an integrated circuit (IC) die and a power supply coupled to the IC die, wherein the integrated circuit die includes a source, a drain, a stack of semiconductor structures, and a gate structure.

[0114] In one or more seventeenth embodiments, a method includes: receiving a multilayer stack comprising a plurality of semiconductor material layers interleaved with a plurality of sacrificial layers, such that a first semiconductor material layer in the semiconductor material layers has a first thickness not less than five angstroms greater than a second thickness of a second semiconductor material layer in the semiconductor material layers; etching the multilayer stack to form a fin structure; growing a source structure and a drain structure from the semiconductor material layer of the fin structure, such that the first semiconductor material layer in the semiconductor material layers has a first source-to-drain length greater than a second source-to-drain length of the second semiconductor material layer in the semiconductor material layers; and replacing the sacrificial layer with a gate structure coupled to the semiconductor material layer.

[0115] In one or more eighteenth embodiments, further to the seventeenth embodiment, the first semiconductor material layer in the semiconductor material layers is the bottommost semiconductor material layer in the semiconductor material layers, and the first thickness is not less than seven angstroms greater than the second thickness.

[0116] In one or more nineteenth embodiments, further to the seventeenth or eighteenth embodiment, the first source-to-drain length is no less than 20% greater than the second source-to-drain length.

[0117] In one or more twentieth embodiments, further to the seventeenth to nineteenth embodiments, a first semiconductor material layer in the semiconductor material layers is above a second semiconductor material layer in the semiconductor material layers.

[0118] It will be appreciated that the present invention is not limited to the embodiments described above, but can be practiced with modifications and variations without departing from the scope of the appended claims. For example, the above embodiments may include a specific combination of features. However, the above embodiments are not limited thereto, and in various embodiments, the above embodiments may include only a subset of such features, a different order of such features, a different combination of such features, and / or additional features other than those explicitly listed. Therefore, the scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A device comprising: source and drain; a stack of semiconductor structures between the source and the drain, wherein a first semiconductor structure in the semiconductor structures has a first thickness, a second semiconductor structure in the semiconductor structures has a second thickness, and the first thickness is not less than three angstroms greater than the second thickness; as well as A gate structure is adjacent to and between the stack of semiconductor structures.

2. The device according to claim 1, wherein The first of the semiconductor structures has a first source-to-drain length, and the second of the semiconductor structures has a second source-to-drain length, and wherein the first source-to-drain length is greater than the second source-to-drain length.

3. The device according to claim 2, wherein The first source-to-drain length is no less than 10% greater than the second source-to-drain length, and the first thickness is no less than five angstroms greater than the second thickness.

4. The device according to claim 2, wherein The first semiconductor structure of the semiconductor structures is a bottommost semiconductor structure of a stack of semiconductor structures.

5. The device according to claim 4, wherein The first thickness is not less than seven angstroms greater than the second thickness.

6. The device according to claim 4, wherein The second thickness is not less than 75 angstroms and not more than 100 angstroms.

7. The device according to claim 1, wherein The first of the semiconductor structures has a first source-to-drain length, and the second of the semiconductor structures has a second source-to-drain length, and wherein the second source-to-drain length is greater than the first source-to-drain length.

8. The device according to claim 7, wherein The second source-to-drain length is no less than 10% greater than the first source-to-drain length, and the first thickness is no less than five angstroms greater than the second thickness.

9. The device according to claim 8, wherein The second one of the semiconductor structures is a bottommost semiconductor structure of a stack of semiconductor structures, and the first one of the semiconductor structures is a topmost semiconductor structure of the stack of semiconductor structures.

10. The device according to claim 9, wherein A third semiconductor structure in the semiconductor structure has a third source-to-drain length and a third thickness, wherein the second source-to-drain length is not less than 10% greater than the third source-to-drain length, and the second thickness is not less than three angstroms less than the third thickness, and wherein the third semiconductor structure in the semiconductor structure is immediately below the first semiconductor structure in the semiconductor structure.

11. The device according to any one of claims 1 to 10, wherein Each of the semiconductor structures comprises silicon, and wherein the source and the drain are epitaxial to the semiconductor structure.

12. The device according to any one of claims 1 to 10, further comprising: an integrated circuit (IC) die, the integrated circuit (IC) die comprising the source, the drain, the stack of semiconductor structures, and the gate structure; as well as A power supply is coupled to the IC die.

13. An apparatus comprising: Source and drain structures; a stack of semiconductor structures, the stack of semiconductor structures being vertically aligned and extending between an interface with the source structure and an interface with the drain structure, a first semiconductor structure of the semiconductor structures having a first source-to-drain length that is not less than 10% greater than a second source-to-drain length of a second semiconductor structure of the semiconductor structures, wherein the first semiconductor structure of the semiconductor structures has a first thickness that is not less than five angstroms greater than a second thickness of the second semiconductor structure of the semiconductor structures; as well as A gate structure is adjacent to the stack of semiconductor structures.

14. The device according to claim 13, wherein The first semiconductor structure in the semiconductor structures is a bottommost semiconductor structure of a stack of semiconductor structures.

15. The device according to claim 14, wherein The first thickness is not less than seven angstroms greater than the second thickness.

16. The device according to claim 14, wherein The second thickness is not less than 75 angstroms and not more than 100 angstroms.

17. The device according to claim 13, wherein The first of the semiconductor structures is above the second of the semiconductor structures in the stack of semiconductor structures.

18. The device according to claim 17, wherein The second one of the semiconductor structures is a bottommost semiconductor structure of a stack of semiconductor structures, and the first one of the semiconductor structures is a topmost semiconductor structure of the stack of semiconductor structures.

19. The device according to claim 17, wherein A third semiconductor structure in the semiconductor structure has a third source-to-drain length and a third thickness, wherein the second source-to-drain length is not less than 10% greater than the third source-to-drain length, and the second thickness is not less than three angstroms less than the third thickness, and wherein the third semiconductor structure in the semiconductor structure is immediately below the first semiconductor structure in the semiconductor structure.

20. The apparatus according to any one of claims 13 to 19, further comprising: an integrated circuit (IC) die, the integrated circuit (IC) die comprising the source structure, the drain structure, a stack of the semiconductor structure, and a stack of the gate structure; as well as A power supply is coupled to the IC die.

21. A method comprising: receiving a multilayer stack comprising a plurality of semiconductor material layers interleaved with a plurality of sacrificial layers, wherein a first semiconductor material layer of the semiconductor material layers has a first thickness that is not less than five angstroms greater than a second thickness of a second semiconductor material layer of the semiconductor material layers; etching the multilayer stack to form a fin structure; growing a source structure and a drain structure from the semiconductor material layers of the fin structure, wherein the first one of the semiconductor material layers has a first source-to-drain length that is greater than a second source-to-drain length of a second one of the semiconductor material layers; and The sacrificial layer is replaced with a gate structure coupled to the layer of semiconductor material.

22. The method according to claim 21, wherein The first semiconductor material layer among the semiconductor material layers is the bottommost semiconductor material layer among the semiconductor material layers, and wherein the first thickness is not less than seven angstroms greater than the second thickness.

23. The method according to claim 22, wherein The first source-to-drain length is no less than 20% greater than the second source-to-drain length.

24. The method according to claim 21, wherein The first one of the semiconductor material layers is above the second one of the semiconductor material layers.

25. The method according to claim 24, wherein The second one of the semiconductor material layers is the bottommost semiconductor material layer of the stack of semiconductor material layers, and the first one of the semiconductor material layers is the topmost semiconductor material layer of the stack of semiconductor material layers.

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