Etch stop architecture for power devices and passive components

Abstract

The invention relates to an etch stop architecture for power devices and passive components. A semiconductor device includes: a semiconductor substrate (310 and / or 320); a source electrode (334), a gate electrode (332), and a drain electrode (336) on the semiconductor substrate; a step dielectric structure on the semiconductor substrate and laterally between the gate electrode and the drain electrode; and a metal layer (370) on the step dielectric structure. The step dielectric structure comprises: a first dielectric layer (330 and / or 340) on the semiconductor substrate; a first etch stop layer (342) on the first dielectric layer; and a second dielectric layer (350) on the first etch stop layer, where the first dielectric layer has a first lateral dimension greater than a second lateral dimension of the second dielectric layer. The metal layer includes a first field plate (372) on at least a first region of the first dielectric layer and a second field plate (374) on at least a second region of the second dielectric layer.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductors, and more particularly, to etch stop architectures for power devices and passive components. Background Art

[0002] A high electron mobility transistor (HEMT) may include a heterojunction formed using different semiconductor materials. A channel may be formed near the heterojunction and between source and drain regions. The channel can be switched on or off by applying an appropriate voltage level to the gate structure. Gallium nitride (GaN)-based HEMT devices can exhibit high breakdown electric fields, high electron mobility, low resistance, high current, faster switching speeds, high thermal conductivity, and excellent reverse recovery performance. Therefore, they are suitable for applications requiring low loss and high efficiency, such as power electronics and radio frequency (RF) circuits. Summary of the Invention

[0003] This Summary is provided to introduce examples of the disclosed concepts in a simplified form that are further described below in the Detailed Description including the provided drawings.

[0004] According to certain aspects, a semiconductor device may include: a semiconductor substrate; a source electrode, a gate electrode, and a drain electrode on the semiconductor substrate; a stepped dielectric structure on the semiconductor substrate and laterally between the gate electrode and the drain electrode; and a metal layer on the stepped dielectric structure. The stepped dielectric structure includes: a first dielectric layer on the semiconductor substrate; a first etch stop layer on the first dielectric layer; and a second dielectric layer on the first etch stop layer, wherein the first dielectric layer has a first lateral dimension that is greater than a second lateral dimension of the second dielectric layer. The metal layer includes a first field plate on at least a first region of the first dielectric layer and a second field plate on at least a second region of the second dielectric layer.

[0005] According to certain aspects, a method may include: depositing a first dielectric layer on a semiconductor device, the semiconductor device including a channel layer and a barrier layer; depositing a first etch stop layer on the first dielectric layer; depositing a second dielectric layer on the first etch stop layer; etching selected areas of the second dielectric layer using the first etch stop layer as an etch stop, the etched second dielectric layer and the first dielectric layer forming a stepped dielectric structure; and depositing a metal layer on the stepped dielectric structure to form a plurality of field plates on the stepped dielectric structure.

[0006] The foregoing summary has generally outlined various features of the examples of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of the examples will be described below. The described examples may be readily used as a basis for modifying or designing other examples within the scope of the appended claims.

[0007] This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used alone to determine the scope of the claimed subject matter. The subject matter should be understood by reference to appropriate portions of the entire specification of this disclosure, any or all of the figures, and each claim. The foregoing, as well as other features and examples, are described in more detail below in the following description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Illustrative examples are described in detail below with reference to the following figures.

[0009] Figure 1A is a schematic diagram illustrating a cross-sectional view of an example of an enhancement mode high electron mobility transistor (HEMT).

[0010] Figure 1B Includes illustration of using multiple field plate modulation Figure 1A Schematic diagram and graph of examples of the electric field in the channel layer of a HEMT.

[0011] Figure 2 is a schematic diagram illustrating a cross-sectional view of an example of a HEMT including multiple field plates.

[0012] Figure 3 FIG2 is a schematic diagram illustrating an example of a HEMT including multiple field plates formed using an etch stop layer.

[0013] Figure 4A 、 4B , 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, and 4L are schematic diagrams illustrating an example of a process of fabricating a HEMT including multiple field plates using an etch stop layer.

[0014] Figure 5A 、 5B , 5C, 5D, 5E, 5F, 5G, and 5H are schematic diagrams illustrating an example of a process of fabricating a HEMT including multiple field plates using an etch stop layer.

[0015] Figure 6 FIG. 1 is a schematic diagram illustrating an example of a HEMT including multiple field plates and a charged etch stop layer.

[0016] Figure 7A is a schematic diagram illustrating an example of a HEMT including one or more tilted field plates.

[0017] Figure 7B Includes illustration of field plate modulation Figure 7A Schematic diagram and graph of examples of the electric field in the channel layer of a HEMT.

[0018] Figure 8A 、 8B 8C are schematic diagrams illustrating examples of capacitors integrated with HEMTs in semiconductor devices.

[0019] Figure 9A and 9B FIG2 is a schematic diagram illustrating an example of a planar inductor formed using the techniques disclosed herein.

[0020] Figure 10 Included is a flow chart illustrating an example of a process for fabricating a HEMT including multiple field plates using one or more etch stop layers.

[0021] The drawings and the accompanying detailed description are provided for understanding the features of the various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description can be easily used as the basis for modifying or designing other examples within the scope of the appended claims. Those skilled in the art will readily appreciate from the following description that alternative embodiments of the illustrated structures and methods can be adopted without departing from the principles of the present disclosure or the benefits of the claims. Where possible, the same reference numerals can be used to refer to the same elements that are common in the drawings. Drawings are used to clearly illustrate related elements or features, and the drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0022] The present disclosure generally relates to semiconductor devices and their fabrication. In some examples, the semiconductor device includes a gallium nitride (GaN)-based high electron mobility transistor (HEMT) having multiple field plates fabricated using an etch stop layer. The multiple field plates can reduce the peak electric field in the HEMT's channel and, therefore, can improve the off-state breakdown voltage and reduce the dynamic on-state resistance (or current collapse) during high-voltage switching. One or more etch stop layers can be used to achieve precise control and uniformity of the thickness of the interlayer dielectric (and, therefore, the field plate height above the channel). In some examples, in addition to using the field plate length and height to control the electric field in the channel layer, charge can be introduced onto the etch stop layer to modify the electron density and electric field in the channel layer, thereby modifying the breakdown voltage and dynamic on-state resistance of the HEMT during high-voltage switching. In some examples, passive components (such as capacitors and inductors with controlled and reproducible dielectric thickness) can be integrated with the semiconductor device using the fabrication techniques disclosed herein. Other benefits and advantages may also be achieved, such as low process variation, higher yield, high device performance uniformity, etc.

[0023] GaN-based HEMTs may include a heterojunction formed by a channel layer (e.g., a GaN layer) and a barrier layer (e.g., an aluminum gallium nitride (AlGaN) layer). A high-density two-dimensional electron gas (2DEG) may be used to form a conductive channel at the heterojunction. For example, the 2DEG may have a density greater than about 10 13 cm -2 GaN-based HEMTs are attractive for high-frequency and high-power applications due to their high breakdown electric field, high electron mobility, low static resistance, and high thermal conductivity. In many applications, it may be desirable to use a HEMT with a high breakdown voltage and / or low dynamic on-state resistance (or current collapse) during high-voltage switching operations.

[0024] When a HEMT is in the off state and has a high drain-to-source voltage, high electric fields in the HEMT's channel layer (e.g., beneath the gate, drain contact, and / or field plate) can cause current collapse and even breakdown of the HEMT. A field plate (FP) can be used in a HEMT to manage the electric field distribution between the source and drain in the off state, thereby increasing the off-state breakdown voltage and reducing the dynamic on-state resistance (or current collapse) during high-voltage switching operations. The FP and the region of the HEMT below the FP can form a field-plate transistor with different threshold voltages (e.g., different negative pinch-off voltages for turning off the field-plate transistor), where the FP can be the gate electrode of the field-plate transistor. The FP can be connected to different voltage levels (e.g., a source bias voltage, a gate bias voltage, or another bias voltage level) so that the FP can turn off the field-plate transistor at different regions under different bias conditions, thereby modifying the electric field at different regions of the channel layer. For example, when a HEMT is in the off state and has a high drain voltage, a field plate atop the drain side of the HEMT's channel (e.g., the drain access region) and connected to the HEMT's source can disconnect the corresponding field plate transistor and, therefore, the conductive channel beneath the field plate. Accordingly, the length of the channel layer's depletion region, which maintains the voltage drop and electric field, can be increased, and thus, the peak electric field in the channel layer for a given drain voltage can be reduced. By adjusting the length and height of the field plate, the pinch-off voltage of the field plate transistor can be adjusted, and the electric field distribution between the drain and gate of the HEMT can be made more uniform, thereby reducing the peak electric field in the channel layer at high drain voltages. This reduction in the peak electric field on the gate-to-drain side of the HEMT can result in a higher off-state breakdown voltage.

[0025] The reduction in peak electric field in the channel of a HEMT using FP can also reduce hot carrier degradation and dynamic on-state resistance (or current collapse) caused by high electric field trapping effects. For example, when a lateral HEMT device is in the off-state with a high drain bias, the large negative gate-to-drain bias and, therefore, the high electric field can produce electron injection and trapping at regions such as the heterojunction interface and the surface of the barrier layer. Additionally, when the HEMT device is operated at high voltages (e.g., several hundred volts), hard switching can produce hot electrons in the channel, which can be injected and trapped, for example, in the dielectric, at the surface, in the GaN channel, and / or in the buffer layer. The trapped negative charge can at least partially deplete the channel of carriers (e.g., electrons), thereby causing a reduction in the channel carrier density and, therefore, an increase in the channel resistance and a decrease in the current (I) between the drain and source. DS ) reduction. When a HEMT device is turned on, it may take a certain amount of time for electrons to be released from surface states and buffer traps, allowing the drain-to-source resistance to gradually decrease and eventually stabilize at the static on-state resistance. Reducing the peak electric field in the HEMT channel can reduce electron injection and trapping, thereby reducing the dynamic on-state resistance (or current collapse).

[0026] Some field plate arrangements (e.g., source-connected field plates and / or gate-connected field plates) can also reduce gate-to-source capacitance, reduce gate-to-drain capacitance (e.g., due to reduced peak electric fields), and / or increase gate conductance. Reducing capacitance and increasing gate conductance can lead to increased device gain, bandwidth, and operating frequency. Reducing the electric field can also have other benefits, such as reducing leakage current, reducing time-dependent dielectric breakdown (TDDB) at the gate, and improving reliability.

[0027] The electric field distribution between the drain and gate of a HEMT can depend on, for example, the length and height of the field plate, as well as the properties (e.g., permittivity) and thickness of the dielectric layer beneath the field plate. Integrated passive components such as capacitors and inductors may also require reproducible and more precise control of dielectric thickness. However, achieving good uniformity and precise control of dielectric thickness for each field plate can be challenging due to process variations. For example, field plates may be fabricated using multiple cycles of dielectric and metal deposition and etching, where the etching may have low selectivity between the etched metal and the interlayer dielectric (ILD) layer beneath the metal layer. Consequently, an overetch (e.g., 30% to 50%) may be performed to ensure complete metal removal outside the FP region. When performing the overetch, controlling the field plate height can be difficult due to process variations, and the thickness of the ILD layer can vary significantly. Consequently, variations in the FP height, and therefore the pinch-off voltage of the field plate transistor, can be large, which can adversely affect HEMT performance, such as breakdown voltage, off-state leakage, gate-to-drain capacitance, and dynamic on-state resistance (or current collapse). Yield and device performance uniformity across and between wafers may also be low.

[0028] In some examples disclosed herein, a semiconductor device may include a field plate structure formed on a stepped dielectric structure fabricated using an etch stop layer to more precisely control the thickness of the interlayer dielectric (ILD) layer. Consequently, the semiconductor device may have a well-controlled thickness of the ILD layer between the field plate and the channel layer, and thus may have a well-controlled field plate height, a well-controlled pinch-off voltage of the field plate transistor, and well-controlled channel electric field modulation and dynamic on-state resistance. In some examples, the etch stop layer may be charged, where the charge density (or charge amount) may be controlled to tune the electric field and electron density of the channel layer, the pinch-off voltage of the field plate transistor and / or HEMT, and the static on-state resistance and dynamic on-state resistance of the HEMT. Integrated planar inductors and capacitors may also be formed in semiconductor devices using the fabrication processes and stepped dielectric structures disclosed herein.

[0029] In one example, a semiconductor device may include a source electrode, a gate electrode, and a drain electrode on a semiconductor substrate. The semiconductor device may also include a stepped dielectric structure on the semiconductor substrate and laterally between the gate electrode and the drain electrode, and a metal layer on the stepped dielectric structure. The steps may have steps with upright sidewalls or inclined sidewalls. The stepped dielectric structure may include at least a first dielectric layer on the semiconductor substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The first dielectric layer below the second dielectric layer may have a first lateral dimension greater than a second lateral dimension of the second dielectric layer, such that the at least two dielectric layers form a stepped dielectric structure. The metal layer may form a field plate structure comprising at least a first field plate on at least a first region of the first dielectric layer of the stepped dielectric structure and a second field plate on at least a second region of the second dielectric layer. The first region of the first dielectric layer may have a first uniform thickness, and the second region of the second dielectric layer may also have a second uniform thickness, so that the field plate transistors below the first and second field plates have different respective pinch-off voltages. In some examples, the first etch stop layer may include charge stored in or on the first etch stop layer for tuning the electric field and electron density in the channel of the semiconductor device. In some examples, the sidewalls of the second dielectric layer in the stepped dielectric structure may be sloped, so that the field plate structure may also include a sloped field plate between the first and second field plates. These arrangements can further reduce the peak electric field in the channel layer and further increase the breakdown voltage of the semiconductor device.

[0030] The techniques disclosed herein can achieve controlled thickness of the ILD layer and controlled height of the field plates, thereby improving the yield and performance uniformity of semiconductor devices with high breakdown voltages, such as GaN-based HEMTs. The techniques disclosed herein can be used to fabricate multiple field plates with controlled heights and no gaps between them, thereby reducing the peak electric field in the channel, reducing dynamic on-state resistance, and increasing breakdown voltage. In one example, a stepped dielectric structure can be fabricated with many steps of small step heights to approximate a tilted structure, which allows a large number of small field plates to be formed on the stepped dielectric structure to approximate a tilted field plate. The etch stop layer used to control the thickness of the ILD layer can also store charge, where the charge density (or total stored charge) can be another parameter used to control the electric field, pinch-off voltage, and on-state resistance. During the process of fabricating the field plates, the ILD layer with uniform thickness can also be used to form other active or passive devices.

[0031] Various features will be described below with reference to the drawings. The illustrated examples may not have all aspects or advantages shown. An aspect or advantage described in conjunction with a particular example is not necessarily limited to that example and may be practiced in any other example, even if not so described or explicitly described. In addition, the methods described herein may be described with a particular order of operations, but other methods according to other examples may be implemented with various other orders having more or fewer operations (e.g., including different serial or parallel execution of various operations).

[0032] Various examples are described herein. Although specific examples may illustrate various aspects of the features generally described above, examples may incorporate any combination of the features generally described above (which are described in more detail in the examples below). For ease of reference, three-dimensional xyz axes are depicted in some figures. Some cross-sectional views of various semiconductor devices herein may be general depictions illustrating various aspects or concepts related to these semiconductor devices. More specifically, except to the extent described herein, some drain contact structures depicted in the cross-sectional views may not necessarily accurately depict the structures of these drain contact contacts. The illustrations of these drain contact structures are intended to illustrate various aspects or concepts related to those drain contact structures.

[0033] Various examples are described in the context of HEMTs. Some examples may be implemented in enhancement-mode lateral HEMTs for high-voltage (e.g., approximately 650 V to approximately 1,200 V) applications or low- to medium-voltage (e.g., approximately 10 V to approximately 100 V, or approximately 10 V to approximately 200 V) applications. In other examples, the semiconductor device may include a bidirectional field-effect transistor (FET), a gate-controlled Schottky barrier diode (e.g., a gate-to-drain shorting structure or a gate-to-source shorting structure), or the like. Some examples may be implemented using any epitaxial structure, any field plate and / or ohmic contact structure, a planar or three-dimensional structure (e.g., a fin structure), and / or various other modifications.

[0034] For illustrative purposes, some of the examples disclosed herein may focus on III-nitride-based devices, such as GaN-based HEMTs. However, the present disclosure is not limited to GaN-based HEMTs and may be applied to other devices including heterostructures formed from other semiconductor materials (e.g., other III-nitride or other III-V semiconductor materials), where the heterostructures can induce a two-dimensional electron gas (2DEG) at the heterojunction interface.

[0035] GaN-based HEMTs may include a heterostructure that induces 2DEG at the interface between two GaN-based materials with different band gaps. In one example, the heterostructure may consist of a GaN layer and an Al x Ga (1-x)N layer is formed, where x is the concentration of aluminum. The GaN layer has a higher concentration than Al x Ga (1-x) The N layer has a narrower band gap, and the Al x Ga (1-x) N can act as a barrier layer due to its wider bandgap. Due to the bandgap mismatch, large conduction band offset, and spontaneous polarization and piezoelectric polarization characteristics of the III-nitride layer, a high-mobility 2DEG can be generated in the GaN layer (with a narrower bandgap) near the heterostructure interface to form a conductive channel in the GaN layer (which is called a channel layer). Compared to silicon-based transistors, GaN-based transistor devices can have a high breakdown electric field, high electron mobility, low resistance, high current, faster switching speed, high thermal conductivity, and excellent reverse recovery performance, and are therefore suitable for applications that may require low loss and high efficiency performance, such as power electronics or radio frequency (RF) circuits.

[0036] A GaN-based transistor may include a gate structure positioned between a source structure and a drain structure. The drain structure may include a metal contact (e.g., a drain electrode) coupled to a channel layer and forming an ohmic contact with the channel layer. The source structure may include a metal contact (e.g., a source electrode) coupled to the channel layer and forming an ohmic contact with the channel layer. Depending on the architecture of the gate structure, the GaN-based transistor may be an enhancement-mode high electron mobility transistor (e-HEMT), which can be in an off-state in the absence of a positive gate voltage and can be turned on when a positive voltage is applied to the gate electrode, or a depletion-mode high electron mobility transistor (d-HEMT), which can be in an on-state in the absence of a negative gate voltage and can be turned off when a negative voltage is applied to the gate electrode.

[0037] For example, the gate structure of an e-HEMT may include a p-GaN layer formed over a barrier layer, and a gate electrical contact (e.g., a metal gate electrode) formed on the p-GaN layer, which together form a p-GaN gate structure. The p-GaN layer may be a GaN layer doped with, for example, magnesium (Mg), which acts as an acceptor, rendering the GaN layer p-type, or p-doped. The p-GaN layer can deplete electrons from the 2DEG channel beneath the p-GaN gate structure, disabling the path between the source and drain when no gate drive voltage is applied to the gate electrical contact. When a positive voltage greater than the gate threshold voltage is applied to the gate electrical contact, the gate structure can attract electrons to fill the 2DEG beneath the gate structure, thereby turning on the e-HEMT.

[0038] In contrast, the gate structure of a d-HEMT may include an insulator layer (e.g., a dielectric layer) above a blocking layer and a gate electrical contact (e.g., a metal gate electrode) on the insulator layer. In the absence of a voltage signal applied to the gate electrical contact, the 2DEG beneath the gate structure may not be depleted, and thus a path in the channel layer between the drain and source structures may be enabled in the absence of a positive gate voltage. The d-HEMT can be turned off by applying a negative voltage to the gate electrical contact to deplete electrons from the 2DEG beneath the gate structure. In some applications, such as switch-mode power applications, an e-HEMT may be used instead of a d-HEMT, for example, to reduce leakage current, lower power loss, simplify drive circuitry, and / or improve device stability.

[0039] GaN-based HEMTs can be attractive for high-frequency and high-power applications due to, for example, their high breakdown voltage, high electron mobility, low static resistance, and high thermal conductivity. However, GaN-based HEMTs can suffer from current collapse, an undesirable phenomenon in which the dynamic on-state drain-to-source resistance increases during high-voltage switching operations (e.g., when the GaN-based HEMT is turned on and off and a high voltage level is applied to the drain of the HEMT). Current collapse can lead to, for example, power loss, temperature rise, and reliability issues.

[0040] Current collapse can be caused by electron and / or hole trapping and can manifest as a transient and recoverable decrease in drain current (and an increase in effective resistance) during high-voltage switching operations. Several factors can contribute to current collapse, including electrons trapped at the surface of the barrier layer and / or in the buffer layer, as well as hot electrons trapped during high-voltage switching. For example, for a HEMT comprising an AlGaN barrier layer and a GaN channel layer, when the HEMT is in the off state and has the following voltage states: a high drain voltage (e.g., several hundred volts, such as about 600 V or higher), a gate voltage below threshold, and a grounded source voltage, high-energy electrons from the 2DEG can be injected toward the top of the AlGaN barrier layer and trapped via surface states (thereby creating a negatively charged surface) due to the high electric field caused by the large negative gate-to-drain bias. A large positive drain-to-substrate voltage can cause electrons to be injected from the substrate and trapped in the buffer stack between the channel layer and the substrate. Furthermore, in the off-state, the high electric field induced by the high drain voltage can ionize holes in the heterostructure between the gate and drain contact structure or beneath the drain contact structure. Due to the bias-induced electric field, these ionized holes can be pulled toward the gate and / or source contact structure in the off-state, which can leave a fixed negative charge in the heterostructure. When the HEMT is operated at a high drain voltage (e.g., several hundred volts), hard switching can generate hot electrons in the channel due to the high electric field. The hot electrons can be injected and trapped, for example, in the dielectric, at the surface of the barrier layer, in the channel layer, and / or in the buffer layer. The trapped and fixed negative charges in the heterostructure can at least partially deplete the 2DEG channel of carriers (e.g., electrons), causing a decrease in the channel carrier density and, therefore, an increase in resistance.

[0041] When the HEMT is turned on (e.g., when the gate voltage is above the threshold voltage in an e-HEMT), the dynamic on-state drain-to-source resistance may initially be higher compared to the static on-state drain-to-source resistance due to negative charge depletion of carriers, resulting in a lower channel carrier density. As trapped electrons and fixed negative charges gain energy to escape the well, they may gradually de-trapped and / or may be gradually neutralized by holes injected from the drain. The remaining negative charge may continue to deplete the 2DEG, causing the drain-to-source resistance to slowly decrease.

[0042] When the HEMT is in the off state, if the drain is biased at a relatively low voltage, the electric field in the channel layer can be low, except in the region near the gate structure where the 2DEG is depleted and the channel is disconnected. At high drain biases, the electric field in the channel (e.g., at the edge of the gate region) can exceed the threshold field for impact ionization, thereby generating hot carriers that can degrade the performance of the HEMT. When the electric field in the channel is high enough, these high-energy carriers can cause current collapse and even physical failure and permanent damage, such as breakdown of the HEMT.

[0043] To reduce current collapse and increase breakdown voltage, a HEMT may include one or more metal field plates on top of the dielectric layer above the drain access region. The one or more metal field plates may be connected to, for example, the gate, source, or another bias voltage level, and thus may be biased to deplete the underlying channel layer when the HEMT is in the off state. In this way, under similar drain bias conditions, the channel area that sustains the electric field and voltage drop may be increased in a HEMT with one or more field plates, and thus the channel layer peak electric field in the channel layer of the HEMT may be reduced. As a result, the HEMT may maintain a higher drain voltage and a higher voltage difference (V ) between the drain and source before the peak electric field in the channel layer reaches the threshold field to cause permanent damage to the HEMT. DS At a given drain bias, the electric field distribution in the channel layer of a HEMT can depend on the length and height of each field plate. As the length of the field plate increases, the channel area that sustains the electric field and voltage drop can increase, and the peak electric field in the channel layer can decrease. The magnitude of the peak electric field in the channel layer can also be varied by changing the field plate height (e.g., by varying the dielectric thickness). Therefore, a desired electric field distribution in the channel layer can be achieved by selecting an appropriate length and height for each of one or more field plates.

[0044] Figure 1A 1 is a cross-sectional view of an example of a HEMT 100. In the example shown, the HEMT 100 is an enhancement-mode HEMT and includes a substrate 105, a channel layer 110 (e.g., including a GaN layer) grown on the substrate 105, a barrier layer 120 (e.g., including an AlGaN layer) above the channel layer 110, and drain, source, and gate structures. The drain, source, and gate structures may be electrically isolated by one or more dielectric layers 160. The gate structure is between the drain and source structures and may be closer to the source structure (e.g., to achieve a high breakdown voltage). In some examples, Figure 1A The HEMT 100 shown in FIG. 1 may be a half-pitch HEMT device including the HEMT 100 and a mirrored version of the HEMT 100 that shares a drain structure with the HEMT 100 .

[0045] The substrate 105 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or another suitable substrate (e.g., a Qromis Substrate Technology (QST) substrate, a sapphire substrate, or another silicon-based substrate). In one example, the substrate 105 may include a bulk silicon wafer and one or more transition layers or buffer layers of a suitable material for accommodating the lattice mismatch between the substrate 105 and the channel layer 110 (e.g., to reduce or minimize the generation and / or propagation of lattice defects in the channel layer 110). For example, the transition layer or buffer layer may have a gradient concentration of one or more elements in a direction normal to the surface of the substrate 105 (e.g., the z-direction) to gradually change the lattice constant.

[0046] The channel layer 110 and the barrier layer 120 may be epitaxially grown on the upper substrate 105. Due to the different band structures of the channel layer 110 and the barrier layer 120, a heterostructure may be formed therefrom. The heterostructure may induce a 2DEG 112 near the interface between the channel layer 110 and the barrier layer 120. The 2DEG 112 may conduct current in a two-dimensional plane (e.g., the xy plane). In some examples, the channel layer 110 may be part of the substrate 105. In the illustrated example, the channel layer 110 comprises a GaN layer. The channel layer 110 may comprise an intrinsic material, or a material that has been unintentionally doped, such as by diffusion of dopants from another layer. In the illustrated example, the barrier layer 120 comprises an AlGaN layer, which has a wider bandgap than GaN. Other materials may also be used for the channel layer 110 and the barrier layer 120. For example, the channel layer 110 may include InAlGaN (In i Al j Ga 1-i-j N) (where 0≤i≤1, 0≤j≤1, and 0≤i+j≤1), and the barrier layer 120 may include indium aluminum gallium nitride (InGaN). k Al l Ga 1-k-l N)(where 0≤k≤1, 0≤l≤1, and 0≤k+l≤1).

[0047] The gate structure of the HEMT 100 may include a gate semiconductor layer 130 above the upper surface of the barrier layer 120. In some examples, the gate semiconductor layer 130 may include a p-doped semiconductor layer. For example, the gate semiconductor layer 130 may include a GaN layer, or more generally, an In m Al n Ga 1-m-nN layer (where 0≤m<1, 0≤n<1, and 0≤m+n≤1). The p-type dopant used to dope the gate semiconductor layer 130 may include, for example, magnesium (Mg), carbon (C), zinc (Zn), etc., or a combination thereof. In some examples, the concentration of the electrically activated dopant in the gate semiconductor layer 130 may be equal to or greater than about 1×10 17 cm -3 In some examples, the concentration may be equal to or greater than about 1×10 18 cm -3 Other materials, dopants, and / or concentrations may be used in other examples. The gate semiconductor layer 130 may be formed by epitaxial growth and selective etching using an etch mask, or may be formed by selective area growth using a growth mask. The etch mask or growth mask may define the shape and size of the gate semiconductor layer 130. The doping density and thickness of the p-doped gate semiconductor layer 130 and the thickness of the barrier layer 120 below the gate semiconductor layer 130 may be selected so that the p-doped gate semiconductor layer 130 can deplete the 2DEG 112 below the gate semiconductor layer 130, so that the HEMT 100 is turned off in the absence of a positive gate voltage and can be turned on by applying a positive voltage to the gate structure.

[0048] A gate electrical contact 132 (e.g., a gate electrode) may be formed on the gate semiconductor layer 130 to apply a gate voltage to the gate semiconductor layer 130. The gate electrical contact 132 may be electrically connected to a gate drive circuit via electrical interconnects, such as conductive traces and / or vias (not shown). In the illustrated example, the gate electrical contact 132 may extend laterally beyond the gate semiconductor layer 130 to form a field plate 134. The field plate 134 may be used in high-voltage and low-voltage GaN power devices to, for example, reduce current collapse and dynamic on-state resistance and increase breakdown voltage. The gate electrical contact 132 may include one or more metals and / or metal alloy materials with high conductivity. Depending on the metal work function of the gate electrical contact 132 and the band structure of the gate semiconductor layer 130, the metal-to-semiconductor contact between the gate electrical contact 132 and the gate semiconductor layer 130 may be, for example, an ohmic contact or a Schottky contact with a high or low barrier height. The Schottky contact between the gate electrical contact 132 and the gate semiconductor layer 130 can reduce gate leakage.

[0049] At the source region of HEMT 100, a source electrical contact 140 (e.g., a source electrode) may extend through barrier layer 120 and contact the source region of channel layer 110. In some examples, source electrical contact 140 may not extend into barrier layer 120 and / or channel layer 110, and carriers may tunnel from channel layer 110 through barrier layer 120. In some examples, source electrical contact 140 may be regrown. Source electrical contact 140 may comprise a metal or metal alloy and may form a low-barrier metal-to-semiconductor contact (e.g., an ohmic contact) with channel layer 110. One or more field plates 142 and 144 may be formed in one or more dielectric layers 160 and may be coupled to source electrical contact 140 or another voltage bias circuit (e.g., a voltage source). Field plates 142 and 144 may be used to reduce current collapse and dynamic on-state resistance, and / or increase the breakdown voltage of HEMT 100.

[0050] Figure 1A An example is shown in which field plate 134 is connected to gate electrical contact 132 and field plates 142 and 144 are connected to source electrical contacts. Figure 1A In other examples not shown in FIG, the field plates may be biased differently in different examples. In one example, all field plates may be connected to the source electrical contact 140. Field plate 134 and field plates 142 and 144 may include a metal or metal alloy, such as titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), titanium tungsten aluminum (TiWAl), titanium aluminum nitride (TiAlN), or combinations thereof.

[0051] At the drain region of HEMT 100, drain electrical contact 150 (e.g., drain electrode) may extend through dielectric layer 160 and barrier layer 120 and may contact the drain region of channel layer 110. In some examples, drain electrical contact 150 may not extend into barrier layer 120 and / or channel layer 110, and carriers may tunnel through barrier layer 120. In some examples, drain electrical contact 150 may be regrown. Drain electrical contact 150 may include a metal or a metal alloy and may form a low-barrier metal-to-semiconductor contact (e.g., an ohmic contact) with channel layer 110. As described above, in some examples, Figure 1A The HEMT 100 shown in FIG. 1 may be a half-pitch HEMT device including the HEMT 100 and a mirrored version of the HEMT 100 that shares a drain electrical contact 150 with the HEMT 100 .

[0052] The one or more dielectric layers 160 may include one or more dielectric materials that isolate and protect the gate structure, drain structure, and source structure. The one or more dielectric layers 160 may include multiple dielectric layers of the same dielectric material or different dielectric materials deposited in one or more deposition processes. For example, the dielectric layer 160 may include an oxide-based material or a nitride-based material, such as silicon oxide (e.g., phosphosilicate glass (PSG)), aluminum oxide, silicon nitride, silicon oxynitride (SiON), etc. In some examples, the dielectric layer 160 may further include one or more etch stop layers, such as silicon nitride (SiN), aluminum oxide, etc., for controlling the etch depth of the etching process (e.g., for patterning the dielectric layer or metal layer).

[0053] In some examples, the electrical contacts or other metal electrical interconnects described above may each include one or more adhesion layers (e.g., Ti) and / or one or more metal barrier layers (e.g., TiN, TaN, etc.) between a metal material (e.g., Al, Cu, W, etc., or a combination thereof) and one or more dielectric materials of the one or more dielectric layers 160. The one or more metal barrier layers may prevent metal atoms from diffusing into the dielectric layer 160. The one or more adhesion layers may be used to improve adhesion of the metal material to the one or more dielectric materials of the dielectric layer 160 to reduce or avoid defects and reliability issues, such as interface delamination.

[0054] Figure 1B Shows the use of multiple field plates for modulation Figure 1A 1. An example of an electric field in the channel layer of HEMT 100. As shown, HEMT 100 may include a core transistor 102 at a gate region that can be turned off when the bias voltage at the gate is below the gate threshold voltage. HEMT 100 may also include multiple field plate transistors in a region below the field plate. For example, a first field plate transistor 162 may be formed below field plate 134, a second field plate transistor 164 may be formed below field plate 142, and a third field plate transistor 166 may be formed below field plate 144. The field plates may serve as gates for the field plate transistors. The threshold voltages (e.g., pinch-off voltages) of first field plate transistor 162, second field plate transistor 164, and third field plate transistor 166 may depend on, for example, the height of the field plate above channel layer 110 and the material of dielectric layer 160. Thus, field plates of different heights may have different threshold voltages and may be turned on or off under different bias conditions.

[0055] In one example, the field plate can be biased such that when the gate of the HEMT 100 is biased at a voltage below the threshold voltage and the drain of the HEMT 100 is biased at a relatively low voltage, the core transistor 102 can be in an off-state and the field-plate transistor can be in an on-state. Under this condition, the core transistor 102 can maintain a voltage drop between the drain and source, and thus maintain an electric field in the channel layer, while the field-plate transistor can maintain a small or no voltage drop and electric field. As a result, the electric field in the channel layer can peak at the edge of the gate of the HEMT 100 (e.g., the drain of the core transistor 102) and can decrease in a direction toward the drain region (e.g., along the x-direction).

[0056] As the bias voltage at the drain increases, the voltage level at the edge of the gate of the HEMT 100 (e.g., the drain of the core transistor 102) may increase, and thus the voltage difference between the gate (e.g., the field plate 134) and the source (e.g., the drain of the core transistor 102) of the first field plate transistor 162 may be lower than the negative pinch-off voltage of the first field plate transistor 162. Therefore, the first field plate transistor 162 may also be turned off to maintain the voltage drop and electric field between the drain and source of the first field plate transistor 162. The electric field in the channel layer under this condition may have another peak at the edge of the field plate 134 and may gradually decrease along the x-direction.

[0057] As the bias voltage at the drain further increases, the voltage level at the edge of the field plate 134 (e.g., the drain of the first field plate transistor 162) may increase, and thus the voltage difference between the gate (e.g., the field plate 142) and the source (e.g., the drain of the first field plate transistor 162) of the second field plate transistor 164 may fall below the negative pinch-off voltage of the second field plate transistor 164. Therefore, the second field plate transistor 164 may be further turned off to maintain the voltage difference and corresponding electric field between the drain and source of the second field plate transistor 164. The electric field in the channel layer under this condition may have another peak at the edge of the field plate 142 (e.g., the drain of the second field plate transistor 164) and may gradually decrease along the x-direction.

[0058] As the bias voltage at the drain increases further, the voltage level at the edge of field plate 142 may increase, and thus the voltage difference between the gate (e.g., field plate 144) and source (e.g., drain of second field plate transistor 164) of third field plate transistor 166 may become lower than the negative pinch-off voltage of third field plate transistor 166. Therefore, third field plate transistor 166 may also be turned off to maintain the voltage difference and corresponding electric field between the drain and source of third field plate transistor 166. The electric field in the channel layer under this condition may have another peak at the edge of field plate 144 and may gradually decrease along the x-direction. In this way, the channel layer may be able to maintain a large total voltage drop between the drain and source before the peak electric field in the channel layer reaches a threshold, causing impact ionization, hot carrier generation, current collapse, and breakdown of HEMT 100.

[0059] like Figure 1B As shown in FIG, when a field plate (e.g., field plate 142) is above the region between the gate and the source, a fourth field plate transistor 168 may also be formed below the field plate 142. The fourth field plate transistor 168 is further capable of maintaining the voltage drop and electric field between the drain and source of the HEMT 100 when the HEMT 100 is in the off state, thereby further increasing the breakdown voltage of the HEMT 100.

[0060] Figure 1B Graph 170 in FIG. 1 shows an example of the distribution of the electric field in the channel layer of the HEMT 100 when the HEMT 100 is in the off state and the drain voltage is high. Figure 1B In the example shown in graph 170 of FIG. 1 , there may be discontinuities between the three field plates in the drain access region, and thus there may also be gaps in the pinch-off voltage. The electric field in the channel layer of HEMT 100 may have a first peak 172 near the edge of the gate of HEMT 100 (e.g., the edge of gate semiconductor layer 130), a second peak 174 near the edge of field plate 134, a third peak 176 near the edge of field plate 142, and a fourth peak 178 near the edge of field plate 144. The total area under graph 170 may represent the voltage difference (V between the drain and source of HEMT 100). DS Without the field plates 134, 142, and 144, most of the voltage difference (V DS ) can be maintained by the core transistor 102, and the peak electric field can be at the edge of the gate of the HEMT 100 (eg, the edge of the gate semiconductor layer 130), and can be at V DS When the field plates 134, 142 and 144 are provided, the voltage difference between the drain and the source (V DS) can be maintained by the core transistor 102 and the field plate transistors 162, 164, and 166, and thus the peak electric field can be significantly reduced under the same bias conditions. As a result, the current collapse can be reduced and the breakdown voltage in the HEMT 100 can be increased.

[0061] As described above, the electric field in the channel layer can be tuned by varying, for example, the length and height of the field plate. Thus, a desired electric field distribution in the channel layer under high drain voltage conditions can be achieved by selecting the appropriate length and height of the field plate. Field plates can be used to reduce peak electric fields in both e-HEMTs and d-HEMTs. Some field plate arrangements, such as source-connected field plates and / or gate-connected field plates, can reduce gate-to-source capacitance, reduce gate-to-drain capacitance (e.g., due to reduced peak electric field in the drain access region), and / or increase gate conductance. Reducing capacitance and increasing gate conductance can result in increased device gain, bandwidth, and operating frequency. Reducing the electric field can also have other benefits, such as reducing leakage current, reducing time-dependent dielectric breakdown (TDDB) at the gate, and improving reliability.

[0062] Figure 2 2 is a cross-sectional view of an example of a HEMT 200 including multiple source-connected field plates. The HEMT 200 may be an example of an implementation of the HEMT 100 and may be an e-HEMT or a d-HEMT. In the illustrated example, the HEMT 200 may include a substrate 210, an epitaxial layer 220 grown on the substrate 210, and a gate structure 232, a source structure 234, and a drain structure 236 formed on the epitaxial layer 220. Multiple dielectric layers may be deposited and patterned, and multiple metal layers may be formed on the respective dielectric layers and patterned to form multiple field plates. The dielectric layers may include, for example, SiO2, SiN x Or Al2O3 layer. The metal layer may include, for example, Cu, Al, W, Ti, Au, Ni, Pt, TiW, TiN, TaN, TiWAl, TiAlN or a combination thereof. Figure 2 In the example shown in , the field plate can be connected to the source electrical contact. In other examples, the field plate can be connected to the gate electrical contact, the source electrical contact, other voltage sources, or a combination thereof.

[0063] Substrate 210 may be similar to substrate 105 of HEMT 100. Epitaxial layer 220 may include, for example, a channel layer and a barrier layer, such as channel layer 110 and barrier layer 120. Gate structure 232 may include a gate electrical contact and a semiconductor layer (e.g., a p-doped GaN layer) or a dielectric layer. A first dielectric layer 230 may be formed on epitaxial layer 220 and patterned to define gate, source, and drain regions. Metal or metal alloy material may be deposited in the gate, source, and drain regions to form gate, source, and drain electrical contacts.

[0064] A second dielectric layer 240 may be deposited over the first dielectric layer 230, the gate electrical contact, the source electrical contact, and the drain electrical contact. In some examples, the second dielectric layer 240 may be etched at the source and drain regions to expose the source and drain electrical contacts. A first metal layer 242 may then be formed (e.g., by sputtering) over the second dielectric layer 240. Regions of the first metal layer 242 between the gate and drain regions may be removed by etching. To completely remove the metal material in these regions, the first metal layer 242 may be overetched (e.g., by approximately 30% to 50%) down to the underlying second dielectric layer 240. Due to process variations, the amount of overetching may vary across the wafer and may also vary from wafer to wafer or batch to batch. Consequently, the thickness of the remaining second dielectric layer 240 may vary across the wafer and may also vary from wafer to wafer or batch to batch. A portion 244 of the first metal layer 242 may remain in the region between the gate and drain and may serve as a first field plate.

[0065] A third dielectric layer 250 may then be formed on the remaining first metal layer 242 and the exposed second dielectric layer 240. In some instances, the third dielectric layer 250 may be etched at the source and drain regions to expose metal electrical contacts at the source and drain. A second metal layer 252 may then be formed on the third dielectric layer 250. Some regions of the second metal layer 252 between the gate and drain regions may be removed by etching. In order to completely remove the metal material in these regions, the second metal layer 252 may be overetched down to the underlying third dielectric layer 250. Due to process variations, the amount of overetching may vary across the wafer and may also vary from wafer to wafer or batch to batch. Therefore, the thickness of the remaining third dielectric layer 250 may vary across the wafer and may also vary from wafer to wafer or batch to batch. A portion 254 of the second metal layer 252 may remain in the region between the gate and drain and may serve as a second field plate. As shown in FIG. Figure 2 As shown in , because it may be difficult to precisely control the over-etching process in the second dielectric layer 240, it may be difficult to control the thickness of the remaining second dielectric layer 240 and the total thickness of the dielectric material below the portion 254 (the second field plate) of the second metal layer 252. Consequently, the height of the second field plate may vary from device to device, and the threshold voltage of the field plate transistor formed below the second field plate may vary from device to device.

[0066] Figure 2It is also shown that a fourth dielectric layer 260 can be formed on the remaining second metal layer 252 and the exposed third dielectric layer 250. In some examples, the fourth dielectric layer 260 can be etched at the source and drain regions to expose metal electrical contacts at the source and drain. A third metal layer 262 can then be formed on the fourth dielectric layer 260. Some areas of the third metal layer 262 between the gate and drain regions can be removed by etching. In order to completely remove the metal material in these areas, the third metal layer 262 can be over-etched down to the underlying fourth dielectric layer 260. However, due to process variations, the amount of over-etching can vary across the wafer and can also vary from wafer to wafer or batch to batch. Therefore, the thickness of the remaining fourth dielectric layer 260 can vary across the wafer and can also vary from wafer to wafer or batch to batch. A portion 264 of the third metal layer 262 can remain in the region between the gate and drain and can serve as a third field plate. As shown in FIG. Figure 2 As shown in , since it may be difficult to precisely control the over-etching process in the third dielectric layer 250, it may be difficult to control the thickness of the remaining third dielectric layer 250 and the total thickness of the dielectric material of the third metal layer 262 below the portion 264 (the third field plate). As a result, the height of the third field plate may vary from device to device, and the threshold voltage of the field plate transistor formed below the third field plate may vary from device to device.

[0067] Additional cycles of dielectric and metal deposition and etching may be used to form additional field plates to tune the electric field in the channel layer of the HEMT 200. However, as Figure 2 As shown in and described above, etching can have low selectivity between the etched metal and the underlying dielectric layer. Therefore, an overetch (e.g., 30% to 50%) may be performed to ensure complete removal of the metal outside the field plate region. However, due to process variations when performing the overetch, it can be difficult to control the height of the field plate, and variations in the thickness of the interlayer dielectric (ILD) layer and the threshold voltage of the field plate transistor can be large, which can adversely affect the yield and uniformity of the performance of the HEMT, such as breakdown voltage, off-state leakage, and dynamic on-resistance or current collapse. Therefore, achieving good uniformity and precise control of the dielectric thickness of each field plate can be challenging, and therefore achieving good uniformity and precise control of the threshold voltage (e.g., pinch-off voltage) of the corresponding field plate transistor formed below the field plate can be challenging.

[0068] According to some examples disclosed herein, a semiconductor device may include a field plate structure formed on a stepped dielectric structure fabricated using an etch stop layer to more precisely control the thickness of the interlayer dielectric (ILD) layer. Consequently, the semiconductor device may have a well-controlled thickness of the ILD layer between the field plate and the channel layer, and thus may have a well-controlled height of the field plate, a well-controlled pinch-off voltage of the field plate transistor, and well-controlled channel electric field modulation and dynamic on-state resistance. In some examples, the etch stop layer may be charged, where the charge density (or charge amount) may be used as another parameter (in addition to the field plate length and height) to tune the electric field and electron density of the channel layer, the pinch-off voltage of the field plate transistor and / or HEMT, and the static on-state resistance and dynamic on-state resistance of the HEMT. The fabrication process and stepped dielectric structure may also be used to form integrated planar inductors and capacitors in semiconductor devices with more precisely controlled interlayer dielectric thickness.

[0069] Figure 3 An example of a HEMT 300 including multiple field plates and an etch stop layer is shown. HEMT 300 may be another example of an implementation of HEMT 100 and may be an e-HEMT or a d-HEMT. In the example shown, HEMT 300 may include a substrate 310, an epitaxial layer 320 grown on substrate 310, and a gate structure 332, a source structure 334, and a drain structure 336 formed on epitaxial layer 320. Multiple dielectric layers may be deposited and patterned (e.g., etched using an etch stop layer) to form a stepped dielectric structure in the drain access region between the drain and the gate. The dielectric layers may include, for example, SiO2, SiN x or Al2O3 layer. The etch stop layer may comprise, for example, a dielectric material, a piezoelectric material, a semiconductor material, polysilicon, or a combination thereof. In some instances, one or more of the etch stop layers may be charged. The stepped dielectric structure may comprise a plurality of planar steps with well-controlled heights. One or more metal layers may be formed on the stepped dielectric structure to form a plurality of field plates with different heights. The metal layer may comprise, for example, Cu, Al, W, Ti, Au, Ni, Pt, TiW, TiN, TaN, TiWAl, TiAlN, or a combination thereof. In Figure 3 In the example shown in , the field plate can be connected to the source electrical contact. In other examples, the field plate can be connected to the gate electrical contact, the source electrical contact, other voltage sources, or a combination thereof.

[0070] Substrate 310 may be similar to substrate 105 of HEMT 100. Epitaxial layer 320 may include, for example, a channel layer and a barrier layer, such as channel layer 110 and barrier layer 120. Gate structure 332 may include a gate electrical contact and a semiconductor layer (e.g., a p-doped GaN layer) or a dielectric layer. In one example, a first dielectric layer 330 may be formed on epitaxial layer 320 and patterned to define gate, source, and drain regions. Metal or metal alloy material may be deposited in the gate, source, and drain regions to form gate, source, and drain electrical contacts.

[0071] A second dielectric layer 340 may be deposited on the first dielectric layer 330, the gate electrical contact, the source electrical contact, and the drain electrical contact. In some instances, the second dielectric layer 340 may be etched at the source and drain regions to expose the source and drain electrical contacts. A first etch stop layer 342 may be formed on the second dielectric layer 340 and the exposed drain and source contacts. The first etch stop layer 342 and the dielectric layers (e.g., the second dielectric layer 340 and the first dielectric layer 330) may have different etch rates under the same dry or wet etching conditions. For example, under one etching condition, the dielectric layer may be etched at an etch rate much higher than the etch rate of the etch stop layer. Under another etching condition, the dielectric layer may be etched at an etch rate much lower than the etch rate of the etch stop layer. As described above, the first etch stop layer 342 may comprise, for example, a dielectric material, a piezoelectric material, a semiconductor material, polysilicon, or a combination thereof. In one example, the dielectric layer can include SiN, and the first etch stop layer 342 can include Al 2 O 3 . In some examples, the first etch stop layer 342 can be charged, as described in more detail below.

[0072] A third dielectric layer 350 may be formed on the first etch stop layer 342 and then patterned by etching to remove the third dielectric layer 350 in the drain region, the source region, and at least one region between the drain and gate. The etching may use a first etch recipe that may have a higher etch rate for the third dielectric layer 350 but a lower etch rate for the first etch stop layer 342. Due to the lower etch rate of the underlying first etch stop layer 342, even when overetching is performed to completely remove regions of the third dielectric layer 350, the etching may still stop at the first etch stop layer 342. Optionally, a second etch recipe that may have a higher etch rate for the first etch stop layer 342 but a lower etch rate for the second dielectric layer 340 may be used to etch the exposed regions of the first etch stop layer 342. Consequently, the exposed regions of the first etch stop layer 342 may be etched by overetching, while less or no second dielectric layer 340 may be etched.

[0073] A second etch stop layer 352 may be formed over the third dielectric layer 350 and the exposed drain and source contacts. The second etch stop layer 352 may be similar to or different from the first etch stop layer 342 and may have an etch rate different from the etch rate of the dielectric layer (e.g., the third dielectric layer 350) under the same dry or wet etching conditions. In some examples, the second etch stop layer 352 may be charged, as described in more detail below. In some examples, the second etch stop layer 352 and the first etch stop layer 342 may have different amounts and / or polarities of charge. A fourth dielectric layer 360 may be formed over the second etch stop layer 352 and then patterned by etching to remove the fourth dielectric layer 360 from the drain region, the source region, and at least one region between the drain and gate. The etching may use an etch recipe that may have a higher etch rate for the fourth dielectric layer 360 but a lower etch rate for the second etch stop layer 352. Due to the low etch rate of the underlying second etch stop layer 352, even when overetching is performed to completely remove areas of the fourth dielectric layer 360, etching can still stop at the second etch stop layer 352. Optionally, another etching recipe that may have a high etch rate for the second etch stop layer 352 but a low etch rate for the third dielectric layer 350 can be used to etch the exposed areas of the second etch stop layer 352. Thus, the exposed areas of the second etch stop layer 352 can be completely etched by overetching, while less or no underlying third dielectric layer 350 is etched.

[0074] In the illustrated example, the stepped dielectric structure can have at least three steps, and each of the three steps can have a uniform height. Additional cycles of deposition and etching of the etch stop layer and dielectric layer described above can be used to form additional etch stop layers and patterned dielectric layers to form additional steps of the stepped dielectric structure. In this process flow, etching can be more precisely controlled to avoid etching into underlying material layers, and the thickness of each of the remaining dielectric layers can be close to the thickness of the deposited dielectric layer. As a result, the thickness (e.g., rise) of each step of the stepped dielectric structure, and therefore the height of each field plate formed on the stepped dielectric structure, can be more precisely and reproducibly controlled, even with process variations.

[0075] After forming the stepped dielectric structure, a metal layer 370 may be formed over the stepped dielectric structure and the exposed drain and source contacts. In some examples, regions of the metal layer 370 (e.g., regions proximate to the drain) may be removed by etching. In the illustrated example, the metal layer 370 may form three field plates, such as a first field plate 372, a second field plate 374, and a third field plate 376, over the stepped dielectric structure. The three field plates have different heights, and thus the corresponding field plate transistors may have different threshold voltages (e.g., pinch-off voltages). A desired electric field distribution in the channel layer of the HEMT 300 may be achieved by selecting the appropriate height and length of the field plates and the charge introduced into the etch stop layer and / or dielectric layer.

[0076] Figure 4A 、 4B 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, and 4L illustrate examples of a process for fabricating a HEMT (eg, HEMT 300) including multiple field plates using an etch stop layer. Figure 4A A semiconductor wafer is shown, comprising a substrate 410, an epitaxial layer 420 on the substrate 410, and a gate structure 432, a source structure 434, and a drain structure 436 formed on the epitaxial layer 420. As described above, the substrate 410 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate (e.g., a QST substrate, a sapphire substrate, or another silicon-based substrate). In one example, the substrate 410 may comprise a bulk silicon wafer and may comprise one or more transition layers or buffer layers of a suitable material for accommodating the lattice mismatch between the substrate 410 and the epitaxial layer 420 (e.g., to reduce or minimize the generation and / or propagation of lattice defects). For example, the transition layer or buffer layer may have a gradient concentration of one or more elements in a direction normal to the surface of the substrate 410 (e.g., the z-direction) to gradually change the lattice constant.

[0077] Due to the different band structures of the channel layer and the barrier layer, the epitaxial layer 420 may include, for example, a channel layer and a barrier layer forming a heterostructure that can induce a 2DEG near the interface between the channel layer and the barrier layer. The 2DEG can conduct current in a two-dimensional plane (e.g., the xy plane). In some examples, the channel layer may include a GaN layer. In some examples, the channel layer may include an unintentionally doped material, such as a material doped by diffusion of a dopant from another layer, or may include an intrinsic material. In some examples, the barrier layer may include an AlGaN layer, which has a wider bandgap than GaN. Other materials may also be used for the channel layer and the barrier layer.

[0078] The gate structure 432 may include a gate semiconductor layer or a gate dielectric layer above the upper surface of the barrier layer of the epitaxial layer 420, and may also include a gate electrical contact (e.g., a gate electrode). The gate structure 432 having the gate semiconductor layer may be used to form an e-HEMT, and the gate structure 432 having the gate dielectric layer may be used to form a d-HEMT. In some examples, the gate semiconductor layer may include a p-doped semiconductor layer, such as described above with respect to Figure 1A The p-doped GaN layer described above. In one example, the p-doped GaN layer at the gate structure 432 can be formed by epitaxial growth on the epitaxial layer 420, followed by selective etching to remove the p-doped GaN layer in other areas. In another example, the p-doped GaN layer at the gate structure 432 can be formed by depositing and patterning the dielectric layer 430 to expose the epitaxial layer 420 at the gate region, and then selectively growing p-doped GaN on the exposed epitaxial layer 420.

[0079] A dielectric layer 430 may be deposited before or after forming the gate semiconductor layer or the gate dielectric layer. The dielectric layer 430 may comprise, for example, an oxide-based material or a nitride-based material, such as silicon oxide (e.g., PSG), aluminum oxide, silicon nitride, etc. The dielectric layer 430 may be patterned to expose the epitaxial layer 420 and the gate semiconductor layer or gate dielectric layer at the drain and source regions. A metal layer may be deposited on the exposed regions by, for example, metal sputtering and etching and / or planarization. The deposited metal layer may form gate electrical contacts, source electrical contacts, and drain electrical contacts. In some examples, before depositing the dielectric layer 430, gate electrical contacts, source electrical contacts, and drain electrical contacts may be formed on the epitaxial layer 420. A dielectric layer 440 may be deposited on the semiconductor wafer to cover the gate electrical contacts, source electrical contacts, and drain electrical contacts. The thickness of the dielectric layer 440 can be determined based on the desired height of the first field plate and can be controlled by, for example, controlling the deposition rate and deposition time.

[0080] Figure 4B It is shown that the dielectric layer 440 at the drain and source regions can be removed (e.g., by selectively etching using an etch mask) to expose the drain and source electrical contacts. An etch stop layer 442 can then be deposited or grown on the semiconductor wafer, such as Figure 4C . The etch stop layer 442 may have an etch rate that is different from the etch rate of the dielectric layer 440. The etch stop layer 442 may include, for example, a dielectric material, a piezoelectric material, a semiconductor material, polysilicon, or a combination thereof. In one example, the dielectric layer 440 may include SiN x, and the etch stop layer 442 may include Al 2 O 3. The dielectric layer 440 and the etch stop layer 442 may be formed using any suitable technique, such as ion beam deposition, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), sputtering, etc.

[0081] exist Figure 4D , a dielectric layer 450 having a desired thickness can be formed on the etch stop layer 442. Dielectric layer 450 can include the same or different dielectric material as the dielectric material of dielectric layer 440 and can be formed using any suitable technique, such as the deposition techniques described above. The thickness of dielectric layer 450 can be determined based on the desired height of the second field plate and can be controlled by, for example, controlling the deposition rate and deposition time. Dielectric layer 450 can be conformally deposited on the semiconductor wafer and may or may not have a flat top surface after deposition.

[0082] Figure 4E The dielectric layer 450 is shown as being removed at selected areas, such as portions of the gate region, source region, drain region, and drain access region, by, for example, dry or wet etching. The etching can be highly selective, with a high etch rate for the dielectric material in the dielectric layer 450 and a very low etch rate for the material of the etch stop layer 442. An etch mask can be used to define the area for etching. The etching time can be long enough to completely remove the dielectric layer 450 at the selected areas. Due to the low etch rate of the underlying etch stop layer 442, overetching can be avoided by etching into the dielectric layer 440.

[0083] Optionally, in Figure 4F In the embodiment of the present invention, another etching process and the same etching mask can be used to completely or partially remove the areas of the etch stop layer 442 exposed after the dielectric etching. The etching process can be different from the etching process used to etch the dielectric layer 450 and can have an etch selectivity that preferentially etches the etch stop layer 442 and has a low etch rate with respect to the dielectric material of the underlying dielectric layer 440. Therefore, the etching time can be long enough to completely remove the etch stop layer 442 at the exposed areas without etching into the dielectric layer 440.

[0084] Figure 4G The etch stop layer 452 is shown as being conformally formed on top of the semiconductor wafer. The etch stop layer 452 can be similar to the etch stop layer 442 and can be formed using deposition techniques such as those described above. A dielectric layer 460 having a desired thickness can then be formed on the etch stop layer 452, such as Figure 4H. Dielectric layer 460 may comprise the same or different dielectric material as dielectric layer 450 and may be formed using any suitable technique, such as the deposition techniques described above. The thickness of dielectric layer 460 may be determined based on the desired height of the third field plate and may be controlled, for example, by controlling the deposition rate and deposition time. Dielectric layer 460 may be conformally deposited on the semiconductor wafer and may or may not have a flat top surface after deposition.

[0085] Figure 4I The dielectric layer 460 is shown as being removed at selected areas, such as portions of the gate region, source region, drain region, and drain access region, by, for example, dry or wet etching. The etching can be highly selective, such as a high etch rate for the dielectric material in the dielectric layer 460 and a much lower etch rate for the material of the etch stop layer 452. An etch mask can be used to define the selected areas for etching. The etching time can be long enough to completely remove the dielectric layer 460 at the selected areas. Due to the low etch rate of the underlying etch stop layer 452, overetching may not etch into the dielectric layer 450.

[0086] Optionally, in Figure 4J In the embodiment of the present invention, another etching process and the same etching mask can be used to remove the areas of the etch stop layer 452 that are exposed after etching the selected areas of the dielectric layer 460. The etching process can be different from the etching process used to etch the dielectric layer 460 and can have an etch selectivity that preferentially etches the etch stop layer 452 and has a low etch rate with respect to the dielectric material of the underlying dielectric layer 450. Therefore, the etching time can be long enough to completely remove the etch stop layer 452 at the exposed areas without etching into the dielectric layer 450.

[0087] like Figure 4J As shown in FIG, a stepped dielectric structure comprising at least three steps may be Figures 4A to 4J Each of the three steps may have a uniform height. Additional cycles of deposition and etching of the etch stop layer and dielectric layer described above may be used to form additional etch stop layers and patterned dielectric layers to form additional steps of the stepped dielectric structure.

[0088] Figure 4K After forming the stepped dielectric structure, a metal layer 470 may be formed on the semiconductor wafer. The metal layer 470 may cover the stepped dielectric structure and the exposed drain and source electrical contacts. The metal layer 470 may be formed, for example, by metal sputtering and may include, for example, a metal or metal alloy such as Cu, Al, W, Ti, Au, Ni, Pt, TiW, TiN, TaN, TiWAl, TiAlN, or a combination thereof.

[0089] like Figure 4LAs shown in FIG, the metal layer 470 can be patterned by selectively etching areas of the metal layer 470. The metal layer 470 can be patterned to, for example, isolate the drain electrical contact from the source electrical contact and to provide a desired length for the third field plate. In the depicted example, the metal layer 470 can be patterned to form three field plates, such as a first field plate 472, a second field plate 474, and a third field plate 476, on the stepped dielectric structure. The three field plates have different heights, and thus the corresponding field plate transistors can have different threshold voltages (e.g., pinch-off voltages). The desired electric field distribution in the channel layer of the HEMT can be achieved by selecting appropriate heights and lengths of the field plates.

[0090] exist Figures 4A to 4L In the process flow shown in FIG, the deposited dielectric layer at the drain and source regions may be removed while forming the stepped dielectric structure. In some other examples, the deposited dielectric layer at the drain and / or source regions may be removed after forming the stepped dielectric structure, and a metal layer deposited on the semiconductor wafer may form a field plate on the stepped dielectric structure and also form a drain electrical contact and / or a source electrical contact.

[0091] Figure 5A 、 5B 5C, 5D, 5E, 5F, 5G, and 5H illustrate another example of a process for fabricating a HEMT (eg, HEMT 300) including multiple field plates using an etch stop layer. Figure 5A A semiconductor wafer is shown that includes a substrate 510, an epitaxial layer 520 on the substrate 510, and a gate structure 532, a source structure 534, and a drain structure 536 formed on the epitaxial layer 520. The substrate 510 may be similar to the substrate 410. The epitaxial layer 520 may be similar to the epitaxial layer 420 and may include, for example, a channel layer and a barrier layer that form a heterostructure that induces a 2DEG near the interface between the channel layer and the barrier layer due to their different band structures.

[0092] The gate structure 532 may include a gate semiconductor layer or a gate dielectric layer above the upper surface of the barrier layer of the epitaxial layer 520, and may also include a gate electrical contact (e.g., a gate electrode). The gate structure 532 having the gate semiconductor layer may be used to form an e-HEMT, and the gate structure 532 having the gate dielectric layer may be used to form a d-HEMT. In some examples, the gate semiconductor layer may include a p-doped semiconductor layer, such as a p-doped GaN layer, as described above with respect to Figure 1AIn one example, the p-doped GaN layer at the gate structure 532 can be formed by epitaxial growth on the epitaxial layer 520, followed by selective area etching to remove the p-doped GaN layer in other areas. In another example, the p-doped GaN layer at the gate structure 532 can be formed by depositing and patterning the dielectric layer 530 to expose the epitaxial layer 520 at the gate region, followed by selective area growth to expose the p-doped GaN on the epitaxial layer 520.

[0093] The dielectric layer 530 may be deposited before or after forming the gate semiconductor layer or the gate dielectric layer. The dielectric layer 530 may include, for example, an oxide-based material or a nitride-based material, such as silicon oxide (e.g., PSG), aluminum oxide, silicon nitride, etc. The dielectric layer 530 may be patterned to expose the epitaxial layer 520 (e.g., the channel layer of the epitaxial layer 520) and the gate semiconductor layer or the gate dielectric layer at the drain and source regions. A metal layer may be deposited on the exposed regions by, for example, metal deposition (e.g., sputtering) and etching and / or planarization. The deposited metal layer may form gate electrical contacts, source electrical contacts, and drain electrical contacts. In some examples, the gate electrical contacts, source electrical contacts, and drain electrical contacts may be formed on the epitaxial layer 520 before depositing the dielectric layer 530.

[0094] although Figure 5A The illustrated example shows that the source structure 534 and the drain structure 536 can be formed in the source region and the drain region before forming the stepped dielectric structure, but in some other examples, the source structure 534 and the drain structure 536 may not be formed in the source region and the drain region. Figure 5A In some other examples, the source structure 534 and the gate structure 532 may be formed by the process shown in FIG. Figure 5A is formed in the process shown, but the drain structure 536 may not be formed by Figure 5A It is formed during the process shown and may be formed after forming the stepped dielectric structure.

[0095] A dielectric layer 540 may be deposited on the semiconductor wafer to cover the gate electrical contact, the source electrical contact, and the drain electrical contact (if already formed). The thickness of the dielectric layer 540 may be determined based on the desired height of the first field plate and may be controlled by, for example, controlling the deposition rate and deposition time. An etch stop layer 542 may then be deposited on the semiconductor wafer. The etch stop layer 542 may have an etch rate that is different from the etch rate of the dielectric layer 540. The etch stop layer 542 may include, for example, a dielectric material, a piezoelectric material, a semiconductor material, polysilicon, or a combination thereof. In one example, the dielectric layer 540 may include SiN x, and etch stop layer 542 may include Al2O3. Dielectric layer 540 and etch stop layer 542 may be formed using any suitable technique, such as ion beam deposition, CVD, PVD, PECVD, ALD, sputtering, etc. A dielectric layer 550 having a desired thickness may be formed on etch stop layer 542. Dielectric layer 550 may include a dielectric material that is the same as or different from that of dielectric layer 540 and may be formed using any suitable technique, such as the deposition techniques described above. The thickness of dielectric layer 550 may be determined based on the desired height of the second field plate and may be controlled by, for example, controlling the deposition rate and deposition time. Dielectric layer 550 may be conformally deposited on the semiconductor wafer and may or may not have a flat top surface after deposition.

[0096] Figure 5B The dielectric layer 550 is shown as being removed at selected areas (e.g., a portion of the gate region and the drain access region) by, for example, dry or wet etching. The etching process can be highly selective and can have a high etch rate for the dielectric material in the dielectric layer 550 and a very low etch rate for the material of the etch stop layer 542. An etch mask can be used to define the area for etching. The etching time can be long enough to completely remove the dielectric layer 550 at the selected areas. Due to the low etch rate of the underlying etch stop layer 542, overetching may not etch into the dielectric layer 540. Optionally, another etching process and the same etching mask can be used to remove the areas of the etch stop layer 542 exposed after etching the dielectric layer 550. The etching process can be different from the etching process used to etch the dielectric layer 550 and can have an etch selectivity that preferentially etches the stop layer 542 and a low etch rate for the dielectric material of the underlying dielectric layer 540. Thus, the etching time can be long enough to completely remove the etch stop layer 542 in the exposed areas without etching into the dielectric layer 540.

[0097] Figure 5C It is shown that an etch stop layer 552 can be conformally formed on top of the semiconductor wafer.Etch stop layer 552 can be similar to etch stop layer 542 and can be formed using deposition techniques such as those described above. Figure 5D A dielectric layer 560, shown having a desired thickness, may then be formed on the etch stop layer 552. Dielectric layer 560 may comprise the same or different dielectric material as dielectric layer 550 and may be formed using any suitable technique, such as the deposition techniques described above. The thickness of dielectric layer 560 may be determined based on the desired height of the third field plate and may be controlled by, for example, controlling the deposition rate and deposition time. Dielectric layer 560 may be conformally deposited on the semiconductor wafer and may or may not have a flat top surface after deposition.

[0098] Figure 5EIt is shown that dielectric layer 560 at selected areas (e.g., portions of the gate region and drain access region) can be removed by, for example, dry or wet etching. The etching can have high selectivity, such as a high etch rate for the dielectric material in dielectric layer 550 and a very low etch rate for the material of etch stop layer 552. An etch mask can be used to define the selected areas for etching. The etching time can be long enough to completely remove dielectric layer 560 at the selected areas. Due to the low etch rate of the underlying etch stop layer 552, overetching may not etch into dielectric layer 550. Optionally, another etching process and the same etching mask can be used to remove areas of etch stop layer 552 that are exposed after etching selected areas of dielectric layer 560. The etching process can be different from the etching process used to etch dielectric layer 560 and can have an etch selectivity that preferentially etches stop layer 552 and has a low etch rate for the dielectric material of the underlying dielectric layer 550. Thus, the etching time may be long enough to completely remove the etch stop layer 552 in the exposed areas without etching into the dielectric layer 550 .

[0099] like Figure 5E As shown in FIG, a stepped dielectric structure comprising at least three steps may be Figures 5A to 5E Each of the three steps may have a uniform height. Additional etch stop layers and patterned dielectric layers may be formed using additional cycles of deposition and etching of the etch stop layers and dielectric layers described above to form additional steps of the stepped dielectric structure.

[0100] exist Figure 5F In the embodiment, the dielectric layer and the etch stop layer formed at the drain region and the source region, including, for example, dielectric layers 540, 550, and 560, and etch stop layers 542 and 552, can be removed by etching. The etching can expose the drain electrical contact and the source electrical contact. Figure 5A In the example shown in the process where no drain and / or source electrical contacts are formed, etching may etch into epitaxial layer 520 to expose a channel layer of epitaxial layer 520 , for example, at the drain and / or source regions.

[0101] Figure 5G A metal layer 570 can be formed on the semiconductor wafer. The metal layer 570 can cover the stepped dielectric structure and the exposed drain and source electrical contacts. The metal layer 570 can be formed by, for example, metal sputtering and can include, for example, a metal or metal alloy such as Cu, Al, W, Ti, Au, Ni, Pt, TiW, TiN, TaN, TiWAl, TiAlN, or a combination thereof. Figure 5A In the example of the process shown, the metal layer 570 may also contact the channel layer of the epitaxial layer 520 to form a drain electrical contact and / or a source electrical contact.

[0102] like Figure 5HAs shown in FIG, the metal layer 570 can be patterned by selectively etching areas of the metal layer 570. The metal layer 570 can be patterned to, for example, isolate the drain electrical contact from the source electrical contact and to set the desired length of the third field plate. In the depicted example, the metal layer 570 can be patterned to form three field plates on the stepped dielectric structure, for example, a first field plate 572, a second field plate 574, and a third field plate 576. The three field plates have different heights, and thus the corresponding field plate transistors can have different threshold voltages (e.g., pinch-off voltages). The desired electric field distribution in the channel layer of the HEMT can be achieved by selecting the appropriate height and length of the field plates.

[0103] As described above, in some examples, charge can be introduced onto the etch stop layer to further modify the electric field in the channel layer and achieve a desired electric field distribution, and also to tune the electron density in the channel layer, the threshold voltage of the field plate transistor, the static on-state resistance and dynamic on-state resistance of the channel, the gate-to-drain capacitance, etc. In some examples, the etch stop layer can be used to store charge at the gate structure in addition to or as an alternative to the gate semiconductor layer to control the gate threshold voltage of the core transistor of the HEMT.

[0104] Figure 6 An example of a HEMT 600 including multiple field plates and a charged etch stop structure is shown. The HEMT 600 may be formed, for example, as described above with respect to Figures 4A to 5H The HEMT 600 is formed by the process described. In the illustrated example, the HEMT 600 includes a substrate 610, an epitaxial layer 620 grown on the substrate 610, and a gate structure 632, a source structure 634, and a drain structure 636 formed on the epitaxial layer 620. The substrate 610 can be similar to the substrate 105, 210, 310, 410, or 510. The epitaxial layer 620 can be similar to the epitaxial layer 220, 320, 420, or 520 and can include, for example, a channel layer and a barrier layer forming a heterostructure that can induce a 2DEG near the interface between the channel layer and the barrier layer due to their different band structures. A plurality of dielectric layers 630, 640, 650, and 660 can be deposited and patterned (e.g., etched using an etch stop layer) to form a stepped dielectric structure in the drain access region between the drain and the gate, as described above. The dielectric layer can include, for example, SiO2, SiN x and / or Al2O3 layers. The stepped dielectric structure may include multiple planar steps with well-controlled heights. A metal layer 670 may be formed (e.g., by sputtering) on ​​the stepped dielectric structure and patterned to form multiple field plates with different heights, such as field plates 672, 674, and 676. The metal layer may include, for example, Cu, Al, W, Ti, Au, Ni, Pt, TiW, TiN, TaN, TiWAl, TiAlN, or a combination thereof. Figure 6In the example shown in , the field plate can be connected to the source electrical contact. In other examples, the field plate can be connected to the gate electrical contact, the source electrical contact, other voltage sources, or a combination thereof.

[0105] Etch stop layers (e.g., etch stop layers 642 and 652) can be used to control the etching of the dielectric layer so that the etching does not etch into the underlying dielectric layer. In some examples, one or more of the etch stop layers 642 and 652 can be charged. In some examples, the etch stop layer 678 can be deposited and patterned after forming the metal layer 670 to form a charge storage layer on the dielectric layer 660. In some examples, before forming the metal layer 670, the etch stop layer 678 can be deposited on the dielectric layer 660 and patterned to form the charge storage layer, wherein the patterned etch stop layer 678 can serve as an etch stop for the patterned metal layer 670 so that the etching of the metal layer 670 in the drain access region does not etch into the dielectric layer 660 to reduce the thickness and thickness uniformity of the dielectric layer 660. The charge density (or amount of charge) on each etch stop layer can be selected to control the electric field and electron density of the channel layer, the threshold voltage of the field plate transistor, the static on-state resistance and dynamic on-state resistance of the channel layer, the gate-to-drain capacitance, etc.

[0106] The etch stop layer may comprise, for example, a dielectric material, a piezoelectric material, a semiconductor material, polysilicon, or a combination thereof. Other materials having an etch rate different from that of the dielectric layer may also be used in the etch stop layer. Various techniques may be used to add charge to the etch stop layer, and the technique used may depend on the material of the etch stop layer. In one example, an etch stop layer (e.g., an aluminum oxide layer) may be formed by ALD, wherein charge (e.g., negative charge) may be introduced in situ onto the etch stop layer (e.g., at the interface between the etch stop layer and the dielectric layer) during the ALD deposition of the etch stop layer. For example, an Al2O3 etch stop layer may be conformally formed on a semiconductor wafer by cyclically exposing the semiconductor wafer to hydrogen (H2) plasma and trimethylaluminum (TMA). The negative charge may at least partially deplete the underlying 2DEG, and thus may change the threshold voltage of the corresponding field plate transistor as described above.

[0107] In some examples, negative or positive charge can be introduced into the etch stop layer by injecting charged particles into the etch stop layer (e.g., a shallow fixed charge injection used to control the threshold voltage of a field effect transistor (FET)). In some examples, the etch stop layer may comprise a piezoelectric material such as piezoelectric aluminum nitride (AlN), and when the piezoelectric material is exposed to stress or an electric field, charge can be introduced onto the surface of the etch stop layer. In some examples, the etch stop layer may comprise polysilicon, and charge can be introduced onto the interface between a dielectric material layer and the polysilicon, where the polysilicon can be formed by, for example, depositing a dielectric material and doping the dielectric material with silicon. Other materials with an etch rate different from that of the dielectric layer can also be used in the etch stop layer. Other techniques can also be used to introduce charge into the etch stop layer. The charge density on different etch stop layers can be different and can be individually adjusted to control the electron density of the underlying 2DEG and the threshold voltage of the field plate transistor. For example, the charge density may be highest on the etch stop layer 678 and may be lower on the etch stop layer 642 or in the gate structure if charge is introduced into the gate structure as described above.

[0108] In some examples, the stepped dielectric structure may include many steps having small step heights and / or small step widths to approximate an inclined dielectric structure having one or more slopes on the sidewalls. As a result, the metal layer formed on the stepped dielectric structure may have a substantially continuously varying height, and the corresponding field plate transistor may have a substantially continuously varying threshold voltage. Figure 1B The number of peaks in the electric field distribution caused by discontinuities between adjacent field plates shown in FIG can be reduced, reducing the electric field near the gate of the HEMT to improve gate TDDB and improving breakdown voltage. In some examples, the edges of the dielectric layer in the stepped dielectric structure can be sloped, so that the stepped dielectric structure can have regions with continuously varying thicknesses between adjacent steps. Consequently, the corresponding field plate transistors in some drain access regions can have continuously varying threshold voltages. This reduces the number of peaks in the electric field distribution caused by discontinuities between adjacent field plates and further reduces the electric field near the gate of the HEMT. In some examples, as will be described below, the thickness between adjacent steps can be reduced, and a relatively large number of steps can be formed in the dielectric structure to form a relatively large number of field plates, thereby approximating a sloped field plate.

[0109] Figure 7A An example of a HEMT 700 including a tilted field plate is shown. The HEMT 700 may be similar to the HEMT 300 or the HEMT 600. The HEMT 700 may be formed, for example, from the HEMT 300 described above with respect to FIG. Figures 4A to 5HThe process described is used to form a HEMT. In the illustrated example, HEMT 700 includes a substrate 710, an epitaxial layer 720 grown on substrate 710, and a gate structure 732, a source structure 734, and a drain structure 736 formed on GaN-based layer 720. Substrate 710 may be similar to substrates 105, 210, 310, 410, 510, or 610. Epitaxial layer 720 may be similar to epitaxial layer 220, 320, 420, 520, or 620 and may include, for example, a channel layer and a barrier layer forming a heterostructure that may induce a 2DEG near the interface between the channel layer and the barrier layer due to their different band structures. Multiple dielectric layers 730, 740, 750, and 760 may be deposited and patterned (e.g., etched using an etch stop layer) to form a stepped dielectric structure in the drain access region between the drain and gate, as described above. The dielectric layer may include, for example, SiO2, SiN x and / or Al2O3 layers. A stepped dielectric structure may comprise multiple planar steps with well-controlled heights.

[0110] In HEMT 700, the sidewalls of dielectric layers 750 and 760 may be sloped. The sloped sidewalls of dielectric layers 750 and 760 may be formed by, for example, wet etching, which can etch the slope vertically and horizontally; dry etching, in which the etching beam is tilted relative to the surface normal direction of dielectric layers 750 and 760; or grayscale lithography.

[0111] Etch stop layers, such as etch stop layers 742 and 752, can be used to control the etching of the dielectric layers described above so that the etching does not etch into the underlying dielectric layer. In some examples, one or more of the etch stop layers 742 and 752 can be charged. The amount of charge or charge density on each etch stop layer can be selected to control the electric field and electron density of the channel layer, the threshold voltage of the field plate transistor, the static on-state resistance and dynamic on-state resistance of the channel layer, the gate-to-drain capacitance, etc.

[0112] A metal layer 770 may be formed on the stepped dielectric structure (e.g., by sputtering) and patterned to form a continuous field plate structure comprising a plurality of field plates having different heights above the epitaxial layer 620, such as field plates 772, 774, and 776. The metal layer may comprise, for example, Cu, Al, W, Ti, Au, Ni, Pt, TiW, TiN, TaN, TiWAl, TiAlN, or a combination thereof. Due to the angled edges of the dielectric layers 750 and 760, the metal layer 770 may form an angled field plate 773 having a height varying between the field plates 772 and 774, and an angled field plate 775 having a height varying between the field plates 774 and 776. Thus, discontinuities in the height of the continuous field plate structure may be reduced, and discontinuities in the threshold voltage of the corresponding field plate transistors may also be reduced. Figure 7A In the example shown in , the field plate can be connected to the source electrical contact. In other examples, the field plate can be connected to the gate electrical contact, the source electrical contact, other voltage sources, or a combination thereof.

[0113] Figure 7B Display of field plate modulation Figure 7A Example of the electric field in the channel layer of HEMT 700. Figure 7B A continuous field plate structure including field plates 772, 773, 774, 775, and 776 is shown. Field plates 772, 773, 774, 775, and 776 may have different heights than the channel layer, and etch stop layers 742 and 752 may have stored charge. As shown, the height of the continuous field plate structure may be discontinuous. Consequently, there may be no discontinuity in the threshold voltage of the corresponding field plate transistor. Both the threshold voltage of the corresponding field plate transistor and the electron density in the channel layer of HEMT 700 may vary in the x-direction.

[0114] Figure 7B Graph 780 in FIG. 7 shows an example of an electric field distribution in the channel layer of HEMT 700 when the HEMT is in the off state and the drain voltage is high. As depicted, due to the discontinuity between the gate structure 732 and the continuous field plate structure connected to the source structure 734, the electric field in the channel layer of HEMT 700 may have a first peak 782 near the edge of the gate structure 732 and may then decrease as described above with respect to FIG. Figure 1B In the channel region below the continuous field plate structure, the electric field may increase at a different slope, may reach a peak 784 near the edge of the continuous field plate structure, and may then decrease in a direction toward the drain structure 736 (e.g., the x-direction). The total area under the curve 780 may represent the voltage difference (V DS), which may be high before the electric field in the channel layer is high enough to cause breakdown of HEMT 700. Furthermore, under given drain bias conditions, the peak electric field in the channel layer of HEMT 700 may be lower than the peak electric field in the channel layer of a HEMT without a continuous field plate structure due to the larger region of the channel layer that maintains a high electric field and a large voltage drop. Consequently, the current collapse and dynamic on-state resistance of HEMT 700 may be lower.

[0115] By more precisely controlling the thickness of the dielectric layer using the fabrication processes disclosed herein, other passive or active devices can be fabricated during the process flow used to fabricate the HEMT and, therefore, integrated with the HEMT. For example, capacitors can be formed from the various structures in the HEMT disclosed herein. In some examples, planar inductors can be fabricated using the fabrication processes disclosed herein and monolithically integrated with the HEMT.

[0116] Figure 8A 、 8B 8C illustrate examples of capacitors integrated with a HEMT in a semiconductor device. As described above, the HEMT may include an epitaxial layer 820 grown on a substrate 810. The HEMT may also include a gate structure 830, a drain structure, and a source structure formed on the epitaxial layer 820. The HEMT may further include a field plate overlying a stepped dielectric structure fabricated using the techniques disclosed herein. Various structures within the HEMT can form capacitors of varying capacitance values.

[0117] Figure 8A A first capacitor formed in a gate region 800 of a HEMT is shown. The first capacitor may be formed by a gate structure 830 (e.g., a gate electrical contact, such as a metal gate electrode), a dielectric layer 840, and a metal layer 850. Metal layer 850 may be part of a metal layer forming a continuous field plate structure, such as metal layers 370, 470, 570, 670, or 770 described above. Dielectric layer 840 may have a low thickness, so that the first capacitor may have a high capacitance per unit area.

[0118] Figure 8B A second capacitor is shown formed in the first field plate region 802 of the HEMT. The second capacitor can be formed by the channel layer of epitaxial layer 820, dielectric layer 832 and dielectric layer 840, and first field plate 852, which can be part of a continuous field plate structure. The thickness of dielectric layer 832 and dielectric layer 840 can be controlled by controlling the dielectric deposition process. Because the dielectric layer in the second capacitor includes both dielectric layer 832 and dielectric layer 840, the second capacitor can have a lower capacitance per unit area than the first capacitor.

[0119] Figure 8CA third capacitor formed in the second field plate region 804 of the HEMT is shown. The third capacitor may be formed by the channel layer of epitaxial layer 820, dielectric layer 832, dielectric layer 840, etch stop layer 842, dielectric layer 860, and second field plate 854, which may be part of a continuous field plate structure. The thickness of dielectric layers 832, 840, and 860 can be controlled by controlling the dielectric deposition process. Because the etch stop layer is used to form a stepped dielectric structure, the total thickness of the dielectric layer between epitaxial layer 820 and second field plate 854 can be more precisely controlled, and thus the capacitance of the third capacitor can be more precisely controlled, even in the presence of process variations. Due to the thicker dielectric material in the third capacitor, the third capacitor may have a lower capacitance per unit area than the second capacitor. In addition, the charge built up in etch stop layer 842 may also change the capacitance of the third capacitor.

[0120] Figure 9A and 9B An example of an inductor 900 formed using the techniques disclosed herein is shown. Figure 9A is a top view of the inductor 900, and Figure 9B is a cross-sectional view of inductor 900 along line AA'. In the depicted example, inductor 900 can include a planar inductor 920 formed on a metal layer, and planar inductor 920 can be connected to pads 914 and 916 using vias 910 and metal interconnects 906 formed in another metal layer. Two dielectric layers 902 and 908 and two etch stop layers 904 and 912 can be used to form inductor 900. The dielectric layers and etch stop layers can include the materials described above.

[0121] In the depicted example, an etch stop layer 904 may be formed on dielectric layer 902. A metal layer may be formed on etch stop layer 904 and may be etched using etch stop layer 904 to form metal interconnect 906. A dielectric layer 908 may be deposited over etch stop layer 904 and metal interconnect 906. An etch stop layer 912 may be formed on dielectric layer 908. Etch stop layer 912 and dielectric layer 908 may be etched to form holes or trenches, which may be filled with one or more metallic materials (e.g., including an adhesion layer, a diffusion barrier, and a metal) to form vias 910 (or metal plugs). A metal layer may then be formed (e.g., by sputtering) on ​​etch stop layer 912. The metal layer may be patterned by etching using an etch mask and etch stop layer 912 to form a planar inductor 920 (e.g., having a spiral structure) and pads 914 and 916 in the metal layer.

[0122] Figure 10 Flowchart 1000 is included that illustrates an example of a process for fabricating a HEMT including multiple field plates using one or more etch stop layers. Note that Figure 10The operations depicted in FIG provide a specific process for manufacturing an example of a HEMT disclosed herein according to a specific example. Other sequences of operations may also be performed to manufacture a HEMT according to an alternative example. For example, an alternative example may perform the operations in a different order. Additionally, Figure 10 The individual operations depicted in flowchart 1000 may include multiple sub-steps that may be performed in various sequences appropriate to the individual operations. Furthermore, some operations may be added or removed depending on the specific instance. In some embodiments, two or more operations may be performed in parallel. In some instances, two or more operations in flowchart 1000 may be performed repeatedly. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0123] The operation at block 1010 of flowchart 1000 may include forming a first dielectric layer on a semiconductor device. The semiconductor device may include a HEMT. The HEMT may include a substrate, an epitaxial layer grown on the substrate, and at least a gate structure formed on the epitaxial layer. The substrate may include, for example, substrate 105, 210, 310, 410, 510, 610, or 710. The epitaxial layer may include, for example, epitaxial layer 220, 320, 420, 520, 620, or 720, and may include, for example, a channel layer and a barrier layer forming a heterostructure that may induce a 2DEG near the interface between the channel layer and the barrier layer due to their different band structures. The gate structure may include, for example, a gate semiconductor layer or a gate dielectric layer above the upper surface of the barrier layer of the epitaxial layer, and may also include a gate electrical contact (e.g., a gate electrode). In some examples, the semiconductor device may also include a source structure and / or a drain structure formed on the epitaxial layer. The source structure and the drain structure may include metal contacts contacting the channel layer at the source region and the drain region, respectively. In some examples, the first dielectric layer may include a dielectric material between the drain structure and the gate structure and between the gate structure and the source structure (e.g., dielectric layer 330, 430, 530, 630, or 730), and a dielectric layer formed over the drain structure, the gate structure, and the source structure (e.g., dielectric layer 340, 440, 540, 640, or 740). As described above, the first dielectric layer may include, for example, an oxide-based material or a nitride-based material, such as silicon oxide (e.g., PSG), Al2O3, SiN x The first dielectric layer may be formed using any suitable technique, such as ion beam deposition, CVD, PVD, PECVD, ALD, sputtering, etc. The thickness of the first dielectric layer may be determined based on a desired threshold voltage (eg, pinch-off voltage) of the first field plate transistor.

[0124] At box 1020, a first etch stop layer (e.g., etch stop layer 342, 442, 542, 642, or 742) may be deposited on the first dielectric layer. The first etch stop layer may have an etch rate that is different from the etch rate of the first dielectric layer under the same etching conditions. The first etch stop layer may include, for example, a dielectric material, a piezoelectric material, a semiconductor material, polysilicon, or a combination thereof. In one example, the first dielectric layer may include SiN, and the first etch stop layer may include Al2O3. The first etch stop layer may be formed on the first dielectric layer using, for example, ion beam deposition, CVD, PVD, PECVD, ALD, sputtering, etc. In some examples, the charge may be as described above with respect to, for example, Figure 6 As described above, charge is introduced onto the first etch stop layer to tune the electric field and electron density in the channel layer. For example, charge can be introduced onto the first etch stop layer by depositing the first etch stop layer using atomic layer deposition, by injecting charged particles into the first etch stop layer, by depositing a piezoelectric material, by depositing a dielectric material and doping the dielectric material with silicon, etc. The charge density on the first etch stop layer can be determined based on a desired threshold voltage (e.g., pinch-off voltage) of the second field plate transistor.

[0125] At block 1030, a second dielectric layer (e.g., dielectric layer 350, 450, 550, 650, or 750) may be deposited on the first etch stop layer. Like the first dielectric layer, the second dielectric layer may also include, for example, an oxide-based material or a nitride-based material, such as silicon oxide (e.g., PSG), Al2O3, SiN x etc. and may be formed using any suitable technique, such as ion beam deposition, CVD, PVD, PECVD, ALD, sputtering, etc. The thickness of the second dielectric layer may be determined based on a desired threshold voltage (eg, pinch-off voltage) of the second field plate transistor.

[0126] The operation at block 1040 may include etching selected areas of the second dielectric layer using the first etch stop layer as an etch stop to form a stepped dielectric structure. In some examples, etching the selected areas of the second dielectric layer may include etching the second dielectric layer at the gate, source, and drain regions of the semiconductor device. In some examples, etching the selected areas of the second dielectric layer may include etching the second dielectric layer only at the gate region of the semiconductor device. In some examples, etching the selected areas of the second dielectric layer may include etching the second dielectric layer at the gate and source regions, but not etching the drain region of the semiconductor device. The etching may be performed for a sufficient period of time to completely remove the second dielectric layer at the selected areas. Due to the low etch rate of the first etch stop layer between the first and second dielectric layers, overetching the second dielectric layer may not etch into the first dielectric layer. In some examples, the edge regions of the remaining second dielectric layer on the sides of the gate region may be etched using, for example, wet etching, tilted dry etching, or grayscale lithography to form tilted sidewalls. In some examples, after etching the second dielectric layer, the exposed first etch stop layer may be removed using a different etch process that may have a higher etch rate for the first etch stop layer but a much lower etch rate for the first dielectric layer.

[0127] Optionally, at block 1042, a second etch stop layer may be deposited on the semiconductor device, at block 1044, a third dielectric layer may be deposited on the second etch stop layer, and at block 1046, selected areas of the third dielectric layer may be etched using the second etch stop layer as an etch stop to form additional steps of the stepped dielectric structure. The operations at blocks 1042, 1044, and 1046 may be similar to the operations at blocks 1020, 1030, and 1040 described above. In some examples, the charge may be as described above with respect to, for example, Figure 6 The described method introduces a charge density on the second etch stop layer to tune the electric field and electron density in the channel layer. The charge density on the second etch stop layer can be determined based on the desired threshold voltage (e.g., pinch-off voltage) of the third field plate transistor. The thickness of the third dielectric layer can also be determined based on the desired threshold voltage of the third field plate transistor. In some examples, the edge region of the etched third dielectric layer can be etched to form the sloped sidewalls described above. In some examples, the operations at blocks 1042, 1044, and 1046 can be performed repeatedly to form additional steps of the stepped dielectric structure. For example, many dielectric layers with low layer heights can be formed to approximate a dielectric structure having sloped sidewalls with one or more slopes.

[0128] In some examples, the dielectric layer at the drain region and / or the source region may not be etched at blocks 1040 and 1046. After forming the stepped dielectric structure, the dielectric layer at the drain region and / or the source region and the one or more etch stop layers may be etched to expose the drain structure and / or the source structure, or the channel layer at the drain region and / or the source region (if the drain structure and / or the source structure have not yet been formed).

[0129] At block 1050, a metal layer may be deposited on the stepped dielectric structure to form a field plate structure. When the stepped dielectric structure includes many dielectric layers with low layer thicknesses to approximate a dielectric structure with sloped sidewalls, the metal layer formed on the stepped dielectric structure may have substantially continuously varying heights, and the corresponding field plate transistor may have substantially continuously varying threshold voltages. Figure 7A and 7B When the plurality of planar steps of the inclined sidewall are shown in , the field plate structure may include two or more planar field plates and one or more inclined field plates. In some examples, the deposited metal layer may also form a drain contact structure at the drain region and / or a source contact structure at the source region.

[0130] As used herein, the term "semiconductor substrate" may refer to a semiconductor wafer without other layers or circuits formed therein, or a semiconductor wafer containing various layers and circuits formed therein. As used herein, the term "layer" may refer to a continuous layer, or a region or portion of a layer.

[0131] In this description, the term "coupled" may encompass any connection, communication, or signal path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not modify the functional relationship between devices A and B such that device B is controlled by device A via the control signal generated by device A.

[0132] Furthermore, in this description, the statement “based on” means “based at least in part on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0133] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by the manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0134] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0135] Circuits or devices described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0136] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, such as NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0137] In the claims, reference may be made to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0138] References herein to a FET being "on" or "enabled" mean that the FET's conductive channel exists and drain current can flow through the FET. References herein to a FET being "off" or "disabled" mean that the conductive channel does not exist, and therefore drain current does not flow through the FET. However, an "off" FET can have current flowing through the transistor's body diode.

[0139] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0140] Although some elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0141] Use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this description.

[0142] In this description, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter, or if the parameter is zero, within a reasonable range of about zero.

[0143] As used herein, the terms "and" and "or" may have various meanings, which are also expected to depend at least in part on the context in which such terms are used. Generally, if "or" is used in connection with a list, such as A, B, or C, then it is intended to mean A, B, and C, which are used in an inclusive sense here, and A, B, or C, which are used in an exclusive sense here. In addition, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Furthermore, the term "at least one of...", if used in connection with a list, such as A, B, or C, may be interpreted to mean A, B, C, or a combination of A, B, and / or C, such as AB, AC, BC, AA, ABC, AAB, ACC, AABBCCC, etc.

[0144] Although various examples have been described in detail, it should be understood that various changes, substitutions, and modifications may be made therein without departing from the scope defined by the appended claims. The devices, structures, materials, and processes discussed above are examples. Various examples may omit, substitute, or add various programs or components as appropriate. In addition, features described with respect to a particular example may be combined in various other examples. Different aspects and elements of the examples may be combined in a similar manner. In addition, technology evolves and, therefore, many elements are examples, which do not limit the scope of this disclosure to those specific examples.

[0145] Specific details are given in the description to provide a thorough understanding of the examples. However, examples can be practiced without these specific details. For example, well-known circuits, processes, systems, structures, and techniques can be shown without unnecessary details to avoid confusing the examples. This description only provides examples and is not intended to limit the scope, applicability, or configuration of the present invention. On the contrary, the previous description of the examples will provide inspiring descriptions for implementing various examples for those skilled in the art. Various changes can be made to the functions and configurations of the elements without departing from the spirit and scope of the present disclosure. Within the scope of the claims, modifications may be made in the described examples, and other examples are possible.

Claims

1. A semiconductor device comprising: semiconductor substrates; a source electrode, a gate electrode, and a drain electrode, which are located on the semiconductor substrate; a stepped dielectric structure on the semiconductor substrate and laterally between the gate electrode and the drain electrode, the stepped dielectric structure comprising: a first dielectric layer on the semiconductor substrate; a first etch stop layer on the first dielectric layer; and a second dielectric layer on the first etch stop layer, the first dielectric layer having a first lateral dimension greater than a second lateral dimension of the second dielectric layer; and A metal layer is on the stepped dielectric structure, the metal layer including a first field plate on at least a first region of the first dielectric layer and a second field plate on at least a second region of the second dielectric layer.

2. The semiconductor device according to claim 1, wherein: The first region of the first dielectric layer has a first thickness; The second region of the second dielectric layer has a second thickness; and A third region of the first dielectric layer directly above the second region of the second dielectric layer has a first uniform thickness.

3. The semiconductor device according to claim 1, wherein: The first dielectric layer in the stepped dielectric structure has a first planar surface; and The second dielectric layer in the stepped dielectric structure has a second planar surface. The semiconductor device according to claim 1 , wherein sidewalls of the second dielectric layer in the stepped dielectric structure are inclined. 5 . The semiconductor device according to claim 1 , wherein the first etch stop layer includes charges stored in or on the first etch stop layer.

6. The semiconductor device according to claim 1 , wherein the stepped dielectric structure further comprises: a second etch stop layer on the second dielectric layer; and a third dielectric layer on the second etch stop layer, The metal layer includes a third field plate on at least a portion of the third dielectric layer. 7 . The semiconductor device according to claim 6 , wherein a sidewall of the third dielectric layer in the stepped dielectric structure is inclined. 8 . The semiconductor device according to claim 6 , wherein the second etch stop layer includes charges stored in or on the second etch stop layer. 9 . The semiconductor device of claim 6 , wherein the stepped dielectric structure further comprises a third etch stop layer on at least a region of the third dielectric layer, the third etch stop layer comprising charges stored in or on the third etch stop layer.

10. The semiconductor device of claim 1, wherein the metal layer comprises a planar inductor over a planar dielectric layer.

11. The semiconductor device of claim 1, further comprising a capacitor comprising a planar dielectric layer. 12 . The semiconductor device according to claim 1 , wherein the first etch stop layer covers the first region of the first dielectric layer. 13 . The semiconductor device of claim 1 , wherein the first etch stop layer comprises a dielectric material, a piezoelectric material, a semiconductor material, polysilicon, or a combination thereof. 14 . The semiconductor device according to claim 1 , wherein the metal layer is electrically coupled to the source electrode or the gate electrode. 15 . The semiconductor device according to claim 1 , wherein the semiconductor substrate comprises a heterostructure formed of a channel layer and a barrier layer. 16 . The semiconductor device according to claim 1 , further comprising a p-doped semiconductor layer or a gate dielectric layer between the gate electrode and the semiconductor substrate. 17 . The semiconductor device of claim 1 , wherein the stepped dielectric structure comprises three or more dielectric layers, the three or more dielectric layers comprising the first dielectric layer and the second dielectric layer.

18. The semiconductor device according to claim 1, wherein: The stepped dielectric structure comprises a plurality of dielectric layers; and The lateral dimensions and heights of the dielectric layers in the plurality of dielectric layers are selected so that the plurality of dielectric layers approximate a tilted structure.

19. A method comprising: depositing a first dielectric layer on a semiconductor device, the semiconductor device comprising a channel layer and a barrier layer; depositing a first etch stop layer on the first dielectric layer; depositing a second dielectric layer on the first etch stop layer; etching selected areas of the second dielectric layer using the first etch stop layer as an etch stop, the etched second dielectric layer and the first dielectric layer forming a stepped dielectric structure; as well as A metal layer is deposited on the stepped dielectric structure to form a plurality of field plates on the stepped dielectric structure.

20. The method of claim 19, wherein depositing the first etch stop layer on the first dielectric layer comprises introducing charge into or onto the first etch stop layer.

21. The method of claim 20, wherein introducing charge into or onto the first etch stop layer comprises: depositing the first etch stop layer using atomic layer deposition; injecting charged particles into the first etch stop layer; depositing piezoelectric materials; depositing a dielectric material and doping the dielectric material with silicon; or Its combination.

22. The method of claim 19, further comprising, before depositing the metal layer: depositing a second etch stop layer on the semiconductor device; depositing a third dielectric layer on the second etch stop layer; and Selected areas of the third dielectric layer are etched using the second etch stop layer as the etch stop to form additional steps of the stepped dielectric structure.

23. The method of claim 22, wherein: Etching the selected areas of the second dielectric layer includes etching the second dielectric layer at gate, source, and drain regions of the semiconductor device; and Etching the selected areas of the third dielectric layer includes etching the third dielectric layer at the gate region, the source region, and the drain region of the semiconductor device.

24. The method of claim 22, wherein: Etching the selected area of ​​the second dielectric layer includes etching the second dielectric layer at a gate region of the semiconductor device; Etching the selected area of ​​the third dielectric layer includes etching the third dielectric layer at the gate region of the semiconductor device; and The method further includes etching the second dielectric layer and the third dielectric layer at source and drain regions of the semiconductor device before depositing the metal layer.

25. The method of claim 22, wherein: Etching the selected areas of the second dielectric layer includes etching the second dielectric layer at gate and source regions of the semiconductor device; Etching the selected areas of the third dielectric layer includes etching the third dielectric layer at the gate region and the source region of the semiconductor device; and The method further includes etching the second dielectric layer and the third dielectric layer at a drain region of the semiconductor device before depositing the metal layer.

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