Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein a semiconductor structure is formed on the substrate, and the semiconductor structure comprises a gate dielectric layer and a sacrifice layer formed on the gate dielectric layer; performing decoupling plasma nitridation treatment on the semiconductor structure, so that the nitrogen content of the semiconductor structure after the treatment is higher than that before the treatment; performing a heavy ion implantation process on the semiconductor structure after the treatment, so that the nitrogen element in the sacrifice layer is pushed into the gate dielectric layer; and removing the sacrifice layer. The application reduces or avoids the diffusion of nitrogen elements into the substrate, avoids the negative influence of the diffusion of nitrogen elements into the substrate on the element diffusion and channel mobility in the subsequent ion implantation process, effectively controls the thermal budget in the process, reduces or avoids the risk of crystallization in the gate dielectric layer, and improves the process stability.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In general semiconductor devices, the high-k metal gate (HKMG) structure, which is composed of a high-k dielectric material and a metal gate, is usually fabricated using back-gate technology. This enables the semiconductor device to accommodate a high thermal budget and adjust the threshold voltage of the semiconductor device through the metal gate stack.

[0003] However, due to the need for multiple annealing processes in the HKMG structure's pre-HK process, the high-dielectric-constant material layer requires a high thermal budget. Therefore, excessive thermal budgeting during this process can lead to crystallization in the high-dielectric-constant material layer, which reduces its dielectric constant. Furthermore, the presence of crystals can cause grain boundary leakage, resulting in poorer quality and uniformity of the metal gate and increased leakage. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to reduce or avoid the risk of crystallization in the gate dielectric layer and improve process stability.

[0005] This application provides a method for manufacturing a semiconductor device, comprising:

[0006] A substrate is provided on which a semiconductor structure is formed, the semiconductor structure including a gate dielectric layer and a sacrificial layer formed on the gate dielectric layer;

[0007] The semiconductor structure is subjected to decoupling plasma nitriding treatment, and the nitrogen content of the semiconductor structure after treatment is higher than that of the semiconductor structure before treatment.

[0008] The processed semiconductor structure is subjected to a high-mass ion implantation process to push nitrogen elements from the sacrificial layer into the gate dielectric layer;

[0009] Remove the sacrificial layer.

[0010] In one embodiment, the high-mass ion implantation process uses high-mass ions with a relative atomic mass range of 39.95 AMU to 121.76 AMU.

[0011] In one embodiment, the high-mass ion includes at least one of germanium ions, gallium ions, argon ions, arsenic ions, indium ions, antimony ions, and boron difluoride ions.

[0012] In one embodiment, the sacrificial layer includes at least one of a photoresist layer or an amorphous silicon layer.

[0013] In one embodiment, the thickness of the sacrificial layer ranges from 30 Å to 90 Å.

[0014] In one embodiment, the ratio of the thickness of the semiconductor structure to the thickness of the substrate ranges from 1 to 3.

[0015] In one embodiment, after removing the sacrificial layer, the method of manufacturing the semiconductor device further includes:

[0016] A protective layer is formed on the gate dielectric layer;

[0017] A virtual gate is formed on the protective layer;

[0018] A source region and a drain region are formed in the substrate on both sides of the virtual gate, respectively;

[0019] An interlayer dielectric layer is formed on the protective layer on both sides of the virtual gate;

[0020] Remove the dummy gate to form an opening within the interlayer dielectric layer that exposes the protective layer;

[0021] A metal gate is formed within the opening.

[0022] In one embodiment, the gate dielectric layer is made of a high dielectric constant material, and the protective layer is made of titanium nitride.

[0023] In one embodiment, the formation process of the substrate and the semiconductor structure includes:

[0024] Provide substrate;

[0025] A shallow trench isolation structure is formed within the substrate;

[0026] An oxide layer is formed on the substrate, and the oxide layer covers the shallow trench isolation structure to form the substrate including the substrate, the shallow trench isolation structure and the oxide layer;

[0027] The gate dielectric layer is formed on the oxide layer;

[0028] The sacrificial layer is formed on the gate dielectric layer to form the semiconductor structure.

[0029] Accordingly, this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above.

[0030] An unexpected benefit of this application is that a semiconductor structure including a gate dielectric layer and a sacrificial layer is formed on the substrate. While protecting the gate dielectric layer, the thickness of the semiconductor structure is increased, thereby reducing or avoiding the diffusion of nitrogen into the substrate during the subsequent decoupling plasma nitriding process. This prevents nitrogen from diffusing into the substrate and negatively impacting element diffusion and channel mobility in the subsequent ion implantation process. At the same time, by performing a high-mass atom implantation process after decoupling plasma nitriding, the thermal budget in the process is effectively controlled, thereby reducing or avoiding the risk of crystallization in the gate dielectric layer and improving process stability. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application.

[0033] Figure 2 This is a schematic diagram of the structure corresponding to the step of providing a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0034] Figure 3 This is a schematic diagram of the structure corresponding to the step of forming a semiconductor structure on a substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0035] Figure 4 This is a schematic diagram of the structure corresponding to the step of decoupling plasma nitriding treatment of the semiconductor structure in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0036] Figure 5 This is a schematic diagram of the structure corresponding to the step of performing a high-mass ion implantation process on the processed semiconductor structure in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0037] Figure 6 This is a schematic diagram of the structure corresponding to the step of removing the sacrificial layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0038] The reference numerals in the figures include: 100-substrate; 101-substrate; 102-shallow trench isolation structure; 103-oxide layer; 110-semiconductor structure; 111-gate dielectric layer; 112-sacrificial layer. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0044] The high-k metal gate (HKMG) structure, composed of a high-k dielectric material and a metal gate, fabricated using post-gate technology, boasts a high thermal budget and allows for adjustment of the threshold voltage of semiconductor devices through metal gate stacking. In the pre-HK process described above, decoupled plasma nitriding (DPN) is typically used to treat the high-k dielectric material layer, increasing its thermal stability and reliability. Simultaneously, DPN is usually performed in conjunction with post-nitriding annealing (PNA) to fix the nitrogen on the surface of the high-k dielectric material layer.

[0045] However, the HKMG structure requires multiple annealing processes during manufacturing, demanding high thermal budgets. Excessive thermal budgeting during this process can lead to crystallization in the high-dielectric-constant material layer, reducing its dielectric constant. Simultaneously, the presence of crystals can cause grain boundary leakage, resulting in poorer metal gate quality and uniformity, and increased leakage. Furthermore, the decoupling plasma nitriding process involves ion bombardment of the high-dielectric-constant material layer's surface, degrading its surface quality and negatively impacting gate performance.

[0046] At the 28nm process node, the combination of decoupling plasma nitriding and post-nitriding annealing can increase the stability and reliability of high dielectric constant material layers. However, since both the high dielectric constant material layer and the subsequently formed interlayer dielectric layer are relatively thin, the nitriding depth during the decoupling plasma nitriding process is difficult to control. Nitrogen elements tend to accumulate at the interface between the substrate and the oxide layer, which can adversely affect the performance of semiconductor devices.

[0047] Based on this, this application provides a semiconductor device and a method for manufacturing the same, which reduces or avoids the risk of crystallization in the gate dielectric layer and improves process stability.

[0048] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application. See also... Figure 1 One embodiment of this application provides a method for manufacturing a semiconductor device, which includes the following steps S01 to S04.

[0049] Step S01: Provide a substrate on which a semiconductor structure is formed, the semiconductor structure including a gate dielectric layer and a sacrificial layer formed on the gate dielectric layer.

[0050] It should be noted that by forming a sacrificial layer on the gate dielectric layer, the gate dielectric layer can be protected from damage during subsequent process steps. Simultaneously, by forming a semiconductor structure including both a sacrificial layer and a gate dielectric layer, the thickness of the film covering the substrate can be increased, thereby reducing the probability of nitrogen elements penetrating the semiconductor structure and diffusing into the substrate during subsequent decoupling plasma nitriding treatment.

[0051] Step S02: The semiconductor structure is subjected to decoupling plasma nitriding treatment, and the nitrogen content of the semiconductor structure after treatment is higher than that of the semiconductor structure before treatment.

[0052] Step S03: Perform a high-mass ion implantation process on the processed semiconductor structure to push nitrogen elements from the sacrificial layer into the gate dielectric layer.

[0053] It should be noted that after the semiconductor structure is decoupled by plasma nitriding, the surface and interior of the sacrificial layer are enriched with a large amount of nitrogen. The high-mass ion implantation process can push the nitrogen enriched in the sacrificial layer into the gate dielectric layer, which can further increase the nitrogen content of the gate dielectric layer and reduce the thermal budget of the process, thereby helping to prevent crystallization in the gate dielectric layer.

[0054] Step S04: Remove the sacrificial layer.

[0055] The semiconductor device manufacturing method described above increases the thickness of the semiconductor structure by forming a semiconductor structure including a gate dielectric layer and a sacrificial layer on a substrate. This protects the gate dielectric layer while reducing or avoiding the diffusion of nitrogen into the substrate during the subsequent decoupling plasma nitriding process. This prevents nitrogen from diffusing into the substrate and negatively impacting element diffusion and channel mobility in the subsequent ion implantation process. Furthermore, by performing a high-mass atom implantation process after decoupling plasma nitriding, the thermal budget in the process is effectively controlled, thereby reducing or avoiding the risk of crystallization in the gate dielectric layer and improving process stability.

[0056] See Figure 2 and Figure 3 A substrate 100 is provided, on which a semiconductor structure 110 is formed. The semiconductor structure 110 includes a gate dielectric layer 111 and a sacrificial layer 112 formed on the gate dielectric layer 111. Optionally, the material of the gate dielectric layer 111 includes a high-k dielectric material (High-K, HK), and the sacrificial layer 112 includes at least one of a photoresist layer or an amorphous silicon layer.

[0057] In one embodiment, the ratio of the thickness of the semiconductor structure 110 to the thickness of the substrate 100 ranges from 1 to 3. Optionally, the thickness of the sacrificial layer 112 ranges from 30 Å to 90 Å. It should be noted that the thicknesses of the substrate and the gate dielectric layer and sacrificial layer in the semiconductor structure can be adjusted according to actual needs. Adjusting the overall thickness of the semiconductor structure can reduce or avoid the risk of nitrogen diffusion into the substrate during the subsequent decoupling plasma nitriding process, while also preventing nitrogen accumulation at the substrate interface. Adjusting the thickness of the sacrificial layer can help increase the nitrogen content in the gate dielectric layer while protecting it. The specific auxiliary process will be described in detail during the subsequent decoupling plasma nitriding process and high-mass ion implantation process.

[0058] Continue reading Figure 2 and Figure 3 In one embodiment, the formation process of the substrate 100 and the semiconductor structure 110 includes: providing a substrate 101; forming a shallow trench isolation structure 102 within the substrate 101; forming an oxide layer 103 on the substrate 101, wherein the oxide layer 103 covers the shallow trench isolation structure 102, to form a substrate 100 including the substrate 101, the shallow trench isolation structure 102, and the oxide layer 103; forming a gate dielectric layer 111 on the oxide layer 103; and forming a sacrificial layer 112 on the gate dielectric layer 111 to form the semiconductor structure 110. It should be noted that the specific formation methods and related process flows of the substrate and semiconductor structure are well known to those skilled in the art, and will not be elaborated upon further in this application.

[0059] In one embodiment, the substrate 101 is made of silicon (Si), and the oxide layer 103 is made of silicon oxide. In other embodiments of this application, the material selection and thickness settings of the various films within the substrate and semiconductor structure can be adjusted as needed, and this application does not impose any limitations on this.

[0060] See Figure 4 The semiconductor structure 110 is subjected to decoupled plasma nitridation (DPN) treatment, and the nitrogen (N) content of the semiconductor structure 110 after treatment is higher than that of the semiconductor structure 110 before treatment.

[0061] It should be noted that in practical applications, by adjusting the thickness of the sacrificial layer and the gate dielectric layer, some nitrogen elements in the decoupling plasma nitriding process can penetrate into the gate dielectric layer, while the majority of the remaining nitrogen elements are enriched in the interior and surface of the sacrificial layer. This avoids nitrogen elements diffusing into the substrate, thereby reducing the probability of nitrogen elements entering the substrate or accumulating at the substrate interface and avoiding adverse effects on the performance of semiconductor devices.

[0062] See Figure 5 The processed semiconductor structure 110 undergoes a high-mass ion implantation process to push nitrogen elements from the sacrificial layer 112 into the gate dielectric layer 111. In one embodiment, the high-mass ion implantation process uses high-mass ions with a relative atomic mass range of 39.95 AMU to 121.76 AMU. Optionally, the high-mass ions include at least one of germanium ions (Ge), gallium ions (Ga), arsenic ions (As), argon ions (Ar), indium ions (In), antimony ions (Sb), and boron difluoride ions (BF2).

[0063] Continue reading Figure 5 Taking the case of using argon ions (Ar) as an example, during the process of high-mass ion implantation, the high-mass ions push the nitrogen elements enriched on the surface and inside of the sacrificial layer 112 into the gate dielectric layer 111, thereby passivating the defects in the gate dielectric layer 111 and further increasing the nitrogen content of the gate dielectric layer 111.

[0064] It is important to emphasize that since the thermal budget of the high-mass ion implantation process is lower than that of the high-temperature annealing process, replacing the high-temperature annealing process with the high-mass ion implantation process can further increase the nitrogen content of the gate dielectric layer while reducing the thermal budget of the process, thereby helping to prevent crystallization in the gate dielectric layer.

[0065] See Figure 6The sacrificial layer 112 is removed. In one embodiment, the sacrificial layer 112 can be removed using a dry etching process or a wet etching process. The specific removal method can be selected according to the materials of the sacrificial layer 112 and the gate dielectric layer 111. For example, when the gate dielectric layer is hafnium dioxide (HfO2) and the sacrificial layer is a photoresist layer, an ashing process and a wet cleaning process can be used to remove the sacrificial layer. Those skilled in the art can select a suitable removal method based on their professional knowledge, and this application does not limit this.

[0066] In one embodiment, after removing the sacrificial layer, the method for manufacturing the semiconductor device further includes: forming a protective layer on the gate dielectric layer; forming a dummy gate on the protective layer; forming a source region and a drain region in the substrate on both sides of the dummy gate, respectively; forming an interlayer dielectric layer on the protective layer on both sides of the dummy gate; removing the dummy gate to form an opening in the interlayer dielectric layer to expose the protective layer; and forming a metal gate in the opening. In other embodiments of this application, other process methods may be used to form the metal gate, and this application is not limited thereto.

[0067] In one embodiment, the protective layer is made of titanium nitride (TiN), the dummy gate is made of polysilicon, the interlayer dielectric layer is made of at least one of silicon oxide and silicon nitride, and the metal gate is made of common metal and alloy materials, such as tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), or alloys containing the above metals, etc. This application does not limit this.

[0068] In one embodiment, both the formation of a protective layer on the gate dielectric layer and the formation of an interlayer dielectric layer on the protective layers on both sides of the dummy gate can be achieved using chemical vapor deposition (CVD). After the interlayer dielectric layer is deposited, it can be planarized to make its surface flush with the surface of the dummy gate. Optionally, chemical mechanical polishing (CMP) can be used for planarization.

[0069] In one embodiment, the process of forming a dummy gate includes: depositing a gate material layer on a protective layer, forming a patterned mask layer on the gate material layer, etching the gate material layer based on the mask layer to form a dummy gate on the protective layer, and finally removing the mask layer. Optionally, a wet etching process is used to remove the mask layer.

[0070] In one embodiment, an ion implantation process is used to form source and drain regions in the substrate on both sides of the virtual gate. The specific formation process is common knowledge known to those skilled in the art and will not be elaborated here.

[0071] Accordingly, this application also provides a semiconductor device manufactured using the semiconductor device manufacturing method described above. See also... Figure 6 One embodiment of this application provides a semiconductor device including a substrate 100 and a gate dielectric layer 111 located on the substrate 100. The substrate 100 includes a substrate 101, a shallow trench isolation structure 102, and an oxide layer 103. The shallow trench isolation structure 102 is disposed within the substrate 101, and the oxide layer 103 covers the substrate 101 and the shallow trench isolation structure 102. Optionally, the substrate 101 is made of silicon, the oxide layer 103 is made of silicon oxide, and the gate dielectric layer 111 is made of a high-dielectric material.

[0072] In one embodiment, the semiconductor device further includes a protective layer, a source region, a drain region, an interlayer dielectric layer, and a metal gate, wherein the protective layer is disposed on the gate dielectric layer, the metal gate is disposed on the protective layer, the source region and the drain region are respectively disposed in the substrate on both sides of the metal gate, and the interlayer dielectric layer covers the protective layer on both sides of the metal gate.

[0073] The unexpected effect of this application is that it forms a semiconductor structure including a gate dielectric layer and a sacrificial layer on the substrate, which increases the thickness of the semiconductor structure while protecting the gate dielectric layer. This reduces or avoids the diffusion of nitrogen into the substrate during the subsequent decoupling plasma nitriding process, thereby preventing the diffusion of nitrogen into the substrate and its negative impact on element diffusion and channel mobility in the subsequent ion implantation process. At the same time, by performing a high-mass atom implantation process after the decoupling plasma nitriding process, the thermal budget in the process is effectively controlled, thereby reducing or avoiding the risk of crystallization in the gate dielectric layer and improving process stability.

[0074] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0075] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which a semiconductor structure is formed, the semiconductor structure including a gate dielectric layer and a sacrificial layer formed on the gate dielectric layer; The semiconductor structure is subjected to decoupling plasma nitriding treatment, and the nitrogen content of the semiconductor structure after treatment is higher than that of the semiconductor structure before treatment. The processed semiconductor structure is subjected to a high-mass ion implantation process to push nitrogen elements from the sacrificial layer into the gate dielectric layer; Remove the sacrificial layer; The high-mass ion implantation process uses high-mass ions with relative atomic masses ranging from 39.95 AMU to 121.76 AMU.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The high-mass ions include at least one of germanium ions, gallium ions, argon ions, arsenic ions, indium ions, antimony ions, and boron difluoride ions.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The sacrificial layer includes at least one of a photoresist layer or an amorphous silicon layer.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The thickness of the sacrificial layer ranges from 30 Å to 90 Å.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The ratio of the thickness of the semiconductor structure to the thickness of the substrate ranges from 1 to 3.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After removing the sacrificial layer, the method for manufacturing the semiconductor device further includes: A protective layer is formed on the gate dielectric layer; A virtual gate is formed on the protective layer; A source region and a drain region are formed in the substrate on both sides of the virtual gate, respectively; An interlayer dielectric layer is formed on the protective layer on both sides of the virtual gate; Remove the dummy gate to form an opening within the interlayer dielectric layer that exposes the protective layer; A metal gate is formed within the opening.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The gate dielectric layer is made of a high dielectric constant material, and the protective layer is made of titanium nitride.

8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The formation process of the substrate and the semiconductor structure includes: Provide substrate; A shallow trench isolation structure is formed within the substrate; An oxide layer is formed on the substrate, and the oxide layer covers the shallow trench isolation structure to form the substrate including the substrate, the shallow trench isolation structure and the oxide layer; The gate dielectric layer is formed on the oxide layer; The sacrificial layer is formed on the gate dielectric layer to form the semiconductor structure.

9. A semiconductor device, characterized in that, It is manufactured using the manufacturing method of any one of claims 1 to 8.

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