Novel vertical field effect transistor structure and manufacturing method

Abstract

The invention discloses a novel vertical field effect transistor structure which comprises an N-type epitaxy and a dielectric layer on the N-type epitaxy, an ohmic contact hole is embedded in the dielectric layer, and a source electrode and a grid electrode of a vertical field effect transistor both utilize metal of the ohmic contact hole as connecting metal; the invention further discloses a manufacturing method of the novel vertical field effect transistor structure, and the manufacturing cost is reduced by saving a layer of photomask.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a novel vertical field effect transistor structure and a manufacturing method thereof. Background Art

[0002] VDMOS, short for vertical field-effect transistor, offers advantages such as low leakage current, fast switching speed, low on-resistance, high voltage withstand capability, and low switching losses. It is widely used in power electronics devices such as inverters, DC-DC converters, and AC motor drives.

[0003] In the traditional structure, a separate metal plate is required to wrap the CT hole so that the source and gate CT holes are covered with metal and connected. Figure 1 As shown, Figure 1 Only the Metal and CT layers are shown, which include the gate metal 10 and the source metal 12. Figure 1 The cross-sectional view of the cell area at the AA' section is as follows Figure 2 As shown, because there is a Metal layer, the cell area is completely covered by metal; because there is a separate Metal layer, the sources of adjacent cells are covered with Metal, as shown in Figure 6 shown.

[0004] As can be seen, traditional VDMOS requires a dedicated metal layer in the cell region to connect the source and gate holes to form electrodes and to form metal field plates in the terminal region to modulate the electric field. However, the additional metal layer increases manufacturing costs. Summary of the Invention

[0005] In order to solve the problems existing in the prior art, the purpose of the present invention is to provide a novel vertical field effect transistor structure and manufacturing method. The present invention reduces the manufacturing cost by saving a layer of mask.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is: a new vertical field-effect transistor structure, including an N-type epitaxial layer and a dielectric layer on the N-type epitaxial layer, wherein an ohmic contact hole is embedded in the dielectric layer, and the source and gate of the vertical field-effect transistor both use the metal of the ohmic contact hole as the connecting metal.

[0007] As a further improvement of the present invention, the connection metal includes a gate hole metal and a source hole metal, and the contacts between the gate hole metal and the source hole metal and the metal of the ohmic contact hole are all hole metal contacts.

[0008] As a further improvement of the present invention, a P-well is provided between the N-type epitaxial layer and the dielectric layer.

[0009] As a further improvement of the present invention, an N-type contact region for implanting N-type ions and a P-type contact region for implanting P-type ions are provided between the P-well and the dielectric layer.

[0010] The present invention also discloses a method for manufacturing a novel vertical field effect transistor structure, comprising the following steps:

[0011] Step 1: On the N-type epitaxial layer, a P-type ring mask is used to implant P-type ions into the terminal region, and a P-type ring is formed by high-temperature push-through to bear the voltage.

[0012] Step 2: After growing field oxide, the active area is etched out through a photomask of the active area, including the cell area and the stop ring;

[0013] Step 3: After growing an oxide layer, N-type ions are implanted to form a JFET region;

[0014] Step 4: After growing the gate oxide, polysilicon is deposited, and then the areas where polysilicon is not needed are etched away through a polysilicon mask;

[0015] Step 5: P-type ions are implanted in a self-aligned manner, and a P-well is formed by high-temperature push-junction.

[0016] Step 6: After growing an oxide layer, N-type ions are implanted through a photomask of N-type ions to form an ohmic contact with the source. After depositing a dielectric layer, P-type ions are implanted, and another dielectric layer is deposited.

[0017] Step 7: Etch out the locations that need to be connected to electrodes through a photomask of a contact hole;

[0018] Step 8: Deposit metal in the metal contact hole to form an electrode, and then only retain the metal in the metal contact hole by etching back.

[0019] The present invention solves the problem of increased manufacturing costs caused by the traditional VDMOS requiring the source and gate to be connected with metal using a separate metal layer through process and layout structure modulation.

[0020] The beneficial effects of the present invention are:

[0021] 1. The present invention provides a novel vertical field-effect transistor structure and manufacturing method, which can significantly reduce manufacturing costs by eliminating the metal layer while ensuring that all electrical parameters of the device are consistent with those of the traditional structure.

[0022] 2. The novel vertical field effect transistor structure and manufacturing method of the present invention can adjust the window size of the CT metal as the source metal contact through the shape and size of the CT on the layout and the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of the structure of the Metal and CT layers of a traditional field-effect transistor;

[0024] Figure 2 for Figure 1 AA' cross-section diagram;

[0025] Figure 3 Schematic diagram of the structure of the CT layer in an embodiment of the present invention;

[0026] Figure 4 for Figure 3 The cell area cross-section of the BB' section;

[0027] Figure 5 for Figure 3 Cross-sectional view of the electrode contact area of ​​CC' section;

[0028] Figure 6 Schematic diagram of a conventional field-effect transistor where the sources of adjacent cells are covered with a metal layer;

[0029] Figure 7 This is a schematic diagram of connecting a separate area marked with CT and a cell area in an embodiment of the present invention.

[0030] Reference numerals:

[0031] 1. N-type epitaxy, 2. Dielectric layer, 3. Ohmic contact hole, 4. Terminal region, 5. Gate hole metal, 6. Source hole metal, 7. P-well, 8. N-type contact region, 9. P-type contact region, 10. Gate metal, 11. Source metal, 12. Polysilicon. DETAILED DESCRIPTION

[0032] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Example

[0034] A novel vertical field-effect transistor structure includes an N-type epitaxial layer 1 and a dielectric layer 2 on the N-type epitaxial layer 1. The dielectric layer 2 is embedded with an ohmic contact hole 3. The source and gate of the vertical field-effect transistor both use the metal in the ohmic contact hole 3 as connecting metal. The connecting metal includes a gate hole metal 5 and a source hole metal 6. The contact between the gate hole metal 5 and the source hole metal 6 and the metal in the ohmic contact hole 3 is all hole metal contact. A P-well 7 is provided between the N-type epitaxial layer 1 and the dielectric layer 2. An N-type contact region 8 for implanting N-type ions and a P-type contact region 9 for implanting P-type ions are provided between the P-well 7 and the dielectric layer 2.

[0035] In this embodiment, the source and gate both use the metal of the CT hole as the connection metal, such as Figure 3 As shown, Figure 3 Only CT layers are displayed. Figure 3 The cross-section of the cell area at section BB' is as follows Figure 4 As shown, since there is no Metal layer, the source of the cell area uses hole metal as ohmic contact. Figure 3 The cross-sectional view of the electrode contact area at CC' section is as follows Figure 5 As shown in the figure, a separate area is required for the source electrode contact, and all the contacts here are hole metal contacts. Because there is one less metal layer, the manufacturing cost is greatly reduced. By connecting the source with the metal of the CT hole, as shown in the figure, Figure 7 As shown in the figure, a separate area needs to be completely marked with CT and connected to the cell area. This can save the metal layer, reduce costs, and simplify the process.

[0036] This embodiment also provides a method for manufacturing a novel vertical field effect transistor structure, comprising the following steps:

[0037] 1. On the N-type epitaxial layer 1, a P-type ring mask is used to inject P-type ions into the terminal area, and a P-type ring is formed by high-temperature push-junction to bear the voltage.

[0038] 2. After growing field oxygen, the active area (AA) is etched out through a photomask of the active area, including the cell area and the cutoff ring.

[0039] 3. After growing an oxide layer, N-type ions are injected to form the JFET region.

[0040] 4. After growing the gate oxide, polysilicon 12 is deposited, and then the areas where polysilicon 12 is not needed are etched away through a layer of polysilicon 12 (poly) mask.

[0041] 5. P-type ions are injected in a self-aligned manner, and a P-well 7 is formed by high-temperature push-junction.

[0042] 6. After growing an oxide layer, N-type ions are injected through a mask of N-type ions (N+) to form an ohmic contact with the source. After depositing a dielectric layer 2, P-type ions are injected and another dielectric layer is deposited.

[0043] 7. Etch out the locations that need to be connected to electrodes through a layer of contact hole (CT) mask.

[0044] 8. Depositing metal: Traditional structures require a separate metal mask to form electrodes. In this structure, metal is deposited directly in the contact holes to form electrodes, and then only the metal in the holes is retained by etching back. The etching back here does not require a mask plate, thus saving a metal mask plate, reducing manufacturing costs, and simplifying the process.

[0045] The above-described embodiments merely represent specific implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

Claims

1. A novel vertical field effect transistor structure, comprising an N-type epitaxial layer and a dielectric layer on the N-type epitaxial layer, wherein an ohmic contact hole is embedded in the dielectric layer, characterized in that: The source and gate of the vertical field effect transistor both use the metal in the ohmic contact hole as connection metal.

2. The novel vertical field effect transistor structure according to claim 1, characterized in that: The connection metal includes a gate hole metal and a source hole metal, and the contacts between the gate hole metal and the source hole metal and the metal of the ohmic contact hole are all hole metal contacts.

3. The novel vertical field effect transistor structure according to claim 1, characterized in that: A P well is provided between the N-type epitaxial layer and the dielectric layer.

4. The novel vertical field effect transistor structure according to claim 3, characterized in that: An N-type contact region for implanting N-type ions and a P-type contact region for implanting P-type ions are provided between the P-well and the dielectric layer.

5. A method for manufacturing a novel vertical field effect transistor structure, characterized in that: The following steps are involved: Step 1: On the N-type epitaxial layer, a P-type ring mask is used to implant P-type ions into the terminal region, and a P-type ring is formed by high-temperature push-through to bear the voltage. Step 2: After growing field oxide, the active area is etched out through a photomask of the active area, including the cell area and the stop ring; Step 3: After growing an oxide layer, N-type ions are implanted to form a JFET region; Step 4: After growing the gate oxide, polysilicon is deposited, and then the areas where polysilicon is not needed are etched away through a polysilicon mask; Step 5: P-type ions are implanted in a self-aligned manner, and a P-well is formed by high-temperature push-junction. Step 6: After growing an oxide layer, N-type ions are implanted through a photomask of N-type ions to form an ohmic contact with the source. After depositing a dielectric layer, P-type ions are implanted, and another dielectric layer is deposited. Step 7: Etch out the locations that need to be connected to electrodes through a photomask of a contact hole; Step 8: Deposit metal in the metal contact hole to form an electrode, and then only retain the metal in the metal contact hole by etching back.

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