Integrated circuit structure and manufacturing method thereof

Abstract

An integrated circuit structure and a method of fabricating the same are provided. The method includes forming a semiconductor device over a semiconductor substrate, wherein the semiconductor device includes a gate structure and first and second source / drain regions; forming a front-side interconnect structure over a front side of the semiconductor device, where the front-side interconnect structure includes a front-side metal wire and a front-side dielectric layer, and the front-side metal wire is electrically connected to the first source / drain region of the semiconductor device; depositing a high-k dielectric layer over a backside of the semiconductor device, wherein the high-k dielectric layer has a dielectric constant greater than 3.9; etching an opening in the high-k dielectric layer to expose a backside of the second source / drain region; and forming a backside metal feature in the opening of the high-k dielectric layer.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to integrated circuit structures and methods of fabricating the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with increasingly smaller and more complex circuits than the previous one. During IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a method for fabricating an integrated circuit structure is provided. The method includes: forming a semiconductor device over a semiconductor substrate, wherein the semiconductor device includes a gate structure and first and second source / drain regions on opposite sides of the gate structure; forming a frontside interconnect structure over a front side of the semiconductor device, wherein the frontside interconnect structure includes a frontside metal line and a frontside dielectric layer, and the frontside metal line is electrically connected to the first source / drain region of the semiconductor device; depositing a first high-k dielectric layer over a backside of the semiconductor device, wherein the first high-k dielectric layer has a dielectric constant greater than 3.9; etching a first opening in the first high-k dielectric layer to expose a backside of the second source / drain region; and forming a first backside metal feature in the first opening in the first high-k dielectric layer.

[0004] According to some embodiments of the present disclosure, a method for fabricating an integrated circuit structure is provided. The method includes forming a semiconductor device over a semiconductor substrate, wherein the semiconductor device includes a gate structure and first and second source / drain regions on opposite sides of the gate structure; forming a frontside interconnect structure over a front side of the semiconductor device, wherein the frontside interconnect structure includes a frontside metal line and a frontside dielectric layer, and the frontside metal line is electrically connected to the first source / drain region of the semiconductor device; depositing a first high-k dielectric layer over a backside of the semiconductor device, wherein a thermal conductivity of the first high-k dielectric layer is greater than 1.4 W / mK; and forming a first backside metal feature in the first high-k dielectric layer.

[0005] According to some embodiments of the present disclosure, an integrated circuit structure includes a semiconductor device, a front metal connection, a front dielectric layer, a back metal connection, and a back dielectric layer. The semiconductor device includes a gate structure and first and second source / drain regions on opposite sides of the gate structure. The front metal connection is located above a front side of the semiconductor device and electrically connected to the first source / drain region of the semiconductor device. The front dielectric layer has a first dielectric constant and surrounds the front metal connection. The back metal connection is located above a back side of the semiconductor device and electrically connected to the second source / drain region of the semiconductor device. The back dielectric layer has a second dielectric constant and surrounds the back metal connection. The second dielectric constant is greater than the first dielectric constant. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of this disclosure are in accordance with the accompanying Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1 to 17 are cross-sectional views of integrated circuit structures at various intermediate fabrication stages according to some embodiments of the present disclosure;

[0008] Figure 18 is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0009] Figure 19 FIG. 1 illustrates a backside multilayer interconnection (MLI) structure according to some embodiments of the present disclosure;

[0010] Figure 20 is a graph of voltage versus time illustrating an integrated circuit structure according to some embodiments of the present disclosure;

[0011] Figures 21 to 23 illustrates a method for fabricating an integrated circuit structure at various intermediate fabrication stages according to some embodiments of the present disclosure;

[0012] Figure 24 FIGURE 1 illustrates a backside MLI structure according to some embodiments of the present disclosure;

[0013] Figure 25 is a diagram illustrating noise reduction in an integrated circuit structure with a backside high-k dielectric according to some embodiments of the present disclosure;

[0014] Figure 26 is a cross-sectional view of a package structure according to some embodiments of the present disclosure;

[0015] Figure 27 is a cross-sectional view of a package structure according to some embodiments of the present disclosure;

[0016] Figure 28A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0017] Figure 28B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0018] Figure 29A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0019] Figure 29B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0020] Figure 30A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0021] Figure 30B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0022] Figure 31A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0023] Figure 31B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0024] Figure 32A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure;

[0025] Figure 32B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure.

[0026]

Explanation of symbols

[0027] 100: Integrated circuit structure

[0028] 110:Substrate

[0029] 120: device layer

[0030] 120D: Interlayer dielectric (ILD) layer

[0031] 140: carrier substrate

[0032] 150: Backside dielectric layer

[0033] 150O: Opening

[0034] 160: conductive layer

[0035] 160': Conductive characteristics

[0036] 162:Metal barrier / adhesion layer

[0037] 162':Metal barrier / adhesion layer

[0038] 164:Metal Materials

[0039] 164':Metal Materials

[0040] 170: Backside dielectric layer

[0041] 170O: Opening

[0042] 170O': Opening

[0043] 180: conductive layer

[0044] 180': Conductive characteristics

[0045] 182:Metal barrier / adhesion layer

[0046] 182':Metal barrier / adhesion layer

[0047] 184:Metal Materials

[0048] 184':Metal Materials

[0049] 200: Insert structure

[0050] 300:Packaging substrate

[0051] 400: Heat dissipation structure

[0052] 410: Thermal interface material

[0053] 500: Integrated circuit structure

[0054] BC: Contact

[0055] BD: Backside Intermetal Dielectric (IMD) layer

[0056] BM:Metal wiring

[0057] BM_VDD: High power rail

[0058] BM_VSS: Low power rail

[0059] BM1: Back side metal connection

[0060] BM2: Back side metal connection

[0061] BM3: Back side metal connection

[0062] BM4: Back-side metal wiring

[0063] BMLI: Backside Multilayer Interconnect (MLI) structure

[0064] BV: Backside Metal Via

[0065] BV1: Backside Metal Via

[0066] BV2: Backside Metal Via

[0067] BV3: Backside Metal Via

[0068] C1: Connector

[0069] C2: Connector

[0070] C3: Connector

[0071] DE:Device

[0072] DM: Backside dummy metal

[0073] DM2: Backside dummy metal

[0074] DM4: Backside dummy metal

[0075] FC: plug

[0076] FD: Front-side intermetal dielectric (IMD) layer

[0077] FM: Metal wiring

[0078] FMLI: Front-side Multilayer Interconnect (MLI) structure

[0079] FV: Metal Through Hole

[0080] G: Gate structure

[0081] NS:Nanosheets

[0082] PM1: resist layer

[0083] PM2: resist layer

[0084] PMO1: Opening

[0085] PMO2: Opening

[0086] PMO2': Opening

[0087] PS1: Package structure

[0088] PS2: Package structure

[0089] RDL1: Redistribution Structure, Redistribution Layer

[0090] RDL2: Redistribution Structure, Redistribution Layer

[0091] RV:Through hole

[0092] SD: Source / Drain Region

[0093] SDE: Epitaxial Characterization

[0094] SDM: Metal / Alloy Characterization

[0095] SUB: Core layer

[0096] SV: Self-aligned front and back vias

[0097] SW: Spacer

[0098] TSVM:Through Silicon Via

[0099] U1: bottom filler

[0100] U2: bottom filler

[0101] Vin: Node

[0102] Vout: Node DETAILED DESCRIPTION

[0103] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are merely examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0104] As used herein, "approximately," "about," "substantially," or "substantially" may generally mean within 20%, or within 10%, or within 5% of a given value or range. The quantities given herein are approximate, meaning that the terms "approximately," "about," "substantially," or "substantially" can be inferred unless explicitly stated. However, those skilled in the art will recognize that the values ​​or ranges recited throughout the description are merely examples and may be reduced or changed as integrated circuits are scaled down.

[0105] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0106] A gate all around (GAA) transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning processes combine photolithography processes with self-aligned processes, thereby allowing patterns to be produced that have, for example, smaller spacing than would otherwise be obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate using a photolithography process and patterned. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0107] The term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) that has at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, a multi-gate device may be referred to as a gate all around (GAA) device or a nanosheet device with gate material disposed on at least four sides of at least one channel of the device. The channel region may be referred to as a "nanowire," which, as used herein, includes channel regions having various geometries (e.g., cylindrical, rod-shaped) and various sizes. In some examples, a multi-gate device may be referred to as a FinFET device. However, one skilled in the art will recognize that the teachings may apply to a single channel (e.g., a single nanosheet) or any number of channels. One skilled in the art may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.

[0108] Figures 1 to 17 is a cross-sectional view of an integrated circuit structure at various intermediate stages of fabrication according to some embodiments of the present disclosure. It should be understood that additional operations may be performed by Figures 1 to 17 The depicted processes are provided before, during, and after, and some of the steps described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchangeable.

[0109] See Figure 1. In some embodiments, a substrate 110 is provided. The substrate 110 may include a substantially single crystal material, such as bulk silicon. In some other embodiments, the substrate 110 may include another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. In some embodiments, the substrate 110 may include an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a layer of semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is disposed on a substrate, such as a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.

[0110] In some embodiments, one or more active and / or passive devices DE are formed on the wafer region of the substrate 110. In the depicted embodiment, the device DE is a gate-all-around (GAA) transistor fabricated using channel stacking technology, and the stacked nanosheets NS can enhance the on-state current (I on ). Figure 1 The cross section in FIG is taken along the longitudinal axis of the nanosheet NS in a direction parallel to the direction of current flow between the source / drain regions SD. The nanosheet NS can be formed by patterning an epitaxial stack comprising alternating sacrificial layers and channel layers disposed above the substrate 110 using optical lithography and etching techniques; and then replacing the sacrificial layers with gate structures G. In some embodiments, as shown in FIG. Figure 1 The gate structure G of the device DE in FIG. 1 may be a high-k metal gate (HKMG) gate structure that may be formed using a gate-last process flow. Figure 1 Two nanosheets NS are shown, although device DE may include any number of nanosheets. In some other embodiments, device DE comprises nanowires. In some other embodiments, device DE may be a planar transistor or a fin field-effect transistor (FinFET). A FinFET is a three-dimensional metal oxide semiconductor field effect transistor (MOSFET) structure formed in a fin-like strip of semiconductor protrusions called fins.

[0111] The source / drain region SD is a semiconductor region in contact with the nanosheet NS. In some embodiments, the source / drain region SD may include a heavily doped region and a relatively lightly doped drain extension. In some embodiments, the source / drain region SD may include an epitaxial growth region. Figure 1 In FIG, the device DE may include spacers SW on opposite sidewalls of the gate structure G. The spacers SW may separate the gate structure G from the source / drain regions SD.

[0112] An interlayer dielectric (ILD) layer 120D may be deposited over the source / drain regions SD. Contact plugs FC may be formed in the ILD layer 120D using photolithography, etching, and deposition techniques. For example, a patterned mask may be formed over the ILD layer 120D and used to etch openings extending through the ILD layer 120D to expose the gate structure G and the source / drain regions SD. A conductive liner may then be formed in the openings in the ILD layer 120D. The openings are then filled with a conductive fill material (e.g., W, Al, Cu, Ru, Ni, Co, alloys thereof, combinations thereof, and the like) using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, or the like, or combinations thereof). A planarization process (e.g., a chemical mechanical process (CMP)) may then be used to remove any excess conductive material from the surface of the ILD layer 120D. The resulting conductive plug FC extends into the ILD layer 120D and forms a contact plug FC, thereby making a physical and electrical connection to the gate structure G or source / drain regions SD of the device DE. In this case, the combination of the device DE, the ILD layer 120D, and the contact plug FC can be referred to as the device layer 120. The device layer 120 can also be referred to as the front-end structure in this case. In some embodiments, one or more devices DE are stacked on top of each other in the device layer 120. For example, an n-type device and a p-type device can be stacked on top of each other as a complementary field-effect transistor (CFET).

[0113] A front-side multilayer interconnect (MLI) structure FMLI is formed on the front side of device layer 120. The front-side MLI structure FMLI may include at least three front-side metallization layers. The number of front-side metallization layers may vary depending on the design specifications of the integrated circuit structure. Each front-side metallization layer includes one or more front-side inter-metal dielectric (IMD) layers FD, one or more horizontal interconnects (e.g., metal wires FM) extending horizontally within each of the IMD layers, and one or more vertical interconnects (e.g., metal vias FV) extending vertically within each of the IMD layers. The metal vias FV connect a lower metal wire among the metal wires FM to an upper metal wire among the metal wires FM. The bottommost metallization layer (e.g., metal wire FM) contacts a front-side contact plug FC to electrically connect signals from the metal wires FM to the source / drain regions SD.

[0114] See Figure 2 . Drawn on Figure 1 The structure in FIG. 1 is bonded to a carrier substrate 140. Carrier substrate 140 is bonded to substrate 110 via the front-side MLI structure FMLI, allowing backside processing of substrate 110 to be performed. In this embodiment, carrier substrate 140 may be similar to substrate 110 and comprise a silicon material. Alternatively, carrier substrate 140 may comprise a glass substrate or another suitable material. Carrier substrate 140 may be bonded to the front-side MLI structure FMLI using molecular forces such as direct bonding or optical fusion bonding, or using other bonding techniques such as metal diffusion or anodic bonding.

[0115] See Figure 3 One or more processes are performed to remove material from the backside of the source / drain regions SD, thereby exposing the backside of the source / drain regions SD. For example, a planarization process (e.g., a CMP process or a grinding process) is performed on the backside of the substrate 110, thereby thinning the substrate 110. In some embodiments, after the planarization process, one or more etching processes are performed to remove the substrate 110.

[0116] See Figures 4 to 17 , Figures 4 to 17 The diagram shows the formation of a backside multilayer interconnection (MLI) structure BMLI on the back side of the device layer 120. Figure 4 The backside dielectric layer 150 is deposited on the backside of the source / drain region SD by, for example, ALD, CVD, PVD, or the like or a combination thereof. The backside dielectric layer 150 may include a high-k dielectric material such as HfO2, ZrO2, HfAlO x 、HfSiO x, Al2O3, Si3N4, AlN, BeO, SiC, diamond, the like, or combinations thereof. In some embodiments, the dielectric constant (k value) of the backside dielectric layer 150 is greater than that of silicon dioxide, which is about 3.9. In some embodiments, the dielectric constant (k value) of the backside dielectric layer 150 is in a range from about 5 to about 10. In some embodiments, the dielectric constant (k value) of the backside dielectric layer 150 may be greater than the dielectric constant (k value) of the IMD layer FD and / or the dielectric constant (k value) of the ILD layer 120D. The backside dielectric layer 150 may be an amorphous dielectric layer, a polycrystalline dielectric layer, a crystalline dielectric layer, or combinations thereof.

[0117] The material of the high-k backside dielectric layer 150 may be selected to have good thermal conductivity (κ th In some embodiments, the thermal conductivity (κ th value) is greater than the thermal conductivity of silicon oxide (κ th For example, the high-k backside dielectric layer 150 may include AlN, BeO, SiC, diamond, the like, or a combination thereof. In some embodiments, the thermal conductivity (κ th In some embodiments, the thermal conductivity (κ) of the backside dielectric layer 150 is in the range of about 50 W / mK to about 1200 W / mK. th value) can be greater than the thermal conductivity of the IMD layer FD (κ th value) and / or the thermal conductivity (κ th In this case, the thermal conductivity (κ th The thermal conductivity (κ) is the ease with which heat is transferred across a material. th Thermal conductivity (κ) is a fundamental property that is independent of the material quantity. Thermal conductivity can be expressed as the steady-state heat flow through a unit area of ​​material resulting from a temperature gradient perpendicular to that unit area. th value) can be expressed in W / mK.

[0118] In some other embodiments, the high-k backside dielectric layer 150 may be selected without regard to thermal conductivity (κ th For example, the high-k backside dielectric layer 150 may include Al2O3, Si3N4, or the like, or a combination thereof. In some embodiments, the thermal conductivity (κ th The thermal conductivity (κ) of the back dielectric layer 150 may be in the range of about 1 W / mK to about 50 W / mK. th The thermal conductivity of the IMD layer FD (κ th value) and / or the thermal conductivity (κ th value).

[0119] See Figure 5 and Figure 6 A lithography process (e.g., optical lithography or electron beam lithography) is performed to form a resist layer PM1 having an opening PMO1 over the backside dielectric layer 150. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The opening PMO1 may be vertically aligned with the backside of the source / drain region SD of the device DE.

[0120] See Figure 7 The backside dielectric layer 150 is etched using the resist layer PM1 as an etching mask, thereby creating an opening 150O in the backside dielectric layer 150. The etching process may include dry etching (e.g., reactive ion etching), wet etching, or a combination thereof. The opening 150O may expose the backside of the source / drain region SD. After the etching process, the resist layer PM1 is removed from the backside dielectric layer 150 by a suitable ashing and / or stripping process, and the resulting structure is shown in FIG. Figure 8 middle.

[0121] See Figure 9 A metal material 164 is deposited over the backside dielectric layer 150 and into the opening 150O. In some embodiments, the metal material 164 may include Al, W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, combinations thereof, or the like. The metal material is deposited to fill the opening 150O using a suitable deposition technique (e.g., CVD, PVD, ALD, sputtering, electroplating, the like, or combinations thereof). In some embodiments, prior to depositing the metal material 164, one or more metal barrier / adhesion layers 162 may be conformally deposited over the backside dielectric layer 150 and into the opening 150O. The one or more metal barrier / adhesion layers 162 may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using PVD, sputtering, electroplating, ALD, or the like. The one or more metal barrier / adhesion layers 162 may protect the backside dielectric layer 150 from metal diffusion (e.g., copper diffusion) and metal poisoning. The combination of the metal barrier / adhesion layer 162 and the metal material 164 may be referred to as a conductive layer 160 .

[0122] See Figure 10 A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess metal material outside the opening 150O while leaving metal material in the opening 150O to serve as the backside contact BC. For example, the first portion of the metal barrier / adhesion layer 162 and the first portion of the metal material 164 outside the opening 150O (see FIG. Figure 9) is removed, and the second portion of the metal barrier / adhesion layer 162 and the second portion of the metal material 164 in the opening 150O (see Figure 9 ) is maintained. The remaining second portion of the metal barrier / adhesion layer 162 and the remaining second portion of the metal material 164 (see Figure 9 ) may be referred to as metal barrier / adhesion layer 162′ and metal material 164′. The combination of metal barrier / adhesion layer 162′ and metal material 164′ may be referred to as conductive feature 160′, thereby forming backside contact BC. In some embodiments, the shape of backside contact BC may include circular, rectangular, oval, diamond, or the like when viewed from the top.

[0123] See Figure 11 The backside dielectric layer 170 is deposited over the backside dielectric layer 150 and the backside contact BC by, for example, ALD, CVD, PVD, or the like or a combination thereof. The backside dielectric layer 170 may include a high-k dielectric material such as HfO2, ZrO2, HfAlO x 、HfSiO x , Al2O3, Si3N4, AlN, BeO, SiC, diamond, the like, or combinations thereof. In some embodiments, the dielectric constant (k value) of the backside dielectric layer 170 is greater than that of silicon dioxide, which is about 3.9. In some embodiments, the dielectric constant (k value) of the backside dielectric layer 150 is in a range from about 5 to about 100. In some embodiments, the dielectric constant (k value) of the backside dielectric layer 170 may be greater than the dielectric constant (k value) of the IMD layer FD and / or the dielectric constant (k value) of the ILD layer 120D. The backside dielectric layer 170 may be an amorphous dielectric layer, a polycrystalline dielectric layer, a crystalline dielectric layer, or combinations thereof.

[0124] The material of the high-k backside dielectric layer 170 may be selected to have good thermal conductivity (κ th In some embodiments, the thermal conductivity (κ th value) is greater than the thermal conductivity of silicon oxide (κ th For example, the high-k backside dielectric layer 170 may include AlN, BeO, SiC, diamond, the like, or a combination thereof. In some embodiments, the thermal conductivity (κ th In some embodiments, the thermal conductivity (κ) of the backside dielectric layer 170 is in the range of 100 W / mK to about 3000 W / mK. th value) can be greater than the thermal conductivity of the IMD layer FD (κ th value) and / or the thermal conductivity (κ th value).

[0125] In some other embodiments, the high-k backside dielectric layer 170 may be selected without regard to thermal conductivity (κ th For example, the high-k backside dielectric layer 170 may include Al2O3, Si3N4, the like, or a combination thereof. In such embodiments, the thermal conductivity (κ) of the backside dielectric layer 170 is th value) can be less than the thermal conductivity of silicon oxide (κ th In such embodiments, the thermal conductivity (κ th The thermal conductivity of the IMD layer FD (κ th value) and / or the thermal conductivity (κ th value).

[0126] In some embodiments, the backside dielectric layer 170 may have the same material as the backside dielectric layer 150 and thus have the same dielectric constant (k value) and thermal conductivity (κ th In some alternative embodiments, the backside dielectric layer 170 may have a different material than the material of the backside dielectric layer 150 and thus have a different dielectric constant (k value) and a different thermal conductivity (κ th value).

[0127] See Figure 12 and Figure 13 A lithography process (e.g., optical lithography or electron beam lithography) is performed to form a resist layer PM2 having openings PMO2 over the backside dielectric layer 170. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. Openings PMO2 may be vertically aligned with the backside contacts BC and the backside of the source / drain regions SD of the device DE.

[0128] See Figure 14 The backside dielectric layer 170 is etched using the resist layer PM2 as an etch mask, thereby creating an opening 170O in the backside dielectric layer 170. The etching process may include dry etching (e.g., reactive ion etching), wet etching, or a combination thereof. The opening 170O may expose the backside of the backside contact BC. After the etching process, the resist layer PM2 is removed from the backside dielectric layer 170 by a suitable ashing and / or stripping process, and the resulting structure is shown in FIG. Figure 15 middle.

[0129] See Figure 16A metal material 184 is deposited over the backside dielectric layer 170 and into the opening 170O. In some embodiments, the metal material 184 may include Al, W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, combinations thereof, or the like. The metal material is deposited to fill the opening 170O using a suitable deposition technique (e.g., CVD, PVD, ALD, sputtering, electroplating, the like, or combinations thereof). In some embodiments, prior to depositing the metal material 184, one or more metal barrier / adhesion layers 182 may be conformally deposited over the backside dielectric layer 170 and into the opening 170O. The one or more metal barrier / adhesion layers 182 may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using PVD, sputtering, electroplating, ALD, or the like. The one or more metal barrier / adhesion layers 182 may protect the backside dielectric layer 170 from metal diffusion (e.g., copper diffusion) and metal poisoning. The combination of the metal barrier / adhesion layer 182 and the metal material 184 may be referred to as a conductive layer 180 .

[0130] See Figure 17 A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess metal material outside the opening 170O while leaving metal material in the opening 170O to serve as the backside metal wiring BM. For example, the first portion of the metal barrier / adhesion layer 182 and the first portion of the metal material 184 outside the opening 170O (see FIG. Figure 16 ) is removed, and the second portion of the metal barrier / adhesion layer 182 and the second portion of the metal material 184 in the opening 170O (see Figure 16 ) is maintained. The remaining second portion of the metal barrier / adhesion layer 182 and the remaining second portion of the metal material 184 (see Figure 16 ) may be referred to as metal barrier / adhesion layer 182′ and metal material 184′. The combination of metal barrier / adhesion layer 182′ and metal material 184′ may be referred to as conductive feature 180′, thereby forming backside contact BC. In some embodiments, the shape of backside metal connection BM may include a circle, rectangle, oval, diamond, or the like when viewed from the top. Figures 4 to 17 The back side metallization layer is formed into a back side MLI structure BMLI. In some embodiments, by repeating the Figures 4 to 17 In the step of , a plurality of backside metallization layers are formed and stacked on each other, and the backside MLI structure BMLI may include a plurality of metallization layers.

[0131] Figure 18is a schematic diagram of an integrated circuit structure 100 according to some embodiments of the present disclosure. The integrated circuit structure 100 includes a device layer 120, a front-side MLI structure FMLI, and a back-side MLI structure BMLI. As shown above, the front-side MLI structure FMLI is formed over the front side of the device layer 120, and the back-side MLI structure BMLI is formed over the back side of the device layer 120. The back-side MLI structure BMLI may include one or more back-side metallization layers. The number of back-side metallization layers may vary according to the design specifications of the integrated circuit structure. The back-side metallization layers each include one or more back-side inter-metal dielectric (IMD) layers BD, one or more horizontal interconnects (e.g., back-side metal wires BM) extending horizontally in the IMD layers, and one or more vertical interconnects (e.g., back-side metal vias BV or back-side metal contacts BC) extending vertically in the IMD layers. The back-side metal vias BV connect a lower metal wire in the back-side metal wires BM to an upper back-side metal wire in the back-side metal wires BM. In some embodiments, the bottommost metallization layer (e.g., backside metal contact BC) contacts the source / drain regions SD to provide an electrical connection to the source / drain regions SD from the backside metal wire BM. In this case, the backside dielectric layers 150 and 170 can be referred to as backside IMD layers BD. In some embodiments, the height of the backside metal wire BM is greater than the height of the frontside metal wire FM, and thus the height of the backside IMD layer BD can be greater than the height of the frontside IMD layer FD.

[0132] Figure 19 The diagram illustrates a backside MLI structure BMLI according to some embodiments of the present disclosure. The backside MLI structure BMLI may include four metallization layers. The first metallization layer includes a backside metal wire BM1 and a backside metal contact BC. The second metallization layer includes a backside metal wire BM2 and a backside metal via BV1. The third metallization layer includes a backside metal wire BM3 and a backside metal via BV2. The fourth metallization layer includes a backside metal wire BM4 and a backside metal via BV3. A first of the backside metal wires (e.g., a first of the backside metal wires BM4) may be connected to a high power node, thereby serving as a high power rail BM_VDD. A second of the backside metal wires (e.g., a second of the backside metal wires BM4) may be connected to a low power node, thereby serving as a low power rail BM_VSS.

[0133] Figure 20 is a graph of voltage versus time for an integrated circuit structure according to some embodiments of the present disclosure. For example, Figure 19 In the integrated circuit structure including the backside MLI structure BMLI, the node Vin is connected to the high power rail BM_VDD, and the node Vout is measured. Figure 20In FIG. 1 , the condition “Vin” indicates an input voltage (e.g., a sine wave) at the node Vin. The condition “Vout_1” indicates an output voltage at the node Vout for an integrated circuit structure that includes a low-k backside dielectric layer in the backside MLI structure BMLI. The low-k backside dielectric layer may include silicon oxide. The condition “Vout_2” indicates an output voltage at the node Vout for an integrated circuit structure that includes a high-k backside dielectric layer in the backside MLI structure BMLI. In some embodiments, the high-k backside dielectric layer may be selected to have good thermal conductivity (κ th value), such as AlN, BeO, SiC, diamond, etc. In some embodiments, the high-k backside dielectric layer can be selected without considering the thermal conductivity (κ th value), such as Al2O3, Si3N4, etc. Figure 20 As shown in FIG. 1 , the amplitude of the condition “Vout_2” is smaller than that of the condition “Vout_2”. It can be further inferred that the high-k dielectric can reduce the ground rail voltage bounce noise.

[0134] Figures 21 to 23 The method for manufacturing an integrated circuit structure according to some embodiments of the present disclosure is shown in various intermediate manufacturing stages. Figures 1 to 17 Except that the backside dummy metal DM is formed in the backside dielectric layer 170 and adjacent to the backside metal line BM.

[0135] See Figure 21 . A lithography process (e.g., optical lithography or electron beam lithography) is performed to form a resist layer PM2 having openings PMO2 and PMO2′ over the back dielectric layer 170. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The opening PMO2 may be vertically aligned with the back contact BC and the back side of the source / drain region SD of the device DE. The opening PMO2′ may be adjacent to the opening PMO2. The opening PMO2′ may not be vertically aligned with the back contact BC.

[0136] After forming the resist layer PM2, the backside dielectric layer 170 is etched using the resist layer PM2 as an etch mask, thereby creating openings 170O and 170O' in the backside dielectric layer 170. The opening 170O can expose the back side of the backside contact BC. The opening 170O' can expose the backside dielectric layer 150 without exposing any functional features. After the etching process, the resist layer PM2 is removed from the backside dielectric layer 170 by a suitable ashing and / or stripping process.

[0137] See Figure 22A metal material 184 is deposited over the backside dielectric layer 170 and into the openings 170O and 170O'. In some embodiments, one or more metal barrier / adhesion layers 182 may be conformally deposited over the backside dielectric layer 170 and into the openings 170O and 170O' prior to depositing the metal material 184. The one or more metal barrier / adhesion layers 182 may protect the backside dielectric layer 170 from metal diffusion (e.g., copper diffusion) and metal poisoning.

[0138] See Figure 23 A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess metal material outside the openings 170O and 170O' while leaving metal material in the openings 170O and 170O'. For example, the first portion of the metal barrier / adhesion layer 182 and the first portion of the metal material 184 outside the openings 170O and 170O' (see FIG. Figure 16 ) is removed, and the second portion of the metal barrier / adhesion layer 182 and the second portion of the metal material 184 in the openings 170O and 170O′ (see Figure 16 ) is maintained. The remaining second portion of the metal barrier / adhesion layer 182 and the remaining second portion of the metal material 184 (see Figure 16 ) can be referred to as a metal barrier / adhesion layer 182' and a metal material 184'. The metal barrier / adhesion layer 182' and the metal material 184' in the opening 170O can form a backside metal wiring BM. The metal barrier / adhesion layer 182' and the metal material 184' in the opening 170O can form a backside dummy metal DM adjacent to the metal wiring BM. The backside dielectric layer 170 can separate the backside metal wiring BM from the backside dummy metal DM. Through the configuration of the backside metal wiring BM, the backside dielectric layer 170 and the backside dummy metal DM, a vertical metal-insulator-metal (MIM) structure is formed, thereby increasing parasitic capacitance. Other details of this embodiment are similar to Figures 1 to 17 Those details are illustrated in the embodiments of the present invention and therefore are not repeated herein.

[0139] Figure 24 The figure illustrates a backside MLI structure BMLI according to some embodiments of the present disclosure. The backside MLI structure BMLI may include four metallization layers. The first metallization layer includes a backside metal wire BM1 and a backside metal contact BC. The second metallization layer includes a backside metal wire BM2, a backside dummy metal DM2, and a backside metal via BV1. The third metallization layer includes a backside metal wire BM3 and a backside metal via BV2. The fourth metallization layer includes a backside metal wire BM4, a backside dummy metal DM4, and a backside metal via BV3. The configuration of the backside dummy metals DM2 and DM4 creates a vertical MIM structure, thereby increasing parasitic capacitance.

[0140] Figure 25 is a graph illustrating noise reduction for an integrated circuit structure with a backside high-k dielectric according to some embodiments of the present disclosure. The noise reduction can be calculated as the result of a division by taking the maximum value of the input voltage at the node Vin (see Figure 19 and Figure 24 ) and the maximum value of the output voltage at the node Vout (see Figure 19 and Figure 24 ) divided by the amplitude of the input voltage at node Vin (see Figure 19 and Figure 24 ). Condition #1 is indicated as shown in Figure 19 The noise of the integrated circuit structure including the high-k backside dielectric layer but without the MIM structure is reduced. Condition #2 indicates that the Figure 24 The noise reduction of the integrated circuit structure with the high-k backside dielectric layer and the MIM structure in the backside MLI structure BMLI is shown in FIG. The dotted line DL indicates the noise reduction of the integrated circuit structure including the low-k backside dielectric layer without the MIM structure and the high-k backside dielectric layer. Figure 25 In the embodiment of the present invention, compared to the integrated circuit structure using a low-k backside dielectric layer (e.g., the case indicated by the dashed line DL), the integrated circuit structure including a high-k backside dielectric layer has a greater noise reduction (e.g., Case #1 and Case #2) than the integrated circuit structure using a low-k backside dielectric layer (e.g., the case indicated by the dashed line DL), for example, by about 2 to about 4 times. In addition, compared to the integrated circuit structure without the MIM structure (e.g., Case #1), the integrated circuit structure with the MIM structure has a greater noise reduction (e.g., Case #2). It can be inferred that the vertical MIM structure can increase parasitic capacitance.

[0141] Figure 26 FIG1 is a cross-sectional view of a package structure PS1 according to some embodiments of the present disclosure. The package structure PS1 includes an integrated circuit structure 100, an interposer structure 200, a package substrate 300, and a heat dissipation structure 400. In this embodiment, the integrated circuit structure 100 is formed by forming a backside MLI structure BMLI (see FIG1 ). Figure 17 and Figure 23) is performed after a singulation process. Each of the semiconductor dies (e.g., the integrated circuit structure 100) may include a front-side MLI structure FMLI, a device layer 120, and a back-side MLI structure BMLI using a high-k back-side dielectric layer. The interposer structure 200 may include a core layer SUB, a plurality of through-vias RV formed in the core layer SUB, and redistribution structures RDL1 and RDL2 on opposite sides of the core layer SUB. In some embodiments, the core layer SUB is a substrate such as a bulk semiconductor substrate (e.g., a silicon substrate), a silicon-on-insulator (SOI) substrate, or a multi-layer semiconductor material substrate. The redistribution layer RDL1 may include one or more dielectric layers and one or more conductive layers sandwiched between the dielectric layers and electrically and physically connected to the connector C1. The redistribution layer RDL2 may include one or more dielectric layers and one or more conductive layers sandwiched between the dielectric layers and electrically and physically connected to the connector C2.

[0142] The integrated circuit structure 100 is connected to the redistribution structure RDL1 of the interposer structure 200 by the connector C1. The package substrate 300 is connected to the redistribution structure RDL2 of the interposer structure 200 by the connector C2. In some embodiments, the package substrate 300 is a printed circuit board including a metallization layer, and the through-vias are embedded in the package substrate 300 and together provide the wiring function of the package substrate 300. The high-k backside dielectric layer of the backside MLI structure BMLI may have a high thermal conductivity (κ th This reduces thermal resistance and thus bonding temperature. In some embodiments of the present disclosure, a backside MLI structure (BMLI) using a high-k backside dielectric layer is placed near the interposer structure 200, thereby receiving power from the package substrate 300 with good heat dissipation capabilities.

[0143] In some embodiments, the heat dissipation structure 400 is a heat sink comprising a base and a plurality of fin structures supported by the base. The heat dissipation structure 400 is attached to the integrated circuit structure 100 by a thermal interface material 410. In some embodiments, the thermal interface material 410 may be a polymer having good thermal conductivity (Tk). In some embodiments, the thermal interface material 410 may include a polymer with a thermally conductive filler. Suitable thermally conductive filler materials may include aluminum oxide, boron nitride, aluminum nitride, aluminum, copper, silver, indium, combinations thereof, or the like. In other embodiments, the thermal interface material 410 may include other materials, such as metal-based or solder-based materials including silver, indium paste, or the like.

[0144] An underfill U1 may be formed to cover the electrical connector C1 and fill the space between the semiconductor die (eg, the integrated circuit structure 100 ) and the interposer structure 200 . An underfill U2 may be formed to cover the electrical connector C2 and fill the space between the interposer structure 200 and the package substrate 300 .

[0145] Figure 27 is a cross-sectional view of the package structure PS2 according to some embodiments of the present disclosure. The details of this embodiment are similar to Figure 26 The details shown in FIG. 1 are as follows, except that the package structure PS2 further includes another integrated circuit structure (or another semiconductor die) 500 stacked on the integrated circuit structure 100. As mentioned above, the integrated circuit structure 100 is a semiconductor die obtained by a singulation process performed after forming the backside MLI structure BMLI (see FIG. Figure 17 and Figure 23 ). The semiconductor die (e.g., the integrated circuit structure 100) may include a front-side MLI structure FMLI, a device layer 120, and a back-side MLI structure BMLI using a high-k back-side dielectric layer. The integrated circuit structure 500 is bonded to the integrated circuit structure 100 by a connector C3. The heat dissipation structure 400 is attached to the integrated circuit structure 500 by a thermal interface material 410. Other details of this embodiment are similar to Figure 26 Those details are illustrated in FIG and therefore are not repeated herein.

[0146] Figure 28A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 17 The details shown are similar to those shown above, except that the source / drain regions SD are electrically connected to the backside metal wiring BM via through-silicon vias (TSVMs). The through-silicon vias (TSVMs) may be formed in the device layer 120. The through-silicon vias (TSVMs) may extend from the bottom of the front-side MLI structure FMLI to the backside metal wiring BM. In some embodiments, the through-silicon vias (TSVMs) may laterally contact the source / drain regions SD, thereby establishing an electrical (power) connection. As mentioned above, the backside metal wiring BM is surrounded by the high-k backside IMD layer (BD). Other details of the present disclosure are similar to those shown above and are therefore not repeated here. In this case, the source / drain regions SD may include epitaxial features (SDE) and metal / alloy features (SDM).

[0147] Figure 28B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 28AThe details shown in the figure are the same, except that the backside dummy metal DM is used in this embodiment. As mentioned above, the backside metal line BM and the backside dummy metal DM are surrounded by the high-k backside IMD layer BD. The other details of this disclosure are similar to those shown above and are therefore not repeated here.

[0148] Figure 29A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 17 The details shown in the figure are the same, except that the source / drain regions SD are electrically connected to the backside metal wiring BM by self-aligned front and back vias SV, which can serve as embedded power rails. The self-aligned front and back vias SV can be formed in the device layer 120. The self-aligned front and back vias SV can be manufactured from the front side of the substrate in a self-aligned manner. For example, the conductive material of the self-aligned front and back vias SV is deposited into the deep source / drain openings and etched back to lower the top surface of the self-aligned front and back vias SV, followed by forming the source / drain regions SD in the deep source / drain openings and above the self-aligned front and back vias SV. As mentioned above, the backside metal wiring BM is surrounded by the high-k backside IMD layer BD. Other details of this embodiment are similar to those shown in the figures above and are therefore not repeated herein.

[0149] Figure 29B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 29A The details shown in the figure are the same, except that the backside dummy metal DM is used in this embodiment. As mentioned above, the backside metal line BM and the backside dummy metal DM are surrounded by the high-k backside IMD layer BD. The other details of this disclosure are similar to those shown above and are therefore not repeated here.

[0150] Figure 30A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 17 The details discussed above are the same, except that the back contact BC connecting the source / drain region SD to the back metal wire BM is connected only to the bottom of the epitaxial feature SDE in the source / drain region SD. Conversely, the back contact BC does not contact the metal / alloy feature SDM in the source / drain region SD. As mentioned above, the back metal wire BM is surrounded by the high-k back IMD layer BD. Other details of this disclosure are similar to those described above and are therefore not repeated here.

[0151] Figure 30B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 30AThe details shown in the figure are the same, except that the backside dummy metal DM is used in this embodiment. As mentioned above, the backside metal line BM and the backside dummy metal DM are surrounded by the high-k backside IMD layer BD. The other details of this disclosure are similar to those shown above and are therefore not repeated here.

[0152] Figure 31A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 30A The details discussed above are the same, except that the back contact BC connecting the source / drain region SD to the back metal wire BM is connected to both the bottom of the epitaxial feature SDE in the source / drain region SD and the bottom of the metal / alloy feature SDM in the source / drain region SD. As mentioned above, the back metal wire BM is surrounded by the high-k back IMD layer BD. Other details of the present disclosure are similar to those described above and are therefore not repeated here.

[0153] Figure 31B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 31A The details shown in the figure are the same, except that the backside dummy metal DM is used in this embodiment. As mentioned above, the backside metal line BM and the backside dummy metal DM are surrounded by the high-k backside IMD layer BD. The other details of this disclosure are similar to those shown above and are therefore not repeated here.

[0154] Figure 32A is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 31A The details shown in the figure are similar to those shown above, except that the size of the back contact BC is enlarged by reducing the gate cut and increasing the width of the active region. Other details of the present disclosure are similar to those shown in the figure above, and therefore are not repeated here.

[0155] Figure 32B is a schematic diagram of an integrated circuit structure according to some embodiments of the present disclosure. The details of this embodiment are similar to those described above. Figure 32A The details shown in the figure are the same, except that the backside dummy metal DM is used in this embodiment. As mentioned above, the backside metal line BM and the backside dummy metal DM are surrounded by the high-k backside IMD layer BD. The other details of this disclosure are similar to those shown above and are therefore not repeated here.

[0156] Based on the above discussion, it can be seen that the present disclosure provides advantages to integrated circuit structures. However, it should be understood that other embodiments may provide additional advantages, that not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. Another advantage is that the backside power delivery structure utilizes an insulator with a high dielectric constant to increase capacitance, thereby enhancing noise reduction, which in turn stabilizes the power wiring. Another advantage is that the backside power delivery structure utilizes an insulator with a high thermal conductivity to improve heat dissipation. Yet another advantage is that the integrated circuit structure may further include a vertical MIM structure to increase parasitic capacitance, thereby enhancing noise reduction.

[0157] According to some embodiments of the present disclosure, a method for fabricating an integrated circuit structure is provided. The method includes: forming a semiconductor device over a semiconductor substrate, wherein the semiconductor device includes a gate structure and first and second source / drain regions on opposite sides of the gate structure; forming a frontside interconnect structure over a front side of the semiconductor device, wherein the frontside interconnect structure includes a frontside metal line and a frontside dielectric layer, and the frontside metal line is electrically connected to the first source / drain region of the semiconductor device; depositing a first high-k dielectric layer over a backside of the semiconductor device, wherein the first high-k dielectric layer has a dielectric constant greater than 3.9; etching a first opening in the first high-k dielectric layer to expose a backside of the second source / drain region; and forming a first backside metal feature in the first opening in the first high-k dielectric layer.

[0158] In some embodiments, the dielectric constant of the first high-k dielectric layer is in a range of 5 to 10.

[0159] In some embodiments, the dielectric constant of the first high-k dielectric layer is greater than a dielectric constant of the front dielectric layer.

[0160] In some embodiments, forming the first backside metal feature includes depositing a metal material in the first high-k dielectric layer and into the first opening in the first high-k dielectric layer; and planarizing the metal material until the first high-k dielectric layer is exposed.

[0161] In some embodiments, the method further includes depositing a metal barrier layer into the first opening in the first high-k dielectric layer before depositing the metal material.

[0162] In some embodiments, the method further includes depositing a second high-k dielectric layer over the second high-k dielectric layer, wherein the second high-k dielectric layer has a dielectric constant greater than 3.9; etching a second opening in the second high-k dielectric layer to expose the first backside metal feature; and forming a second backside metal feature over the first backside metal feature.

[0163] In some embodiments, forming the second backside metal feature includes depositing a metal material over the second high-k dielectric layer and into the second opening in the second high-k dielectric layer; and planarizing the metal material until the second high-k dielectric layer is exposed.

[0164] In some embodiments, the first high-k dielectric layer and the second high-k dielectric layer include different materials.

[0165] In some embodiments, the first high-k dielectric layer and the second high-k dielectric layer include the same material.

[0166] According to some embodiments of the present disclosure, a method for fabricating an integrated circuit structure is provided. The method includes forming a semiconductor device over a semiconductor substrate, wherein the semiconductor device includes a gate structure and first and second source / drain regions on opposite sides of the gate structure; forming a frontside interconnect structure over a front side of the semiconductor device, wherein the frontside interconnect structure includes a frontside metal line and a frontside dielectric layer, and the frontside metal line is electrically connected to the first source / drain region of the semiconductor device; depositing a first high-k dielectric layer over a backside of the semiconductor device, wherein a thermal conductivity of the first high-k dielectric layer is greater than 1.4 W / mK; and forming a first backside metal feature in the first high-k dielectric layer.

[0167] In some embodiments, the thermal conductivity of the first high-k dielectric layer is in a range of 50 W / mK to 1200 W / mK.

[0168] In some embodiments, the thermal conductivity of the first high-k dielectric layer is greater than a thermal conductivity of the front dielectric layer.

[0169] In some embodiments, the method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein a thermal conductivity of the second high-k dielectric layer is greater than 1.4 W / mK; and forming a second backside metal feature in the second high-k dielectric layer and over the first backside metal feature.

[0170] In some embodiments, the thermal conductivity of the second high-k dielectric layer is greater than the thermal conductivity of the front-side dielectric layer.

[0171] According to some embodiments of the present disclosure, an integrated circuit structure includes a semiconductor device, a front metal connection, a front dielectric layer, a back metal connection, and a back dielectric layer. The semiconductor device includes a gate structure and first and second source / drain regions on opposite sides of the gate structure. The front metal connection is located above a front side of the semiconductor device and electrically connected to the first source / drain region of the semiconductor device. The front dielectric layer has a first dielectric constant and surrounds the front metal connection. The back metal connection is located above a back side of the semiconductor device and electrically connected to the second source / drain region of the semiconductor device. The back dielectric layer has a second dielectric constant and surrounds the back metal connection. The second dielectric constant is greater than the first dielectric constant.

[0172] In some embodiments, the second dielectric constant of the backside dielectric layer is greater than 3.9.

[0173] In some embodiments, a thermal conductivity of the backside dielectric layer is in a range of 50 W / mK to 1200 W / mK.

[0174] In some embodiments, a thermal conductivity of the backside dielectric layer is greater than a thermal conductivity of the frontside dielectric layer.

[0175] In some embodiments, the backside dielectric layer and the backside metal wiring form a backside interconnect structure, and the integrated circuit structure further includes an interposer structure combined with the backside interconnect structure.

[0176] In some embodiments, a height of the backside metal wiring is greater than a height of the frontside metal wiring.

[0177] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and replacements may be made herein for such equivalent constructions without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing an integrated circuit structure, characterized in that Include: forming a semiconductor device over a semiconductor substrate, wherein the semiconductor device comprises a gate structure and first and second source / drain regions on opposite sides of the gate structure; forming a front-side interconnect structure over a front side of the semiconductor device, wherein the front-side interconnect structure comprises a front-side metal wire and a front-side dielectric layer, and the front-side metal wire is electrically connected to the first source / drain region of the semiconductor device; Depositing a first high-k dielectric layer over a backside of the semiconductor device, wherein the first high-k dielectric layer has a dielectric constant greater than 3.9; etching a first opening in the first high-k dielectric layer to expose a back side of the second source / drain region; and A first backside metal feature is formed in the first opening of the first high-k dielectric layer.

2. The method according to claim 1, wherein The dielectric constant of the first high-k dielectric layer is in a range of 5 to 10.

3. The method according to claim 1, wherein The dielectric constant of the first high-k dielectric layer is greater than a dielectric constant of the front dielectric layer.

4. The method according to claim 1, wherein The step of forming the first backside metal feature comprises: depositing a metal material in the first high-k dielectric layer and into the first opening in the first high-k dielectric layer; and The metal material is planarized until the first high-k dielectric layer is exposed.

5. A method for manufacturing an integrated circuit structure, characterized in that Include: forming a semiconductor device over a semiconductor substrate, wherein the semiconductor device comprises a gate structure and first and second source / drain regions on opposite sides of the gate structure; forming a front-side interconnect structure over a front side of the semiconductor device, wherein the front-side interconnect structure comprises a front-side metal wire and a front-side dielectric layer, and the front-side metal wire is electrically connected to the first source / drain region of the semiconductor device; depositing a first high-k dielectric layer over a backside of the semiconductor device, wherein a thermal conductivity of the first high-k dielectric layer is greater than 1.4 W / mK; and A first backside metal feature is formed in the first high-k dielectric layer.

6. The method according to claim 5, wherein The thermal conductivity of the first high-k dielectric layer is in a range of 50 W / mK to 1200 W / mK.

7. The method according to claim 5, wherein The thermal conductivity of the first high-k dielectric layer is greater than the thermal conductivity of the front dielectric layer.

8. An integrated circuit structure, characterized in that: Include: A semiconductor device comprising a gate structure and first and second source / drain regions on opposite sides of the gate structure; a front side metal connection over a front side of the semiconductor device and electrically connected to the first source / drain region of the semiconductor device; a front dielectric layer having a first dielectric constant and surrounding the front metal wiring; a backside metal connection over a backside of the semiconductor device and electrically connected to the second source / drain region of the semiconductor device; and A backside dielectric layer has a second dielectric constant and surrounds the backside metal wiring, wherein the second dielectric constant is greater than the first dielectric constant.

9. The integrated circuit structure according to claim 8, wherein: The second dielectric constant of the back dielectric layer is greater than 3.

9.

10. The integrated circuit structure according to claim 8, wherein: The thermal conductivity of the back dielectric layer is greater than the thermal conductivity of the front dielectric layer.

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