Formation method of semiconductor structure
By fabricating the gate oxide layer in steps and utilizing a third silicon oxide layer with a high etching selectivity, the gate oxide quality and cost issues in the fabrication of BCD and SGT devices on the chip are resolved, achieving higher chip performance and lower manufacturing costs.
Patent Information
- Application Number
- CN202510906146.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-01
- Publication Date
- 2025-09-30
AI Technical Summary
When the prior art manufactures BCD devices and SGT devices simultaneously on a single chip, there are problems such as reduced gate oxide layer quality and increased manufacturing costs.
The method of manufacturing the first gate oxide layer and the second gate oxide layer in steps is adopted. By forming a third silicon oxide layer after planarization, the silicon nitride layer is removed and the second gate layer is formed with a high etching selectivity, thereby avoiding the increase of the mask process.
The formation quality of the gate oxide layer is improved, the manufacturing cost is reduced, and the use of the photomask process is reduced.
Smart Images
Figure CN120730801A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art
[0002] IPD, short for Intelligent Power Device, refers to a high-performance semiconductor power switch with built-in protection circuitry that can absorb energy from inductive loads. It is also known as a smart switch or high-side / low-side switch. With the rise of software-based automation, autonomous driving, and functional safety, high-side switches are rapidly replacing fuses, which lack software configuration capabilities, low reliability, and diagnostic capabilities.
[0003] The BCD (Bipolar-CMOS-DMOS) process enables analog and digital signal control, as well as high-power supply processing, on a single chip. Shielded-Gate Deep Trench (SGT) devices, with their extremely low parasitic resistance, high-temperature reliability, and saturation-region reliability, meet the high-performance MOSFET requirements for in-vehicle intelligent high-side switches.
[0004] Currently, the industry typically manufactures BCD and SGT devices separately on two chips, then integrates them through subsequent packaging. The BCD and SGT devices are connected via bonding, resulting in high parasitic resistance and capacitance, resulting in poor performance matching. This approach not only increases manufacturing costs but also limits further improvements in chip performance. However, some manufacturing processes in the industry can simultaneously manufacture BCD and SGT devices on a single chip.
[0005] However, the prior art still has many problems in the process of simultaneously manufacturing BCD devices and SGT devices on a single chip. Summary of the Invention
[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, thereby improving the formation quality of a gate oxide layer, reducing photomask processes and lowering manufacturing costs.
[0007] To solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming a mask structure on the substrate, the mask structure comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer stacked in sequence; forming a plurality of first gate trenches in the first region; forming a first dielectric layer and a polysilicon layer in the first gate trenches, the polysilicon layer being located on the first dielectric layer, and the first dielectric layer and the polysilicon layer not completely filling the first gate trenches; forming a dielectric material layer in the first gate trenches and on the mask structure; performing a planarization process on the dielectric material layer, the planarization process stopping on the silicon nitride layer; forming a third silicon oxide layer on the silicon nitride layer, the silicon oxide layer covering the exposed dielectric The method further comprises etching back a portion of the third silicon oxide layer and a portion of the dielectric material layer located on the first region to form a second dielectric layer in the first gate trench, wherein the second dielectric layer is located on the first dielectric layer and the polysilicon layer, and the first dielectric layer and the second dielectric layer cover the polysilicon layer; removing a portion of the silicon nitride layer located on the first region; forming a first gate oxide layer and a first gate layer in the first gate trench, wherein the first gate silicon oxide layer covers the first gate layer and exposes the top surface of the first gate layer, and the first gate oxide layer and the first gate layer fully fill the first gate trench; removing the remaining third silicon oxide layer and the silicon nitride layer; forming a second gate oxide layer in the second region; and forming a second gate layer on the second gate oxide layer.
[0008] Optionally, during the process of forming the first gate trenches, the method further includes: forming second gate trenches in the first region, wherein the second gate trenches are located at the periphery of the plurality of first gate trenches.
[0009] Optionally, the process of forming the first dielectric layer and the polysilicon layer in the first gate trench also includes: forming the first dielectric layer and the polysilicon layer in the second gate trench, and the first dielectric layer and the polysilicon layer fully fill the second gate trench.
[0010] Optionally, before forming the dielectric material layer, the method further includes: forming a plurality of isolation trenches in the second region.
[0011] Optionally, the process of forming the dielectric material layer in the first gate trench and on the mask structure further includes: forming the dielectric material layer in the isolation trench to form an isolation layer.
[0012] Optionally, the method of etching back to remove a portion of the third silicon oxide layer and a portion of the dielectric material layer located on the first region includes: forming a sacrificial layer, the sacrificial layer exposing a portion of the third silicon oxide layer on the first region; and etching back to remove a portion of the third silicon oxide layer and a portion of the dielectric material layer located on the first region using the sacrificial layer as a mask.
[0013] Optionally, the method of removing the portion of the silicon nitride layer located on the first region includes: removing the portion of the silicon nitride layer located on the first region using the third silicon oxide layer as a mask.
[0014] Optionally, the method for forming a first gate oxide layer and a second gate layer in the first gate trench includes: forming the first gate oxide layer on the sidewall of the first gate trench; forming a gate material layer in the second gate trench and on the substrate, the gate material layer covering the third silicon oxide layer; and etching back the gate material layer using the third silicon oxide layer as a mask to form the second gate layer.
[0015] Optionally, the method for forming the second gate oxide layer in the second region includes: oxidizing a portion of the second region using a furnace process to form the second gate oxide layer.
[0016] Optionally, before forming the first dielectric layer and the polysilicon layer, the method further includes: forming a first well region in the second region, wherein the first well region has first ions.
[0017] Optionally, before forming the second gate oxide layer in the second region, it also includes: forming a first body region, a drift region and a second body region in the first well region, the drift region is located between the first body region and the second body region, there are second ions in the first body region and the second body region, there are third ions in the drift region, the first ions and the second ions have the same electrical type, and the third ions have an electrical type opposite to that of the first ions.
[0018] Optionally, the second gate layer is located on a portion of the first body region and a portion of the drift region.
[0019] Optionally, after forming the second gate layer, it also includes: forming a side wall on the side wall of the second gate layer; after forming the side wall, forming a first source-drain doped layer on both sides of the second gate layer, wherein the first source-drain doped layer on one side is located in the first body region, and the first source-drain doped layer on the other side is located in the drift region, the first source-drain doped layer has first source-drain ions, and the first source-drain ions are of the same electrical type as the third ions; forming a heavily doped layer in the first body region and the second body region, the heavily doped layer has doped ions, and the doped ions are of the same electrical type as the second ions.
[0020] Optionally, after forming the second gate layer, it also includes: forming a second well region in the first region, the second well region covering the first gate oxide layer and the second gate layer, and having fourth ions in the second well region; forming a second source-drain doping layer in the second well region, the second source-drain doping layer being located between adjacent first gate trenches, and having second source-drain ions in the second source-drain doping layer, and the electrical type of the second source-drain ions is opposite to that of the fourth ions.
[0021] Optionally, the planarization process adopts a chemical mechanical polishing process.
[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0023] In the method for forming a semiconductor structure according to the technical solution of the present invention, the first gate oxide layer and the second gate oxide layer are fabricated in separate steps to avoid mutual interference during their formation, thereby reducing the formation quality of the first gate oxide layer and the second gate oxide layer. After the planarization process, the third silicon oxide layer is formed. The third silicon oxide layer has a high etching selectivity with the silicon nitride layer and the second gate layer, respectively. Therefore, no additional photomask process is required during the removal of the portion of the silicon nitride layer located on the first region and during the formation of the second gate layer, thereby reducing the use of photomasks in the process and effectively reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figures 1 to 16 It is a schematic structural diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0025] As described in the background art, the prior art still has many problems in the process of simultaneously manufacturing BCD devices and SGT devices on a single chip, which will be described in detail below.
[0026] BCD devices utilize a planar gate process, enabling analog and digital signal control and high-voltage processing on a single chip. SGT devices, on the other hand, utilize a trench gate process. Due to their exceptionally low RSP, high-temperature reliability, and saturation-region reliability, they can be used as switches, meeting the performance requirements of automotive switches. The integration of planar and trench gate processes on the same chip for intelligent switches can reduce manufacturing costs and improve product competitiveness.
[0027] However, due to the significant differences in the process technology between planar gates and trench gates, if the gate oxide is completed in a single step, the quality of the gate oxide will inevitably be reduced. If the gate oxide is prepared separately, additional masks are required, which increases manufacturing costs.
[0028] On this basis, the present invention provides a method for forming a semiconductor structure, wherein the first gate oxide layer and the second gate oxide layer are formed in steps, thereby avoiding mutual interference during the formation of the first gate oxide layer and the second gate oxide layer, thereby reducing the formation quality of the first gate oxide layer and the second gate oxide layer. After the planarization process, the third silicon oxide layer is formed. The third silicon oxide layer has a high etching selectivity with the silicon nitride layer and the second gate layer, respectively. Therefore, when removing the portion of the silicon nitride layer located on the first region and when forming the second gate layer, no additional mask process is required, thereby reducing the use of masks in the process and effectively reducing production costs.
[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0030] Figures 1 to 16 It is a schematic structural diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.
[0031] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a first region I and a second region II.
[0032] In this embodiment, the first region I is used to form a trench gate device, specifically a shielded gate deep trench device (Split Gate Trench, SGT), and the second region II is used to form a planar gate BCD device (Bipolar-CMOS-DMOS), specifically a laterally diffused metal oxide semiconductor device (Laterally Diffused Metal Oxide Semiconductor, LDMOS).
[0033] In other embodiments, the planar gate BCD device may also be a complementary metal oxide semiconductor (CMOS) device.
[0034] In this embodiment, the substrate 100 includes a base and an epitaxial layer (not shown) located on the base, wherein the epitaxial layer is doped with N-type ions.
[0035] In this embodiment, the substrate 100 is made of silicon.
[0036] Please refer to Figure 2 A mask structure is formed on the substrate 100, wherein the mask structure includes a first silicon oxide layer 101, a silicon nitride layer 102, and a second silicon oxide layer 103 stacked in sequence.
[0037] In this embodiment, the mask structure is not only used as a hard mask for subsequent etching of the gate trench, but the ONO structure (Oxide-Nitride-Oxide) adopted by the mask structure is also used as a protective layer or etching stop layer in subsequent processes, thereby reducing the photomask process in the manufacturing process and reducing the manufacturing cost.
[0038] Please refer to Figure 3 , a plurality of first gate trenches 104 are formed in the first region I.
[0039] In this embodiment, the process of forming the first gate trenches 104 further includes: forming second gate trenches 105 in the first region I, wherein the second gate trenches 105 are located at the periphery of the first gate trenches 104 .
[0040] In this embodiment, the method for forming the first gate trench 104 and the second gate trench 105 includes: forming a patterned layer (not shown) on the mask structure, the patterned layer exposing a portion of the top surface of the mask structure; and sequentially etching the mask structure and the first region I using the patterned layer as a mask to form the first gate trench 104 and the second gate trench 105 in the first region I.
[0041] Please continue to refer to Figure 3 In this embodiment, after forming the first gate trench 104 and the second gate trench 105 , the method further includes forming a first well region 106 in the second region II, wherein the first well region 106 has first ions.
[0042] In this embodiment, the method for forming the first well region 106 includes: performing the first ion implantation process on the second region II based on a mask process to form the first well region 106 in the second region II.
[0043] In this embodiment, the first ions are P-type ions.
[0044] Please refer to Figure 4 A first dielectric layer 107 and a polysilicon layer 108 are formed in the first gate trench 104 . The polysilicon layer 108 is located on the first dielectric layer 107 , and the first dielectric layer 107 and the polysilicon layer 108 do not completely fill the first gate trench 104 .
[0045] In this embodiment, the process of forming the first dielectric layer 107 and the polysilicon layer 108 in the first gate trench 104 also includes: forming the first dielectric layer 107 and the polysilicon layer 108 in the second gate trench 105, and the first dielectric layer 107 and the polysilicon layer 108 fully fill the second gate trench 105.
[0046] In this embodiment, the method for forming the first dielectric layer 107 and the polysilicon layer 108 includes: oxidizing the sidewalls of the first gate trench 104 and the second gate trench 105 using a furnace tube process to form the first dielectric layer 107 on the sidewalls of the first gate trench 104 and the second gate trench 105; forming the polysilicon layer 108 in the first gate trench 104 and the second gate trench 105 using a chemical vapor deposition process; and etching back the first dielectric layer 107 and the polysilicon layer 108 in the first gate trench 104.
[0047] It should be noted that the polysilicon layer 108 formed using the chemical vapor deposition process also fills the mask openings within the mask structure. During the process of etching back the polysilicon layer 108, the polysilicon layer 108 within the mask openings is also removed. The second silicon oxide layer 103 can serve as a stop layer for etching back the polysilicon layer 108. The first dielectric layer 107 and the polysilicon layer 108 fill the second gate trench 105 to serve as a terminal ring in the shielded gate deep trench device.
[0048] In this embodiment, the material of the first dielectric layer 107 is silicon oxide.
[0049] Please refer to Figure 5 After forming the first dielectric layer 107 and the polysilicon layer 108 , a plurality of isolation trenches 109 are formed in the second region II.
[0050] In this embodiment, the method for forming the isolation trench 109 includes: forming a patterned layer (not shown) on the mask structure, the patterned layer exposing a portion of the top surface of the mask structure; and etching the mask structure and the second region II in sequence using the patterned layer as a mask to form the isolation trench 109 in the second region II.
[0051] Please refer to Figure 6 , forming a dielectric material layer 110 in the first gate trench 104 and on the mask structure; performing a planarization process on the dielectric material layer 110 , and stopping the planarization process on the silicon nitride layer 102 .
[0052] In this embodiment, the process of forming the dielectric material layer 110 in the first gate trench 104 and on the mask structure further includes: forming the dielectric material layer 110 in the isolation trench 109 to form an isolation layer 111 .
[0053] In this embodiment, the dielectric material layer 110 is formed by a high-density plasma filling process.
[0054] In this embodiment, the planarization process adopts a chemical mechanical polishing process.
[0055] In this embodiment, the dielectric material layer 110 is made of silicon oxide.
[0056] Please refer to Figure 7 After the planarization process, a third silicon oxide layer 112 is formed on the silicon nitride layer 102 , and the silicon oxide layer covers the exposed surface of the dielectric material layer 110 .
[0057] In this embodiment, the third silicon oxide layer 112 is formed by a chemical vapor deposition process.
[0058] Please refer to Figure 8 , back-etching removes a portion of the third silicon oxide layer 112 and a portion of the dielectric material layer 110 located on the first region I, and forms a second dielectric layer 113 in the first gate trench 104, the second dielectric layer 113 is located on the first dielectric layer 107 and the polysilicon layer 108, and the first dielectric layer 107 and the second dielectric layer 113 cover the polysilicon layer 108.
[0059] In this embodiment, the method for etching back to remove a portion of the third silicon oxide layer 112 and a portion of the dielectric material layer 110 located on the first region I includes: forming a sacrificial layer (not shown), the sacrificial layer exposing a portion of the third silicon oxide layer 112 on the first region I; and etching back to remove a portion of the third silicon oxide layer 112 and a portion of the dielectric material layer 110 located on the first region I using the sacrificial layer as a mask.
[0060] In this embodiment, the sacrificial layer exposes the third silicon oxide layer 112 on the first gate trench 104 , while the third silicon oxide layer 112 on the second gate trench 105 remains.
[0061] In this embodiment, the third silicon oxide layer 112 is etched back using a wet etching process.
[0062] Please continue to refer to Figure 8 , removing the portion of the silicon nitride layer 102 located on the first region I.
[0063] Since the silicon oxide layer cannot be removed by a photoresist layer mask process, and the silicon nitride layer 102 and the third silicon oxide layer 112 have a higher etching selectivity ratio, in this embodiment, the method for removing the portion of the silicon nitride layer 102 located on the first region I includes: removing the sacrificial layer, and removing the portion of the silicon nitride layer 102 on the first region I using the third silicon oxide layer 112 as a mask.
[0064] In this embodiment, a wet etching process is used to remove the silicon nitride layer 102 .
[0065] In this embodiment, after removing the silicon nitride layer 102, a first gate oxide layer and a first gate layer are formed in the first gate trench 104. The first gate oxide layer covers the first gate layer and exposes the top surface of the first gate layer. The first gate oxide layer and the first gate layer fully fill the first gate trench 104. For a detailed process, please refer to Figures 9 to 11 .
[0066] Please refer to Figure 9 , forming the first gate oxide layer 114 on the sidewalls of the first gate trench 104 .
[0067] In this embodiment, the first gate oxide layer 114 is formed by directly oxidizing the sidewalls of the first gate trench 104 using a furnace process, and the material of the first gate oxide layer 114 is silicon oxide.
[0068] Please refer to Figure 10A gate material layer 115 is formed in the second gate trench 105 and on the substrate 100 , and the gate material layer 115 covers the third silicon oxide layer 112 .
[0069] In this embodiment, the gate material layer 115 is made of polysilicon, and the gate material layer 115 is formed by a polysilicon filling process.
[0070] Please refer to Figure 11 , using the third silicon oxide layer 112 as a mask, the gate material layer 115 is etched back to form the first gate layer 116 .
[0071] In this embodiment, since there is a large etching selectivity ratio between the third silicon oxide layer 112 and the gate material layer 115 of polysilicon material, the gate material layer 115 can be directly etched back using the third silicon oxide layer 112 as a mask, and the third silicon oxide layer 112 serves as a stop layer for etching back the gate material layer 115.
[0072] In this embodiment, the process of etching back the gate material layer 115 adopts a dry etching process.
[0073] In this embodiment, the formed first gate silicon oxide layer covers the first gate layer 116 and exposes the top surface of the first gate layer 116 . The first gate oxide layer 114 and the first gate layer 116 completely fill the first gate trench 104 .
[0074] Please refer to Figure 12 , removing the remaining third silicon oxide layer 112 and the silicon nitride layer 102.
[0075] In this embodiment, a photomask process is not required to remove the remaining third silicon oxide layer 112 and the silicon nitride layer 102 , and a wet etching process is used to remove the remaining third silicon oxide layer 112 and the silicon nitride layer 102 .
[0076] Please refer to Figure 13 After removing the remaining third silicon oxide layer 112 and the silicon nitride layer 102, a first body region 117, a drift region 118 and a second body region 119 are formed in the first well region 106, and the drift region 118 is located between the first body region 117 and the second body region 119. There are second ions in the first body region 117 and the second body region 119, and there are third ions in the drift region 118. The first ions and the second ions have the same electrical type, and the third ions have an electrical type opposite to that of the first ions.
[0077] In this embodiment, the second ions are P-type ions, and the third ions are N-type ions.
[0078] In this embodiment, the method for forming the first body region 117 and the second body region 119 includes: performing the second ion implantation treatment on the first well region 106 based on a mask process to form the first body region 117 and the second body region 119; the method for forming the drift region 118 includes: performing the third ion implantation treatment on the first well region 106 based on a mask process to form the drift region 118.
[0079] Please refer to Figure 14 After forming the first body region 117 , the second body region 119 and the drift region 118 , a second gate oxide layer 120 is formed in the second region II.
[0080] In this embodiment, the method for forming the second gate oxide layer 120 in the second region II includes: oxidizing a portion of the second region II using a furnace process to form the second gate oxide layer 120 .
[0081] It should be noted that, in this embodiment, before forming the second gate oxide layer 120 , the first silicon oxide layer 101 on the substrate 100 is removed by a wet etching process.
[0082] Please refer to Figure 15 After forming the second gate oxide layer 120 , a second gate layer 121 is formed on the second gate oxide layer 120 .
[0083] In this embodiment, the second gate layer 121 is made of polysilicon. The method for forming the second gate layer 121 includes: forming a material layer (not shown) using a polysilicon deposition process, and performing a patterned etching process on the material layer to form the second gate layer 121 .
[0084] In this embodiment, the second gate layer 121 is located on a portion of the first body region 117 and a portion of the drift region 118 .
[0085] Please continue to refer to Figure 15 After forming the second gate layer 121 , the method further includes: forming a sidewall spacer 122 on the sidewall of the second gate layer 121 .
[0086] In this embodiment, the method for forming the sidewall spacer 122 includes: forming a sidewall spacer material layer (not shown) by a chemical vapor deposition process; and performing an etching back process on the sidewall spacer material layer to form the sidewall spacer 122 .
[0087] In this embodiment, the sidewall spacer 122 is made of silicon nitride.
[0088] Please refer to Figure 16After forming the sidewall spacer 122 , a first source / drain doped layer 123 is formed on both sides of the second gate layer 121 , and a heavily doped layer 124 is formed in the first body region 117 and the second body region 119 .
[0089] In this embodiment, the first source-drain doped layer 123 on one side is located in the first body region 117, and the first source-drain doped layer 123 on the other side is located in the drift region 118. The first source-drain doped layer 123 has first source-drain ions, and the first source-drain ions are of the same electrical type as the third ions; the heavily doped layer 124 has doped ions, and the doped ions are of the same electrical type as the second ions.
[0090] In this embodiment, the first source and drain ions are N-type ions, and the doping ions are P-type ions. The heavily doped layer 124 serves as a lead contact of the BCD device to reduce contact resistance.
[0091] Please continue to refer to Figure 16 After forming the second gate layer 121, it also includes: forming a second well region 125 in the first region I, the second well region 125 covering the first gate oxide layer 114 and the second gate layer 121; forming a second source and drain doping layer 126 in the second well region 125.
[0092] In this embodiment, the second well region 125 serves as a channel of the SGT device, and the first source-drain doped layer 123 and the second source-drain doped layer 126 are formed simultaneously.
[0093] In this embodiment, the second well region 125 has fourth ions therein, the second source-drain doped layer 126 is located between adjacent first gate trenches 104 , and the second source-drain doped layer 126 has second source-drain ions therein, and the electrical type of the second source-drain ions is opposite to that of the fourth ions.
[0094] In this embodiment, the fourth ions are P-type ions, and the second source and drain ions are N-type ions.
[0095] In this embodiment, the first gate oxide layer 114 and the second gate oxide layer 120 are formed in separate steps to avoid mutual interference during the formation of the first gate oxide layer 114 and the second gate oxide layer 120, thereby reducing the formation quality of the first gate oxide layer 114 and the second gate oxide layer 120. After the planarization process, the third silicon oxide layer 112 is formed. The third silicon oxide layer 112 has a high etching selectivity with the silicon nitride layer 102 and the second gate layer 121, respectively. Therefore, no additional mask process is required when removing the portion of the silicon nitride layer 102 located on the first region I and when forming the second gate layer 121, thereby reducing the number of masks used in the process and effectively reducing manufacturing costs.
[0096] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate comprising a first region and a second region; forming a mask structure on the substrate, the mask structure comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer stacked in sequence; forming a plurality of first gate trenches in the first region; forming a first dielectric layer and a polysilicon layer in the first gate trench, wherein the polysilicon layer is located on the first dielectric layer, and the first dielectric layer and the polysilicon layer do not completely fill the first gate trench; forming a dielectric material layer in the first gate trench and on the mask structure; performing a planarization process on the dielectric material layer, wherein the planarization process stops on the silicon nitride layer; forming a third silicon oxide layer on the silicon nitride layer, wherein the silicon oxide layer covers the exposed surface of the dielectric material layer; Etching back to remove a portion of the third silicon oxide layer and a portion of the dielectric material layer located on the first region, and forming a second dielectric layer in the first gate trench, wherein the second dielectric layer is located on the first dielectric layer and the polysilicon layer, and the first dielectric layer and the second dielectric layer cover the polysilicon layer; removing a portion of the silicon nitride layer located on the first region; forming a first gate oxide layer and a first gate layer in the first gate trench, wherein the first gate silicon oxide layer covers the first gate layer and exposes a top surface of the first gate layer, and the first gate oxide layer and the first gate layer completely fill the first gate trench; removing the remaining third silicon oxide layer and the silicon nitride layer; forming a second gate oxide layer in the second region; A second gate layer is formed on the second gate oxide layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the first gate trenches further includes: forming second gate trenches in the first region, wherein the second gate trenches are located at the periphery of the first gate trenches.
3. The method for forming a semiconductor structure according to claim 2, wherein: The process of forming the first dielectric layer and the polysilicon layer in the first gate trench also includes: forming the first dielectric layer and the polysilicon layer in the second gate trench, and the first dielectric layer and the polysilicon layer fully fill the second gate trench.
4. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the dielectric material layer, the method further includes: forming a plurality of isolation trenches in the second region.
5. The method for forming a semiconductor structure according to claim 4, wherein: The process of forming the dielectric material layer in the first gate trench and on the mask structure further includes: forming the dielectric material layer in the isolation trench to form an isolation layer.
6. The method for forming a semiconductor structure according to claim 1, wherein: The method for etching back to remove a portion of the third silicon oxide layer and a portion of the dielectric material layer located on the first area includes: forming a sacrificial layer, the sacrificial layer exposing a portion of the third silicon oxide layer on the first area; and etching back to remove a portion of the third silicon oxide layer and a portion of the dielectric material layer located on the first area using the sacrificial layer as a mask.
7. The method for forming a semiconductor structure according to claim 1, wherein: The method for removing the portion of the silicon nitride layer located on the first region includes: removing the portion of the silicon nitride layer located on the first region using the third silicon oxide layer as a mask.
8. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a first gate oxide layer and a second gate layer in the first gate trench includes: forming the first gate oxide layer on the sidewall of the first gate trench; forming a gate material layer in the second gate trench and on the substrate, the gate material layer covering the third silicon oxide layer; and etching back the gate material layer using the third silicon oxide layer as a mask to form the second gate layer.
9. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the second gate oxide layer in the second region includes: oxidizing a portion of the second region using a furnace process to form the second gate oxide layer.
10. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first dielectric layer and the polysilicon layer, the method further includes: forming a first well region in the second region, wherein the first well region has first ions.
11. The method for forming a semiconductor structure according to claim 10, wherein: Before forming the second gate oxide layer in the second region, it also includes: forming a first body region, a drift region and a second body region in the first well region, the drift region is located between the first body region and the second body region, there are second ions in the first body region and the second body region, there are third ions in the drift region, the first ions and the second ions have the same electrical type, and the third ions have an electrical type opposite to that of the first ions.
12. The method for forming a semiconductor structure according to claim 11, wherein: The second gate layer is located on a portion of the first body region and a portion of the drift region.
13. The method for forming a semiconductor structure according to claim 11, wherein: After forming the second gate layer, it also includes: forming a side wall on the side wall of the second gate layer; after forming the side wall, forming a first source-drain doped layer on both sides of the second gate layer, wherein the first source-drain doped layer on one side is located in the first body region, and the first source-drain doped layer on the other side is located in the drift region, the first source-drain doped layer has first source-drain ions, and the first source-drain ions are of the same electrical type as the third ions; forming a heavily doped layer in the first body region and the second body region, the heavily doped layer has doped ions, and the doped ions are of the same electrical type as the second ions.
14. The method for forming a semiconductor structure according to claim 1, wherein: After forming the second gate layer, it also includes: forming a second well region in the first region, the second well region covers the first gate oxide layer and the second gate layer, and the second well region has fourth ions; forming a second source-drain doping layer in the second well region, the second source-drain doping layer is located between adjacent first gate trenches, the second source-drain doping layer has second source-drain ions, and the electrical type of the second source-drain ions is opposite to that of the fourth ions.
15. The method for forming a semiconductor structure according to claim 1, wherein: The planarization process adopts a chemical mechanical polishing process.