Semiconductor device manufacturing method and semiconductor device

Abstract

The invention discloses a semiconductor device manufacturing method and a semiconductor device, and the method comprises the steps: forming a stress counteracting layer and a denaturation processing barrier layer on a pseudo gate deposition layer, and obtaining a first semiconductor device; performing first chemical mechanical polishing on the first semiconductor device by taking the top surface of the pseudo gate platform at the top of the pseudo gate deposition layer as a chemical mechanical polishing stop layer to obtain a second semiconductor device; performing material modification processing on the top dummy gate platform of the second semiconductor device to obtain a third semiconductor device; and second chemical mechanical polishing is carried out on the third semiconductor device by taking the top of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a fourth semiconductor device, and compared with the first semiconductor device, the height difference of the dummy gate deposition layer of the fourth semiconductor device is reduced. By using the scheme provided by the invention, the surface flatness of the dummy gate can be improved, the silicon nitride residue condition can be improved, the gate height loss can be reduced, and the performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present application generally relates to the field of semiconductor technology. More specifically, the present application relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] The high-k-metal gate (HKMG) process is widely adopted at process nodes 28nm and below, integrating high-voltage (HV), medium-voltage (MV), and low-voltage (LV) operating regions as required. In integrated circuit manufacturing, the shallow trench isolation oxide (STI) and active area (AA) are not aligned, and the thickness of the isolation oxide varies in the HV / LV regions. These factors, combined, can lead to multiple height differences in the dummy gate (Poly). Furthermore, the polysilicon polishing process is affected by pattern density, resulting in inconsistent silicon nitride thickness remaining above the dummy gate after polysilicon polishing. This can easily lead to incomplete silicon nitride etching or insufficient gate height after over-etching in subsequent processes (DPRM), impacting device performance.

[0003] In view of this, there is an urgent need to provide a semiconductor device manufacturing method to improve the surface flatness of the dummy gate, which is conducive to improving the silicon nitride residue and reducing the gate height loss, thereby improving the performance of the semiconductor device. Summary of the Invention

[0004] To address at least one or more of the above-mentioned technical issues, the present application provides, in multiple aspects, a semiconductor device fabrication method and a semiconductor device. The semiconductor device fabrication method can improve the surface flatness of the dummy gate, thereby improving silicon nitride residue and reducing gate height loss, thereby enhancing the performance of the semiconductor device.

[0005] In a first aspect, the present application provides a method for manufacturing a semiconductor device, comprising: forming a stress-compensating layer and a denaturation treatment barrier layer on a dummy gate deposition layer to obtain a first semiconductor device; the dummy gate deposition layer has steps with different heights; performing a first chemical mechanical polishing on the first semiconductor device with the top surface of the top dummy gate platform of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a second semiconductor device; performing a material denaturation treatment on the top dummy gate platform of the second semiconductor device to obtain a third semiconductor device; performing a second chemical mechanical polishing on the third semiconductor device with the top of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a fourth semiconductor device, wherein the height difference of the dummy gate deposition layer of the fourth semiconductor device is reduced compared with the first semiconductor device.

[0006] In some embodiments, after obtaining the fourth semiconductor device, the method further includes: cyclically performing the material modification process and the second chemical mechanical polishing until the height difference of the dummy gate deposition layer is less than a predetermined value.

[0007] In some embodiments, the number of cycles is determined based on a height difference and / or a number of steps of the dummy gate deposition layer of the first semiconductor device.

[0008] In some embodiments, the stress-compensating layer is an oxide layer, and the degeneration treatment barrier layer is a silicon nitride layer; wherein, forming the stress-compensating layer and the degeneration treatment barrier layer on the dummy gate deposition layer includes: depositing an oxide layer and a silicon nitride layer in sequence on the dummy gate deposition layer. In some embodiments, performing material modification on the top dummy gate platform includes performing furnace nitridation on the top dummy gate platform, so that the top dummy gate platform is converted into silicon nitride. In some embodiments, the stress-compensating layer is a silicon nitride layer, and the degeneration treatment barrier layer is an oxide layer; wherein, forming the stress-compensating layer and the degeneration treatment barrier layer on the dummy gate deposition layer includes: sequentially depositing a silicon nitride layer and an oxide layer on the dummy gate deposition layer. In some embodiments, performing a material modification process on the top dummy gate platform includes performing a furnace oxidation process on the top dummy gate platform, so that the top dummy gate platform is converted into oxide. In some embodiments, the method further includes removing the remaining stress compensation layer and the degradation barrier layer on the fourth semiconductor device.

[0009] In some embodiments, removing the residual stress-compensating layer and the degeneration treatment barrier layer on the fourth semiconductor device includes: performing any of the following treatments on the residual stress-compensating layer and the degeneration treatment barrier layer on the fourth semiconductor device: chemical mechanical polishing, dry etching, and wet etching.

[0010] In a second aspect, the present application provides a semiconductor device, comprising: a semiconductor device manufactured based on the semiconductor device manufacturing method described in any one of the first aspects.

[0011] The technical solution provided by this application can have the following unexpected beneficial effects: The semiconductor device manufacturing method and semiconductor device provided in the present application are obtained by forming a stress-compensating layer and a denaturation treatment barrier layer on a dummy gate deposition layer, and then performing a first chemical mechanical polishing on the first semiconductor device using the top dummy gate platform of the dummy gate deposition layer as a chemical mechanical polishing stop layer, so that the stress-compensating layer can be preset on the side wall of the top dummy gate platform while exposing the top dummy gate platform, thereby forming a second semiconductor device.

[0012] Furthermore, embodiments of the present application can perform a material denaturation treatment on the top dummy gate platform of the second semiconductor device, thereby denaturing the material of the top dummy gate platform, and utilizing a stress-compensating layer pre-set on the sidewalls of the top dummy gate platform to offset the stress generated during the material denaturation of the top dummy gate platform. Simultaneously, a denaturation treatment barrier layer is utilized to prevent material denaturation of locations other than the top dummy gate platform in the second semiconductor device, thereby obtaining a third semiconductor device. Furthermore, a second chemical mechanical polishing is performed on the third semiconductor device using the dummy gate deposited layer as a chemical mechanical polishing stop layer, thereby grinding away the top dummy gate platform that has undergone the material denaturation treatment, reducing the height difference of the dummy gate deposited layer, and achieving planarization of the dummy gate deposited layer, thereby obtaining a fourth semiconductor device. Furthermore, optionally, the deposited stress-compensating layer and the denaturation treatment barrier layer remaining on the fourth semiconductor device are removed to prevent the residual stress-compensating layer and the denaturation treatment barrier layer from negatively impacting the performance of the semiconductor device.

[0013] In general, the solution provided in the embodiments of the present application can improve the surface flatness of the dummy gate, which is beneficial to improving the silicon nitride residue and reducing the gate height loss, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein: Figure 1 A schematic diagram showing the height difference of a dummy gate formed on polysilicon in the current process; Figure 2 A schematic diagram showing the inconsistent SiN thickness retained on the dummy gate after polysilicon polishing in the current process; Figure 3 A schematic diagram showing insufficient gate height caused by over-etching of SiN in the current process; Figure 4 A schematic diagram showing that SiN is not etched cleanly in the current process; Figure 5 An exemplary flow chart showing a method for manufacturing a semiconductor device according to some embodiments of the present application is provided; Figure 6 An exemplary flow chart showing a method for manufacturing a semiconductor device according to some other embodiments of the present application is provided; Figure 7 A schematic structural diagram of a semiconductor device to be processed in the semiconductor device manufacturing method of the present application is shown; Figure 8 A schematic structural diagram of a first semiconductor device obtained in the semiconductor device manufacturing method of the present application is shown; Figure 9 A schematic structural diagram of a second semiconductor device obtained in the semiconductor device manufacturing method of the present application is shown; Figure 10 A schematic structural diagram of a third semiconductor device obtained in the semiconductor device manufacturing method of the present application is shown; Figure 11 A schematic structural diagram of a fourth semiconductor device obtained in the semiconductor device manufacturing method of the present application is shown; Figure 12 shows a schematic structural diagram of a semiconductor device that has undergone a second material modification process; Figure 13 shows a schematic structural diagram of a semiconductor device that has undergone a second chemical mechanical polishing process; Figure 14 The figure shows the kinetic curve of ammonia nitridation in the furnace tube in the semiconductor device manufacturing method of the present application; Figure 15 The figure shows the kinetic curve of dry oxygen oxidation in a furnace tube in the semiconductor device manufacturing method of the present application.

[0015] Among them, 1 represents silicon nitride, 2 represents dummy gate, 3 represents high dielectric material, 4 represents isolation oxide, 5 represents AA region, 6 represents silicon substrate, 7 represents shallow trench isolation oxide, 8 represents gate, 9 represents residual dummy gate, 10 represents dummy gate deposition layer, 11 represents denaturation treatment barrier layer, 12 represents stress compensation layer, 13 represents CMP stop layer, and 14 represents top dummy gate platform. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. For the sake of simplicity and clarity of explanation, figure marks may be repeated in the drawings to indicate corresponding or similar elements where appropriate. In addition, this application sets forth many specific details in order to provide a thorough understanding of the embodiments described herein. However, those skilled in the art will understand that the embodiments described herein can be practiced without these specific details. In other cases, well-known methods, processes, and components are not described in detail to avoid obscuring the embodiments described herein. Moreover, this description should not be regarded as limiting the scope of the embodiments described herein. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0017] It should be understood that the terms "first" or "second" and the like in the claims, description, and drawings disclosed in this application are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprising" used in the description and claims of this application indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0018] It should also be understood that the terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this specification and claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" as used in this specification and claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0019] As used in this specification and claims, the term “if” can be interpreted as “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [described condition or event] is detected” can be interpreted as meaning “upon determination” or “in response to determining” or “upon detection of [described condition or event]” or “in response to detecting [described condition or event],” depending on the context.

[0020] As mentioned in the background, in integrated circuit manufacturing, the shallow trench isolation oxide (STI) is not on the same level as the AA region, and the thickness of the isolation oxide varies in different HV / LV regions, resulting in multiple levels of height differences in the dummy gate (Poly). Furthermore, the polysilicon polishing process is affected by pattern density. The combination of these factors can lead to inconsistent silicon nitride thickness remaining on the dummy gate after polysilicon polishing. This can easily lead to incomplete etching of the silicon nitride in subsequent processes, or insufficient gate height after over-etching, thus affecting device performance.

[0021] Figure 1 Schematic diagram showing the height difference of the pseudo gate formed by polysilicon in the current process. Figure 1 As shown, it is shown that the STI Oxide and the AA region are not at the same level, so the dummy gate Poly and the silicon nitride SiN thereon have multiple levels of height difference. Figure 2A schematic diagram illustrates the inconsistent SiN thickness remaining on the dummy gates after dummy gate formation and polysilicon polishing in the current process. It can be understood that a thicker silicon nitride layer remains on the lower dummy gates (indicated by the dashed line), while a thinner layer remains on the higher dummy gates. The figure shows a difference in SiN residual thickness exceeding 80 Å (angstroms, where 1 Å equals 0.1 nanometer) on the upper portions of different dummy gates. Figure 3 It shows the situation in which the gate height is insufficient after SiN over-etching in the current process, for example, the gate height on the AA region is lost to a certain extent. Figure 4 It shows the situation that SiN is not etched cleanly in the current process. For example, in the STIOxide area, a dummy gate remains therein because SiN is not etched cleanly.

[0022] In view of this, there is an urgent need to provide a semiconductor device manufacturing method to improve the surface flatness of the dummy gate, which is conducive to improving the silicon nitride residue and reducing the gate height loss, thereby improving the performance of the semiconductor device.

[0023] The specific implementation of the present application will be described in detail below with reference to the accompanying drawings.

[0024] Figure 5 An exemplary flow chart 100 of a method for manufacturing a semiconductor device according to some embodiments of the present application is shown. Figure 7 FIG1 shows a schematic structural diagram of a semiconductor device to be processed in a semiconductor device manufacturing method according to an embodiment of the present application. Figure 8 FIG2 shows a schematic structural diagram of a first semiconductor device obtained in a method for manufacturing a semiconductor device according to an embodiment of the present application. Figure 9 FIG2 shows a schematic structural diagram of a second semiconductor device obtained in the semiconductor device manufacturing method according to an embodiment of the present application. Figure 10 The schematic diagram of the structure of the third semiconductor device obtained in the semiconductor device manufacturing method of the embodiment of the present application is shown. Figure 5 and Figures 7 to 10 To describe the semiconductor device manufacturing method of the embodiment of the present application. In the embodiments of this application, Figure 7 As shown, due to the fact that the STI Oxide and the AA region are not on the same horizontal plane, the thickness of the isolation oxide in different HV / LV regions is different, etc., a pseudo gate step with a height difference appears on the pseudo gate deposition layer of the unprocessed semiconductor device, forming at least one pseudo gate platform / step, for example, two steps are shown in the figure.

[0025] In step S101, a stress-compensating layer and a denaturation treatment barrier layer are formed on the dummy gate deposition layer to obtain a first semiconductor device. In the embodiment of the present application, the stress-compensating layer refers to a deposition layer used to compensate for the stress generated in the subsequent denaturation treatment, and the denaturation treatment barrier layer refers to a deposition layer that prevents material denaturation in the subsequent denaturation treatment. Figure 8 As shown, a stress-compensating layer and a denaturation treatment barrier layer may be sequentially deposited on the dummy gate deposition layer until the surface of the dummy gate deposition layer is completely covered, so as to obtain the first semiconductor device.

[0026] In step S102, the first semiconductor device is subjected to a first chemical mechanical polishing process using the top surface of the dummy gate platform on the top of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a second semiconductor device. Figure 9 As shown, the first semiconductor device is subjected to chemical-mechanical polishing (CMP) using the top surface of the top dummy gate platform of the dummy gate deposition layer as a chemical-mechanical polishing stop layer (CMP Stop Layer) to expose the top dummy gate platform to obtain a second semiconductor device.

[0027] In step S103, a material modification process is performed on the top dummy gate platform of the second semiconductor device to obtain a third semiconductor device. In the embodiment of the present application, the material modification process may refer to a process for changing the properties and chemical composition of the material, and may include, but is not limited to, nitridation or oxidation, such as furnace tube ammonia nitridation or furnace tube dry oxygen oxidation.

[0028] like Figure 10 As shown, after the material modification process, the material of the top dummy gate platform is changed from polysilicon to silicon nitride or silicon oxide. The specific modified material depends on the modification process used. During the material modification process of the top dummy gate platform, a stress compensation layer preset on the sidewall of the top dummy gate platform is used to offset the stress generated by the material modification of the top dummy gate platform, thereby preventing cracks in the dummy gate deposited layer caused by the stress generated by expansion. At the same time, the modification process barrier layer is used to prevent material modification at locations other than the top dummy gate platform in the second semiconductor device.

[0029] In step S104 , a second chemical mechanical polishing is performed on the third semiconductor device using the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a fourth semiconductor device.

[0030] like Figure 11 As shown in FIG, a second chemical mechanical polishing is performed on the third semiconductor device using the top surface of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a fourth semiconductor device. As can be seen from the figure, the height difference of the dummy gate deposition layer of the fourth semiconductor device is reduced compared to the first semiconductor device.

[0031] It can be understood that if there is only one dummy gate step with a height difference (this situation is not shown in the figure), only one dummy gate platform is formed, and the height difference is small, then the third semiconductor device can be chemically mechanically polished using the dummy gate deposition layer as a chemical mechanical polishing stop layer to achieve flattening of the dummy gate deposition layer.

[0032] The present invention provides a semiconductor device fabrication method and semiconductor device. A first semiconductor device is obtained by forming a stress-compensating layer and a denaturation barrier layer on a dummy gate deposited layer. The first semiconductor device is then subjected to a first chemical mechanical polishing (CMP) process using the top dummy gate terrace of the dummy gate deposited layer as a CMP stop layer. This process exposes the top dummy gate terrace while pre-setting the stress-compensating layer on the sidewalls of the top dummy gate terrace, thereby forming a second semiconductor device. Furthermore, embodiments of the present invention can perform a material denaturation process on the top dummy gate terrace of the second semiconductor device, thereby denaturing the material of the top dummy gate terrace. The stress-compensating layer pre-setting on the sidewalls of the top dummy gate terrace offsets the stress generated by the material denaturation of the top dummy gate terrace. The denaturation barrier layer prevents material denaturation of any portion of the second semiconductor device other than the top dummy gate terrace, thereby obtaining a third semiconductor device. The third semiconductor device is then subjected to a second CMP process using the dummy gate deposited layer as a CMP stop layer. This process removes the top dummy gate terrace that has undergone the material denaturation process, reduces the height difference of the dummy gate deposited layer, and achieves planarization of the dummy gate deposited layer, thereby obtaining a fourth semiconductor device.

[0033] It is understandable that the fourth semiconductor device may contain residual stress-compensating layer and denaturation barrier layer that have not been completely polished, requiring further processing to obtain a target semiconductor device with a flat and clean dummy gate deposited layer. Therefore, further optionally, the residual stress-compensating layer and denaturation barrier layer on the fourth semiconductor device are removed to obtain the target semiconductor device, thereby preventing the residual stress-compensating layer and denaturation barrier layer from negatively impacting the performance of the semiconductor device.

[0034] In general, the solution provided in the embodiment of the present application can reduce the height difference of the dummy gate deposition layer, improve the surface flatness of the dummy gate, and is conducive to improving the silicon nitride residue and reducing the gate height loss, thereby improving the performance of the semiconductor device.

[0035] In some embodiments, there may be more than one dummy gate step with a height difference, for example Figure 7 The semiconductor device shown in FIG has two dummy gate steps on the dummy gate deposition layer, or the height difference of the dummy gate platform is large, and the steps cannot be eliminated by one treatment due to the limitation of the denaturation treatment. In this case, multiple treatments can be performed to flatten the dummy gate deposition layer. Figure 6To explain in detail, Figure 6 An exemplary flow chart 200 showing a method for manufacturing a semiconductor device according to another embodiment of the present invention is shown. Figure 6 , the semiconductor device manufacturing method shown in the embodiment of the present application may include: In step S201 , a stress compensation layer and a denaturation treatment barrier layer are formed on the dummy gate deposition layer to obtain a first semiconductor device.

[0036] In step S202 , a first chemical mechanical polishing is performed on the first semiconductor device using the top surface of the dummy gate platform on the top of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a second semiconductor device.

[0037] In step S203 , a material modification process is performed on the top dummy gate platform of the second semiconductor device to obtain a third semiconductor device.

[0038] In step S204 , a second chemical mechanical polishing is performed on the third semiconductor device using the top dummy gate platform of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a fourth semiconductor device.

[0039] Steps S201~S204 are combined with the previous Figure 5 and Figures 7 to 10 The steps S101 to S104 described are similar and will not be repeated here.

[0040] It is understandable that if there are more than one dummy gate steps with a height difference, after the material denaturation process is completed on the current top dummy gate platform, the next dummy gate platform will be used as the new top dummy gate platform. Figure 11 As shown, the third semiconductor device is chemically mechanically polished using the top surface of the dummy gate terrace (shown in the dashed box, previously the second-highest dummy gate terrace) of the dummy gate deposited layer as a chemical mechanical polishing stop layer, thereby exposing the top dummy gate terrace and obtaining the fourth semiconductor device. As can be seen from the figure, the dummy gate deposited layer still has a dummy gate step (shown in the dashed box), and residual stress-compensating layer and denaturation treatment barrier layer remain at the bottom of the step.

[0041] Alternatively, if the height difference of the dummy gate platform is large, and the material modification process is affected by factors such as temperature and has a significant thickness self-limiting effect, the height difference of each treatment is limited. For example, the height difference that can be improved by each furnace nitriding treatment is approximately 50 Å. Then, after completing a material modification treatment on the current top dummy gate platform, the current top dummy gate platform remains the top dummy gate platform, but the height difference is reduced. For example, if the height difference of the original dummy gate platform is greater than 50 Å, such as 140 Å, a material modification treatment can transform the 50 Å thick dummy gate deposited layer into, for example, silicon nitride. In this case, the height difference of the dummy gate platform is reduced to 90 Å.

[0042] For the above two situations, it can be determined in step S206 whether the height difference of the dummy gate deposition layer on the fourth semiconductor device is less than a predetermined value. If it exceeds the predetermined value, it can return to the front and perform the material denaturation treatment (step S203) and the second chemical mechanical polishing (step S204) in a loop until the height difference of the dummy gate deposition layer is less than the predetermined value. If it is less than the predetermined value, the loop can be ended. In an embodiment of the present application, the number of cycles can be determined based on the height difference and / or the number of steps of the dummy gate deposition layer of the first semiconductor device. For example, when the height of each step does not exceed the maximum thickness of a single material denaturation treatment, the number of cycles is equal to the number of steps. In addition, the above predetermined value can be set to between 1 Å and 5 Å, depending on the actual application.

[0043] Figure 12 A schematic diagram of the structure of a semiconductor device undergoing a second material modification process is shown. As shown, the material of the current top dummy gate platform of the semiconductor device has been modified from polysilicon to silicon nitride or silicon oxide. The specific modified material depends on the modification process used. Similarly, during the material modification process of the top dummy gate platform, a stress-compensating layer pre-set on the sidewall of the top dummy gate platform is used to offset the stress generated during the material modification of the top dummy gate platform, preventing cracks in the dummy gate deposited layer caused by expansion stress. At the same time, a modification barrier layer is used to prevent material modification at locations other than the top dummy gate platform in the semiconductor device.

[0044] Figure 13 The semiconductor device is shown to have been subjected to a second chemical mechanical polishing process. As shown in the figure, the top surface of the dummy gate deposition layer is used as the chemical mechanical polishing stop layer. Figure 12 The semiconductor device shown is subjected to a second chemical mechanical polishing process, thereby grinding away the top dummy gate platform that has undergone the material modification process. In this embodiment, the height difference of the dummy gate deposition layer has been substantially eliminated, achieving planarization of the dummy gate deposition layer.

[0045] Similarly, if a deposited stress-compensating layer and a denaturation barrier layer remain on the semiconductor device after the material denaturation-CMP cycle, the remaining deposited stress-compensating layer and the denaturation barrier layer can be removed in step S205 to obtain the target semiconductor device. In the embodiment of the present application, the remaining deposited stress-compensating layer and the denaturation barrier layer on the semiconductor device can be subjected to chemical mechanical polishing, dry etching, or wet etching to fully remove the remaining deposited stress-compensating layer and the denaturation barrier layer.

[0046] In the above embodiment, by performing material denaturation and CMP treatment in multiple cycles, it is possible to flexibly adapt to various step conditions that may appear on the dummy gate deposition layer, such as a large height difference of the dummy gate steps, a large number of dummy gate steps, etc., thereby obtaining a flat dummy gate deposition layer, which is convenient for subsequent further process processing.

[0047] In some embodiments, the materials of the stress-compensating layer and the denaturation treatment barrier layer can be further designed, and a matching process will be used to perform material denaturation treatment on the top pseudo-gate platform. It can be understood that the stress-compensating layer is used to offset the stress generated in the material denaturation treatment. Therefore, a material with a stress direction opposite to that generated in the material deformation treatment can be used as a stress-compensating layer, and this characteristic can be used to offset the stress generated in the material denaturation treatment. For example, the stress range of the oxide layer can be -60Mpa~-200Mpa, while the stress range of the silicon nitride layer can be 50Mpa~500Mpa. Therefore, the stress-compensating layer and the corresponding material denaturation treatment can be set by utilizing the opposite stress characteristics of the two. The denaturation treatment barrier layer can be selected to be consistent with the denatured material, thereby preventing the material below it from being denatured, but the embodiments of the present application are not limited to this.

[0048] In some embodiments, the stress-compensating layer may be an oxide layer, which may be composed of silicon dioxide, and the denaturation treatment barrier layer may be a silicon nitride layer. Thus, the oxide layer and the silicon nitride layer may be sequentially deposited on the dummy gate deposition layer to form a first semiconductor device. In these embodiments, the first semiconductor device may be further subjected to a first chemical-mechanical polishing (CMP) using the top dummy gate platform of the dummy gate deposition layer as a chemical-mechanical polishing stop layer (CMP stop layer) to expose the top dummy gate platform, thereby obtaining a second semiconductor device. The top dummy gate platform may then be subjected to a furnace ammonia nitridation treatment, nitriding the top dummy gate platform to silicon nitride, thereby obtaining a third semiconductor device.

[0049] Figure 14 The figure shows the kinetic curve of ammonia nitridation in the furnace tube in the semiconductor device manufacturing method of the present application. Figure 14As shown, according to the kinetic curve of ammonia nitriding of the furnace tube, the appropriate temperature and time can be selected to obtain the corresponding denaturation thickness. For example, it can be seen from the figure that as the temperature increases and the reaction time becomes longer, the denaturation thickness increases. However, when the temperature is low, the effect of the increase in reaction time on the thickness is relatively small, so the reaction time can be shortened by adjusting the temperature. For example, the temperature of the furnace tube ammonia nitriding treatment can be set to between 700°C and 1200°C, and the treatment time can be 0.5 to 1.5 hours, as shown in the dotted box in the figure. In these embodiments, the stress range that can be offset by the oxide layer can be -60Mpa to -200Mpa.

[0050] In other embodiments, the stress-compensating layer may be a silicon nitride layer, and the denaturation treatment barrier layer may be an oxide layer. Thus, a silicon nitride layer and an oxide layer may be sequentially deposited on the dummy gate deposited layer to form a first semiconductor device. In these embodiments, a first chemical-mechanical polishing (CMP) may be further performed on the first semiconductor device using the top dummy gate platform of the dummy gate deposited layer as a CMP stop layer to expose the top dummy gate platform, thereby obtaining a second semiconductor device. The top dummy gate platform may then be subjected to a furnace dry oxygen oxidation treatment to convert the top dummy gate platform into oxide, thereby obtaining a third semiconductor device.

[0051] Figure 15 The figure shows the kinetic curve of dry oxygen oxidation in the furnace tube in the semiconductor device manufacturing method of the present application. Figure 15 As shown, the appropriate temperature and time can be selected according to the kinetic curve of the dry oxygen oxidation in the furnace tube to obtain the corresponding denaturation thickness. For example, it can be seen from the figure that as the temperature increases and the reaction time becomes longer, the denaturation thickness increases. In particular, as the temperature increases, the denaturation thickness increases sharply with the increase of the reaction time. In order to better control the denaturation thickness, an interval in which the thickness increases slightly slower can be selected. For example, the temperature of the dry oxygen oxidation treatment in the furnace tube can be set to between 750°C and 900°C, and the treatment time can be 35min~85min, as shown in the dotted box in the figure. In these embodiments, the stress range that can be offset by the silicon nitride layer can be 50Mpa~500Mpa.

[0052] pass Figure 14 and Figure 15A comparison of the two processes reveals significant differences in their kinetic curves. Specifically, furnace tube ammonia nitriding typically produces a denaturation thickness between 25 Å and 55 Å, with a slower denaturation rate. Furnace tube dry oxygen oxidation typically produces a denaturation thickness between 5nm and 15nm, with a faster denaturation rate. This suggests that furnace tube dry oxygen oxidation offers greater denaturation thickness and a deeper oxidation depth, enabling planarization of dummy gates with greater height differences when combined with chemical mechanical polishing. Furnace tube ammonia nitriding is more suitable for applications with smaller dummy gate height differences and allows for more detailed control of the denaturation thickness.

[0053] The present application also provides a semiconductor device manufactured by the semiconductor device manufacturing method according to the embodiment of the present application. Figure 13 A schematic diagram of the structure of the target semiconductor device obtained by the semiconductor device fabrication method of the present application is shown. As shown in the figure, the STI oxide and the AA region of the semiconductor device are not on the same horizontal plane. In addition, due to the different thicknesses of the isolation oxide in different HV / LV regions, the lower surface of the dummy gate deposited layer of the semiconductor device presents steps with a height difference. However, after being processed by the method of the embodiment of the present application, the upper surface of the dummy gate deposited layer is flat, that is, the dummy gate deposited layer in the semiconductor device is planarized.

[0054] Although multiple embodiments of the present application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art can conceive of many changes, modifications, and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The accompanying claims are intended to define the scope of protection of the present application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a stress-compensating layer and a denaturation-blocking layer on the dummy gate deposition layer to obtain a first semiconductor device; The pseudo gate deposition layer has steps with different heights; performing a first chemical mechanical polishing on the first semiconductor device using a top surface of a dummy gate platform on top of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a second semiconductor device; performing material modification processing on the top dummy gate platform of the second semiconductor device to obtain a third semiconductor device; The third semiconductor device is subjected to a second chemical mechanical polishing process using the top of the dummy gate deposition layer as a chemical mechanical polishing stop layer to obtain a fourth semiconductor device, wherein the height difference of the dummy gate deposition layer of the fourth semiconductor device is reduced compared with the first semiconductor device.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: After obtaining the fourth semiconductor device, the method further includes: The material modification process and the second chemical mechanical polishing are cyclically performed until a height difference of the dummy gate deposition layer is smaller than a predetermined value.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The number of cycles is determined based on a height difference and / or a number of steps of the dummy gate deposition layer of the first semiconductor device.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The stress-compensating layer is an oxide layer, and the degeneration treatment barrier layer is a silicon nitride layer; wherein the forming of the stress-compensating layer and the degeneration treatment barrier layer on the dummy gate deposition layer comprises: The oxide layer and the silicon nitride layer are sequentially deposited on the dummy gate deposition layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: Performing material modification on the top pseudo-gate platform includes: The top dummy gate platform is subjected to furnace nitriding treatment, so that the top dummy gate platform is converted into silicon nitride.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The stress-compensating layer is a silicon nitride layer, and the degeneration treatment barrier layer is an oxide layer; wherein the forming of the stress-compensating layer and the degeneration treatment barrier layer on the dummy gate deposition layer comprises: The silicon nitride layer and the oxide layer are sequentially deposited on the dummy gate deposition layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: Performing material modification on the top pseudo-gate platform includes: The top dummy gate platform is subjected to a furnace tube oxidation treatment, so that the top dummy gate platform is converted into oxide.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The method further comprises: The stress compensation layer and the degeneration process barrier layer remaining on the fourth semiconductor device are removed.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The removing of the residual stress compensation layer and the degeneration treatment barrier layer on the fourth semiconductor device includes: Perform any of the following treatments on the remaining stress-compensating layer and the denaturation-processing barrier layer on the fourth semiconductor device: Chemical mechanical polishing, dry etching and wet etching.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured based on the semiconductor device manufacturing method according to any one of claims 1 to 9.

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