Semiconductor device

Abstract

A semiconductor device includes a substrate having a first surface and an opposing second surface, a pair of trench isolations penetrating the substrate, a first well region and a second well region in the substrate between the pair of trench isolations and in contact with each other. The semiconductor device includes nanosheets and sacrificial dielectric patterns alternately stacked on the first well region and the second well region, a first passive gate structure overlapping first ends of the nanosheets and the sacrificial dielectric patterns in a second horizontal direction, and a second passive gate structure overlapping the nanosheet and a second end of the sacrificial dielectric pattern. The semiconductor device further includes a first impurity region on the first well region and connected to the first well region, a second impurity region on the second well region and connected to the second well region, a first contact connected to the first impurity region, and a second contact connected to the second impurity region.

Description

Technical Field

[0001] Example embodiments of the inventive concepts relate to semiconductor devices, and more particularly, to semiconductor devices including field effect transistors and diodes. Background Art

[0002] As semiconductor device sizes decrease, the need to increase the integration density of field-effect transistors on substrates has led to the development of nanosheet field-effect transistors (NSFETs), which consist of multiple nanosheets stacked on the same layout area. Recently, as semiconductor device integration increases and their sizes continue to decrease, the need to develop new structures that can improve the reliability of diodes with nanosheet field-effect transistors and similar structures has emerged. Summary of the Invention

[0003] Example embodiments of the inventive concepts are directed to a semiconductor device including a lateral diode and providing improved performance and reliability.

[0004] According to an example embodiment of the present invention, a semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; a pair of trench isolations, the pair of trench isolations penetrating the substrate; a first well region and a second well region, the first well region and the second well region being arranged in the substrate along a first horizontal direction between the pair of trench isolations, the first well region and the second well region being in contact with each other; a plurality of nanosheets and a plurality of sacrificial dielectric patterns, the plurality of nanosheets and the plurality of sacrificial dielectric patterns being alternately stacked in a vertical direction on the first well region and the second well region; a first passive gate structure, the first passive gate structure overlapping with first ends of the plurality of nanosheets and the plurality of sacrificial dielectric patterns in a second horizontal direction perpendicular to the first horizontal direction; and a second A passive gate structure, wherein the second passive gate structure overlaps with the second ends of the plurality of nanosheets and the plurality of sacrificial dielectric patterns in the second horizontal direction, and the first end and the second end are opposite to each other in the first horizontal direction; a first impurity region, wherein the first impurity region is located on the first well region and connected to the first well region, and the first impurity region penetrates the plurality of nanosheets and the plurality of sacrificial dielectric patterns in a vertical direction; a second impurity region, wherein the second impurity region is located on the second well region and connected to the second well region, and the second impurity region penetrates the plurality of nanosheets and the plurality of sacrificial dielectric patterns in the vertical direction; a first contact, wherein the first contact is connected to the first impurity region; and a second contact, wherein the second contact is connected to the second impurity region.

[0005] According to example embodiments of the inventive concepts, a semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; a pair of trench isolations penetrating the substrate and spaced apart from each other in a first horizontal direction; a plurality of nanosheets and a plurality of sacrificial dielectric patterns, the plurality of nanosheets and the plurality of sacrificial dielectric patterns being alternately stacked on the substrate in a vertical direction between the pair of trench isolations; a first passive gate structure overlapping first ends of the plurality of nanosheets and the plurality of sacrificial dielectric patterns in a second horizontal direction perpendicular to the first horizontal direction; a second passive gate structure overlapping second ends of the plurality of nanosheets and the plurality of sacrificial dielectric patterns in the second horizontal direction, the first ends and the second ends being opposite to each other in the first horizontal direction; a first impurity region penetrating the substrate, the plurality of nanosheets, and the plurality of sacrificial dielectric patterns in the vertical direction; a second impurity region penetrating the substrate, the plurality of nanosheets, and the plurality of sacrificial dielectric patterns in the vertical direction; a first contact connected to the first impurity region; and a second contact connected to the second impurity region.

[0006] According to example embodiments of the present inventive concepts, a semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; a pair of trench isolations penetrating the substrate; a first well region and a second well region, the first well region and the second well region being disposed in the substrate along a first horizontal direction between the pair of trench isolations, the first well region and the second well region contacting each other; a plurality of nanosheets and a plurality of sacrificial dielectric patterns, the plurality of nanosheets and the plurality of sacrificial dielectric patterns being alternately stacked along a vertical direction on the first well region and the second well region; a first impurity region penetrating the plurality of nanosheets and the plurality of sacrificial dielectric patterns along the vertical direction on the first well region, the first impurity region contacting the first well region; a second impurity region penetrating the plurality of nanosheets and the plurality of sacrificial dielectric patterns along the vertical direction on the second well region, the second impurity region contacting the second well region; a first contact connected to the first impurity region; a second contact connected to the second impurity region; and a backside power supply network disposed below the second surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present disclosure, reference is now made to the following brief description taken in conjunction with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0008] Figure 1A is a plan view illustrating components of a semiconductor device according to example embodiments.

[0009] Figure 1B It is along Figure 1A A cross-sectional view taken along line BB' in FIG.

[0010] Figure 2A is a plan view illustrating components of a semiconductor device according to example embodiments.

[0011] Figure 2B It is along Figure 2A A cross-sectional view taken along line BB' in FIG.

[0012] Figure 3A is a plan view of a semiconductor device according to example embodiments.

[0013] Figure 3B is a plan view of another semiconductor device according to example embodiments.

[0014] Figure 4 is a cross-sectional view of a semiconductor device according to example embodiments.

[0015] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 14 are cross-sectional views illustrating operations in a method of fabricating a semiconductor device according to example embodiments.

[0016] Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 and Figure 23 are cross-sectional views illustrating operations in a method of fabricating a semiconductor device according to other example embodiments.

[0017] Figure 24 A configuration of a system including a semiconductor device according to example embodiments is shown. DETAILED DESCRIPTION

[0018] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When preceding a list of elements, expressions such as "at least one of" modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C," "at least one of A, B, or C") can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as, for example, ABC, AB, BC, and AC.

[0019] It will be understood that elements and / or their properties may be described herein as being "the same" or "equal" to other elements, and it will be further understood that elements and / or their properties described herein as being "the same", "identical" or "equal" to other elements may be "same", "identical" or "equal" or "substantially the same", "substantially the same" or "substantially equal" to other elements and / or their properties. Elements and / or their properties that are "substantially the same", "substantially the same" or "substantially equal" to other elements and / or their properties will be understood to include elements and / or their properties that are the same, identical or equal to other elements and / or their properties within manufacturing tolerances and / or material tolerances. Elements and / or their properties that are the same or substantially the same and / or identical or substantially the same as other elements and / or their properties may be identical or substantially the same in structure, identical or substantially the same in function, and / or identical or substantially the same in composition. Although the terms "same", "equal" or "the same" may be used in the description of some example embodiments, it will be understood that some imprecision may exist. Thus, when one element, value, and / or attribute is referred to as being the same as another element, value, and / or attribute, it should be understood that the one element, value, and / or attribute is the same as the other element, value, and / or attribute within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0020] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value include a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the terms "approximately" or "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but rather that the degree of freedom of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "approximately" or "substantially," it will be understood that these numerical values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0021] Figure 1A is a plan view illustrating components of a semiconductor device 10 according to example embodiments. Figure 1BIt is along Figure 1A A cross-sectional view taken along line BB' in FIG.

[0022] refer to Figure 1A and Figure 1B The semiconductor device 10 may include a lateral diode formed on a substrate 101. The substrate 101 may include a wafer containing silicon (Si). In some example embodiments, the substrate 101 may be or include a semiconductor material such as germanium (Ge) or a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or combinations thereof. In some example embodiments, the substrate 101 may have a silicon-on-insulator (SOI) structure.

[0023] A pair of trench isolations (STIs) may be provided on the substrate 101 to separate (or isolate) regions forming the lateral diode. In some embodiments, each trench isolation (STI) may be a shallow trench isolation extending through the substrate 101. The trench isolation (STI) may have a double-layer structure including an interface layer and a buried dielectric layer.

[0024] Furthermore, as shown in the figure, substrate 101 may include a first well region NW and a second well region PW disposed between a pair of trench isolations (STI) in a first horizontal direction (X direction) and in contact with each other (e.g., directly in contact with each other along the Y direction). Each of the first well region NW and the second well region PW may be formed using a doping process. For example, the first well region NW is a region doped with impurities having a first conductivity type, and the second well region PW is a region doped with impurities having a second conductivity type different from the first conductivity type. Here, the first conductivity type may be n-type, and the second conductivity type may be p-type, but are not limited thereto. Therefore, the first well region NW may also be referred to as an n-type well, and the second well region PW may be referred to as a p-type well.

[0025] In the semiconductor device 10 of the present invention, a lateral PN junction diode can be formed by a contact interface IF where the first well region NW and the second well region PW contact each other. Furthermore, the semiconductor device 10 can include a gate structure GS, which can be vertically offset (or otherwise misaligned) relative to the contact interface IF. In an example embodiment, and as shown, the gate structure GS is not directly above the contact interface IF. In other words, the gate structure GS does not directly overlap the contact interface IF.

[0026] In some example embodiments, the substrate 101 including the first well region NW and the second well region PW may be planarized (e.g., to reduce the thickness (Z direction) of the substrate 101) such that the upper (or top) surfaces of the first well region NW and the second well region PW may be substantially at the same height as the upper (or top) surface of the substrate 101, and the lower (or bottom) surfaces of the first well region NW and the second well region PW may be substantially at the same height as the lower (or bottom) surface of the substrate 101.

[0027] Multiple nanosheets N1, N2, N3 (collectively referred to as nanosheets NS) and multiple sacrificial dielectric patterns 110S may form a stacked structure 111 including multiple nanosheets NS and multiple sacrificial dielectric patterns 110S alternately stacked on the first well region NW and the second well region PW along a vertical direction (Z direction).

[0028] In some example embodiments, the nanosheets NS may be spaced apart from each other in the vertical direction (Z direction), and a sacrificial dielectric pattern may be included between adjacent nanosheets NS (e.g., nanosheets N1 and N2). Each nanosheet NS may include a semiconductor element (such as Si or Ge), or a compound semiconductor (such as SiC, GaAs, InAs, or InP), or equivalents thereof.

[0029] In example embodiments, each nanosheet NS may be a sheet-like structure having a semiconductor pattern and having a width in a first horizontal direction (X direction) greater than a thickness in a vertical direction (Z direction). For example, the width of each nanosheet NS in the first horizontal direction (X direction) may be in a range of approximately 5 nm to approximately 100 nm, and the thickness in the vertical direction (Z direction) may be in a range of approximately 1 nm to approximately 10 nm. However, example embodiments are not limited thereto, and the width and thickness of the nanosheet NS may vary depending on design and application requirements. In some embodiments, at least one nanosheet (e.g., N1, N2, N3) among the plurality of nanosheets NS may have a different thickness in the vertical direction (Z direction) than the remaining nanosheets NS.

[0030] Although Figure 1B Three nanosheets N1, N2, and N3 are shown spaced apart from each other in the vertical direction (Z direction), but it should be understood that the number of nanosheets NS is not limited thereto and may be increased or decreased according to application and design requirements. According to example embodiments, in semiconductor device 10, nanosheets NS may form part of a lateral diode.

[0031] According to example embodiments, in the semiconductor device 10, a sacrificial dielectric pattern 110S may be disposed between the nanosheets NS. The plurality of sacrificial dielectric patterns 110S include a dielectric pattern. The sacrificial dielectric pattern 110S may constitute a portion of a lateral diode. Although Figure 1B Three sacrificial dielectric patterns 110S are shown spaced apart from each other in the vertical direction (Z direction), but it will be understood that the number of sacrificial dielectric patterns 110S is not limited thereto and may be increased or decreased according to application and design needs.

[0032] In some example embodiments, the width of the nanosheet NS in the first horizontal direction (X direction) may be substantially the same as the width of the sacrificial dielectric pattern 110S in the first horizontal direction (X direction). In some example embodiments, an end of the nanosheet NS in the first horizontal direction (X direction) and each end of a pair of trench isolations (STI) on the upper surface of the substrate 101 may coincide with (or otherwise be aligned with) each other in the vertical direction (Z direction).

[0033] The semiconductor device 10 may include a gate structure GS disposed at opposite ends of the nanosheet NS and the sacrificial dielectric pattern 110S in a first horizontal direction (X direction). Each gate structure GS may extend along and overlap (e.g., completely overlap) edges of the nanosheet NS and the sacrificial dielectric pattern 110S in a second horizontal direction (Y direction). Each gate structure GS may also partially overlap edges of the nanosheet NS and the sacrificial dielectric pattern 110S in the first horizontal direction (X direction). Figure 1A and Figure 1B The illustrated gate structure GS may be referred to as a passive gate structure or a dummy gate structure. This is distinct from an "active gate structure" or a "functional gate structure," which refers to a gate structure used to control the output current of a semiconductor device (i.e., the flow of carriers in the channel). The gate structure GS may not be used to control the output current of the semiconductor device 10 (or to operate in other ways).

[0034] The gate structure GS may include a gate spacer 120 and a gate electrode 130 surrounded by the gate spacer 120. In some example embodiments, the gate spacer 120 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or any combination thereof. In some example embodiments, the gate electrode 130 may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or any combination thereof. For example, the gate electrode 130 may include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or any combination thereof.

[0035] The semiconductor device 10 may include a first impurity region NC on the first well region NW, the first impurity region NC being electrically connected to the first well region NW and penetrating the nanosheet NS and the sacrificial dielectric pattern 110S in the vertical direction (Z direction). The semiconductor device 10 may include a second impurity region PC on the second well region PW, the second impurity region PC being electrically connected to the second well region PW and penetrating the nanosheet NS and the sacrificial dielectric pattern 110S in the vertical direction (Z direction). Figure 1A and Figure 1B As shown, the first impurity region NC and the second impurity region PC may form a portion of a lateral diode.

[0036] The first impurity region NC and the second impurity region PC may electrically connect the first well region NW and the second well region PW to the contact CT. Therefore, the first impurity region NC may include impurities of the same conductivity type as the first well region NW (e.g., n-type impurities), and the second impurity region PC may include impurities of the same conductivity type as the second well region PW (e.g., p-type impurities). Figure 9 As described, the first and second impurity regions NC and PC may be formed using an ion implantation process and a thermal treatment process, for example, and may have a predetermined conductivity type and a predetermined depth.

[0037] In some example embodiments, the upper (or top) surfaces of the first impurity region NC and the second impurity region PC may be at substantially the same height (in the Z direction) as the upper (or top) surface of the third nanosheet N3 (or the topmost nanosheet among the plurality of nanosheets NS). In some example embodiments, the lower (or bottom) surface of the first impurity region NC and the lower (or bottom) surface of the second impurity region PC may be located inside the substrate 101 at a depth from the upper surface of the substrate 101.

[0038] The inter-gate dielectric layer 140 may be disposed to cover the pair of gate structures GS and the nanosheet NS. The inter-gate dielectric layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or any combination thereof.

[0039] The contact CT may be formed to penetrate the inter-gate dielectric layer 140 and into the third nanosheet N3 (or the topmost nanosheet among the plurality of nanosheets NS) and a portion of the sacrificial dielectric pattern 110S located below (and in direct contact with) the third nanosheet N3. The contact CT may include a first contact electrically connected to the first impurity region NC and a second contact electrically connected to the second impurity region PC. The contact CT may be disposed between the pair of gate structures GS in a first horizontal direction (X direction).

[0040] In some example embodiments, each contact CT may be formed in a double-layer structure including a buried metal layer 154 and a metal barrier film 152 surrounding the side and bottom surfaces of the buried metal layer 154. In other words, the metal barrier film 152 may be first disposed to contact a portion of the sacrificial dielectric pattern 110S and the third nanosheet N3, and then the buried metal layer 154 may be disposed over and cover the metal barrier film 152. In other embodiments, the metal barrier film 152 may be omitted, and the contact CT may be formed in a single-layer structure including the buried metal layer 154.

[0041] In some example embodiments, the metal barrier film 152 may include, for example, titanium (Ti), tantalum (Ta), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), or any combination thereof. In some example embodiments, the buried metal layer 154 may include at least one of cobalt (Co), tungsten (W), nickel (Ni), ruthenium (Ru), copper (Cu), aluminum (Al), silicides thereof, or alloys thereof. However, the metal barrier film 152 and the buried metal layer 154 are not limited thereto.

[0042] A back-end-of-line (BEOL) structure may be provided on the inter-gate dielectric layer 140 and the contact CT. The BEOL structure may include a via connected to the contact CT and a metal line connected to the via.

[0043] With the development of electronic technology, the miniaturization of semiconductor devices is progressing rapidly. These smaller semiconductor devices require not only faster operating speeds but also higher operating precision. In an exemplary embodiment, the semiconductor device 10 may further include a back side power supply network (BSPDN), which is a wiring structure that provides faster operating speeds and higher operating precision within a relatively small area.

[0044] In the semiconductor device 10 of the present invention, the BSPDN may be formed on the lower surface of the substrate 101. Alternatively, a connection structure may be further formed, such as a via contact for connecting the BSPDN structure and the lateral diode and / or nanosheet field effect transistor.

[0045] Typically, a passive gate structure may be formed on the contact interface of a diode. Due to the presence of the passive gate structure, a band-to-band tunneling effect occurs due to the gate electrode (metal material) of the passive gate structure, which results in leakage current in the semiconductor device.

[0046] In semiconductor device 10, according to the present inventive concept, first impurity region NC and second impurity region PC are formed in a lateral PN junction diode (e.g., a diode including first well region NW and second well region PW), and gate structure GS is vertically offset relative to contact interface IF. By forming gate structure GS offset from contact interface IF, the band-to-band tunneling effect caused by the gate electrode is minimized, reducing leakage current. Consequently, the performance and reliability of semiconductor device 10 are improved.

[0047] Figure 2A is a plan view illustrating components of a semiconductor device 20 according to an example embodiment. Figure 2B It is along Figure 2A A cross-sectional view taken along line BB' in FIG.

[0048] The semiconductor device 20 may be similar in some respects to Figure 1A and Figure 1B The semiconductor device 10 in FIG. 1 can therefore be easily understood with reference thereto, wherein like reference numerals denote like elements that are not described again in detail.

[0049] refer to Figure 2A and Figure 2B , the semiconductor device 20 of the present inventive concept may include a lateral diode including a first impurity region NC2 and a second impurity region PC2 .

[0050] In the semiconductor device 20, the first well region NW and the second well region PW may not exist. The semiconductor device 20 includes a substrate 101, a plurality of nanosheets NS, and a first impurity region NC2 and a second impurity region PC2. The first impurity region NC2 and the second impurity region PC2 penetrate (or are formed in) the plurality of sacrificial dielectric patterns 110S in the vertical direction (Z direction) and contact each other.

[0051] The first impurity region NC2 and the second impurity region PC2 may be doped with impurities of different conductivity types. In some embodiments, the first impurity region NC2 may include n-type impurities, and the second impurity region PC2 may include p-type impurities. Figure 18 As described, the first and second impurity regions NC2 and PC2 may be formed using, for example, an ion implantation process and a thermal treatment process, and may have a predetermined conductivity type and a predetermined depth.

[0052] Thus, a lateral PN junction diode may be formed through a contact interface IF where the first impurity region NC2 and the second impurity region PC2 contact each other. The contact interface IF may be formed across the substrate 101, the nanosheet NS, and the sacrificial dielectric pattern 110S. As shown, the gate structure GS may be formed vertically offset relative to the contact interface IF.

[0053] An upper (or top) surface of the first impurity region NC2 and an upper (or top) surface of the second impurity region PC2 may be at substantially the same height as an upper (or top) surface of the third nanosheet N3 (or the topmost nanosheet). In some example embodiments, a lower (or bottom) surface of the first impurity region NC2 and a lower (or bottom) surface of the second impurity region PC2 are at substantially the same height as a lower (or bottom) surface of the substrate 101.

[0054] The semiconductor device 20 may include a contact CT formed through the inter-gate dielectric layer 140 and into the third nanosheet N3 and the sacrificial dielectric pattern 110S. The contact CT may include a first contact electrically connected to the first impurity region NC2 and a second contact electrically connected to the second impurity region PC2. The contact CT may be disposed between the pair of gate structures GS in a first horizontal direction (X direction).

[0055] In semiconductor device 20, first impurity region NC2 and second impurity region PC2 form a lateral PN junction diode, and gate structure GS is vertically offset relative to contact interface IF of the lateral PN junction diode. By forming gate structure GS offset from contact interface IF, the band-to-band tunneling effect caused by the gate electrode is limited, and leakage current is reduced. As a result, the performance and reliability of semiconductor device 20 are improved.

[0056] According to an example embodiment, Figure 3A and Figure 3B is a schematic plan view of semiconductor device 30 and semiconductor device 40. According to an example embodiment, Figure 4 is a cross-sectional view of the semiconductor device 50 .

[0057] Semiconductor devices 30, 40, and 50 may be similar in some respects to Figure 1A 、 Figure 1B 、 Figure 2A and Figure 2B The semiconductor device 10 and the semiconductor device 20 in the drawings can therefore be easily understood with reference thereto, wherein like reference numerals denote like elements which will not be described again in detail.

[0058] refer to Figure 3AIn semiconductor device 30, multiple nanosheets NS and multiple sacrificial dielectric patterns can be formed on substrate 101 as multiple groups GRP1, GRP2, and GRP3 (collectively referred to as group GRP). Each group includes multiple nanosheets NS and multiple sacrificial dielectric patterns. Each group GRP1, GRP2, and GRP3 of nanosheets and sacrificial dielectric patterns is spaced apart from one another in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). It should be understood that the number of groups is not limited to three, and semiconductor device 30 can include two or more groups of nanosheets.

[0059] In the semiconductor device 30 , the nanosheets NS in the group GRP may be formed in a multi-fin type, wherein the nanosheets NS are spaced apart from each other in the second horizontal direction (Y direction) and each nanosheet consists of a plurality of fins extending in the second horizontal direction (Y direction).

[0060] refer to Figure 3B In the semiconductor device 40, the first impurity region NC and the second impurity region PC may each include a plurality of contacts CT. The plurality of contacts CT may be disposed between a pair of gate structures GS in a first horizontal direction (X direction). Each of the plurality of contacts CT may be electrically connected to a corresponding first impurity region NC and second impurity region PC. For example, Figure 3B As shown, the first impurity region NC may include contacts CT1, CT2, and CT3, and the second impurity region PC may include contacts CT4, CT5, and CT6. It should be understood that the number of contacts is not limited to three, and both the first impurity region NC and the second impurity region PC may include two or more contacts. Additionally or alternatively, the number of contacts on the first impurity region NC and the second impurity region PC may differ. For example, the first impurity region NC may include three contacts, while the first impurity region PC may include four or more contacts.

[0061] refer to Figure 4 In the semiconductor device 50, the passive gate structure (or dummy gate structure) GS may not be formed at the opposite ends (in the X direction) of the nanosheet NS and the sacrificial dielectric pattern 110S. Therefore, the opposite ends of the nanosheet NS and the sacrificial dielectric pattern 110S may contact the inter-gate dielectric layer 140. For example, the ends of the nanosheet NS and the sacrificial dielectric pattern 110S extending in the Y direction may directly contact the inter-gate dielectric layer 140. Similarly, the nanosheet NS and the sacrificial dielectric pattern 110S extend in the X direction and contact the passive gate structure GS ( Figure 1A and Figure 1B ) The overlapping end portions may directly contact the inter-gate dielectric layer 140.

[0062] Figures 5 to 14is a cross-sectional view illustrating operations in a method of manufacturing a semiconductor device according to an example embodiment. It should be understood that additional embodiments of the method may be Figures 5 to 14 Additional operations may be provided before, during, and after the operations in the process, and some of the operations described below may be replaced or removed. The order of operations / processing may be interchangeable, or two or more operations may be performed simultaneously.

[0063] refer to Figure 5 A substrate 101 having a first surface and a second surface opposite the first surface may be prepared. The first surface may correspond to the upper surface (or active surface) of the substrate 101, and the second surface may correspond to the lower surface (or inactive surface) of the substrate 101. A first well region NW and a second well region PW in contact with each other may be formed on the substrate 101. Each of the first well region NW and the second well region PW may be formed using a doping process. For example, the first well region NW may be a region doped with impurities of the first conductivity type, and the second well region PW may be a region doped with impurities of the second conductivity type. In example embodiments, the first conductivity type may be n-type, and the second conductivity type may be p-type, but are not limited thereto.

[0064] refer to Figure 6 Nanosheets NS and sacrificial dielectric patterns 110S may be alternately stacked along the vertical direction (Z direction) on the upper surface of substrate 101. Each nanosheet NS may be a semiconductor pattern. In some example embodiments, nanosheets NS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 spaced apart in the vertical direction (Z direction). Sacrificial dielectric patterns 110S may be formed between nanosheets NS. In some example embodiments, the width (or length) of the nanosheets NS in the first horizontal direction (X direction) and the width (or length) of the sacrificial dielectric patterns 110S in the first horizontal direction (X direction) may be substantially equal.

[0065] refer to Figure 7 Portions of the nanosheet NS and sacrificial dielectric pattern 110S at their opposite ends (in the X direction) may be etched to expose the upper surface of the substrate 101. A pair of trench isolations (STIs) may be formed from the exposed upper surface of the substrate 101. The STIs may be shallow trench isolations (STIs) that extend a certain distance from the upper (or top) surface of the substrate 101 into the first well region NW and the second well region PW. The STIs may be a dual-layer structure comprising an interface layer and a buried dielectric layer.

[0066] refer to Figure 8A sacrificial material film 130S may be formed surrounding opposite ends of the nanosheet NS and the sacrificial dielectric pattern in the first horizontal direction, and a gate spacer 120 may be formed surrounding (or covering) the sacrificial material film 130. In some example embodiments, the sacrificial material film 130S may include polysilicon, but is not limited thereto and may include other suitable materials. In some example embodiments, the gate spacer 120 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or any combination thereof.

[0067] refer to Figure 9 , impurities of different conductivity types may be implanted into the nanosheet NS and the sacrificial dielectric pattern 110S using a suitable ion implantation process (IIP). First, impurities of the same conductivity type as the first well region NW (e.g., n-type impurities) may be implanted into the nanosheet NS, the sacrificial dielectric pattern 110S, and the first well region NW. Next, impurities of the same conductivity type as the second well region PW (e.g., p-type impurities) may be implanted into the nanosheet NS, the sacrificial dielectric pattern 110S, and the second well region PW. In example embodiments, impurities may be implanted throughout the entire thickness (Z direction) of the nanosheet NS and the sacrificial dielectric pattern 110S, and the impurities may be implanted into the first and second well regions NW, PW to a depth from the upper surfaces of the first and second well regions NW, PW. The implantation may be performed using any suitable ion implantation process (IIP), and a detailed description thereof will be omitted here for the sake of brevity.

[0068] refer to Figure 10 After the thermal treatment process, the first and second impurity conductive portions NC and PC may be formed. The first and second impurity conductive portions NC and PC may electrically connect the first and second well regions NW and PW to the contact CT. In some example embodiments, the upper (or top) surface of the first and second impurity conductive portions NC and PC may be substantially at the same height as the upper (or top) surface of the third nanosheet N3. The lowermost (or bottom) surface of the first and second impurity conductive portions NC and PC may be located in the respective first and second well regions NW and PW.

[0069] Next, the sacrificial material film 130S may be removed (see Figure 9 ), and the gate electrode 130 may be formed after the sacrificial material film 130S is removed (see Figure 9 ). In some embodiments, the gate electrode 130 may include doped polysilicon, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or any combination thereof. Thus, a pair of gate structures GS may be formed around the nanosheet NS and the sacrificial dielectric pattern 110S at both ends.

[0070] refer to Figure 11 An inter-gate dielectric layer 140 may be deposited to cover the pair of gate structures GS and the nanosheet NS. In some example implementations, the inter-gate dielectric layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or any combination thereof.

[0071] refer to Figure 12 , a contact hole 140H may be formed in the inter-gate dielectric layer 140 to expose the first impurity conductive region NC and the second impurity conductive region PC.

[0072] In some embodiments, the contact hole 140H may be formed by etching the inter-gate dielectric layer 140 , the third nanosheet N3 (or the topmost nanosheet among the plurality of nanosheets), and an upper portion of the sacrificial dielectric pattern 110S using photolithography and etching processes.

[0073] In other example embodiments, the topmost sacrificial dielectric pattern 110S may not be etched, and the contact hole 140H may be formed by etching the inter-gate dielectric layer 140 and the upper portion of the third nanosheet N3 using, for example, a photolithography and etching process. The lowermost (or bottom) surface of the contact hole 140H may thus be located within the third nanosheet N3 (or the topmost nanosheet among the plurality of nanosheets).

[0074] refer to Figure 13 , the contact hole 140H can be filled (see Figure 12 ) to form contacts CT. The contacts CT may include a first contact electrically connected to the first impurity region NC and a second contact electrically connected to the second impurity region PC. The contacts CT may extend in the vertical direction (Z direction) and may be disposed between the pair of gate structures GS in the first horizontal direction (X direction). In some embodiments, each contact CT may include a dual-layer structure including a buried metal layer 154 and a metal barrier film 152 surrounding the side and bottom surfaces of the buried metal layer 154. The metal barrier film 152 may be deposited on the third nanosheet N3 exposed in the contact hole 140H and the sacrificial dielectric pattern 110S, and the buried metal layer 154 may be disposed on the metal barrier film 152 to cover the metal barrier film 152. In example embodiments, the metal barrier film 152 may be deposited only on the third nanosheet N3 without etching the top sacrificial dielectric pattern 110S.

[0075] In other example embodiments, the metal barrier film 152 may be omitted, and one or more contacts CT may be formed as a single-layer structure including a buried metal layer 154 in contact with the third nanosheet N3 and the sacrificial dielectric pattern 110S. In example embodiments, the buried metal layer 154 may be deposited only on the third nanosheet N3 without etching the top sacrificial dielectric pattern 110S.

[0076] refer to Figure 14 A bottom surface removal process may be performed to reduce the thickness of the bottom surface. The bottom surface removal process for reducing the thickness of substrate 101 may include exposing the bottom surfaces of a pair of trench isolations (STIs) by alternately performing a grinding process and a wet etching process. Therefore, after a portion of substrate 101 is removed, the bottom (or bottom) surface of substrate 101 may be at substantially the same height as the bottom (or bottom) surface of the first well region NW and the bottom (or bottom) surface of the second well region PW.

[0077] A BSPDN ( Figure 1B ), a connection structure such as a via contact for connecting the BSPDN and a lateral diode (eg, a lateral diode including the first well region NW and the second well region PW) may be further formed.

[0078] according to Figures 5 to 14 The semiconductor device 10 manufactured according to the example embodiments disclosed in the disclosure and having the first impurity conductive portion NC and the second impurity conductive portion PC in a lateral PN junction diode has improved performance and reliability.

[0079] Figures 15 to 23 is a cross-sectional view illustrating operations in a method of manufacturing a semiconductor device according to an example embodiment. It should be understood that additional embodiments of the method may be Figures 15 to 23 Additional operations may be provided before, during, and after the operations in the process, and some of the operations described below may be replaced or removed. The order of operations / processing may be interchangeable, or two or more operations may be performed simultaneously.

[0080] refer to Figure 15 A substrate 101 having a first surface and a second surface opposite the first surface may be prepared. The first surface may correspond to an upper surface (or active surface), and the second surface may correspond to a lower surface (or inactive surface). A plurality of nanosheets NS and sacrificial dielectric patterns 110S may be alternately stacked along a vertical direction (Z direction) on the upper surface of the substrate 101. Each nanosheet NS may be or include a semiconductor pattern. In some example embodiments, the nanosheets NS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 spaced apart from each other in the vertical direction (Z direction). The sacrificial dielectric patterns 110S may be formed between the nanosheets NS. In some example embodiments, the width (or length) of the nanosheets NS in the first horizontal direction (X direction) and the width (or length) of the sacrificial dielectric patterns 110S in the first horizontal direction (X direction) may be substantially equal.

[0081] refer to Figure 16A portion of opposite ends of the nanosheet NS and the sacrificial dielectric pattern 110S (in the X direction) may be etched to expose the upper surface of the substrate 101. A pair of trench isolations (STIs) may be formed from the exposed upper surface of the substrate 101. The STIs may be shallow trench isolations (STIs) extending a certain distance from the upper (or top) surface of the substrate 101 into the substrate 101. The STIs may be formed to have a dual-layer structure including an interface layer and a buried dielectric layer.

[0082] refer to Figure 17 A sacrificial material film 130S may be formed surrounding opposite ends of the nanosheet NS and the sacrificial dielectric pattern 110S in the first horizontal direction (X direction), and a gate spacer 120 may be formed surrounding (or covering) the sacrificial material film 130S. In some embodiments, the sacrificial material layer 130S may include, but is not limited to, polysilicon. In some embodiments, the gate spacer 120 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or any combination thereof.

[0083] refer to Figure 18 , impurities of different conductivity types may be implanted into the nanosheets NS, the sacrificial dielectric patterns 110S, and the substrate 101 using a suitable ion implantation process.

[0084] First, first conductivity type impurities (e.g., n-type impurities) may be implanted into a portion of substrate 101, multiple nanosheets NS, and sacrificial dielectric pattern 110S. Next, second conductivity type impurities (e.g., p-type impurities) may be implanted into another portion of substrate 101, multiple nanosheets NS, and sacrificial dielectric pattern 110S. In an exemplary embodiment, the impurities may be implanted throughout the entire thickness (Z direction) of the multiple nanosheets NS and sacrificial dielectric pattern 110S, and may be implanted to a depth from the upper surface of substrate 101. The first conductivity type impurities (e.g., n-type impurities) and the second conductivity type impurities (e.g., p-type impurities) may be implanted into adjacent locations.

[0085] The implantation may be performed using any suitable ion implantation process (IIP), and a detailed description thereof will be omitted here for the sake of brevity.

[0086] refer to Figure 19The first impurity region NC2 and the second impurity region PC2 can be formed by thermally treating implanted impurities of different conductivity types. In some embodiments, the upper surface of the first impurity region NC2 and the upper surface of the second impurity region PC2 can be at substantially the same height as the upper surface of the third nanosheet N3 (or the topmost nanosheet), and the lowermost (or bottom) surface of the first impurity region NC2 and the lowermost (or bottom) surface of the second impurity region PC2 can be spaced apart from the bottom surface of the substrate 101 (e.g., defining a gap). In other words, the lowermost (or bottom) surface of the first impurity region NC2 and the lowermost (or bottom) surface of the second impurity region PC2 can be located within the substrate 101.

[0087] Next, the sacrificial material film 130S ( Figure 18 ) may be removed, and a gate electrode 130 may be formed. In some embodiments, the gate electrode 130 may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or any combination thereof.

[0088] Therefore, a pair of gate structures GS surrounding both ends of the nanosheet NS and the sacrificial dielectric pattern 110S may be formed, respectively.

[0089] refer to Figure 20 The inter-gate dielectric layer 140 may be formed to cover the pair of gate structures GS and the plurality of nanosheets NS. In some embodiments, the inter-gate dielectric layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or any combination thereof.

[0090] refer to Figure 21 , the contact hole 140H may be formed to expose an upper portion of the first impurity region NC2 and an upper portion of the second impurity region PC2 .

[0091] In some embodiments, the contact hole 140H may be formed by etching a portion of the uppermost sacrificial dielectric pattern 110S, the inter-gate dielectric layer 140 , and the third nanosheet N3 using photolithography and etching processes.

[0092] In other embodiments, the contact hole 140H may be formed by etching the inter-gate dielectric layer 140 and the third nanosheet N3 using a photolithography and etching process without etching a portion of the uppermost sacrificial dielectric pattern 110S. Therefore, the bottom surface of the contact hole 140H may be located within the third nanosheet N3 rather than in the uppermost sacrificial dielectric pattern 110S.

[0093] refer to Figure 22 , a contact CT filling the contact hole 140H may be formed (see Figure 21). The contact CT may include a first contact electrically connected to the first impurity region NC2 and a second contact electrically connected to the second impurity region PC2. The contact CT may be disposed between the pair of gate structures GS in the first horizontal direction (X direction).

[0094] In some example embodiments, each contact CT may be a double-layer structure including a buried metal layer 154 and a metal barrier film 152 surrounding the side and bottom surfaces of the buried metal layer 154. The metal barrier film 152 may be deposited on the third nanosheet N3 and the sacrificial dielectric pattern 110S exposed to the contact hole 140H, and the buried metal layer 154 may be provided on the metal barrier film 152 to cover the metal barrier film 152. In example embodiments, the metal barrier film 152 may be omitted, and one or more contacts CT may be formed as a single-layer structure including the buried metal layer 154 in contact with the third nanosheet N3 and the sacrificial dielectric pattern 110S. In example embodiments, the buried metal layer 154 may be deposited only on the third nanosheet N3 without etching the top sacrificial dielectric pattern 110S.

[0095] refer to Figure 23 , a bottom surface removal process may be performed to reduce the thickness of the substrate 101. The bottom surface removal process to reduce the thickness of the substrate 101 may include a process of exposing the bottom surfaces of the pair of trench isolations (STI) by alternately performing a grinding process and a wet etching process. Therefore, after a portion of the substrate 101 is removed, the bottom surface of the substrate 101 may be at substantially the same height as the bottom surface of the first impurity region NC2 and the bottom surface of the second impurity region PC2.

[0096] A BSPDN ( Figure 2B ), a connection structure such as a via contact for connecting the BSPDN and a lateral diode (eg, a lateral diode including the first impurity region NC2 and the second impurity region PC2) may be further formed.

[0097] according to Figures 15 to 23 The semiconductor device 20 manufactured according to the example embodiments disclosed in the specification and having the first impurity region NC2 and the second impurity region PC2 in a lateral PN junction has improved performance and reliability.

[0098] Figure 24 is a configuration of a system 1000 including a semiconductor device according to the above-described example embodiment. Figure 24System 1000 may include a controller 1010, an input / output device 1020, a storage device 1030, an interface 1040, and a bus 1050. System 1000 may be a mobile system or a system for transmitting or receiving information. In some embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, a memory card, etc. Controller 1010 is configured to execute program code stored in memory device 1030 for performing various operations of system 1000. Controller 1010 is any electronic circuit, including but not limited to a microprocessor, a digital signal processor, a microcontroller, or the like.

[0099] The input / output device 1020 can be used to input or output data to or from the system 1000. The system 1000 can be connected to an external device, such as a personal computer or a network, using the input / output device 1020 and can exchange data with the external device. The input / output device 1020 can be, for example, a touch screen, a touchpad, a keyboard, or a display.

[0100] The memory device 1030 may store data for operating the controller 1010 or store data processed by the controller 1010. According to the above embodiments, the memory device 1030 may include any one of the semiconductor devices 10, 20, 30, 40, and 50.

[0101] The interface 1040 can be a data transmission path between the system 1000 and external devices. The controller 1010 is configured to send and receive data using the interface 1040. As will be appreciated by those skilled in the art, the interface 1040 can be configured to use any suitable type of communication protocol. The controller 1010, the input / output device 1020, the storage device 1030, and the interface 1040 can communicate with each other via a bus 1050.

[0102] Although some embodiments have been provided in this disclosure, it should be understood that the disclosed systems and methods may be implemented in many other specific forms without departing from the spirit or scope of the present disclosure. The present embodiments are to be considered illustrative rather than restrictive, and are not intended to be limiting of the details given herein. For example, various elements or components may be combined or integrated into another system, or certain features may be omitted or not implemented.

[0103] In addition, without departing from the scope of the present disclosure, the techniques, systems, subsystems, and methods described and illustrated as discrete or separate in various embodiments may be combined or integrated with other systems, modules, techniques, or methods. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through an interface, device, or intermediate component that is electrically, mechanically, or otherwise. Other examples of changes, substitutions, and modifications are ascertainable by those skilled in the art and may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a substrate having a first surface and a second surface opposite to the first surface; a pair of trench isolations penetrating the substrate; a first well region and a second well region, the first well region and the second well region being disposed in the substrate along a first horizontal direction between the pair of trench isolations, the first well region and the second well region being in contact with each other; a plurality of nanosheets and a plurality of sacrificial dielectric patterns, wherein the plurality of nanosheets and the plurality of sacrificial dielectric patterns are alternately stacked in a vertical direction on the first well region and the second well region; a first passive gate structure overlapping the plurality of nanosheets and first ends of the plurality of sacrificial dielectric patterns in a second horizontal direction perpendicular to the first horizontal direction; a second passive gate structure, the second passive gate structure overlapping the second ends of the plurality of nanosheets and the plurality of sacrificial dielectric patterns in the second horizontal direction, the first ends and the second ends being opposite to each other in the first horizontal direction; a first impurity region, the first impurity region being located on and connected to the first well region, the first impurity region penetrating the plurality of nanosheets and the plurality of sacrificial dielectric patterns in the vertical direction; a second impurity region, the second impurity region being located on and connected to the second well region, the second impurity region penetrating the plurality of nanosheets and the plurality of sacrificial dielectric patterns in the vertical direction; a first contact connected to the first impurity region; as well as A second contact is connected to the second impurity region.

2. The semiconductor device according to claim 1, wherein The first well region and the second well region are in contact in the first horizontal direction and define an interface between the first well region and the second well region, and The first passive gate structure and the second passive gate structure are positioned to be vertically offset relative to the interface.

3. The semiconductor device according to claim 2, wherein The first contact and the second contact are disposed between the first passive gate structure and the second passive gate structure in the first horizontal direction.

4. The semiconductor device according to claim 1, wherein The first impurity region and the second impurity region are regions doped with impurities of different conductivity types in the plurality of nanosheets and the plurality of sacrificial dielectric patterns.

5. The semiconductor device according to claim 4, wherein The plurality of nanosheets include semiconductor patterns, and the plurality of sacrificial dielectric patterns include dielectric patterns.

6. The semiconductor device according to claim 4, wherein The uppermost surface of the first impurity region and the uppermost surface of the second impurity region are at substantially the same height as the uppermost surfaces of the plurality of nanosheets, and The lowermost surface of the first impurity region and the lowermost surface of the second impurity region are located between the first surface and the second surface of the substrate.

7. The semiconductor device according to claim 1, wherein A length of each of the plurality of nanosheets in the first horizontal direction and a length of each of the plurality of sacrificial dielectric patterns in the first horizontal direction are substantially the same.

8. The semiconductor device according to claim 1, wherein The first well region and the second well region are regions in the substrate doped with impurities of different conductivity types, and The first well region and the second well region contact each other to form a lateral diode.

9. The semiconductor device according to claim 8, wherein The upper surface of the first well region and the upper surface of the second well region are at substantially the same height as the first surface of the substrate, and A lowermost surface of the first well region and a lowermost surface of the second well region are at substantially the same height as the second surface of the substrate.

10. The semiconductor device according to claim 1, wherein The first impurity region and the first well region include impurities of a first conductivity type, The second impurity region and the second well region include impurities of a second conductivity type, and The first conductivity type impurities and the second conductivity type impurities have opposite conductivity types.

11. A semiconductor device, comprising: a substrate having a first surface and a second surface opposite to the first surface; a pair of trench isolations penetrating the substrate and spaced apart from each other in a first horizontal direction; a plurality of nanosheets and a plurality of sacrificial dielectric patterns, the plurality of nanosheets and the plurality of sacrificial dielectric patterns being alternately stacked on the substrate along a vertical direction between the pair of trench isolations; a first passive gate structure overlapping the plurality of nanosheets and first ends of the plurality of sacrificial dielectric patterns in a second horizontal direction perpendicular to the first horizontal direction; a second passive gate structure, the second passive gate structure overlapping the second ends of the plurality of nanosheets and the plurality of sacrificial dielectric patterns in the second horizontal direction, the first ends and the second ends being opposite to each other in the first horizontal direction; a first impurity region, the first impurity region penetrating the substrate, the plurality of nanosheets, and the plurality of sacrificial dielectric patterns in the vertical direction; a second impurity region penetrating the substrate, the plurality of nanosheets, and the plurality of sacrificial dielectric patterns in the vertical direction; a first contact connected to the first impurity region; as well as A second contact is connected to the second impurity region.

12. The semiconductor device according to claim 11, wherein The first impurity region and the second impurity region are in contact with each other in the first horizontal direction and define an interface between the first impurity region and the second impurity region. The first passive gate structure and the second passive gate structure are positioned vertically offset relative to the interface, and The first contact and the second contact are disposed between the pair of passive gate structures in the first horizontal direction.

13. The semiconductor device according to claim 11, further comprising: A first well region and a second well region are disposed in the substrate along the first horizontal direction between the pair of trench isolations, wherein the first well region and the second well region are in contact with each other.

14. The semiconductor device according to claim 11, wherein The first impurity region and the second impurity region are doped with impurities of different conductivity types, and The first impurity region and the second impurity region are in contact with each other to form a lateral diode.

15. The semiconductor device according to claim 11, wherein The uppermost surface of the first impurity region and the uppermost surface of the second impurity region are at substantially the same height as the uppermost surfaces of the plurality of nanosheets, and A lowermost surface of the first impurity region and a lowermost surface of the second impurity region are at substantially the same height as the second surface of the substrate.

16. The semiconductor device according to claim 11, wherein A length of each of the plurality of nanosheets in the first horizontal direction and a length of each of the plurality of sacrificial dielectric patterns in the first horizontal direction are substantially the same.

17. A semiconductor device, comprising: a substrate having a first surface and a second surface opposite to the first surface; a pair of trench isolations penetrating the substrate; a first well region and a second well region, the first well region and the second well region being disposed in the substrate along a first horizontal direction between the pair of trench isolations, the first well region and the second well region being in contact with each other; a plurality of nanosheets and a plurality of sacrificial dielectric patterns, wherein the plurality of nanosheets and the plurality of sacrificial dielectric patterns are alternately stacked in a vertical direction on the first well region and the second well region; a first impurity region, wherein the first impurity region penetrates the plurality of nanosheets and the plurality of sacrificial dielectric patterns along the vertical direction on the first well region, and the first impurity region contacts the first well region; a second impurity region, wherein the second impurity region penetrates the plurality of nanosheets and the plurality of sacrificial dielectric patterns along the vertical direction on the second well region, and the second impurity region contacts the second well region; a first contact connected to the first impurity region; a second contact connected to the second impurity region; as well as A backside power supply network is provided below the second surface of the substrate.

18. The semiconductor device according to claim 17, further comprising: A plurality of first contacts and a plurality of second contacts are arranged along the first horizontal direction.

19. The semiconductor device according to claim 17, wherein The plurality of nanosheets and the plurality of sacrificial dielectric patterns constitute a plurality of groups, and The plurality of groups are arranged along a second horizontal direction perpendicular to the first horizontal direction.

20. The semiconductor device according to claim 17, wherein The first well region and the second well region are doped with impurities of different conductivity types, and The first well region and the second well region contact each other to form a lateral diode.

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