Array substrate and display panel

Abstract

The embodiment of the invention discloses an array substrate and a display panel, the array substrate comprises a shading layer and a first active layer, and a first pole plate of the shading layer and a first conductive part of the first active layer are at least partially overlapped to form a first storage capacitor; the first pole plate comprises a first electrode part and a second electrode part, the first conductive part comprises a first part and a second part, the first electrode part and the first part are at least partially overlapped to form a first capacitor part of the first storage capacitor, and the second electrode part and the second part are at least partially overlapped to form a second capacitor part of the first storage capacitor. According to the array substrate disclosed by the embodiment of the invention, the first storage capacitor with relatively high charge capacity is formed by adopting the special-shaped first conductive part and the first polar plate of the light shielding layer, so that the storage capacitor corresponding to the pixel electrode is compensated, and the risk of image ghosting and non-uniform display is reduced; and secondly, based on the fact that the first capacitor part is arranged on at least one side of the second capacitor part, the layout space can be reduced to meet the requirement of the aperture ratio.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] As LCD panels become more advanced, high-resolution and high-quality panels are becoming the trend in panel development. LTPO technology, a high-end panel technology that combines the advantages of low-temperature polysilicon (LTPS) transistors and metal oxide semiconductor transistors, is widely used in small and medium-sized display applications.

[0003] During the research and practice of existing technologies, the inventors of this application discovered that LTPO technology combines the high resolution and high refresh rate of LTPS technology with the low power consumption, high aperture, and high penetration performance of metal oxide semiconductor technology. However, the demand for high resolution reduces the size of the pixel structure, resulting in insufficient storage capacitance, which in turn leads to image sticking and uneven display. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate and a display panel, which can maintain the aperture ratio requirement while increasing the storage capacitance to reduce the risk of image sticking and display unevenness.

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] a light shielding layer, disposed on the substrate, configured to receive a common signal, the light shielding layer comprising a light shielding portion and a first electrode plate, wherein the first electrode plate is connected to one side of the light shielding portion;

[0008] a first thin film transistor, the first thin film transistor comprising a first gate and a first active layer, the first active layer being disposed on a side of the light shielding layer away from the substrate and being disposed in a different layer from the light shielding layer, the first gate being disposed on a side of the first active layer away from the substrate and being disposed in a different layer from the first active layer, the first active layer comprising a connected channel portion and a first conductive portion, and in a thickness direction of the array substrate, at least a portion of the first gate overlapping with the channel portion, and the channel portion overlapping with the light shielding portion;

[0009] a pixel electrode, disposed on a side of the first gate away from the substrate and in a different layer from the first gate; the first conductive portion is configured to transmit a voltage signal to the pixel electrode;

[0010] In the array substrate viewed from a top perspective, the first electrode plate and the first conductive portion at least partially overlap to form a first storage capacitor; the first electrode plate includes a first electrode portion and a second electrode portion, the first electrode portion is connected to at least one side of the second electrode portion, and the first conductive portion includes a first portion and a second portion, the second portion is connected to the channel portion in a lengthwise direction of the channel portion, and the first portion is connected to at least one side of the second portion in a direction intersecting the lengthwise direction of the channel portion;

[0011] The first electrode portion and the first portion at least partially overlap to form a first capacitor portion of the first storage capacitor, and the second electrode portion and the second portion at least partially overlap to form a second capacitor portion of the first storage capacitor.

[0012] Optionally, in some embodiments of the present application, the light shielding layer further includes a second electrode plate connected to at least one side of the second electrode portion, the pixel electrode includes a connecting portion and a third electrode plate, the connecting portion is electrically connected to the first conductive portion, and the third electrode plate is connected to a side of the connecting portion close to the first gate;

[0013] In the array substrate viewed from a top perspective, the third electrode plate and the second electrode plate at least partially overlap to form a second storage capacitor.

[0014] Optionally, in some embodiments of the present application, in the array substrate viewed from a top perspective, the connecting portion is located within the contour area of ​​the first conductive portion, and in the first direction, a portion of the third electrode is located within the contour area of ​​the first conductive portion.

[0015] Optionally, in some embodiments of the present application, the distance from the third electrode plate to the second electrode plate is greater than the distance from the first electrode plate to the first conductive portion.

[0016] Optionally, in some embodiments of the present application, the pixel electrode also includes a fourth plate connected to the third plate on the side close to the first gate. In the array substrate viewed from a top perspective, the fourth plate and the first gate at least partially overlap to form a third storage capacitor.

[0017] Optionally, in some embodiments of the present application, the first gate includes a control portion and an extension portion connected to at least one side of the control portion, and the control portion and the channel portion are arranged in an overlapping manner; the fourth electrode portion includes a third electrode portion and a fourth electrode portion, and the third electrode portion is connected to at least one side of the fourth electrode portion; in the array substrate viewed from a top perspective, the third electrode portion and the extension portion at least partially overlap to form the third capacitor portion of the third storage capacitor, and the fourth electrode portion and the control portion at least partially overlap to form the fourth capacitor portion of the third storage capacitor.

[0018] Optionally, in some embodiments of the present application, in the array substrate viewed from a top perspective, a width direction of the channel portion is a first direction, and a length direction of the channel portion is a second direction; the second electrode portion, the second portion, and the connecting portion extend along the second direction, and the first electrode portion, the first portion, the second electrode plate, and the third electrode plate extend along the first direction;

[0019] In the first direction, one first electrode portion is connected to one side of the second electrode portion, another first electrode portion is connected to the other side of the second electrode portion, one first portion is connected to one side of the second portion, another first portion is connected to the other side of the second portion, and one first electrode portion at least partially overlaps with one first portion to form a first capacitor portion;

[0020] In the first direction, one of the extension portions is connected to one side of the control portion, another of the extension portions is connected to the other side of the control portion, one of the third electrode portions is connected to one side of the fourth electrode portion, another of the third electrode portions is connected to the other side of the fourth electrode portion, and one of the third electrode portions corresponds to at least partially overlapping with one of the extension portions to form a third capacitor portion.

[0021] Optionally, in some embodiments of the present application, the distance from the fourth electrode plate to the first grid is greater than the distance from the first electrode plate to the first conductive portion and is less than the distance from the third electrode plate to the second electrode plate.

[0022] Optionally, in some embodiments of the present application, the first thin film transistor further includes a first input electrode, the first active layer includes a second conductive portion connected to the channel portion, the first input electrode is connected to the second conductive portion through a first via hole, and the pixel electrode is electrically connected to the first conductive portion through a second via hole;

[0023] In the non-opening area of ​​the array substrate in a top view, in the second direction, the connecting portion, the third electrode plate, and the fourth electrode plate are located between the first via hole and the second via hole.

[0024] Optionally, in some embodiments of the present application, the light shielding layer is reused as another first gate of the first thin film transistor.

[0025] Optionally, in some embodiments of the present application, the array substrate further includes a second thin film transistor and a common electrode, the second thin film transistor includes a second gate, a second input electrode, a second output electrode, and a second active layer, and a material of the second active layer is different from a material of the first active layer;

[0026] The second active layer is provided on the substrate, the second gate electrode and the light shielding layer are provided in the same layer on a side of the second active layer away from the substrate, the second input electrode, the second output electrode and the first input electrode are provided in the same layer on a side of the first gate electrode away from the substrate; the common electrode and the pixel electrode are provided in the same layer on a side of the first input electrode away from the substrate;

[0027] In the thickness direction of the array substrate, a first insulating layer is provided between the second active layer and the second gate electrode, a second insulating layer is provided between the light shielding layer and the first active layer, a third insulating layer is provided between the first active layer and the first gate electrode, a fourth insulating layer is provided between the first gate electrode and the first input electrode, and a fifth insulating layer is provided between the pixel electrode and the first input electrode;

[0028] The pixel electrode is directly connected to the first conductive portion; or, the pixel electrode is connected to the first conductive portion through the first input electrode of the first thin film transistor.

[0029] Optionally, in some embodiments of the present application, the fourth insulating layer and the fifth insulating layer are both inorganic insulating layers, the array substrate further includes a common wiring provided in the same layer as the first input electrode, the pixel electrode is directly connected to the first conductive portion through the second via hole, and the common electrode is connected to the common wiring through a third via hole;

[0030] The third via hole penetrates the fifth insulating layer, the second via hole penetrates the third insulating layer to the fifth insulating layer, and the second via hole and the third via hole are configured to be formed by using one photomask.

[0031] Correspondingly, an embodiment of the present application further provides a display panel, which includes an opposing substrate and the array substrate as described in any one of the above embodiments.

[0032] The array substrate of the embodiment of the present application includes a light-shielding layer and a first active layer, the first electrode of the light-shielding layer and the first conductive portion of the first active layer at least partially overlap to form a first storage capacitor; the first electrode includes a first electrode portion and a second electrode portion, the first conductive portion includes a first portion and a second portion, the first electrode portion and the first portion at least partially overlap to form a first capacitor portion of the first storage capacitor, and the second electrode portion and the second portion at least partially overlap to form a second capacitor portion of the first storage capacitor.

[0033] It can be understood that the array substrate of the embodiment of the present application uses a special-shaped first conductive portion and a first electrode of the light-shielding layer to form a first storage capacitor with a higher charge capacity to compensate for the storage capacitor corresponding to the pixel electrode, thereby reducing the risk of image retention and uneven display; secondly, based on the first capacitor portion being on at least one side of the second capacitor portion, the layout space can be reduced to meet the aperture ratio requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present application;

[0035] Figure 2 This is a schematic diagram of a top plan structure of an array substrate provided in an embodiment of the present application, located in a non-opening area;

[0036] Figure 3 yes Figure 2 Schematic diagram of removing the pixel electrode layer;

[0037] Figure 4 yes Figure 2 Schematic diagram of the first active layer in FIG;

[0038] Figure 5 yes Figure 2 Schematic diagram of the middle light-shielding layer;

[0039] Figure 6 1 is a schematic diagram of step B01 of the method for preparing an array substrate provided in an embodiment of the present application;

[0040] Figure 7 2 is a schematic diagram of step B02 of the method for preparing an array substrate provided in an embodiment of the present application;

[0041] Figure 8 2 is a schematic diagram of step B03 of the method for preparing an array substrate provided in an embodiment of the present application;

[0042] Figure 9 1 is a schematic diagram of step B04 of the method for preparing an array substrate provided in an embodiment of the present application;

[0043] Figure 10 1 is a schematic diagram of step B05 of the method for preparing an array substrate provided in an embodiment of the present application;

[0044] Figure 11 1 is a schematic diagram of step B06 of the method for preparing an array substrate provided in an embodiment of the present application;

[0045] Figure 12 is another schematic cross-sectional structure diagram of the array substrate provided in an embodiment of the present application;

[0046] Figure 13Schematic diagram of the structure of the display panel provided in an embodiment of the present application.

[0047] Description of reference numerals:

[0048] Display panel 1000; liquid crystal layer 300; opposing substrate 200; array substrate 100; non-aperture area NA; first thin film transistor t1; second thin film transistor t2; first storage capacitor c1; second storage capacitor c2; third storage capacitor c3; fourth storage capacitor c4; substrate 11; light shielding layer 12; pixel electrode 13; common electrode 14; light shielding portion 120; first electrode plate 121; second electrode plate 122; first gate g1; first input electrode s1; first output electrode d1; first active layer p1; channel portion p10; first conductive portion p11; second conductive portion p12; first electrode portion 1211; second electrode portion 1212; first portion p111 ; second part p112; first capacitor part c11; second capacitor part c12; connecting part 131; third electrode 133; fourth electrode 134; control part g11; extension part g12; third electrode part 1341; fourth electrode part 1342; third capacitor part c31; fourth capacitor part c32; first direction F1; second direction F2; first via k1; second via k2; third via k3; second gate g2; second input pole s2; second output pole d2; second active layer p2; first insulating layer 151; second insulating layer 152; third insulating layer 153; fourth insulating layer 154; fifth insulating layer 155; common routing 141; buffer layer 16. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described here are only used to illustrate and explain the present application and are not used to limit the present application. In this application, the various embodiments can be combined with each other but will not be repeated one by one. In addition, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inner" and "outer" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as labels and do not impose numerical requirements or establish an order.

[0050] The embodiments of the present application provide an array substrate and a display panel, which are described in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.

[0051] Please refer to Figures 1 to 5 An embodiment of the present application provides an array substrate 100 , which includes a substrate 11 , a light shielding layer 12 , a first thin film transistor t1 , and a pixel electrode 13 .

[0052] The light shielding layer 12 is provided on the substrate 11 . The light shielding layer 12 includes a light shielding portion 120 and a first electrode plate 121 . The first electrode plate 121 is connected to one side of the light shielding portion 120 .

[0053] The first thin-film transistor t1 includes a first gate g1 and a first active layer p1. The first active layer p1 is disposed on a side of the light-shielding layer 12 away from the substrate 11 and is disposed in a separate layer from the light-shielding layer 12. The first gate g1 is disposed on a side of the first active layer p1 away from the substrate 11 and is disposed in a separate layer from the first active layer p1. The first active layer p1 includes a connected channel portion p10 and a first conductive portion p11. In the thickness direction of the array substrate 100, at least a portion of the first gate g1 overlaps with the channel portion p10, and the channel portion p10 overlaps with the light-shielding portion 120.

[0054] The pixel electrode 13 is disposed on a side of the first gate g1 away from the substrate 11 and in a different layer from the first gate g1 . The first conductive portion p11 is configured to transmit a voltage signal to the pixel electrode 13 .

[0055] In the array substrate 100, viewed from above, the first electrode plate 121 and the first conductive portion p11 at least partially overlap to form a first storage capacitor c1. The first electrode plate 121 includes a first electrode portion 1211 and a second electrode portion 1212. The first electrode portion 1211 is connected to at least one side of the second electrode portion 1212. The first conductive portion p11 includes a first portion p111 and a second portion p112. The second portion p112 is connected to the channel portion p10 along the length of the channel portion p10. The first portion p111 is connected to at least one side of the second portion p112 in a direction intersecting the length of the channel portion p10.

[0056] The first electrode portion 1211 and the first portion p111 at least partially overlap to form the first capacitor portion c11 of the first storage capacitor c1 , and the second electrode portion 1212 and the second portion p112 at least partially overlap to form the second capacitor portion c12 of the first storage capacitor c1 .

[0057] It can be understood that the array substrate 100 of the embodiment of the present application uses the special-shaped first conductive portion p11 and the first electrode 121 of the light-shielding layer 12 to form a first storage capacitor c1 with a higher charge capacity to compensate for the storage capacitor corresponding to the pixel electrode 13, thereby reducing the risk of image retention and uneven display; secondly, based on the first capacitor portion c11 being on at least one side of the second capacitor portion c12, the layout space can be reduced to meet the aperture ratio requirements of the array substrate 100.

[0058] Optionally, in some embodiments, the light shielding layer 12 is multiplexed as another first gate g1 of the first thin film transistor t1 , that is, the first thin film transistor t1 is a dual-gate transistor, and the light shielding layer 12 and the first gate g1 are connected to the same electrical signal.

[0059] Optionally, in some other embodiments, the light shielding layer 12 is configured to access a public signal.

[0060] Optionally, the array substrate 100 includes an opening area and a non-opening area NA. The opening area is a light-transmitting area that can transmit backlight light, and one opening area corresponds to one sub-pixel. The non-opening area NA is an area within the pixel covered by a light-shielding material (such as a black matrix layer).

[0061] Among them, the first storage capacitor c1 is arranged in the non-opening area NA, the second part p112 is reused as the plate of the second capacitor part c12, and the first capacitor part c11 is also arranged using the surplus lateral space, which can save space and further reduce the space requirement for the non-opening area NA to meet the requirements for the aperture ratio of the array substrate 100 and better achieve high resolution.

[0062] Secondly, the light shielding layer 12 is connected to the common signal, so that the light shielding layer 12 is non-electrically floating, thereby reducing the electrical influence of the light shielding layer 12 on the first active layer p1 and improving the stability of the first thin film transistor t1.

[0063] Optionally, the material of the first active layer p1 may include a metal oxide semiconductor, such as IGZO.

[0064] Please refer to Figure 2 Combine Figures 3 to 5 In some embodiments of the present application, the light-shielding layer 12 further includes a second electrode plate 122 connected to at least one side of the second electrode portion 1212, and the pixel electrode 13 includes a connecting portion 131 and a third electrode plate 133, the connecting portion 131 is electrically connected to the first conductive portion p11, and the third electrode plate 133 is connected to one side of the connecting portion 131 close to the first gate g1.

[0065] In the array substrate 100 viewed from a top perspective, the third electrode plate 133 and the second electrode plate 122 at least partially overlap to form a second storage capacitor c2.

[0066] It can be understood that the array substrate 100 forms a second storage capacitor c2 to further compensate for the storage capacitor corresponding to the pixel electrode 13, thereby reducing the risk of image retention and display unevenness; secondly, the third electrode 133 is close to the first gate g1, that is, the third electrode 133 is located in the non-opening area NA and within the range of the first thin film transistor t1, avoiding additional space occupation to maintain the aperture ratio.

[0067] In some embodiments of the present application, in the array substrate 100 viewed from a top perspective, the width direction of the channel portion p10 is the first direction F1 , and the length direction of the channel portion p10 is the second direction F2 .

[0068] Optionally, in some embodiments of the present application, in the array substrate 100 viewed from above, the connection portion 131 is located within the outline of the first conductive portion p11. In the first direction F1, part of the third electrode 133 is located within the outline of the first conductive portion p11.

[0069] It is understandable that the entire connecting portion 131 is within the contour area of ​​the first conductive portion p11 , and part of the third electrode 133 is also within the contour area, so as to reduce the space occupied by both and facilitate the realization of high resolution and aperture ratio requirements.

[0070] Optionally, in some embodiments of the present application, the distance from the third electrode plate 133 to the second electrode plate 122 is greater than the distance from the first electrode plate 121 to the first conductive portion p11 .

[0071] It can be understood that the dielectric layer thickness of the second storage capacitor c2 is larger, which makes the charge capacity of the second storage capacitor c2 smaller, and the dielectric layer thickness of the first storage capacitor c1 is smaller, which makes the charge capacity of the first storage capacitor c1 larger. Based on this, the combination of the first storage capacitor c1 and the second storage capacitor c2 can better adjust the total storage capacitance requirements.

[0072] Optionally, in some embodiments of the present application, the pixel electrode 13 further includes a fourth electrode plate 134 connected to the side of the third electrode plate 133 close to the first gate g1. In a top view of the array substrate 100, at least a portion of the fourth electrode plate 134 and the first gate g1 overlap to form a third storage capacitor c3.

[0073] It can be understood that the array substrate 100 forms a third storage capacitor c3 to further compensate for the storage capacitor corresponding to the pixel electrode 13, thereby reducing the risk of image sticking and display unevenness; secondly, at least part of the first gate g1 is reused as a capacitor plate without taking up additional space to maintain the aperture ratio.

[0074] Optionally, in some embodiments of the present application, the first gate g1 includes a control portion g11 and an extension portion g12 connected to at least one side of the control portion g11. The control portion g11 and the channel portion p10 are arranged to overlap. The fourth electrode 134 includes a third electrode portion 1341 and a fourth electrode portion 1342. The third electrode portion 1341 is connected to at least one side of the fourth electrode portion 1342. In a top view of the array substrate 100, the third electrode portion 1341 and the extension portion g12 at least partially overlap to form a third capacitor portion c31 of the third storage capacitor c3, and the fourth electrode portion 1342 and the control portion g11 at least partially overlap to form a fourth capacitor portion c32 of the third storage capacitor c3.

[0075] It is understood that the control portion g11 is configured to control the migration of carriers in the channel portion p10. Secondly, the control portion g11 and at least part of the extension portion g12 serve as the plate of the third storage capacitor c3 to increase the capacity of the third storage capacitor c3 and thereby increase the total storage capacitance.

[0076] Optionally, the fourth electrode portion 1342 fully covers the control portion g11 to increase the third storage capacitor c3.

[0077] Optionally, the first thin film transistor t1 further includes a first input electrode s1, the first active layer p1 includes a second conductive portion p12 connected to the channel portion p10, the first input electrode s1 is connected to the second conductive portion p12 through a first via k1, and the pixel electrode 13 is electrically connected to the first conductive portion p11 through a second via k2.

[0078] In the non-opening area NA of the array substrate 100 in a plan view, in the second direction F2 , the connecting portion 131 , the third electrode plate 133 , and the fourth electrode plate 134 are located between the first via hole k1 and the second via hole k2 .

[0079] It is understandable that, in the present application, the connection portion 131 , the third electrode plate 133 and the fourth electrode plate 134 of the pixel electrode 13 are disposed in the region of the first thin film transistor t1 to avoid reducing the aperture ratio of the array substrate 100 .

[0080] Optionally, in some embodiments of the present application, the light shielding portion 120 of the light shielding layer 12 extends toward the first via hole k1 to shield a portion of the second conductive portion p12. The fourth electrode 134 also extends toward the first via hole k1 and covers a portion of the light shielding portion 120 to form a fourth storage capacitor c4.

[0081] Secondly, it should be noted that in the second direction F2, the third electrode portion 1341 exceeds the first gate g1 to prevent the pixel electrode 13 from moving downward as a whole due to process deviation, so that the third electrode portion 1341 can still form a complete third storage capacitor c3 with the first gate g1.

[0082] In addition, in the second direction F2 , the distance that the third electrode portion 1341 extends beyond the first gate g1 is less than half the distance from the third electrode portion 1341 to the first via hole k1 , so as to prevent excessive impact of the data signal on the pixel electrode 13 .

[0083] Optionally, in some embodiments of the present application, the second electrode portion 1212, the second portion p112 and the connecting portion 131 extend along the second direction F2. The first electrode portion 1211, the first portion p111 and the second electrode plate 122 and the third electrode plate 133 extend along the first direction F1.

[0084] In the first direction F1, a first electrode portion 1211 is connected to one side of the second electrode portion 1212, and another first electrode portion 1211 is connected to the other side of the second electrode portion 1212; a first portion p111 is connected to one side of the second portion p112, and another first portion p111 is connected to the other side of the second portion p112. A first electrode portion 1211 corresponds to at least partially overlapping with a first portion p111 to form a first capacitor portion c11.

[0085] In the first direction F1, an extension portion g12 is connected to one side of the control portion g11, and another extension portion g12 is connected to the other side of the control portion g11; a third electrode portion 1341 is connected to one side of the fourth electrode portion 1342, and another third electrode portion 1341 is connected to the other side of the fourth electrode portion 1342. A third electrode portion 1341 corresponds to and at least partially overlaps with an extension portion g12 to form a third capacitor portion c31.

[0086] It can be understood that the two first capacitors c11 and the two third capacitors c31 are provided to increase the total storage capacitance.

[0087] Optionally, in some embodiments of the present application, the distance from the fourth electrode 134 to the first gate g1 is greater than the distance from the first electrode 121 to the first conductive portion p11 and less than the distance from the third electrode 133 to the second electrode 122 .

[0088] It is understandable that the thickness of the dielectric layer of the third storage capacitor c3 is between the thickness of the dielectric layer of the first storage capacitor c1 and the thickness of the dielectric layer of the second storage capacitor c2 to better adjust and match the total storage capacitance.

[0089] Optionally, in some embodiments of the present application, the array substrate 100 further includes a second thin film transistor t2 and a common electrode 14. The second thin film transistor t2 includes a second gate g2, a second input electrode s2, a second output electrode d2, and a second active layer p2. The material of the second active layer p2 is different from that of the first active layer p1.

[0090] The second active layer p2 is disposed on the substrate 11. The second gate electrode g2 and the light shielding layer 12 are disposed in the same layer on a side of the second active layer p2 away from the substrate 11. The second input electrode s2, the second output electrode d2, and the first input electrode s1 are disposed in the same layer on a side of the first gate electrode g1 away from the substrate 11. The common electrode 14 and the pixel electrode 13 are disposed in the same layer on a side of the first input electrode s1 away from the substrate 11.

[0091] In the thickness direction of the array substrate 100, a first insulating layer 151 is arranged between the second active layer p2 and the second gate g2, a second insulating layer 152 is arranged between the light-shielding layer 12 and the first active layer p1, a third insulating layer 153 is arranged between the first active layer p1 and the first gate g1, a fourth insulating layer 154 is arranged between the first gate g1 and the first input electrode s1, and a fifth insulating layer 155 is arranged between the pixel electrode 13 and the first input electrode s1.

[0092] The pixel electrode 13 is directly connected to the first conductive portion p11 .

[0093] It is understood that the second gate electrode g2 and the light shielding layer 12 are provided in the same layer and formed using the same mask to save masks. The second input electrode s2, the second output electrode d2, and the first input electrode s1 are provided in the same layer and formed using the same mask to save masks. The common electrode 14 and the pixel electrode 13 are provided in the same layer and formed using the same mask to save masks.

[0094] Secondly, the pixel electrode 13 is directly connected to the first conductive portion p11 , which can avoid the use of a metal transition portion, thereby achieving the effect of improving the aperture ratio of the array substrate 100 .

[0095] Optionally, in some embodiments of the present application, the fourth insulating layer 154 and the fifth insulating layer 155 are both inorganic insulating layers. The array substrate 100 further includes a common trace 141 disposed on the same layer as the first input electrode s1. The pixel electrode 13 is directly connected to the first conductive portion p11 via a second via k2. The common electrode 14 is connected to the common trace 141 via a third via k3.

[0096] The third via hole k3 penetrates the fifth insulating layer 155. The second via hole k2 penetrates the third insulating layer 153 to the fifth insulating layer 155. The second via hole k2 and the third via hole k3 are configured to be formed using one photomask.

[0097] It is understood that in conventional techniques, an organic layer is typically used as the fifth insulating layer 155. Since the organic layer is coated, its thickness is relatively large. The organic layer and the fourth insulating layer 154 are made of different materials, so two photomasks are required to pattern the fourth insulating layer 154 and the fifth insulating layer 155, respectively. Therefore, compared to conventional solutions, the present embodiment replaces the fifth insulating layer 155 with an inorganic layer. This ensures that the fifth insulating layer 155 and the fourth insulating layer 154 are made of the same material and have a smaller thickness. Therefore, the fifth insulating layer 155 and the fourth insulating layer 154 can be patterned with a single photomask, saving on photomasks.

[0098] Secondly, after the fifth insulating layer 155 is replaced by an inorganic layer, its thickness is thinner, which can improve the transmittance of light.

[0099] It should be explained that the method for preparing the array substrate 100 according to the embodiment of the present application includes the following steps:

[0100] Please refer to Figure 6 , B01 , a buffer layer 16 and a patterned second active layer p2 are formed on the substrate 11 .

[0101] Optionally, forming the patterned second active layer p2 includes the following steps: first forming a layer of a-Si on the buffer layer 16, forming polysilicon after laser annealing, and then forming a pattern by exposure and etching.

[0102] Optionally, the buffer layer 16 may be at least one of silicon oxide and silicon nitride, and may be a single-layer film layer or a multi-layer stacked structure.

[0103] Then go to step B02.

[0104] Please refer to Figure 7 , step B02, forming a first insulating layer 151 and a patterned first metal layer on the buffer layer 16, the first metal layer including a second gate g2 and a light shielding layer 12.

[0105] In step B02 , N+ and N− ion implantation is performed by using the second gate g2 as a shield to form a heavily doped region and a lightly doped region of the second active layer p2 .

[0106] Optionally, a photomask is used to form the patterned first metal layer.

[0107] Optionally, the first insulating layer 151 may be at least one of silicon oxide and silicon nitride, and may be a single-layer film layer or a multi-layer stacked structure.

[0108] Optionally, the first metal layer can be an inorganic metal material with a single-layer structure, such as Cr (chromium), Mo (molybdenum), Mn (manganese), etc., or it can be a multi-layer structure, including a molybdenum-aluminum-molybdenum (Mo / Al / Mo) metal layer structure, an aluminum-molybdenum (Al / Mo) metal layer structure, a molybdenum-copper (Mo / Cu) metal layer structure, or a molybdenum-titanium-copper (Mo / Ti / Cu) metal layer structure, including but not limited to the above materials.

[0109] Then go to step B03.

[0110] Please refer to Figure 8 In step B03 , a second insulating layer 152 is formed on the first insulating layer 151 , followed by activation and hydrogenation treatments, and then a patterned first active layer p1 is formed on the second insulating layer 152 .

[0111] Optionally, the second insulating layer 152 may be at least one of silicon oxide and silicon nitride, and may be a single-layer film layer or a multi-layer stacked structure.

[0112] The material of the first active layer p1 includes metal oxide, such as IGZO.

[0113] Then go to step B04.

[0114] Please refer to Figure 9 , step B04, forming a third insulating layer 153, a patterned second metal layer and a fourth insulating layer 154 on the second insulating layer 152.

[0115] Optionally, the third insulating layer 153 and the fourth insulating layer 154 may be at least one of silicon oxide and silicon nitride, and may be a single-layer film layer or a multi-layer stacked structure.

[0116] Optionally, a deep hole is opened to the first metal layer and the second active layer p2 by a first exposure and etching process, and a first via hole k1 is formed by a second exposure and etching process.

[0117] Optionally, the second metal layer includes the first gate electrode g1. The second metal layer can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, and cobalt, an alloy containing any of the foregoing metal elements, or an alloy combining any of the foregoing metal elements. Furthermore, the second metal layer can have a single-layer structure or a stacked structure of two or more layers.

[0118] Then go to step B05.

[0119] Please refer to Figure 10In step B05 , a patterned third metal layer is formed on the fourth insulating layer 154 using a photomask. The third metal layer includes a first input electrode s1 , a second input electrode s2 , a second output electrode d2 and a common trace 141 .

[0120] Alternatively, the third metal layer may be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, and cobalt, an alloy containing any of the foregoing metal elements, or an alloy combining any of the foregoing metal elements. Furthermore, the second metal layer may have a single-layer structure or a stacked structure of two or more layers.

[0121] Then go to step B06.

[0122] Please refer to Figure 11 , step B06, forming a fifth insulating layer 155 and a patterned transparent conductive layer on the fourth insulating layer 154.

[0123] Optionally, a photomask is used to pattern the fifth insulating layer 155 to form the second via hole k2 and the third via hole k3 . A photomask is used to form a patterned transparent conductive layer to form the pixel electrode 13 and the common electrode 14 .

[0124] The pixel electrode 13 is directly connected to the first conductive portion p11 through the second via hole k2 , and the common electrode 14 is connected to the common wiring 141 through the third via hole k3 .

[0125] The above is the method for preparing the array substrate 100 according to the embodiment of the present application.

[0126] Figure 12 Another structural diagram of the array substrate 100 according to an embodiment of the present application is shown. Figure 12 , parts different from those of the above-described embodiment will be described to avoid redundancy.

[0127] Reference Figure 12 The pixel electrode 13 is connected to the first conductive portion p11 through the first output electrode d1 of the first thin film transistor t1.

[0128] Compared to Figure 1 The array substrate 100 of the corresponding embodiment, Figure 12 The corresponding embodiment uses the first output electrode d1 as the transition portion, which reduces the difficulty of connecting the pixel electrode 13 to the first conductive portion p11.

[0129] Please refer to Figure 13 Accordingly, an embodiment of the present application further provides a display panel 1000 , which includes an opposing substrate 200 and the array substrate 100 as described in any one of the above embodiments.

[0130] Optionally, the display panel 1000 further includes a liquid crystal layer 300 disposed between the array substrate 100 and the opposite substrate 200 .

[0131] It should be noted that the structure of the array substrate 100 of the display panel 1000 of the embodiment of the present application is similar or identical to the structure of the array substrate 100 of any of the above embodiments. Figures 1 to 12 , so I will not repeat it here.

[0132] The array substrate 100 of the display panel 1000 of the present embodiment includes a light shielding layer 12 and a first active layer p1. The first electrode 121 of the light shielding layer 12 and the first conductive portion p11 of the first active layer p1 at least partially overlap to form a first storage capacitor c1. The first electrode 121 includes a first electrode portion 1211 and a second electrode portion 1212. The first conductive portion p11 includes a first portion p111 and a second portion p112. The first electrode portion 1211 and the first portion p111 at least partially overlap to form a first capacitor portion c11 of the first storage capacitor c1. The second electrode portion 1212 and the second portion p112 at least partially overlap to form a second capacitor portion c12 of the first storage capacitor c1.

[0133] It can be understood that the display panel 1000 of the embodiment of the present application uses an irregular first conductive portion p11 and the first electrode 121 of the light-shielding layer 12 to form a first storage capacitor c1 with a higher charge capacity to compensate for the storage capacitor corresponding to the pixel electrode 13, thereby reducing the risk of image afterimages and uneven display; secondly, based on the first capacitor portion c11 being on at least one side of the second capacitor portion c12, the layout space can be reduced to meet the aperture ratio requirements.

[0134] The above is a detailed introduction to an array substrate and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; a light shielding layer, disposed on the substrate, the light shielding layer comprising a light shielding portion and a first electrode plate, wherein the first electrode plate is connected to one side of the light shielding portion; a first thin film transistor, the first thin film transistor comprising a first gate and a first active layer, the first active layer being disposed on a side of the light shielding layer away from the substrate and being disposed in a different layer from the light shielding layer, the first gate being disposed on a side of the first active layer away from the substrate and being disposed in a different layer from the first active layer, the first active layer comprising a connected channel portion and a first conductive portion, and in a thickness direction of the array substrate, at least a portion of the first gate overlapping with the channel portion, and the channel portion overlapping with the light shielding portion; a pixel electrode, disposed on a side of the first gate away from the substrate and in a different layer from the first gate; the first conductive portion is configured to transmit a voltage signal to the pixel electrode; In the array substrate viewed from a top perspective, the first electrode plate and the first conductive portion at least partially overlap to form a first storage capacitor; the first electrode plate includes a first electrode portion and a second electrode portion, the first electrode portion is connected to at least one side of the second electrode portion, and the first conductive portion includes a first portion and a second portion, the second portion is connected to the channel portion in a lengthwise direction of the channel portion, and the first portion is connected to at least one side of the second portion in a direction intersecting the lengthwise direction of the channel portion; The first electrode portion and the first portion at least partially overlap to form a first capacitor portion of the first storage capacitor, and the second electrode portion and the second portion at least partially overlap to form a second capacitor portion of the first storage capacitor.

2. The array substrate according to claim 1, wherein: The light shielding layer further includes a second electrode plate connected to at least one side of the second electrode portion, the pixel electrode includes a connecting portion and a third electrode plate, the connecting portion is electrically connected to the first conductive portion, and the third electrode plate is connected to a side of the connecting portion close to the first gate; In the array substrate viewed from a top perspective, the third electrode plate and the second electrode plate at least partially overlap to form a second storage capacitor.

3. The array substrate according to claim 2, wherein: In the array substrate viewed from above, the width direction of the channel portion is a first direction, the connecting portion is located within the contour area of ​​the first conductive portion, and in the first direction, part of the third electrode plate is located within the contour area of ​​the first conductive portion.

4. The array substrate according to claim 2, wherein: The distance from the third electrode plate to the second electrode plate is greater than the distance from the first electrode plate to the first conductive portion.

5. The array substrate according to claim 2, wherein: The pixel electrode further includes a fourth electrode plate connected to a side of the third electrode plate close to the first gate. In the array substrate viewed from above, at least a portion of the fourth electrode plate and the first gate overlap to form a third storage capacitor.

6. The array substrate according to claim 5, wherein: The first gate includes a control part and an extension part connected to at least one side of the control part, and the control part and the channel part are arranged in an overlapping manner; the fourth plate includes a third electrode part and a fourth electrode part, and the third electrode part is connected to at least one side of the fourth electrode part; in the array substrate viewed from a top perspective, the third electrode part and the extension part at least partially overlap to form the third capacitor part of the third storage capacitor, and the fourth electrode part and the control part at least partially overlap to form the fourth capacitor part of the third storage capacitor.

7. The array substrate according to claim 6, wherein: In the array substrate in a top view, the width direction of the channel portion is a first direction, and the length direction of the channel portion is a second direction; the second electrode portion, the second portion, and the connecting portion extend along the second direction, and the first electrode portion, the first portion, the second electrode plate, and the third electrode plate extend along the first direction; In the first direction, one first electrode portion is connected to one side of the second electrode portion, another first electrode portion is connected to the other side of the second electrode portion, one first portion is connected to one side of the second portion, another first portion is connected to the other side of the second portion, and one first electrode portion at least partially overlaps with one first portion to form a first capacitor portion; In the first direction, one of the extension portions is connected to one side of the control portion, another of the extension portions is connected to the other side of the control portion, one of the third electrode portions is connected to one side of the fourth electrode portion, another of the third electrode portions is connected to the other side of the fourth electrode portion, and one of the third electrode portions corresponds to at least partially overlapping with one of the extension portions to form a third capacitor portion.

8. The array substrate according to claim 5, wherein: The distance from the fourth electrode plate to the first grid is greater than the distance from the first electrode plate to the first conductive portion and is smaller than the distance from the third electrode plate to the second electrode plate.

9. The array substrate according to claim 7, wherein: The first thin film transistor further includes a first input electrode, the first active layer includes a second conductive portion connected to the channel portion, the first input electrode is connected to the second conductive portion through a first via hole, and the pixel electrode is electrically connected to the first conductive portion through a second via hole; In the non-opening area of ​​the array substrate in a top view, in the second direction, the connecting portion, the third electrode plate, and the fourth electrode plate are located between the first via hole and the second via hole.

10. The array substrate according to any one of claims 1 to 9, characterized in that: The light shielding layer is multiplexed as another first gate of the first thin film transistor.

11. The array substrate according to claim 9, wherein: The array substrate further includes a second thin film transistor and a common electrode, the second thin film transistor includes a second gate, a second input electrode, a second output electrode and a second active layer, and the material of the second active layer is different from that of the first active layer; The second active layer is provided on the substrate, the second gate electrode and the light shielding layer are provided in the same layer on a side of the second active layer away from the substrate, the second input electrode, the second output electrode and the first input electrode are provided in the same layer on a side of the first gate electrode away from the substrate; the common electrode and the pixel electrode are provided in the same layer on a side of the first input electrode away from the substrate; In the thickness direction of the array substrate, a first insulating layer is provided between the second active layer and the second gate electrode, a second insulating layer is provided between the light shielding layer and the first active layer, a third insulating layer is provided between the first active layer and the first gate electrode, a fourth insulating layer is provided between the first gate electrode and the first input electrode, and a fifth insulating layer is provided between the pixel electrode and the first input electrode; The pixel electrode is directly connected to the first conductive portion; or, the pixel electrode is connected to the first conductive portion through the first input electrode of the first thin film transistor.

12. The array substrate according to claim 11, wherein: The fourth insulating layer and the fifth insulating layer are both inorganic insulating layers, the array substrate further includes a common wiring provided in the same layer as the first input electrode, the pixel electrode is directly connected to the first conductive portion through the second via hole, and the common electrode is connected to the common wiring through a third via hole; The third via hole penetrates the fifth insulating layer, the second via hole penetrates the third insulating layer to the fifth insulating layer, and the second via hole and the third via hole are configured to be formed by using one photomask.

13. A display panel, characterized in that: The invention comprises an opposing substrate and an array substrate according to any one of claims 1 to 12.

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