Array substrate, preparation method thereof and display panel

Abstract

The embodiment of the invention provides an array substrate, a preparation method thereof and a display panel. According to the array substrate, the first electrode layer is arranged between the source and drain electrode layer and the interlayer insulating layer, a semi-transparent mask plate can be adopted to etch the first electrode layer and the interlayer insulating layer, the process steps are reduced, the included angle between the side wall of the first via hole and the plane where the bottom face of the first via hole is located is larger than or equal to 65 degrees, and the yield of the array substrate is improved. The area of the first via hole can be reduced, and the pixel density is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] With the development of display devices, existing display devices have increasingly higher requirements for thin-film transistors. Low-temperature polysilicon thin-film transistors are widely used in liquid crystal display devices and OLED (Organic Light-Emitting Diode) display devices due to their advantages of fast switching speed and low power consumption. However, the existing preparation process of low-temperature polysilicon thin-film transistors is relatively complex and requires a large number of masks, resulting in high costs. Some display devices will remove some film layers to reduce the number of masks. However, during the preparation process, it was found that when etching the interlayer insulating layer, the slope of the via hole in the interlayer insulating layer is relatively gentle, resulting in a larger space occupied by the thin-film transistor, which in turn leads to a low pixel density.

[0003] Therefore, the existing display device has a technical problem that the slope of the via hole of the interlayer insulating layer is relatively gentle, resulting in a low pixel density of the display device. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate and a method for manufacturing the same, and a display panel, to alleviate the technical problem of low manufacturing efficiency resulting from a relatively complex manufacturing process in existing display devices.

[0005] In order to achieve the above-mentioned objective, according to a first aspect of the present application, an array substrate is provided, comprising:

[0006] substrate;

[0007] an active layer, disposed on one side of the substrate, the active layer comprising an active pattern;

[0008] an interlayer insulating layer, disposed on a side of the active layer away from the substrate, the interlayer insulating layer being provided with a plurality of first via holes;

[0009] a source-drain electrode layer, disposed on a side of the active layer away from the substrate, the source-drain electrode layer comprising a first electrode and a second electrode, the first electrode and the second electrode respectively passing through corresponding first via holes and contacting the active pattern;

[0010] A first electrode layer is provided between the source and drain electrode layer and the interlayer insulating layer;

[0011] The angle between the side wall of the first via hole and the plane where the bottom surface of the first via hole is located is greater than or equal to 65 degrees.

[0012] According to a second aspect of the present application, a method for preparing an array substrate is provided, the method comprising:

[0013] Providing a substrate, and sequentially forming a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer and a first electrode layer on the substrate;

[0014] forming a photoresist layer on the first electrode layer, exposing and developing the photoresist layer using a semi-transparent mask as a shield, etching the first electrode layer, the interlayer insulating layer, and the gate insulating layer based on the photoresist layer to form a first via hole, and then stripping the photoresist layer; wherein an angle between a sidewall of the first via hole and a plane containing a bottom surface of the first via hole is greater than or equal to 65 degrees;

[0015] A source-drain electrode layer, a passivation layer and a second electrode layer are sequentially formed on the first electrode layer.

[0016] According to a third aspect of the present application, a display panel is further provided, comprising the array substrate as described in any one of the above embodiments.

[0017] An embodiment of the present application provides an array substrate, a preparation method thereof, and a display panel; by arranging a first electrode layer between a source / drain layer and an interlayer insulating layer, the array substrate can use a semi-transparent mask to etch the first electrode layer and the interlayer insulating layer, thereby reducing the number of process steps and making the angle between the side wall of the first via hole and the plane where the bottom surface of the first via hole is located greater than or equal to 65 degrees, thereby reducing the area of ​​the first via hole and improving the pixel density.

[0018] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0020] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0021] Figure 1 A perspective view of a comparative display device.

[0022] Figure 2 for Figure 1 The comparison in FIG shows an AA cross-sectional view and a BB cross-sectional view of the device.

[0023] Figure 3 This is a first schematic diagram of an array substrate provided in an embodiment of the present application.

[0024] Figure 4 This is a first schematic diagram of an array substrate provided in an embodiment of the present application.

[0025] Figure 5 This is a first schematic diagram of an array substrate provided in an embodiment of the present application.

[0026] Figure 6 This is a first schematic diagram of an array substrate provided in an embodiment of the present application.

[0027] Figure 7 A flow chart of a method for preparing an array substrate provided in an embodiment of the present application.

[0028] Figure 8 A schematic structural diagram of an array substrate corresponding to some steps of a method for preparing an array substrate provided in an embodiment of the present application.

[0029] Figure 9 This is a structural schematic diagram of an array substrate corresponding to other steps of a method for preparing an array substrate provided in an embodiment of the present application.

[0030] Figure 10 The present invention provides a flowchart of the specific steps of a method for preparing an array substrate provided in an embodiment of the present application.

[0031] Figure 11 for Figure 10 A structural schematic diagram of an array substrate corresponding to some specific steps in a step in a method for preparing an array substrate.

[0032] Figure 12 for Figure 10 A structural schematic diagram of an array substrate corresponding to other specific steps in a step in a method for preparing an array substrate.

[0033] Figure 13 This is a structural schematic diagram of an array substrate corresponding to each specific step of another step in a method for preparing an array substrate provided in an embodiment of the present application.

[0034] Figure 14 This is a schematic structural diagram of a comparative display device corresponding to some steps in a method for preparing a comparative display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0036] In order to illustrate the principles of the technical problems in the embodiments of the present application, some comparative display devices are provided. It can be understood that these comparative display devices cannot be regarded as the prior art in the embodiments of the present application. Figure 1 is a perspective view of a comparative display device, Figure 2 for Figure 1 The comparison in FIG shows the AA cross-sectional view and the BB cross-sectional view of the device. Figure 2 (a) is Figure 1 The AA cross-sectional view of the comparative display device is shown in FIG. Figure 2 (b) in Figure 1 The BB cross-section of the comparative display device is shown in FIG. Figure 1 、 Figure 2 As shown, the comparative display device includes a substrate 11, a light-shielding film 12, a first insulating film 13, an active film 14, a second insulating film 15, a gate film 16, a third insulating film 17, a source-drain film 18, a planarization film 191, a bottom electrode film 192, a passivation film 193 and a top electrode film 194, and the active film 14 includes a channel region 143, a lightly doped region 142 and a heavily doped region 141.

[0037] from Figure 2 As can be seen in the figure, nine masks are required to form the comparative display device: one mask for forming the light shielding film 12, one mask for forming the first insulating film 13 and the active film 14, one mask for forming the gate film 16, one mask for forming the via holes in the third insulating film 17, one mask for forming the source / drain film 18, one mask for forming the via holes in the planarization film 191, one mask for forming the bottom electrode film 192, one mask for forming the via holes in the passivation film 193, and one mask for forming the top electrode film 194. As can be seen, the comparative display device formation process requires a large number of masks and many process steps, resulting in a more complex process, higher costs, and lower production efficiency. Some comparative display devices remove some film layers to reduce the number of masks. However, during the production process, it was found that when etching the interlayer insulating layer, the via holes in the interlayer insulating layer have a relatively gentle slope, resulting in a larger space occupied by the thin-film transistors and, in turn, lower pixel density. Therefore, the existing display device has a technical problem that the slope of the via hole of the interlayer insulating layer is relatively gentle, resulting in a low pixel density of the display device.

[0038] In response to the above technical problems, embodiments of the present application provide an array substrate and a method for manufacturing the same, and a display panel to alleviate the above technical problems.

[0039] Figure 3 This is a first schematic diagram of an array substrate provided in an embodiment of the present application. Figure 4 This is a first schematic diagram of an array substrate provided in an embodiment of the present application. Figure 5 This is a first schematic diagram of an array substrate provided in an embodiment of the present application. Figure 6 This is a first schematic diagram of an array substrate provided in an embodiment of the present application. Figure 7 A flow chart of a method for preparing an array substrate provided in an embodiment of the present application. Figure 8 A schematic structural diagram of an array substrate corresponding to some steps of a method for preparing an array substrate provided in an embodiment of the present application. Figure 9 This is a structural schematic diagram of an array substrate corresponding to other steps of a method for preparing an array substrate provided in an embodiment of the present application. Figure 10 The present invention provides a flowchart of the specific steps of a method for preparing an array substrate provided in an embodiment of the present application. Figure 11 for Figure 10 A structural schematic diagram of an array substrate corresponding to some specific steps in a step in a method for preparing an array substrate. Figure 12 for Figure 10 A structural schematic diagram of an array substrate corresponding to other specific steps in a step in a method for preparing an array substrate. Figure 13 This is a structural schematic diagram of an array substrate corresponding to each specific step of another step in a method for preparing an array substrate provided in an embodiment of the present application.

[0040] like Figures 3 to 6 As shown, an embodiment of the present application provides an array substrate, which includes a substrate 21, an active layer 23, an interlayer insulating layer 26, a source-drain layer 27 and a first electrode layer 28. The active layer 23 is arranged on one side of the substrate 21, and the active layer 23 includes an active pattern 23a; the interlayer insulating layer 26 is arranged on the side of the active layer 23 away from the substrate 21, and the interlayer insulating layer 26 is provided with a plurality of first vias 261; the source-drain layer 27 is arranged on the side of the active layer 23 away from the substrate 21, and the source-drain layer 27 includes a first electrode 271 and a second electrode 272, and the first electrode 271 and the second electrode 272 respectively pass through the corresponding first vias 261 and contact the active pattern 23a; the first electrode layer 28 is arranged between the source-drain layer 27 and the interlayer insulating layer 26; wherein the angle a between the side wall of the first via 261 and the plane where the bottom surface of the first via 261 is located is greater than or equal to 65 degrees.

[0041] An embodiment of the present application provides an array substrate, which, by setting the first electrode layer 28 between the source and drain layer 27 and the interlayer insulating layer 26, can use a semi-transparent mask to etch the first electrode layer 28 and the interlayer insulating layer 26, thereby reducing the process steps and making the angle a between the side wall of the first via 261 and the plane where the bottom surface of the first via 261 is located greater than or equal to 65 degrees, thereby reducing the area of ​​the first via 261 and improving the pixel density.

[0042] Specifically, it can be understood that if the angle between the side wall of the first via and the plane where the bottom surface of the first via 261 is located is greater than or equal to 65 degrees, the side wall of the interlayer insulating layer corresponding to the first via is steeper, so that the space occupied by the first via is smaller, and the area of ​​the first electrode and the second electrode can be reduced accordingly, so that the space occupied by the thin film transistor is relatively small, thereby improving the pixel density.

[0043] In some embodiments, as Figure 3 、 Figure 4 As shown, the first electrode layer 28 includes a mask electrode 281, and the mask electrode 281 is disposed between the first electrode 271 and the interlayer insulating layer 26, or / and the mask electrode 281 is disposed between the second electrode 272 and the interlayer insulating layer 26. By having the first electrode layer 28 include the mask electrode 281, the mask electrode 281 is disposed corresponding to at least one of the first electrode and the second electrode, and the second via 281a is connected to the first via 261, the mask electrode can serve as a hard mask when the interlayer insulating layer 26 is etched, making the sidewall of the interlayer insulating layer corresponding to the first via steeper, reducing the area of ​​the first via, and improving the pixel density.

[0044] Specifically, compared with the comparative display device, when multiple masks are used to etch the third insulating film 17 and the bottom electrode film 192 respectively, the angle of the via hole of the third insulating film 17 can be controlled to be larger, but when a single mask is used to etch the interlayer insulating layer 26 and the first electrode layer 28, the angle of the via hole of the third insulating film 17 can be controlled to be larger. Figure 14 As shown, in order to form the pattern of the first electrode layer 28 in one step, the first electrode layer 28 is directly etched, as shown in FIG. Figure 14 As shown in (a), the pattern of the first electrode layer 28 is retracted relative to the photoresist layer 32, and there is no mask electrode in the first electrode layer 28. Figure 14As shown in (b), when the mask electrode 281 is not provided, the photoresist will be etched during the etching of the interlayer insulating layer 26, causing the photoresist layer 32 to shrink inward, resulting in a gentler angle of the sidewall of the interlayer insulating layer 26 corresponding to the via hole, and the space required for the via hole is larger, which in turn leads to a lower pixel density. In the embodiment of the present application, by making the first electrode layer 28 include the mask electrode 281, when the interlayer insulating layer 26 is etched to form the first via hole 261, since the dry etching method cannot etch the first electrode layer 28, even if the photoresist retreats, the mask electrode 281 can be used as a hard mask to control the area of ​​the first via hole 261, thereby reducing the area of ​​the first via hole and improving the pixel density.

[0045] Specifically, the mask electrode can be set between the first electrode and the interlayer insulating layer, or between the second electrode and the interlayer insulating layer; or between the first electrode and the interlayer insulating layer, and between the second electrode and the interlayer insulating layer.

[0046] In some embodiments, as Figure 4 As shown, the ratio of the area of ​​the mask electrode 281 to the sum of the areas of the first electrode 271 and the second electrode 272 is greater than 0 and less than 100%. By making the ratio of the area of ​​the mask electrode 281 to the sum of the areas of the first electrode 271 and the second electrode 272 greater than 0 and less than 100%, the mask electrode does not occupy additional space when it is formed, thereby reducing the optical impact of the mask electrode on the array substrate, and reducing the space occupied by the mask electrode and the interference with the potential of other conductive layers.

[0047] Specifically, such as Figure 4 As shown, the projection of the mask electrode 281 on the substrate 21 is located within the projection range of the first electrode 271 on the substrate 21 and the projection range of the second electrode 272 on the substrate 21; so that when the mask electrode is formed, the mask electrode does not occupy additional space, reducing the optical impact of the mask electrode on the array substrate, and reducing the space occupied by the mask electrode and the interference with the potential of other conductive layers.

[0048] Specifically, the area of ​​the mask electrode 281 can be 1% to 99% of the sum of the areas of the first electrode 271 and the second electrode 272 . For example, the area of ​​the mask electrode 281 can be 50% of the sum of the areas of the first electrode 271 and the second electrode 272 .

[0049] Specifically, when the projection of the mask electrode 281 on the substrate 21 is located within the projection range of the first electrode 271 on the substrate 21 and the projection range of the second electrode 272 on the substrate 21, when the photoresist is removed, a portion of the first electrode 271 and the second electrode 272 in the first electrode layer can be retained, and the area of ​​the retained portion can be smaller than the sum of the areas of the first electrode 271 and the second electrode 272, which facilitates etching the first electrode layer to form the mask electrode, and the mask electrode can serve as an anti-reflection layer to reduce the photogenerated leakage current generated by the reflection of light through the source and drain layers to the active layer, thereby improving the performance of the array.

[0050] In some embodiments, as Figure 3 As shown, the mask electrode 281 includes a second via hole 281a, which is connected to the first via hole 261, and an edge of the mask electrode 281 is aligned with an edge of the first electrode 271, and another edge of the mask electrode 281 is aligned with an edge of the second electrode 272; so that when the mask electrode is formed, the mask electrode does not occupy additional space, reducing the optical influence of the mask electrode on the array substrate, and reducing the space occupied by the mask electrode and the interference with the potential of other conductive layers.

[0051] Specifically, when the edge of one mask electrode 281 is aligned with the edge of the first electrode 271 and the edge of the other mask electrode 281 is aligned with the edge of the second electrode 272, when the photoresist is removed, the portion of the first electrode layer corresponding to the first electrode 271 and the second electrode 272 can be retained, which facilitates etching the first electrode layer to form a mask electrode, and the mask electrode can serve as an anti-reflection layer to reduce the photogenerated leakage current generated by the reflection of light through the source and drain layers to the active layer, thereby improving the performance of the array.

[0052] Specifically, it can be understood that since the angles of the structures formed after etching of different materials are different, and when etching each film layer, there may be certain deviations due to process limitations, resulting in certain differences between the edge of the mask electrode 281 and the edge of the first electrode and the edge of the second electrode. At this time, it is still considered that the edge of the mask electrode 281 is aligned with the edge of the first electrode 271, and the edge of the other mask electrode 281 is aligned with the edge of the second electrode 272.

[0053] Specifically, such as Figures 3 to 5As shown, taking the corresponding setting of the first electrode layer 28 and the first electrode as an example, it can be seen that the pixel electrode 282 is connected to the mask electrode 281. It can be understood that in the embodiment of the present application, the portion of the first electrode layer 28 corresponding to the first electrode and / or the second electrode is regarded as the mask electrode 281, and the portion of the first electrode layer 28 connected to the mask electrode under the first electrode or the second electrode is regarded as the pixel electrode 282. However, it can be understood that the pixel electrode 282 is connected to the mask electrode 281, and the two transmit the same signal, and are actually two parts of a structure.

[0054] In some embodiments, as Figure 4 As shown, the mask electrode 281 includes a second via hole 281a, which is connected to the first via hole 261, and there is a gap between one side edge of the mask electrode 281 and the edge of the first electrode 271, the other side edge of the mask electrode 281 is aligned with the edge of the second electrode 272, and there is a gap between the edge of the other mask electrode 281 and the edge of the second electrode 272; the mask electrode 281 is retracted within the projection range of the first electrode and the second electrode, so that when the mask electrode is formed, the mask electrode does not occupy additional space, reducing the optical influence of the mask electrode on the array substrate, and reducing the space occupied by the mask electrode and the interference with the potential of other conductive layers.

[0055] In some embodiments, as Figure 5 As shown, the mask electrode 281 contacts a portion of the first electrode 271, another portion of the first electrode 271 directly contacts the interlayer insulating layer 26, and the second electrode 272 directly contacts the interlayer insulating layer 26. By making the mask electrode contact a portion of the first electrode 271, the pixel electrode 282 can be normally conductively connected to the first electrode 271 through the mask electrode, achieving normal function of the array substrate. By making the other portion of the first electrode 271 directly contact the interlayer insulating layer 26 and the second electrode 272 directly contact the interlayer insulating layer 26, the electrical properties of the array substrate can be improved and the thickness of the array substrate can be reduced.

[0056] In some embodiments, as Figures 3 to 5 As shown, the first electrode layer 28 further includes a pixel electrode 282, and the pixel electrode 282 is connected to a portion of the mask electrode 281. By having the first electrode layer 28 include the pixel electrode 282 and the pixel electrode 282 connected to a portion of the mask electrode 281, the connection effect between the pixel electrode 282 and the first electrode or the second electrode is improved, and the pixel electrode 282 can be formed using the same mask as the interlayer insulating layer, thereby reducing the number of masks, reducing process steps, and improving the production efficiency of the display panel.

[0057] In some embodiments, as Figures 3 to 5 As shown, there is a distance between the edge of the mask electrode 281 and the edge of the first via hole 261 .

[0058] Specifically, the above embodiment is described by taking the example of the existence of a gap between the edge of the mask electrode 281 and the edge of the first via 261, but the embodiments of the present application are not limited to this. During the etching process, there may be a situation where the edge of the mask electrode is not etched or the etching degree is low. In this case, the edge of the mask electrode 281 can be aligned with the edge of the first via 261.

[0059] Specifically, such as Figures 3 to 5 As shown, the array substrate 2 further includes a second electrode layer 31, which is arranged on a side of the source and drain layer 27 away from the first electrode layer 28. The second electrode layer 31 includes a common electrode, thereby forming a coupling capacitor between the common electrode and the source and drain layer.

[0060] In some embodiments, as Figure 6 As shown, the first electrode layer 28 includes a common electrode 311, which is insulated from the first electrode 271 and the second electrode 272. The array substrate 2 also includes a second electrode layer 31, which is disposed on a side of the source / drain layer 27 away from the first electrode layer 28. The second electrode layer 31 includes a pixel electrode 282. The first electrode 271 and the second electrode 272 are in direct contact with the interlayer insulating layer 26. By ensuring that the first electrode 271 and the second electrode 272 are in direct contact with the interlayer insulating layer 26, the mask electrode used in the array substrate formation process can be eliminated, leaving only the common electrode. This improves the electrical properties of the array substrate and reduces the thickness of the array substrate.

[0061] Specifically, the above embodiment is described by taking the example of the first electrode 271 and the second electrode 272 directly contacting the interlayer insulating layer 26, but the embodiment of the present application is not limited to this. The first electrode layer may also include a mask electrode, and the setting method of the mask electrode can refer to the above embodiment.

[0062] In some embodiments, the angle a between the side wall of the first via 261 and the plane where the bottom surface of the first via 261 is located is in the range of 75 degrees to 80 degrees, so that the angle a between the side wall of the first via 261 and the plane where the bottom surface of the first via 261 is located is larger, which can reduce the opening area of ​​the first via 261 and improve the pixel density.

[0063] Specifically, the opening area of ​​the first via hole 261 may be the area of ​​the opening on the upper surface of the interlayer insulating layer. The embodiment of the present application can reduce the area of ​​the opening and improve the pixel density by increasing the angle a between the side wall of the first via hole 261 and the plane where the bottom surface of the first via hole 261 is located.

[0064] Specifically, the angle a between the side wall of the first via 261 and the plane in which the bottom surface of the first via 261 is located can be 65 degrees, 66 degrees, 67 degrees, 68 degrees, 69 degrees, 70 degrees, 71 degrees, 72 degrees, 73 degrees, 74 degrees, 75 degrees, 76 degrees, 77 degrees, 78 degrees, 79 degrees, 80 degrees, 81 degrees, 82 degrees, 83 degrees, 84 degrees or 85 degrees.

[0065] Specifically, it can be understood that in the embodiment of the present application, the angle between the side wall of the first via 261 and the plane where the bottom surface of the first via 261 is located is described as an acute angle. It can be understood that when describing it as an obtuse angle, the angle can be determined accordingly based on the angle of the acute angle.

[0066] In some embodiments, as Figures 3 to 6 As shown, the array substrate 2 further includes a buffer layer 22, a gate insulating layer 24, and a gate layer 25. The buffer layer 22 is disposed between the substrate 21 and the active layer 23, and the buffer layer 22 is in contact with the substrate 21. The gate insulating layer 24 is disposed on a side of the active layer 23 away from the buffer layer 22. The gate layer 25 is disposed on a side of the gate insulating layer 24 away from the active layer 23. The gate insulating layer 24 includes a third via 241, which is connected to the first via 261. By connecting the third via 241 to the first via 261, the first electrode and the second electrode can pass through the first and third vias to connect to the active pattern 23a, thereby achieving normal display of the array substrate.

[0067] Specifically, the first via hole and the third via hole can be regarded as two parts of one via hole.

[0068] Specifically, the angle b between the side wall of the third via 241 and the plane where the bottom of the third via 241 is located is the same as the angle between the side wall of the first via and the plane where the bottom of the first via is located. However, when the materials of the interlayer insulating layer and the gate insulating layer are different, there may be a certain difference between the angle between the side wall of the first via and the plane where the bottom of the first via is located and the angle between the side wall of the third via and the plane where the bottom of the third via is located.

[0069] Specifically, the angle b between the side wall of the third via 241 and the plane where the bottom surface of the third via 241 is located can refer to the angle between the side wall of the first via and the plane where the bottom surface of the first via is located, for example, the angle between the side wall of the third via and the plane where the bottom surface of the third via is located is greater than or equal to 65 degrees; specifically, the angle between the side wall of the third via and the plane where the bottom surface of the third via is located can be in the range of 75 degrees to 80 degrees.

[0070] Specifically, such as Figures 3 to 6 As shown, the array substrate 2 includes a substrate 21, a buffer layer 22, an active layer 23, a gate insulating layer 24, a gate layer 25, an interlayer insulating layer 26, a first electrode layer 28, a source and drain layer 27, a passivation layer 29 and a second electrode layer 31 arranged in sequence.

[0071] Specifically, the material of the active layer 23 includes polysilicon.

[0072] Specifically, the material of the gate insulating layer includes a stack of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0073] Specifically, the material of the interlayer insulating layer includes a stack of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0074] Specifically, the material of the first electrode layer includes indium tin oxide. The material of the second electrode layer includes indium tin oxide.

[0075] Specifically, the active layer 23 may include a channel portion 231 , a lightly doped portion 232 and a heavily doped portion 233 , wherein the ion doping concentration of the heavily doped portion 233 is greater than that of the lightly doped portion 232 , and the ion doping concentration of the lightly doped portion 232 is greater than that of the channel portion 231 .

[0076] Specifically, the first electrode is a source electrode and the second electrode is a drain electrode; or the first electrode is a drain electrode and the second electrode is a source electrode.

[0077] Specifically, it can be understood that due to process deviations, the angles between different side walls of the first via and the plane where the bottom surface of the first via 241 is located may be different. For example, the angle between the side wall on the left side of the first via and the plane where the bottom surface of the first via 241 is located may be greater than the angle between the side wall on the right side of the first via and the plane where the bottom surface of the first via 241 is located; similarly, the angles between the side walls of different third vias and the plane where the bottom surface of the third via is located may be different.

[0078] At the same time, an embodiment of the present application provides a method for preparing an array substrate, which prepares the array substrate as described in any of the above embodiments.

[0079] In some embodiments, as Figure 7As shown, the method for preparing the array substrate includes:

[0080] S1, providing a substrate, and sequentially forming a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer and a first electrode layer on the substrate;

[0081] S2, forming a photoresist layer on the first electrode layer, exposing and developing the photoresist layer using a semi-transparent mask as a shield, etching the first electrode layer, the interlayer insulating layer, and the gate insulating layer based on the photoresist layer to form a first via hole, and peeling off the photoresist layer; the angle between the sidewall of the first via hole and the plane where the bottom surface of the first via hole lies is greater than or equal to 65 degrees;

[0082] S3, forming a source-drain electrode layer, a passivation layer and a second electrode layer in sequence on the first electrode layer.

[0083] An embodiment of the present application provides a method for preparing an array substrate, which comprises forming a photoresist layer on a first electrode layer, exposing and developing the photoresist layer using a semi-transparent mask as a shield, and then etching the first electrode layer, the interlayer insulating layer, and the gate insulating layer based on the photoresist layer to form a first via hole, so that the first electrode layer and the interlayer insulating layer can be etched using a mask, and the first electrode layer can be used as a hard mask to etch the interlayer insulating layer, so that the angle between the side wall of the first via hole and the plane where the bottom surface of the first via hole is located is greater than or equal to 65 degrees, which can reduce the area of ​​the first via hole and improve the pixel density.

[0084] Specifically, a method for preparing an array substrate includes:

[0085] Provide a substrate, and sequentially form a buffer layer and an active layer on the substrate, and pattern the active layer; the structure of the array substrate corresponding to this step is as follows Figure 8 As shown in (a);

[0086] A gate insulating layer and a gate layer are formed on the active layer, and the gate layer is patterned; the structure of the array substrate corresponding to this step is as follows: Figure 8 As shown in (b);

[0087] An interlayer insulating layer and a first electrode layer are formed on the gate layer, and a photoresist layer is formed on the first electrode layer. The photoresist layer is exposed and developed using a semi-transparent mask as a shield, and the first electrode layer, the interlayer insulating layer and the gate insulating layer are etched based on the photoresist layer. The first electrode layer is patterned and a first via hole is formed, and the photoresist layer is peeled off. The structure of the array substrate corresponding to this step is as follows: Figure 8 As shown in (c);

[0088] A source-drain electrode layer is formed on the first electrode layer, and the source-drain electrode layer is patterned; the structure of the array substrate corresponding to this step is as follows: Figure 9As shown in (a);

[0089] A passivation layer is formed on the source and drain electrode layer, and the passivation layer is etched to form a via hole; the structure of the array substrate corresponding to this step is as follows: Figure 9 As shown in (b);

[0090] A second electrode layer is formed on the passivation layer; the structure of the array substrate corresponding to this step is as follows Figure 3 shown.

[0091] Specifically, it can be seen that in the preparation process of the array substrate, only a mask plate is needed to form the buffer layer and the active layer, a mask plate is needed to form the gate insulation layer and the gate layer, a mask plate is needed to form the definition vias of the interlayer insulation layer and the first electrode layer, a mask plate is needed to form the source and drain layer, a mask plate is needed to form the vias of the passivation layer, and a mask plate is needed to form the second electrode layer. Compared with the comparative display device, the number of mask plates is reduced, the process steps are reduced, and the preparation efficiency of the array substrate is improved.

[0092] In some embodiments, as Figure 10 As shown, the steps of forming a photoresist layer on the first electrode layer, exposing and developing the photoresist layer using a semi-transparent mask as a shield, etching the first electrode layer, the interlayer insulating layer and the gate insulating layer based on the photoresist layer to form a first via hole, and stripping the photoresist layer include:

[0093] S21, forming a photoresist layer 32 on the first electrode layer, and using a semi-transparent mask as a shield to expose and develop the photoresist layer 32 to form a first photoresist pattern 321 and an opening 321a; the structure of the array substrate corresponding to this step is as follows Figure 11 As shown in (a);

[0094] S22, etching the first electrode layer with the first photoresist pattern as a shield to form a first electrode pattern corresponding to the first photoresist pattern and a second via hole corresponding to the opening; the structure of the array substrate corresponding to this step is as follows: Figure 11 As shown in (b);

[0095] S23, etching the interlayer insulating layer and the gate insulating layer using the first photoresist pattern and the first electrode pattern as shielding to form a first via hole corresponding to the second via hole; the structure of the array substrate corresponding to this step is as follows: Figure 11 As shown in (c);

[0096] S24, ashing the first photoresist pattern to obtain a second photoresist pattern 322; the structure of the array substrate corresponding to this step is as follows Figure 12 As shown in (a);

[0097] S25, etching the first electrode pattern based on the second photoresist pattern;

[0098] S26, peeling off the second photoresist pattern; the structure of the array substrate corresponding to this step is as follows Figure 12 (b) and Figure 12 As shown in (c) in .

[0099] Specifically, when etching the first electrode layer, wet etching can be used, and when etching the interlayer insulating layer and the gate insulating layer, dry etching can be used. However, dry etching cannot etch the first electrode layer or the etching effect on the first electrode layer is poor, so that the first electrode layer can be used as a hard mask, so that the angle between the side wall of the first via and the plane where the bottom of the first via is located is larger, which can reduce the area of ​​the first via and increase the pixel density.

[0100] Specifically, it is understandable that, since the first electrode layer is etched twice, the areas of the second via holes during the two etchings will be different.

[0101] Specifically, the step of forming a source-drain electrode layer on the first electrode layer includes:

[0102] A metal layer is deposited on the first electrode layer; the structure of the array substrate corresponding to this step is as follows Figure 13 As shown in (a);

[0103] The metal layer is patterned to form a source and drain electrode layer; the structure of the array substrate corresponding to this step is as follows Figure 13 As shown in (b) in .

[0104] Specifically, for other structures of the array substrate, the preparation method of the array substrate can refer to the above embodiments.

[0105] Specifically, the above embodiments provide a detailed description of the array substrate from the perspective of the film layer design of the array substrate, the structure of each film layer, the material design, etc. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined, and the projection of the mask electrode on the substrate coincides with the projection of the first electrode on the substrate and the projection of the second electrode on the substrate. The first electrode layer also includes a pixel electrode, and the pixel electrode is connected to part of the mask electrode.

[0106] At the same time, an embodiment of the present application provides a display panel, which includes the array substrate as described in any of the above embodiments.

[0107] Specifically, the display panel may include an array substrate, a color filter substrate, and a liquid crystal layer; however, the embodiments of the present application are not limited thereto, and the display panel may be other display panels.

[0108] Specifically, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0109] Specifically, the display device further includes a backlight module.

[0110] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0111] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0112] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0113] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; an active layer, disposed on one side of the substrate, the active layer comprising an active pattern; an interlayer insulating layer, disposed on a side of the active layer away from the substrate, the interlayer insulating layer being provided with a plurality of first via holes; a source-drain electrode layer, disposed on a side of the active layer away from the substrate, the source-drain electrode layer comprising a first electrode and a second electrode, the first electrode and the second electrode respectively passing through corresponding first via holes and contacting the active pattern; A first electrode layer is provided between the source and drain electrode layer and the interlayer insulating layer; The angle between the side wall of the first via hole and the plane where the bottom surface of the first via hole is located is greater than or equal to 65 degrees.

2. The array substrate according to claim 1, wherein: The first electrode layer includes a mask electrode, and the mask electrode is disposed between the first electrode and the interlayer insulating layer, or / and the mask electrode is disposed between the second electrode and the interlayer insulating layer.

3. The array substrate according to claim 2, wherein: A ratio of an area of ​​the mask electrode to a sum of an area of ​​the first electrode and an area of ​​the second electrode is greater than 0 and less than 100%.

4. The array substrate according to claim 3, wherein: The projection of the mask electrode on the substrate is located within the projection range of the first electrode on the substrate and the projection range of the second electrode on the substrate.

5. The array substrate according to claim 4, wherein: The mask electrode is provided with a second via hole, the second via hole is connected to the first via hole, and an edge of one mask electrode is aligned with an edge of the first electrode, and an edge of another mask electrode is aligned with an edge of the second electrode.

6. The array substrate according to claim 4, wherein: The mask electrode is provided with a second via hole, the second via hole is connected to the first via hole, and there is a gap between one side edge of the mask electrode and the edge of the first electrode, the other side edge of the mask electrode is aligned with the edge of the second electrode, and there is a gap between the edge of the other mask electrode and the edge of the second electrode.

7. The array substrate according to claim 4, wherein: The mask electrode contacts a portion of the first electrode, another portion of the first electrode directly contacts the interlayer insulating layer, and the second electrode directly contacts the interlayer insulating layer.

8. The array substrate according to claim 2, wherein: There is a distance between the edge of the mask electrode and the edge of the first via hole.

9. The array substrate according to claim 2, wherein: The first electrode layer further includes a pixel electrode, and the pixel electrode is connected to a portion of the mask electrode.

10. The array substrate according to claim 1, wherein: The first electrode layer includes a common electrode, and the common electrode is insulated from the first electrode and the second electrode; The array substrate further includes a second electrode layer, which is arranged on a side of the source and drain electrode layer away from the first electrode layer, and includes pixel electrodes; The first electrode and the second electrode are in direct contact with the interlayer insulating layer.

11. The array substrate according to any one of claims 1 to 10, characterized in that: An included angle between a side wall of the first via hole and a plane where a bottom surface of the first via hole is located ranges from 75 degrees to 80 degrees.

12. The array substrate according to any one of claims 1 to 10, characterized in that: The array substrate further includes: a buffer layer, disposed between the substrate and the active layer, and the buffer layer is in contact with the substrate; a gate insulating layer, disposed on a side of the active layer away from the buffer layer; a gate layer, disposed on a side of the gate insulating layer away from the active layer; The gate insulating layer includes a third via hole, and the third via hole is connected to the first via hole.

13. A method for preparing an array substrate, characterized in that: include: Providing a substrate, and sequentially forming a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer and a first electrode layer on the substrate; forming a photoresist layer on the first electrode layer, exposing and developing the photoresist layer using a semi-transparent mask as a shield, etching the first electrode layer, the interlayer insulating layer, and the gate insulating layer based on the photoresist layer to form a first via hole, and then stripping the photoresist layer; wherein an angle between a sidewall of the first via hole and a plane containing a bottom surface of the first via hole is greater than or equal to 65 degrees; A source-drain electrode layer, a passivation layer and a second electrode layer are sequentially formed on the first electrode layer.

14. The method for preparing an array substrate according to claim 13, wherein: The steps of forming a photoresist layer on the first electrode layer, exposing and developing the photoresist layer using a semi-transparent mask as a shield, etching the first electrode layer, the interlayer insulating layer and the gate insulating layer based on the photoresist layer to form a first via hole, and stripping the photoresist layer include: forming a photoresist layer on the first electrode layer, and exposing and developing the photoresist layer using a semi-transparent mask as a shield to form a first photoresist pattern and an opening; Etching the first electrode layer using the first photoresist pattern as a shield to form a first electrode pattern corresponding to the first photoresist pattern and a second via hole corresponding to the opening; Etching the interlayer insulating layer and the gate insulating layer using the first photoresist pattern and the first electrode pattern as shielding to form a first via hole corresponding to the second via hole; ashing the first photoresist pattern to obtain a second photoresist pattern; etching the first electrode pattern based on the second photoresist pattern; The second photoresist pattern is peeled off.

15. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 12.

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