High-voltage light-emitting chip and preparation method thereof

Abstract

The invention discloses a high-voltage light-emitting chip and a preparation method thereof. The high-voltage light-emitting chip comprises at least two light-emitting units which are arranged side by side and are sequentially connected in series. Wherein an isolation groove is formed between every two adjacent light-emitting units, and the isolation grooves are used for isolating the two adjacent light-emitting units; different light-emitting units share the same continuous light-emitting layer, the isolation groove is located on at least one side of the continuous light-emitting layer, and the bottom face of the isolation groove is the surface of the continuous light-emitting layer. According to the technical scheme provided by the invention, the luminance of the high-voltage light-emitting chip is improved, and the risk that the high-voltage light-emitting chip is broken from the isolation groove is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a high-voltage light-emitting chip and a method for manufacturing the same. Background Art

[0002] Micro-LED (Micro Light-Emitting Diode) is a new generation of core display technology with excellent characteristics such as low power consumption, high integration, high display effect and long life.

[0003] In related technology, a high-voltage light-emitting diode (HV-LED) chip is a semiconductor device that achieves high voltage, low current drive by connecting multiple micro-LEDs in series. Its manufacturing process involves dividing a large chip into multiple small light-emitting units on a substrate through isolation trenches, which are then connected in series via electrode connections. Because the isolation trench area does not emit light, and the etching process of the isolation trench damages the sidewalls of the light-emitting units, the brightness of the high-voltage light-emitting chip is reduced. Summary of the Invention

[0004] The embodiments of the present invention provide a high-voltage light-emitting chip and a method for manufacturing the same, so as to improve the light-emitting brightness of the high-voltage light-emitting chip.

[0005] According to one aspect of the present invention, there is provided a high-voltage light-emitting chip comprising at least two light-emitting units arranged side by side and sequentially connected in series;

[0006] Among them, an isolation groove is provided between each two adjacent light-emitting units, and the isolation groove is used to isolate the two adjacent light-emitting units; different light-emitting units share the same continuous light-emitting layer, the isolation groove is located on at least one side of the continuous light-emitting layer, and the bottom surface of the isolation groove is the surface of the continuous light-emitting layer.

[0007] Optionally, each of the light-emitting units includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in sequence; and the first semiconductor layers of different light-emitting units are located on the same side of the light-emitting layer;

[0008] The isolation trench is located between the first semiconductor layers of two adjacent light-emitting units and / or between the second semiconductor layers of two adjacent light-emitting units; the quantum well layers of different light-emitting units are connected together to form the continuous light-emitting layer.

[0009] Optionally, a first isolation trench and a second isolation trench are included between two adjacent light-emitting units;

[0010] The first isolation trench is located between the first semiconductor layers of two adjacent light-emitting units, and the first isolation trench is used to isolate the first semiconductor layers of the two adjacent light-emitting units;

[0011] The second isolation trench is located between the first semiconductor layers of two adjacent light-emitting units, and the second isolation trench is used to isolate the second semiconductor layers of the two adjacent light-emitting units;

[0012] The vertical projections of the first isolation trench and the second isolation trench between two adjacent light-emitting units on the continuous light-emitting layer overlap or at least partially do not overlap.

[0013] Optionally, the high-voltage light-emitting chip further includes:

[0014] An electrode connection structure is located between two adjacent light-emitting units, one end of the electrode connection structure is electrically connected to the first semiconductor layer of one of the two adjacent light-emitting units, and the other end of the electrode connection structure is electrically connected to the second semiconductor layer of the other of the two adjacent light-emitting units.

[0015] Optionally, the electrode connection structure is located on a side of the continuous light-emitting layer away from the first semiconductor layer, and the isolation trench is provided between the first semiconductor layers of two adjacent light-emitting units; wherein the light-emitting unit to which the first semiconductor layer is electrically connected to the electrode connection structure includes a connection opening, the connection opening sequentially penetrating the second semiconductor layer and quantum well layer of the light-emitting unit to expose the first semiconductor layer; the connection opening is connected to the isolation trench located between the first semiconductor layers, and the electrode connection structure for connecting two adjacent light-emitting units in series is located in the isolation trench between the connection opening and the first semiconductor layer;

[0016] Alternatively, the electrode connection structure is located on a side of the continuous light-emitting layer away from the second semiconductor layer, and the isolation groove is provided between the second semiconductor layers of two adjacent light-emitting units; wherein the light-emitting unit to which the second semiconductor layer is electrically connected to the electrode connection structure includes a connection opening, and the connection opening sequentially passes through the first semiconductor layer and the quantum well layer of the light-emitting unit to expose the second semiconductor layer; the connection opening is connected to the isolation groove located between the second semiconductor layers, and the electrode connection structure for connecting two adjacent light-emitting units in series is located in the isolation groove between the connection opening and the second semiconductor layer.

[0017] Optionally, the high-voltage light-emitting chip further includes:

[0018] a buffer layer, wherein the material of the buffer layer is an undoped or low-doped semiconductor material;

[0019] an insulating support layer, located on one side of the buffer layer; the insulating support layer is made of a semiconductor material doped with a resistive impurity; and the resistivity of the insulating support layer is greater than that of the buffer layer;

[0020] The light-emitting unit in the high-voltage light-emitting chip is located on the side of the insulating support layer away from the buffer layer, the isolation groove is located between the first semiconductor layers of two adjacent light-emitting units, and different light-emitting units share the same continuous second semiconductor layer.

[0021] Optionally, the high-voltage light-emitting chip further includes:

[0022] a buffer layer, wherein the material of the buffer layer is an undoped semiconductor material;

[0023] an insulating support layer, located on one side of the buffer layer; the insulating support layer is made of a semiconductor material doped with a resistive impurity; and the resistivity of the insulating support layer is greater than that of the buffer layer;

[0024] The light-emitting unit in the high-voltage light-emitting chip is located on a side of the insulating support layer away from the buffer layer.

[0025] Optionally, the total thickness of the buffer layer and the insulating support layer is in the range of 2um to 10um.

[0026] And / or, the semiconductor material of the buffer layer is the same as the semiconductor material of the insulating support layer; wherein the semiconductor material of the insulating support layer includes GaN, and the barrier impurities include C.

[0027] Optionally, the high-voltage light-emitting chip further includes:

[0028] The Bragg reflection layer is located on a surface of each light emitting unit away from the first buffer layer, a sidewall of the isolation trench, and a bottom surface of the isolation trench.

[0029] According to another aspect of the present invention, a method for preparing a high-voltage light-emitting chip is provided, which is used to prepare the high-voltage light-emitting chip according to any embodiment of the present invention, comprising:

[0030] providing a substrate;

[0031] At least two light-emitting units are formed side by side and connected in series on one side of the substrate, and the substrate is removed; wherein an isolation groove is provided between each two adjacent light-emitting units, and the isolation groove is used to isolate the two adjacent light-emitting units; different light-emitting units share the same continuous light-emitting layer, the isolation groove is located on at least one side of the continuous light-emitting layer, and the bottom surface of the isolation groove is the surface of the continuous light-emitting layer.

[0032] Optionally, before forming at least two light-emitting units arranged side by side and sequentially connected in series on one side of the substrate, the method further includes:

[0033] forming a buffer layer on one side of the substrate, wherein the material of the buffer layer is an undoped or low-doped semiconductor material;

[0034] An insulating support layer is formed on a side of the buffer layer away from the substrate; the insulating support layer is made of a semiconductor material doped with resistive impurities, and the resistivity of the insulating support layer is greater than that of the buffer layer.

[0035] An embodiment of the present invention provides a high-voltage light-emitting chip and a method for preparing the same. The high-voltage light-emitting chip includes at least two light-emitting units arranged side by side and connected in series in sequence. An isolation groove is provided between each two adjacent light-emitting units to isolate the two adjacent light-emitting units. Different light-emitting units share the same continuous light-emitting layer. The isolation groove is located on at least one side of the continuous light-emitting layer, and the bottom surface of the isolation groove is the surface of the continuous light-emitting layer. The technical solution provided by the embodiment of the present invention sets different light-emitting units to share the same continuous light-emitting layer without etching the light-emitting layer. This can avoid the sidewall damage caused by etching the light-emitting layer in the traditional structure, allowing more carriers to recombine and emit light, thereby improving the luminous efficiency of the high-voltage chip. Moreover, since the isolation groove is formed on one or both sides of the light-emitting layer, the high-voltage light-emitting chip has a larger light-emitting layer area, thereby improving the luminous brightness of the high-voltage light-emitting chip. In addition, setting the light-emitting layer as a continuous film layer structure can also reduce the risk of the high-voltage light-emitting chip breaking at the isolation groove.

[0036] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 is a top view of a high-voltage light-emitting chip provided by an embodiment of the present invention;

[0039] Figure 2 yes Figure 1 The structure shown is a cross-section along AA1;

[0040] Figure 3 yes Figure 1The structure shown is a cross-section along BB1;

[0041] Figure 4 is a top view of another high-voltage light-emitting chip provided by an embodiment of the present invention;

[0042] Figure 5 yes Figure 4 The structure shown is a cross-section along CC1;

[0043] Figure 6 yes Figure 4 The structure shown is a cross-section along DD1;

[0044] Figure 7 is a cross-sectional view of another high-voltage light-emitting chip provided by an embodiment of the present invention;

[0045] Figure 8 is a cross-sectional view of another high-voltage light-emitting chip provided by an embodiment of the present invention;

[0046] Figure 9 is a cross-sectional view of another high-voltage light-emitting chip provided by an embodiment of the present invention;

[0047] Figure 10 is a cross-sectional view of another high-voltage light-emitting chip provided by an embodiment of the present invention;

[0048] Figure 11 is a cross-sectional view of another high-voltage light-emitting chip provided by an embodiment of the present invention;

[0049] Figure 12 is a cross-sectional view of another high-voltage light-emitting chip provided by an embodiment of the present invention;

[0050] Figure 13 This is a flow chart of a method for preparing a high-voltage light-emitting chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] An embodiment of the present invention provides a high-voltage light-emitting chip, comprising at least two light-emitting units arranged side by side and connected in series in sequence;

[0054] Among them, an isolation groove is provided between each two adjacent light-emitting units, and the isolation groove is used to isolate the two adjacent light-emitting units; different light-emitting units share the same continuous light-emitting layer, the isolation groove is located on at least one side of the continuous light-emitting layer, and the bottom surface of the isolation groove is the surface of the continuous light-emitting layer.

[0055] The technical solution provided by the embodiments of the present invention configures different light-emitting units to share a single continuous light-emitting layer, eliminating the need for etching the light-emitting layer. This avoids the sidewall damage caused by etching the light-emitting layer in traditional structures, allowing more carriers to recombine and emit light, thereby improving the luminous efficiency of the high-voltage chip. Furthermore, because the isolation grooves are formed on one or both sides of the light-emitting layer, the high-voltage light-emitting chip has a larger light-emitting layer area, thereby increasing the brightness of the high-voltage light-emitting chip. Furthermore, by configuring the light-emitting layer as a continuous film structure, the risk of the high-voltage light-emitting chip breaking at the isolation grooves can be reduced.

[0056] The above is the core inventive concept of the present invention. The structure of the high-voltage light-emitting chip is described in detail below with reference to the accompanying drawings.

[0057] refer to Figures 1 to 7 Each light-emitting unit 30 includes a first semiconductor layer 31, a quantum well layer, and a second semiconductor layer 32 stacked in sequence; and the first semiconductor layers 31 of different light-emitting units 30 are located on the same side of the light-emitting layer; wherein the isolation groove 40 is located between the first semiconductor layers 31 of two adjacent light-emitting units 30 and / or between the second semiconductor layers 32 of two adjacent light-emitting units 30; the quantum well layers of different light-emitting units 30 are connected together to form a continuous light-emitting layer 33.

[0058] Specifically, the first semiconductor layer 31, the light-emitting layer, and the second semiconductor layer 32 are respectively an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer, or a P-type semiconductor layer, a quantum well layer, and an N-type semiconductor layer. The quantum well layers of different light-emitting units 30 are connected together to form a continuous light-emitting layer 33. Among them, the N-type semiconductor layer can be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but not limited thereto; the quantum well (MQW) layer can be an InGaN / GaN layer, an InGaN / AlGaN layer, or an AlGaN / AlGaN layer, but not limited thereto; the P-type semiconductor layer can be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but not limited thereto.

[0059] refer to Figure 1 and Figure 2 When the isolation trench 40 is formed on one side of the light-emitting layer, the isolation trench 40 can be located between the second semiconductor layers 32 of two adjacent light-emitting units 30. The isolation trench 40 is used to isolate the second semiconductor layers 32 of the two adjacent light-emitting units 30. In other words, the high-voltage light-emitting chip includes a continuous light-emitting layer 33, which includes a first surface and a second surface that are opposite to each other; the high-voltage light-emitting chip also includes at least two second semiconductor layers 32 spaced apart on the second surface of the continuous light-emitting layer 33; and the high-voltage light-emitting chip also includes a first semiconductor layer 31 configured as a continuous film layer, which covers the entire first surface of the continuous light-emitting layer 33.

[0060] refer to Figure 4 and Figure 5 When the isolation trench 40 is formed on one side of the light-emitting layer, the isolation trench 40 can be located between the first semiconductor layers 31 of two adjacent light-emitting units 30. The isolation trench 40 is used to isolate the first semiconductor layers 31 of the two adjacent light-emitting units 30. In other words, the high-voltage light-emitting chip includes a continuous light-emitting layer 33, which includes opposing first and second surfaces; the high-voltage light-emitting chip also includes at least two first semiconductor layers 31 spaced apart on the first surface of the continuous light-emitting layer 33; and the high-voltage light-emitting chip also includes a second semiconductor layer 32 configured as a continuous film layer, which covers the entire second surface of the continuous light-emitting layer 33.

[0061] By configuring different light-emitting units 30 to share the same continuous light-emitting layer 33, the light-emitting layer does not need to be etched. This avoids the sidewall damage caused by etching the light-emitting layer in traditional structures, allowing more carriers to recombine and emit light, thereby improving the luminous efficiency of the high-voltage chip. Moreover, because the isolation trench 40 is formed on one side of the continuous light-emitting layer 33 (the side of the continuous light-emitting layer 33 away from the second semiconductor layer 32, or the side of the continuous light-emitting layer 33 away from the first semiconductor layer 31), the high-voltage light-emitting chip has a larger light-emitting layer area, thereby improving the luminous brightness of the high-voltage light-emitting chip. It also prevents the high-voltage light-emitting chip from being affected by the non-luminescence in the isolation trench 40 area, thereby improving the uniformity of the light emission in the area between the left light-emitting unit 30L and the right light-emitting unit 30R. In addition, during the preparation of the high-voltage chip, only the first semiconductor layer 31 or the second semiconductor layer 32 needs to be etched to form the isolation trench 40, which provides a stable support for the light-emitting layer. The resulting high-voltage light-emitting chip structure is more stable and reliable, and the possibility of the high-voltage light-emitting chip breaking at the isolation trench is reduced.

[0062] Furthermore, since the N-type semiconductor layer in the high-voltage light-emitting chip has a relatively thick thickness (0.5 microns to 5 microns) compared to the P-type semiconductor layer in the high-voltage light-emitting chip, only the P-type semiconductor layer in the first semiconductor layer 31 and the second semiconductor layer can be etched to form the isolation trench 40, which can reduce the difficulty of etching the isolation trench 40 and further reduce the possibility of chip breakage. For example, refer to Figure 2 and Figure 5 The first semiconductor layer 31 is an N-type semiconductor layer, the second semiconductor layer 32 is a P-type semiconductor layer, and the thickness of the second semiconductor layer 32 is less than that of the first semiconductor layer 31. Therefore, it is preferred to use Figure 2 In the structure shown, the second semiconductor layer 3 is etched to form an isolation groove 402. At this time, the light-emitting layer is located on the thicker N-type semiconductor layer. Different light-emitting units 30 share the N-type semiconductor layer and the light-emitting layer, which can further improve the structural stability and reliability of the high-voltage light-emitting chip and reduce the possibility of breakage.

[0063] refer to Figure 7When the isolation trenches 40 are formed on opposite sides of the continuous light-emitting layer 33, a first isolation trench 41 and a second isolation trench 42 are formed between two adjacent light-emitting units 30. The first isolation trench 41 is located between the first semiconductor layers 31 of the two adjacent light-emitting units 30 and is used to isolate the first semiconductor layers 31 of the two adjacent light-emitting units 30. The second isolation trench 42 is located between the second semiconductor layers 32 of the two adjacent light-emitting units 30 and is used to isolate the second semiconductor layers 32 of the two adjacent light-emitting units 30. The vertical projections of the first semiconductor layer 31 and the second semiconductor layer 32 of each light-emitting unit 30 on the continuous light-emitting layer 33 at least partially overlap.

[0064] By configuring different light-emitting units 30 to share the same continuous light-emitting layer 33, there is no need to etch the light-emitting layer. This avoids the sidewall damage caused by etching the light-emitting layer in traditional structures, allowing more carriers to recombine and emit light, thereby improving the luminous efficiency of the high-voltage chip. Moreover, because the isolation trenches 40 are formed on opposite sides of the continuous light-emitting layer 33 (the side of the continuous light-emitting layer 33 away from the second semiconductor layer 32, and the side of the continuous light-emitting layer 33 away from the first semiconductor layer 31), the high-voltage light-emitting chip has a larger light-emitting layer area, thereby improving the luminous brightness of the high-voltage light-emitting chip. It also prevents the high-voltage chip from being affected by the non-luminescence in the isolation trench 40 area, thereby improving the uniformity of the light emission in the area between the left and right light-emitting units 30. In addition, during the preparation of the high-voltage chip, etching the first semiconductor layer 31 and the second semiconductor layer 32 to form the isolation trenches 40 can improve the electrical isolation between the two adjacent light-emitting units 30.

[0065] Please continue to refer to 7 , the vertical projections of the first isolation trench 41 and the second isolation trench 42 between two adjacent light-emitting units 30 on the continuous light-emitting layer 33 are overlapped.

[0066] In another embodiment of the present invention, the vertical projections of the first isolation trench 41 and the second isolation trench 42 between two adjacent light-emitting units 30 on the continuous light-emitting layer 33 may at least partially not overlap. Staggering the vertical projections of the first isolation trench 41 and the second isolation trench 42 between two adjacent light-emitting units 30 on the continuous light-emitting layer 33 can reduce the risk of fracture due to a weak film structure in the region of the isolation trench 40.

[0067] Further, Figure 8 is a cross-sectional view of another high-voltage light-emitting chip provided by an embodiment of the present invention, referring to Figure 8 The vertical projections of the first isolation groove 41 and the second isolation groove 42 between two adjacent light-emitting units 30 on the continuous light-emitting layer 33 do not overlap, which can further reduce the risk of the high-voltage light-emitting chip breaking at the isolation groove.

[0068] Based on the above embodiments, optionally, the high-voltage light-emitting chip further includes:

[0069] The electrode connection structure 50 is located between two adjacent light-emitting units 30. One end of the electrode connection structure 50 is electrically connected to the first semiconductor layer 31 of one of the two adjacent light-emitting units 30, and the other end of the electrode connection structure 50 is electrically connected to the second semiconductor layer 32 of the other of the two adjacent light-emitting units 30, thereby realizing the series connection of the two adjacent light-emitting units 30.

[0070] Specifically, when the isolation trench 40 is formed on one side of the light emitting layer and is located between the second semiconductor layers 32 of two adjacent light emitting units 30, refer to Figure 3 The electrode connection structure 50 is located on the side of the continuous light-emitting layer 33 away from the first semiconductor layer 31. The light-emitting unit 30 in which the second semiconductor layer 32 is electrically connected to the electrode connection structure 50 includes a connection opening 301. The connection opening 301 sequentially penetrates the second semiconductor layer 32 and the quantum well layer of the light-emitting unit 30, exposing the first semiconductor layer 31. The connection opening 301 is connected to the isolation trench 40 located between the second semiconductor layers 32. The electrode connection structure 50 for connecting two adjacent light-emitting units 30 in series is located in the isolation trench 40 between the connection opening 301 and the second semiconductor layer 32.

[0071] In the case where the isolation trench 40 is formed on one side of the light emitting layer and is located between the first semiconductor layers 31 of two adjacent light emitting units 30, Figure 6 The electrode connection structure 50 is located on a side of the continuous light-emitting layer 33 away from the second semiconductor layer 32. The light-emitting unit 30 electrically connected to the second semiconductor layer 32 includes a connection opening 301. The connection opening 301 sequentially penetrates the first semiconductor layer 31 and the quantum well layer of the light-emitting unit 30, exposing the second semiconductor layer 32. The connection opening 301 is connected to the isolation trench 40 located between the first semiconductor layers 31. The electrode connection structure 50 for connecting two adjacent light-emitting units 30 in series is located in the isolation trench 40 between the connection opening 301 and the first semiconductor layer 31.

[0072] In the case where the isolation trench 40 is formed on opposite sides of the light-emitting layer, the electrode connection structure 50 is located on a side of the continuous light-emitting layer 33 away from the second semiconductor layer 32, and is electrically connected to the first semiconductor layer 31 through the connection opening 301. Alternatively, the electrode connection structure 50 is located on a side of the continuous light-emitting layer 33 away from the first semiconductor layer 31, and is electrically connected to the second semiconductor layer 32 through the connection opening 301. Details are not repeated here.

[0073] On the basis of the above embodiments, optionally, refer to Figures 3 to 6, a prepared metal wire can be used as the electrode connection structure 50 to directly connect two adjacent light-emitting units 30. In other embodiments of the present invention, the electrode connection structure 50 can be a metal wire formed by an evaporation process during the preparation of the light-emitting chip. The electrode connection structure 50 runs along the wall of the isolation trench from one light-emitting unit to the other light-emitting unit 30 through the isolation trench. It should be noted that an insulating film layer is provided between the electrode connection structure and the wall of the isolation trench to prevent the light-emitting unit from malfunctioning.

[0074] On the basis of the above embodiments, optionally, refer to Figures 9 to 11 , the high-voltage light-emitting chip also includes:

[0075] The Bragg reflector 60 is located on the non-light-emitting side surface of each light-emitting unit 30 . The light-emitting direction of the light-emitting unit 30 is the direction from the continuous light-emitting layer 33 to the first semiconductor layer 31 .

[0076] in, Figure 9 is Figure 2 The cross-sectional structure diagram after the Bragg reflection layer 60 is provided on the structure shown in FIG. Figure 9 A Bragg reflection layer 60 is provided on the sidewall of each light emitting unit 30 , the sidewall and bottom surface of the isolation trench 40 , and the side of the second semiconductor layer 32 in the light emitting unit 30 away from the first semiconductor layer 31 . Figure 10 is Figure 5 The cross-sectional structure diagram after the Bragg reflection layer 60 is provided on the structure shown in FIG. Figure 10 A Bragg reflection layer 60 is provided on the sidewall of each light emitting unit 30, the sidewall of the isolation trench 40, and the side of the second semiconductor layer 32 in the light emitting unit 30 away from the first semiconductor layer 31; in other embodiments of the present invention, Figure 10 In the structure shown, the sidewalls of the isolation trench 40 may not be provided with the Bragg reflection layer 60 to reduce the difficulty of manufacturing; Figure 11 is Figure 7 The cross-sectional structure diagram after the Bragg reflection layer 60 is provided on the structure shown in FIG. Figure 11 A Bragg reflection layer 60 is provided on the sidewalls of each light emitting unit 30, the sidewalls of the first isolation trench 41, the sidewalls and bottom surface of the second isolation trench 42, and the side of the second semiconductor layer 32 in the light emitting unit 30 away from the first semiconductor layer 31. In other embodiments of the present invention, Figure 11 In the structure shown, the Bragg reflection layer 60 may not be provided on the sidewall of the first isolation trench 41 to reduce the difficulty of manufacturing.

[0077] Specifically, the Bragg reflector 60 (DBR) is a multilayer thin-film structure based on the optical interference effect. It forms a periodic structure by alternating layers of high-refractive-index materials and low-refractive-index materials. When the optical thickness (thickness x refractive index) of each layer is 1 / 4 of the wavelength λ of the light emitted by the quantum well layer, the coherence of the reflected light from each layer is enhanced, achieving high reflectivity at specific wavelengths. By providing a Bragg reflector 60 on the non-light-emitting side surface of each light-emitting unit 30, the light output of the high-voltage light-emitting chip can be increased.

[0078] Based on the above embodiments, Figure 12 , optionally, the high voltage light emitting chip also includes:

[0079] The buffer layer 10 is made of an undoped or low-doped semiconductor material;

[0080] The insulating support layer 20 is located on one side of the buffer layer 10; the material of the insulating support layer 20 is a semiconductor material doped with a resistive impurity; the resistivity of the insulating support layer 20 is greater than the resistivity of the buffer layer 10;

[0081] The light emitting unit 30 in the high-voltage light emitting chip is located on a side of the insulating support layer 20 away from the buffer layer 10 .

[0082] Specifically, the buffer layer 10 and the insulating support layer 20 are both semiconductor epitaxial layers. During the preparation of the high-voltage light-emitting chip, the buffer layer 10 and the insulating support layer 20 are sequentially formed on the same side of the substrate. The semiconductor material of the buffer layer 10 includes, but is not limited to, GaN, and the substrate includes, but is not limited to, a sapphire substrate or a silicon substrate. The buffer layer 10 is disposed between the substrate and the light-emitting unit 30. The buffer layer 10 can prevent defects (such as dislocations, microcracks, etc.) from the substrate from propagating to the light-emitting unit 30, thereby improving the crystal quality of the material of the light-emitting unit 30. The insulating support layer 20 is formed on the side of the buffer layer 10 away from the substrate. The semiconductor material of the insulating support layer 20 includes, but is not limited to, GaN, and is doped with resistive impurities, including, but not limited to, C. By doping the semiconductor material of the insulating support layer 20 with resistive impurities, the insulation properties of the insulating support layer 20 can be improved, making the resistivity of the insulating support layer 20 greater than that of the buffer layer 10, thereby making the insulation properties of the insulating support layer 20 stronger than those of the buffer layer 10.

[0083] After the buffer layer 10 and the insulating support layer 20 are sequentially formed on the same side of the substrate, a semiconductor epitaxial layer for preparing the light-emitting unit 30 is sequentially formed on the side of the insulating support layer 20 away from the buffer layer 10, and then at least two light-emitting units 30 are formed by etching the semiconductor epitaxial layer for preparing the light-emitting unit 30. Figure 12The figure shows two adjacent light-emitting units 30 in a high-voltage light-emitting chip, which are the left light-emitting unit 30L and the right light-emitting unit 30R. The embodiment of the present invention does not limit the number of light-emitting units 30, and can be set according to actual conditions. When the number of light-emitting units 30 is large, multiple light-emitting units 30 can be arranged in an array. At least two light-emitting units 30 are arranged on the surface of the insulating support layer 20 away from the buffer layer 10. The insulating support layer 20 can prevent the light-emitting units 30 from being electrically connected from the bottom. In addition, the insulating support layer 20 can also provide additional mechanical strength and stability. After the light-emitting unit 30 is formed, the substrate needs to be removed. By setting the insulating support layer 20 between the buffer layer 10 and the light-emitting unit 30, the undoped buffer layer 10 and the insulating support layer 20 doped with inhibitory impurities are used as the support structure of the light-emitting unit 30, which can ensure the connection strength of adjacent light-emitting units 30, thereby improving the problem of the high-voltage light-emitting chip breaking from the isolation groove 40 and improving the stability of the high-voltage light-emitting chip structure.

[0084] It should be noted that the isolation trench 40 in the embodiment of the present invention is formed on one side of the continuous light-emitting layer 33 , and is formed on the side of the continuous light-emitting layer 33 away from the insulating support layer 20 . Figure 12 The exemplary embodiment shows that the isolation trench 40 is located between the second semiconductor layers 32 of two adjacent light-emitting units 30. Different light-emitting units 30 share the same continuous first semiconductor layer 31 and light-emitting layer, and the insulating support layer 20 and the buffer layer 10 are both located on the side of the first semiconductor layer 31 away from the continuous light-emitting layer 33. That is, after the buffer layer 10 and the insulating support layer 20 are sequentially formed on the same side of the substrate, the first semiconductor layer 31, the continuous light-emitting layer 33, and the second semiconductor layer 32 for preparing the light-emitting units 30 are sequentially formed on the side of the insulating support layer 20 away from the buffer layer 10, and then the second semiconductor layer 32 is etched to form the isolation trench 40 that isolates the light-emitting units 30.

[0085] The light emission direction of the high-voltage light-emitting chip is from the continuous light-emitting layer 33 to the buffer layer 10. A Bragg reflector 60 is provided on the sidewalls of each light-emitting unit 30 and extends toward the insulating support layer 20 and the buffer layer 10 to cover the sidewalls of the insulating support layer 20 and the buffer layer 10. This prevents light from being emitted from the sidewalls of the light-emitting unit 30, the insulating support layer 20, and the buffer layer 10, thereby increasing the light output of the high-voltage light-emitting chip.

[0086] Based on the above embodiments, the semiconductor material of the buffer layer 10 and the insulating support layer 20 can optionally be the same, thereby facilitating the preparation of the buffer layer 10 and the insulating support layer 20 and simplifying the production process of the high-voltage light-emitting chip. The buffer layer 10 is made of undoped or low-doped GaN, while the insulating support layer 20 is made of GaN doped with carbon (C), i.e., the insulating support layer 20 is a high-resistance gallium nitride layer.

[0087] Based on the above embodiments, optionally, the total thickness of the buffer layer 10 and the insulating support layer 20 is in the range of 2 um to 10 um.

[0088] Specifically, if the total thickness of the buffer layer 10 and the insulating support layer 20 is too thin, the connection strength between two adjacent light-emitting units 30 will be low, and the adjacent light-emitting units 30 may be easily broken during the substrate peeling process. If the total thickness of the buffer layer 10 and the insulating support layer 20 is too thick, if the thickness of the overall epitaxial structure is to be kept constant, the thickness of the semiconductor epitaxial layer in the light-emitting unit 30 needs to be reduced, which may easily lead to the light-emitting unit 30 being too thin, affecting the luminous efficiency. If the thickness of the semiconductor epitaxial layer in the light-emitting unit 30 is increased without changing the thickness of the buffer layer 10 and / or the insulating support layer 20, so that the total thickness of the buffer layer 10 and the insulating support layer 20 is too thick, it will lead to increased subsequent polishing work on the buffer layer 10. Setting the total thickness of the buffer layer 10 and the insulating support layer 20 to a range of 2um to 10um can avoid affecting the luminous efficiency or increasing the polishing work when the thickness is too thick, while ensuring the connection strength of adjacent light-emitting units 30.

[0089] The embodiment of the present invention further provides a method for preparing a high-voltage light-emitting chip, which is used to prepare the high-voltage light-emitting chip described in any embodiment of the present invention. Figure 13 This is a flow chart of a method for preparing a high-voltage light-emitting chip provided by an embodiment of the present invention, with reference to Figure 13 , the preparation method of the high-voltage light-emitting chip includes:

[0090] S10. Provide a substrate.

[0091] S20. Form at least two light-emitting units arranged side by side and connected in series on one side of the substrate, and remove the substrate; wherein an isolation groove is provided between each two adjacent light-emitting units, and the isolation groove is used to isolate the two adjacent light-emitting units; different light-emitting units share the same continuous light-emitting layer, the isolation groove is located on at least one side of the continuous light-emitting layer, and the bottom surface of the isolation groove is the surface of the continuous light-emitting layer.

[0092] The technical solution provided by the embodiment of the present invention forms at least two light-emitting units that share the same continuous light-emitting layer, without the need to etch the light-emitting layer. This can avoid the sidewall damage caused by etching the light-emitting layer in the traditional structure, allowing more carriers to recombine and emit light, thereby improving the luminous efficiency of the high-voltage chip; and because the isolation groove is formed on one side or both sides of the light-emitting layer, the high-voltage light-emitting chip has a larger light-emitting layer area, thereby improving the luminous brightness of the high-voltage light-emitting chip.

[0093] refer to Figure 2 and Figure 5In the case where the isolation groove 40 is formed on one side of the continuous light-emitting layer 33, the method for preparing the high-voltage light-emitting chip includes:

[0094] S110 , providing a substrate.

[0095] Specifically, the substrate may be a sapphire substrate, a Si substrate or a SiC substrate, but is not limited thereto.

[0096] S120 , forming a semiconductor epitaxial layer for preparing the light-emitting unit 30 on one side of the substrate, etching the semiconductor epitaxial layer on the side of the continuous light-emitting layer 33 away from the substrate to form an isolation trench 40 , thereby forming at least two light-emitting units 30 .

[0097] Specifically, at least two light-emitting units 30 are formed side by side and connected in series on one side of a substrate, including: forming a semiconductor epitaxial layer for forming the light-emitting units 30 on one side of the substrate, etching the semiconductor epitaxial layer on the side of the continuous light-emitting layer 33 away from the substrate to form an isolation trench 40, thereby forming at least two light-emitting units 30. Each light-emitting unit 30 includes a first semiconductor layer 31, a quantum well layer, and a second semiconductor layer 32 stacked in sequence; the quantum well layers of different light-emitting units 30 are connected together to form a continuous light-emitting layer 33, and the first semiconductor layers 31 of different light-emitting units 30 are located on the same side of the continuous light-emitting layer 33. The isolation trench 40 is located between the first semiconductor layers 31 of two adjacent light-emitting units 30 or between the second semiconductor layers 32 of two adjacent light-emitting units 30.

[0098] When the isolation trench 40 is located between the second semiconductor layers 32 of two adjacent light-emitting units 30, forming the semiconductor epitaxial layers for preparing the light-emitting units 30 on one side of the substrate includes sequentially forming the first semiconductor layer 31, the continuous light-emitting layer 33, and the second semiconductor layer 32 on one side of the substrate. Etching the semiconductor epitaxial layer located on the side of the continuous light-emitting layer 33 away from the substrate to form the isolation trench 40 includes etching the second semiconductor layer 32 located on the side of the continuous light-emitting layer 33 away from the substrate until the continuous light-emitting layer 33 is exposed, thereby forming the isolation trench 40.

[0099] When the isolation trench 40 is located between the first semiconductor layers 31 of two adjacent light-emitting units 30, forming the semiconductor epitaxial layers for preparing the light-emitting units 30 on one side of the substrate includes sequentially forming the second semiconductor layer 32, the continuous light-emitting layer 33, and the first semiconductor layer 31 on one side of the substrate. Etching the semiconductor epitaxial layers located on the side of the continuous light-emitting layer 33 away from the substrate to form the isolation trench 40 includes etching the first semiconductor layer 31 located on the side of the continuous light-emitting layer 33 away from the substrate until the continuous light-emitting layer 33 is exposed, thereby forming the isolation trench 40.

[0100] S130: Remove the substrate.

[0101] The technical solution provided by the present invention is that during the preparation of the high-voltage chip, only the first semiconductor layer 31 or the second semiconductor layer 32 is etched to form the isolation groove 40, so that the light-emitting layer has a stable support. The formed high-voltage light-emitting chip structure is more stable and reliable, and the possibility of breakage is reduced.

[0102] In other embodiments of the present invention, when the isolation trench 40 is located between the first semiconductor layers 31 of two adjacent light-emitting units 30, and the first semiconductor layer 31, the continuous light-emitting layer 33 and the second semiconductor layer 32 are sequentially formed on the substrate, the exposed first semiconductor layer 31 can be etched after removing the substrate, thereby forming an isolation trench 40 located between the first semiconductor layers 31 of the two adjacent light-emitting units 30, and further forming at least two light-emitting units 30.

[0103] refer to Figure 7 and Figure 8 In the case where the isolation groove 40 is formed on two opposite sides of the continuous light-emitting layer 33, the method for preparing the high-voltage light-emitting chip includes:

[0104] S210 , providing a substrate.

[0105] S220 , forming a semiconductor epitaxial layer for preparing the light-emitting unit 30 on one side of the substrate, etching the semiconductor epitaxial layer on the side of the continuous light-emitting layer 33 away from the substrate, and forming an isolation trench 40 on one side of the continuous light-emitting layer 33 .

[0106] S230: Remove the substrate.

[0107] S240 , etching and removing the semiconductor epitaxial layer exposed after the substrate is removed, so as to form an isolation trench 40 on the other side of the continuous light-emitting layer 33 , thereby forming at least two light-emitting units 30 .

[0108] The technical solution provided by the present invention is that during the preparation of the high-voltage chip, the first semiconductor layer 31 and the second semiconductor layer 32 located on opposite sides of the continuous light-emitting layer 33 are etched to form isolation grooves 40, which can improve the electrical isolation between two adjacent light-emitting units 30.

[0109] Based on the above embodiments, optionally, before forming at least two light-emitting units 30 arranged side by side and sequentially connected in series on one side of the substrate, the method further includes:

[0110] A buffer layer 10 is formed on one side of the substrate, and the material of the buffer layer 10 is an undoped or low-doped semiconductor material;

[0111] An insulating support layer 20 is formed on a side of the buffer layer 10 away from the substrate. The insulating support layer 20 is made of a semiconductor material doped with resistive impurities, and has a resistivity greater than that of the buffer layer 10 .

[0112] The technical solution provided by the present invention forms an insulating support layer 20 on the surface of the buffer layer 10 away from the substrate. The undoped or low-doped buffer layer 10 and the insulating support layer 20 doped with a blocking impurity serve as the support structure for the light-emitting units 30. This ensures the connection strength between adjacent light-emitting units 30, thereby improving the problem of high-voltage light-emitting chips breaking at the isolation trench 40 during substrate removal and enhancing structural stability. Furthermore, by providing the insulating support layer 20 doped with a blocking impurity between the buffer layer 10 and the light-emitting units 30, adjacent light-emitting units 30 can be better electrically isolated on the surface of the insulating support layer 20.

[0113] In the case where the continuous light-emitting layer 33 has an isolation groove 40 on the side close to the buffer layer 10, the isolation groove 40 can be formed by etching the semiconductor epitaxial layer between the continuous light-emitting layer 33 and the insulating support layer 20 after peeling off the substrate and removing the buffer layer 10 and the insulating support layer 20 (e.g., Figure 5 structure shown).

[0114] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A high-voltage light-emitting chip, characterized in that: It comprises at least two light-emitting units arranged side by side and connected in series; Among them, an isolation groove is provided between each two adjacent light-emitting units, and the isolation groove is used to isolate the two adjacent light-emitting units; different light-emitting units share the same continuous light-emitting layer, the isolation groove is located on at least one side of the continuous light-emitting layer, and the bottom surface of the isolation groove is the surface of the continuous light-emitting layer.

2. The high-voltage light-emitting chip according to claim 1, characterized in that: Each of the light-emitting units includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in sequence; and the first semiconductor layers of different light-emitting units are located on the same side of the light-emitting layer; The isolation trench is located between the first semiconductor layers of two adjacent light-emitting units and / or between the second semiconductor layers of two adjacent light-emitting units; the quantum well layers of different light-emitting units are connected together to form the continuous light-emitting layer.

3. The high-voltage light-emitting chip according to claim 2, characterized in that: A first isolation trench and a second isolation trench are provided between two adjacent light-emitting units; The first isolation trench is located between the first semiconductor layers of two adjacent light-emitting units, and the first isolation trench is used to isolate the first semiconductor layers of the two adjacent light-emitting units; The second isolation trench is located between the first semiconductor layers of two adjacent light-emitting units, and the second isolation trench is used to isolate the second semiconductor layers of the two adjacent light-emitting units; The vertical projections of the first isolation trench and the second isolation trench between two adjacent light-emitting units on the continuous light-emitting layer overlap or at least partially do not overlap.

4. The high-voltage light-emitting chip according to claim 2, characterized in that: Also includes: An electrode connection structure is located between two adjacent light-emitting units, one end of the electrode connection structure is electrically connected to the first semiconductor layer of one of the two adjacent light-emitting units, and the other end of the electrode connection structure is electrically connected to the second semiconductor layer of the other of the two adjacent light-emitting units.

5. The high-voltage light-emitting chip according to claim 4, characterized in that: The electrode connection structure is located on a side of the continuous light-emitting layer away from the first semiconductor layer, and the isolation trench is provided between the first semiconductor layers of two adjacent light-emitting units; wherein the light-emitting unit to which the first semiconductor layer is electrically connected to the electrode connection structure includes a connection opening, the connection opening sequentially penetrating the second semiconductor layer and quantum well layer of the light-emitting unit to expose the first semiconductor layer; the connection opening is in communication with the isolation trench located between the first semiconductor layers, and the electrode connection structure for connecting two adjacent light-emitting units in series is located in the isolation trench between the connection opening and the first semiconductor layer; Alternatively, the electrode connection structure is located on a side of the continuous light-emitting layer away from the second semiconductor layer, and the isolation groove is provided between the second semiconductor layers of two adjacent light-emitting units; wherein the light-emitting unit to which the second semiconductor layer is electrically connected to the electrode connection structure includes a connection opening, and the connection opening sequentially passes through the first semiconductor layer and the quantum well layer of the light-emitting unit to expose the second semiconductor layer; the connection opening is connected to the isolation groove located between the second semiconductor layers, and the electrode connection structure for connecting two adjacent light-emitting units in series is located in the isolation groove between the connection opening and the second semiconductor layer.

6. The high-voltage light-emitting chip according to claim 2, characterized in that: Also includes: a buffer layer, wherein the material of the buffer layer is an undoped or low-doped semiconductor material; an insulating support layer, located on one side of the buffer layer; the insulating support layer is made of a semiconductor material doped with a resistive impurity; and the resistivity of the insulating support layer is greater than that of the buffer layer; The light-emitting unit in the high-voltage light-emitting chip is located on a side of the insulating support layer away from the buffer layer.

7. The high-voltage light-emitting chip according to claim 6, characterized in that: The total thickness of the buffer layer and the insulating support layer is in the range of 2um to 10um And / or, the semiconductor material of the buffer layer is the same as the semiconductor material of the insulating support layer; wherein the semiconductor material of the insulating support layer includes GaN, and the barrier impurities include C.

8. The high-voltage light-emitting chip according to claim 6, characterized in that: Also includes: The Bragg reflection layer is located on the non-light-emitting side surface of each light-emitting unit; the light-emitting direction of the light-emitting unit is the direction from the continuous light-emitting layer to the first semiconductor layer.

9. A method for preparing a high-voltage light-emitting chip, characterized in that: Used to prepare the high-voltage light-emitting chip according to any one of claims 1 to 8, comprising: providing a substrate; At least two light-emitting units are formed side by side and connected in series on one side of the substrate, and the substrate is removed; wherein an isolation groove is provided between each two adjacent light-emitting units, and the isolation groove is used to isolate the two adjacent light-emitting units; different light-emitting units share the same continuous light-emitting layer, the isolation groove is located on at least one side of the continuous light-emitting layer, and the bottom surface of the isolation groove is the surface of the continuous light-emitting layer.

10. The method for preparing a high-voltage light-emitting chip according to claim 9, wherein: Before forming at least two light-emitting units arranged side by side and sequentially connected in series on one side of the substrate, the method further includes: forming a buffer layer on one side of the substrate, wherein the material of the buffer layer is an undoped or low-doped semiconductor material; An insulating support layer is formed on a side of the buffer layer away from the substrate; the insulating support layer is made of a semiconductor material doped with resistive impurities, and the resistivity of the insulating support layer is greater than that of the buffer layer.

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