Abrasive polishing parameter-based medium-free holographic optical element processing technology and medium-free holographic optical element

Abstract

The application discloses a medium-free holographic optical element processing technology based on grinding polishing parameters and a medium-free holographic optical element, and particularly relates to the field of medium-free holographic optical elements. The optical element comprises three layers of structures in sequence: a first layer of structure is a main conductive layer which is composed of the following components in proportion by mass fraction: 40 parts of reduced graphene oxide, 22 parts of silver nanowires, 12 parts of polyvinyl alcohol composite dispersing agent, 25 parts of deionized water and 1 part of an interfacial stabilizer; and a second layer of structure is an interfacial buffer film which is arranged between the main conductive layer and a pattern structure layer. A controllable-density broken island interfacial buffer structure is constructed between the conductive layer and the pattern structure layer, so as to cut off the potential closed-loop coupling path at the physical level, thereby inhibiting the optical instability phenomenon induced by electrostatic resonance, and solving the problem that the coupling field between the conductive layer and the pattern layer in the prior art cannot be blocked by the structure.

Description

Technical Field

[0001] This invention relates to the field of medium-free holographic optical element technology, and more specifically, to a medium-free holographic optical element processing technology based on grinding and polishing parameters, and to a medium-free holographic optical element. Background Technology

[0002] In the current development of dielectric-free holographic optical components, conductive antistatic layers are widely used to prevent surface charge accumulation in order to maintain the optical stability of the components during long-term operation or in high-dust environments.

[0003] However, as components evolve towards higher integration and subwavelength structural precision, traditional conductive layers (such as doped ITO or graphene films) have exposed a structural electrical coupling vulnerability that has not yet been identified in practical applications: when the conductive layer and the underlying holographic pattern structure form a local microcapacitor structure at the micro-nano scale, if external static charges are continuously superimposed, these regions will evolve into potential closed-loop regions with quasi-resonance characteristics.

[0004] This closed loop can induce periodic electric field pulsations under specific field strengths, which directly affect the local transmission and reflection behavior of the light field, manifesting as unpredictable optical instability phenomena such as diffraction pattern flicker, image drift, or transient defocus.

[0005] More seriously, this optical electrostatic resonance state has positive feedback characteristics: the initial weak resonance will promote more charge accumulation, quickly forming a large-scale synchronous disturbance, which can destroy the phase integrity of the entire holographic coding layer within seconds.

[0006] Existing antistatic designs mainly rely on surface resistance adjustment and charge dissipation layer construction, ignoring the evolution of charge coupling paths in the structural layers and failing to effectively cut off the resonant source;

[0007] It is evident that the implicit resonant coupling field formed between the antistatic conductive layer and the optical structure in dielectric-free holographic elements has become one of the core threats to the stability of current materials. Summary of the Invention

[0008] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide a dielectric-free holographic optical element fabrication process based on grinding and polishing parameters, as well as a dielectric-free holographic optical element. By constructing a controllable density fractured island-shaped interface buffer structure between the conductive layer and the pattern structure layer, the potential closed-loop coupling path is cut off at the physical level, thereby suppressing the optical instability induced by electrostatic resonance and solving the problem mentioned in the background art that the coupling field between the conductive layer and the pattern layer cannot be blocked by the structure.

[0009] To achieve the above objectives, the present invention provides the following technical solution: a dielectric-free holographic optical element based on grinding and polishing parameters, wherein the optical element comprises the following three layers in sequence:

[0010] The first layer is the main conductive layer, which is composed of the following components in the following mass ratios: 40 parts of reduced graphene oxide, 22 parts of silver nanowires, 12 parts of polyvinyl alcohol composite dispersant, 25 parts of deionized water, and 1 part of interface stabilizer.

[0011] The second layer is an interface buffer film, which is disposed between the main conductive layer and the patterned structure layer. It is composed of the following components in the following mass ratio: 80 parts gallium, 14 parts indium, 3 parts tin, 1 part tungsten nanoparticles, 1 part sodium acetate, and 1 part tributylphosphine.

[0012] The third layer is a patterned structure layer, composed of the following components in the following mass ratios: 80 parts silicon nitride powder, 10 parts lithium borate, 6 parts potassium titanate, and 4 parts lead borosilicate glass flux.

[0013] In a preferred embodiment, the main conductive layer is bonded by homogenization and hot pressing to form a continuous conductive film layer, and the surface resistance of the main conductive layer is controlled in the range of 120 to 180 ohms per square.

[0014] The interface buffer film is induced to condense by terminal polishing, forming multiple unconnected fractured island-shaped structural blocks. The boundaries of the fractured island-shaped structural blocks are discontinuously distributed, which is used to cut off the equipotential coupling between the main conductive layer and the underlying pattern structure.

[0015] The pattern structure layer is spray-dried and sintered to form a subwavelength pattern encoding substrate. The substrate has a pattern cross-section with Ra≤2nm and is formed into a periodic structure by ion beam etching.

[0016] In a preferred embodiment, the silver nanowires are dispersed in the main conductive layer in a coating phase formed by a polyvinyl alcohol composite dispersant. The silver nanowires have a diameter of 40 nanometers and a length of 30 micrometers. The overall silver content of the silver nanowires accounts for 22 parts of the total mass of the main conductive layer. The nanowires are prepared by in-situ silver formate reduction to ensure uniform dispersion and continuity of the conductive path.

[0017] In a preferred embodiment, during the formation of the interface buffer film, the interface polishing temperature is controlled between 28°C and 38°C, so that the gallium-indium alloy system preferentially grows along the tungsten nanoparticle-induced region under charge drive, forming no less than 100 fractured island-like structural blocks per unit area, and the block size ranges from 0.3 to 1.8 micrometers.

[0018] In a preferred embodiment, the tungsten nanoparticles are coated with 0.3 parts of fluorinated polytrifluoroethylene to guide the potential distribution in the gallium-indium alloy system to form an asymmetry, thereby increasing the lateral discontinuity ratio of the fracture island region and enhancing the effectiveness of the blocking path.

[0019] In a preferred embodiment, before etching, silicon nitride powder is spray-dried to control its particle size to D90≤300 nm, and then ion-beam etched to form a patterned coding structure with a period of 300 nm and a depth of 50 nm on the surface, while maintaining the integrity of its optical interference phase under the action of the fracture island region.

[0020] In a preferred embodiment, the main conductive layer and the interface buffer film are interfacially bonded by a silane coupling agent, wherein the silane coupling agent is 3-fluoropropyltriethoxysilane, and the amount used is 0.6 parts, which is used to improve interlayer adhesion and prevent the risk of delamination during the subsequent holographic pattern forming process.

[0021] The fabrication process of dielectric-free holographic optical elements based on grinding and polishing parameters includes:

[0022] Step S1, Preparation of the main conductive layer:

[0023] Reduced graphene oxide, silver nanowires, polyvinyl alcohol composite dispersant, deionized water and interface stabilizer were sequentially added to a stirring container, and mechanical stirring and ultrasonic dispersion were combined until a stable and uniform dispersion was formed.

[0024] The dispersion was distributed on the carrier configuration plane using a spin coating process, and a conductive film layer was constructed by hot pressing. The hot pressing temperature was set to 80°C and the hot pressing duration was 90 seconds.

[0025] The formed conductive film layer was tested using a four-probe test method, and the output surface resistance value was limited to between 120 ohms per square and 180 ohms per square.

[0026] Step S2, Construction of the interface buffer membrane:

[0027] Gallium, indium, tin, tungsten nanoparticles, sodium acetate, and tributylphosphine were mixed sequentially according to a preset mass ratio, and a multi-component liquid-phase mixture was generated by a low-temperature hot-melting method; wherein the temperature of the low-temperature hot-melting method was controlled between 40°C and 55°C.

[0028] The obtained liquid phase mixture was spread evenly on the surface of the main conductive layer using a blade scraping method, and then polishing-induced condensation treatment was immediately performed. The polishing pressure was set to 200 g / cm², and the interface temperature was controlled in the range of 28°C to 38°C.

[0029] Guided by the distribution of tungsten nanoparticles, the gallium-indium alloy system undergoes a structural condensation process along the potential gradient direction, forming no fewer than 100 fractured island-like structural blocks with unconnected boundaries, each block having a size controlled between 0.3 micrometers and 1.8 micrometers.

[0030] Step S3, Formation of the pattern structure layer:

[0031] Silicon nitride powder, lithium borate, potassium titanate and lead borosilicate glass flux are mixed evenly, and the particle size of the resulting mixture is controlled to D90≤300 nanometers using a spray drying process.

[0032] The dried material is subjected to a molding process and sintered at 1400°C for 4 hours to generate a structural layer.

[0033] Mechanical polishing is performed on the surface of the sintered structural layer to achieve a surface roughness Ra of no more than 2 nanometers.

[0034] Reactive ion etching is used to perform pattern coding on the surface area of ​​the structural layer. The etching parameters are set to a period of 300 nanometers and a depth of 50 nanometers to form a fixed coded pattern structure.

[0035] Step S4, Structural Integration and Interface Sealing:

[0036] The pattern structure layer with completed pattern etching is stacked face-to-face with the double-layer structure containing the interface buffer film.

[0037] An interface plasma cleaning operation was performed in a nitrogen atmosphere, followed by a hot-press sealing operation with the following parameters: temperature 85°C, pressure 100 g / cm², and duration 120 seconds.

[0038] A 3-fluoropropyltriethoxysilane coupling agent was introduced into the interlayer. The amount of coupling agent used was 0.6 parts. The coupling agent participated in the interfacial reaction during the hot pressing process to construct a bonded bridge chain structure.

[0039] After the three-layer integrated structure is formed, surface integrity testing is performed to ensure that there is no separation or delamination between the main conductive layer, the interface buffer film and the pattern structure layer.

[0040] In a preferred embodiment, in the polishing-induced condensation treatment in step S2, a polishing lubricant consisting of 0.2 parts of fluorosilicone oil and 1.5 parts of glycerol ether is introduced into the liquid-phase mixing system, and the lubricant is continuously applied for 90 seconds at a bidirectional linear polishing frequency of 60 times per minute under temperature control of 28°C to 38°C, inducing gallium-indium alloy to preferentially deposit in the tungsten nanoparticle distribution area and forming island-like structural blocks with a boundary fracture rate of not less than 85%.

[0041] In a preferred embodiment, during the mechanical polishing in step S3, a mirror polishing slurry composed of 0.02-micron cerium oxide and ammonium borate in a mass ratio of 10:1 is applied to the surface of the sintered pattern structure layer. Three cycles of mechanical polishing are continuously performed at a pressure of 120 g / cm² and a circular reciprocating trajectory of 90 times / min. In the last cycle, 0.3 parts of aminosilane solution are introduced as a critical buffer to induce the formation of a passivation layer on the glass phase surface, thereby controlling Ra within the range of 1.5-2 nanometers.

[0042] The technical effects and advantages of this invention are as follows:

[0043] This solution constructs an interface fracture island structure formed by a low-melting-point liquid alloy to achieve spatial separation of the potential coupling path between the main conductive layer and the pattern structure layer. This effectively cuts off the equipotential closed loop in the quasi-resonance state, thereby suppressing interference pattern flicker, phase shift and image defocus caused by electric field pulsation, and improving the operational stability of holographic elements in a highly integrated environment.

[0044] The interface buffer film forms multiple solid fracture island blocks with unconnected boundaries under polishing-induced condensation conditions. Its distribution density and regional isolation characteristics are controllable. At the physical level, it interrupts the lateral conductive extension of the main conductive layer, reduces the in-plane electrostatic resonance driving conditions, and realizes structural-level control over charge distribution and electric field disturbance paths.

[0045] The main conductive layer adopts a graphene oxide-silver nanowire dual-network conductive structure, in which the silver nanowires are dispersed in the coating phase formed by polyvinyl alcohol composite dispersant with a high aspect ratio. After hot pressing and composite, a continuous and uniform conductive channel is constructed, while maintaining a medium surface resistance range to effectively control the electrostatic accumulation rate.

[0046] The introduction of tungsten nanoparticles into the interface buffer film enables spatial selectivity of the direction of local charge induction. Furthermore, the asymmetry of the induced potential distribution is regulated by coating with fluorinated polytrifluoroethylene, thereby increasing the ratio of transverse discontinuities formed by fracture islands in the interface region and enhancing the integrity and uniformity of electric field blocking. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the process flow of the present invention. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Refer to the instruction manual appendix Figure 1 An embodiment of the present invention provides a dielectric-free holographic optical element based on grinding and polishing parameters, wherein the optical element comprises the following three layers in sequence:

[0050] The first layer is the main conductive layer, which is composed of the following components in the following mass ratios: 40 parts of reduced graphene oxide, 22 parts of silver nanowires, 12 parts of polyvinyl alcohol composite dispersant, 25 parts of deionized water, and 1 part of interface stabilizer.

[0051] The second layer is an interface buffer film, which is disposed between the main conductive layer and the patterned structure layer. It is composed of the following components in the following mass ratio: 80 parts gallium, 14 parts indium, 3 parts tin, 1 part tungsten nanoparticles, 1 part sodium acetate, and 1 part tributylphosphine.

[0052] The third layer is a patterned structure layer, composed of the following components in the following mass ratios: 80 parts silicon nitride powder, 10 parts lithium borate, 6 parts potassium titanate, and 4 parts lead borosilicate glass flux.

[0053] It should be noted that the main conductive layer formulation aims to construct a composite conductive network structure with high conductivity, good film-forming properties, and thermo-pressurization stability to meet the combined requirements of surface resistance, interface stability, and process adaptability for dielectric-free holographic optical elements. Reduced graphene oxide serves as the conductive framework, imparting high in-plane electron mobility and structural coverage, and is set at 40 parts to form continuous conductive channels. Silver nanowires are used to construct bridging channels, and at a ratio of 22 parts, they form a three-dimensional conductive complementary structure with graphene, enhancing interlayer conductivity while suppressing the risk of aggregation. Polyvinyl alcohol composite dispersant is set at 12 parts as the interface coating phase to stabilize the distribution of nanowires and provide a flexible interface buffer. Deionized water at 25 parts serves as a solvent to provide system homogeneity, facilitating the formation of a wet film structure with consistent thickness. Interface stabilizer at 1 part is used to regulate the charge distribution of graphene and the rheological boundary of the film formation, enhancing the interfacial coupling stability with the subsequent buffer film. The overall formulation forms a synergistic system of a dual-scale conductive network and a flexible coating phase, ensuring that the main conductive layer has stable conductivity and interface structural integrity.

[0054] The formulation of the interface buffer film is based on gallium as the main phase component, providing a liquid matrix in a ratio of 80 parts. This allows for controlled flow near room temperature, which is beneficial for the subsequent polishing-induced condensation fracture process. Indium and tin are in 14 and 3 parts respectively, forming a low-melting-point alloy system with gallium. Its eutectic structure has a clear solid-liquid phase transition temperature range, enabling the formation of boundary-stable structural migration paths under thermal disturbance conditions and ensuring that interface remelting and re-adhesion do not occur in the fracture area. Tungsten nanoparticles (1 part) possess high density and high potential gradient induction ability, serving as charge-guided micro-regions during the polishing stage. The system forms structural induction sites, which guide the distribution of fracture islands induced by non-uniform electric fields. Sodium acetate and tributylphosphine each account for 1 part. The former participates in regulating the initial diffusion rate and crystallization trend of each element in the metal system, while the latter acts as a dynamic inhibitor of metal-oxygen interface reaction, delaying the local alloy precipitation process and ensuring that the formation time and regional distribution of fracture areas are controllable. In terms of the part ratio setting, this component system constructs a buffer structure with both condensation-induced fracture and interface insulation isolation capabilities, avoiding the coupling disturbance problem caused by equipotential field resonance between the main conductive layer and the pattern structure layer.

[0055] In the formulation design of the pattern structure layer, silicon nitride powder, as the main structural component, constitutes the main framework at 80 parts. It possesses high mechanical strength, a low coefficient of thermal expansion, and good plasma etching responsiveness, maintaining the integrity of the pattern boundaries during subsequent reactive ion etching. Lithium borate, as a structure-regulating phase, is allocated at 10 parts to control the low-temperature sintering behavior of the ceramic system and introduce a microcrystalline transition region, improving the homogeneity and forming accuracy of the etched surface layer. Potassium titanate, at 6 parts, increases the surface polarizability of the material, contributing to the construction of a stable optical phase distribution after etching. Lead borosilicate glass flux, at 4 parts, promotes interfacial wettability and bonding between silicon nitride powder and auxiliary components during sintering, ensuring uniform sintering density, absence of significant porosity, and the formation of an optical coding surface with Ra less than 2 nanometers. This formulation structure maintains stable closure in four dimensions: material system, sintering behavior, etching adaptability, and interfacial compatibility, making it suitable for the construction of subwavelength periodic structures.

[0056] The main conductive layer is bonded together by homogenization and hot pressing to form a continuous conductive film layer, and the surface resistance of the main conductive layer is controlled within the range of 120 to 180 ohms per square meter.

[0057] The interface buffer film is induced to condense by terminal polishing, forming multiple unconnected fractured island-shaped structural blocks. The boundaries of the fractured island-shaped structural blocks are discontinuously distributed, which is used to cut off the equipotential coupling between the main conductive layer and the underlying pattern structure.

[0058] The pattern structure layer is spray-dried and sintered to form a subwavelength pattern encoding substrate. The substrate has a pattern cross-section with Ra≤2nm and is formed into a periodic structure by ion beam etching.

[0059] It should be noted that the construction process of the main conductive layer achieves functional zoning and interface coupling control through the continuous process linkage of the three-layer material system. In the construction of the main conductive layer, an initial wet film is formed by homogenization, and the conductive network is densified and the structure is solidified by the hot pressing composite process. Its surface resistance is stably controlled within the range of 120 to 180 ohms per square meter to ensure that the optical element has the function of conducting electricity without introducing charge retention or lateral coupling interference.

[0060] Based on this, the interface buffer film is condensed by terminal polishing induction, so that the liquid alloy system is transformed into multiple unconnected fractured island-like structural blocks under the action of polishing force field. The boundaries of the islands are discontinuous, which can effectively destroy the equipotential closed path that may be formed between the upper and lower structures and block the electric field coupling induced by high frequency resonance.

[0061] The pattern structure layer forms a compact with controllable particle size during the spray drying stage, and obtains an optical coding surface with low surface roughness after sintering. A stable periodic structure is formed through subsequent ion beam etching, realizing high-precision loading of subwavelength pattern information.

[0062] Throughout the entire structural construction process, the functional parameters and interface behaviors of each layer have been interlocked and performance separated through pre-process settings to ensure the stability of the holographic response and the anti-interference capability of the system operation.

[0063] The silver nanowires are dispersed in the main conductive layer in a coating phase formed by a polyvinyl alcohol composite dispersant. The silver nanowires have a diameter of 40 nanometers and a length of 30 micrometers. The overall silver content of the silver nanowires accounts for 22 parts of the total mass of the main conductive layer. The nanowires are prepared by in-situ silver formate reduction method to ensure dispersion uniformity and continuity of the conductive path.

[0064] It should be noted that by dispersing silver nanowires in a coating phase formed by a polyvinyl alcohol composite dispersant, a stable conductive network is constructed, ensuring that the nanowires are uniformly distributed in the main conductive layer and form an effective bridging structure. The diameter of the silver nanowires is set to 40 nanometers and the length to 30 micrometers, which is beneficial for crossing the lateral gaps between graphene oxide sheets and improving the overall conductivity continuity. The silver content is set to 22 parts, which is a limit design to maximize conductivity without causing agglomeration and interfacial short circuit risks. The silver nanowires are prepared by the in-situ silver formate reduction method, which can achieve simultaneous reduction and embedding in the dispersion system, avoid subsequent agglomeration and sol precipitation, and ensure the integrity of the conductive path structure.

[0065] During the formation of the interface buffer film, by controlling the interface polishing temperature between 28°C and 38°C, the gallium-indium alloy system preferentially grows along the tungsten nanoparticle-induced region under charge-driven conditions, forming no less than 100 fractured island-like structural blocks per unit area, with the block size ranging from 0.3 to 1.8 micrometers.

[0066] It should be noted that by controlling the interface polishing temperature within the range of 28°C to 38°C, the low-melting-point alloy system of gallium and indium is ensured to maintain moderate fluidity under limited thermal disturbance conditions, and preferentially grows along the tungsten nanoparticle-induced region under the action of charge, forming a controlled solidification path. This induction mechanism causes the liquid phase alloy to undergo directional fracture under the local potential gradient, ultimately constructing no less than 100 boundary-disconnected island-like structural blocks with a size of 0.3 to 1.8 micrometers per unit area, which are used to achieve effective separation and coupling blockage of the potential paths between the upper and lower layers.

[0067] The tungsten nanoparticles are coated with 0.3 parts of fluorinated polytrifluoroethylene to guide the potential distribution in the gallium-indium alloy system to form an asymmetry, thereby increasing the lateral discontinuity ratio of the fracture island region and enhancing the effectiveness of the blocking path.

[0068] It should be noted that by coating 0.3 parts of fluorinated polytrifluoroethylene on the surface of tungsten nanoparticles, a stable potential interference layer is constructed. The difference between its insulation and electronegativity is used to guide the non-uniform distribution of the local electric field during the alloy solidification process. This asymmetric potential drives the alloy to form a transversely discontinuous solidification boundary at the interface, thereby increasing the separation density between fracture islands, ensuring the formation of a multi-path potential blocking region inside the buffer film, and improving the stability and spatial coverage of the overall blocking effect.

[0069] Before etching, the silicon nitride powder is spray-dried to control its particle size to D90≤300 nm. Then, it is ion-beam etched to form a pattern coding structure with a period of 300 nm and a depth of 50 nm on the surface, and maintains the integrity of the optical interference phase under the action of the fracture island region.

[0070] It should be noted that by performing spray drying on the silicon nitride powder before etching, the particle size is controlled within the range of D90≤300 nm, ensuring that the substrate formed after sintering has a uniform and dense surface morphology, which is conducive to maintaining pattern accuracy. Secondly, a pattern coding structure with a period of 300 nm and a depth of 50 nm is constructed on the surface by reactive ion etching to achieve subwavelength-level phase modulation function. After the pattern structure layer is formed, it works together with the fracture island region below to maintain the spatial stability of the interference path and avoid phase shift caused by interface potential disturbance.

[0071] The main conductive layer and the interface buffer film are bonded to each other by a silane coupling agent, which is 3-fluoropropyltriethoxysilane and is used in an amount of 0.6 parts. This is used to improve interlayer adhesion and prevent the risk of delamination during the subsequent holographic pattern forming process.

[0072] It should be noted that 0.6 parts of 3-fluoropropyltriethoxysilane are introduced between the main conductive layer and the interface buffer film as a silane coupling agent. Through its end groups, it forms a covalent anchor with the surfaces of the two materials, constructing a stable interfacial bonding network. Under hot-pressing conditions, this coupling agent can simultaneously react with the graphene composite system and the metal buffer material to form a continuous bridge chain structure, improve interlayer adhesion, and suppress the risk of delamination or desorption caused by stress mismatch due to subsequent heat treatment or ion etching.

[0073] The fabrication process of dielectric-free holographic optical elements based on grinding and polishing parameters includes:

[0074] Step S1, Preparation of the main conductive layer:

[0075] Reduced graphene oxide, silver nanowires, polyvinyl alcohol composite dispersant, deionized water and interface stabilizer were sequentially added to a stirring container, and mechanical stirring and ultrasonic dispersion were combined until a stable and uniform dispersion was formed.

[0076] The dispersion was distributed on the carrier configuration plane using a spin coating process, and a conductive film layer was constructed by hot pressing. The hot pressing temperature was set to 80°C and the hot pressing duration was 90 seconds.

[0077] The formed conductive film layer was tested using a four-probe test method, and the output surface resistance value was limited to between 120 ohms per square and 180 ohms per square.

[0078] Step S2, Construction of the interface buffer membrane:

[0079] Gallium, indium, tin, tungsten nanoparticles, sodium acetate, and tributylphosphine were mixed sequentially according to a preset mass ratio, and a multi-component liquid-phase mixture was generated by a low-temperature hot-melting method; wherein the temperature of the low-temperature hot-melting method was controlled between 40°C and 55°C.

[0080] The obtained liquid phase mixture was spread evenly on the surface of the main conductive layer using a blade scraping method, and then polishing-induced condensation treatment was immediately performed. The polishing pressure was set to 200 g / cm², and the interface temperature was controlled in the range of 28°C to 38°C.

[0081] Guided by the distribution of tungsten nanoparticles, the gallium-indium alloy system undergoes a structural condensation process along the potential gradient direction, forming no fewer than 100 fractured island-like structural blocks with unconnected boundaries, each block having a size controlled between 0.3 micrometers and 1.8 micrometers.

[0082] Step S3, Formation of the pattern structure layer:

[0083] Silicon nitride powder, lithium borate, potassium titanate and lead borosilicate glass flux are mixed evenly, and the particle size of the resulting mixture is controlled to D90≤300 nanometers using a spray drying process.

[0084] The dried material is subjected to a molding process and sintered at 1400°C for 4 hours to generate a structural layer.

[0085] Mechanical polishing is performed on the surface of the sintered structural layer to achieve a surface roughness Ra of no more than 2 nanometers.

[0086] Reactive ion etching is used to perform pattern coding on the surface area of ​​the structural layer. The etching parameters are set to a period of 300 nanometers and a depth of 50 nanometers to form a fixed coded pattern structure.

[0087] Step S4, Structural Integration and Interface Sealing:

[0088] The pattern structure layer with completed pattern etching is stacked face-to-face with the double-layer structure containing the interface buffer film.

[0089] An interface plasma cleaning operation was performed in a nitrogen atmosphere, followed by a hot-press sealing operation with the following parameters: temperature 85°C, pressure 100 g / cm², and duration 120 seconds.

[0090] A 3-fluoropropyltriethoxysilane coupling agent was introduced into the interlayer. The amount of coupling agent used was 0.6 parts. The coupling agent participated in the interfacial reaction during the hot pressing process to construct a bonded bridge chain structure.

[0091] After the three-layer integrated structure is formed, surface integrity testing is performed to ensure that there is no separation or delamination between the main conductive layer, the interface buffer film and the pattern structure layer.

[0092] Furthermore, in the polishing-induced condensation treatment in step S2, a polishing lubricant consisting of 0.2 parts of fluorosilicone oil and 1.5 parts of glycerol ether is introduced into the liquid-phase mixing system. Under the temperature control of 28°C to 38°C, the lubricant is continuously applied at a bidirectional linear scraping frequency of 60 times per minute for 90 seconds to induce the preferential deposition of gallium-indium alloy in the tungsten nanoparticle distribution area and form island-shaped structural blocks with a boundary fracture rate of not less than 85%.

[0093] Furthermore, in the mechanical polishing step S3, a mirror polishing slurry composed of 0.02-micron cerium oxide and ammonium borate in a mass ratio of 10:1 is applied to the surface of the sintered pattern structure layer. Three cycles of mechanical polishing are continuously performed at a pressure of 120 g / cm² and a circular reciprocating trajectory of 90 times / minute. In the last cycle, 0.3 parts of aminosilane solution are introduced as a critical buffer to induce the formation of a passivation layer on the glass phase surface, thereby controlling Ra within the range of 1.5-2 nanometers.

[0094] Table 1: Influence of Interface Buffer Film Structure on Conductive Layer Performance

[0095]

[0096] Table 2: Influence of fracture island structure density on phase stability of pattern layers

[0097]

[0098] Table 3 Control Table for Grinding-Induced Fracture Structure

[0099]

[0100] Table 4 Stability of Grinding and Polishing Mirror Surface

[0101]

[0102] Regarding Table 1, it should be noted that the five sets of samples corresponding to the same embodiment were built on the main conductive layer under different interface buffer film structure control conditions. The "unbuilt" state does not introduce any fracture film structure, and the conductive layer is directly exposed to the cross-border potential. The "island structure" series is based on the microscale fracture behavior of low melting point alloys in the condensation-shear composite field. The fracture structure density is gradually controlled by three variables: polishing pressure, temperature control range, and induced particle distribution. The formation of fracture islands achieves spatial separation of transverse potential at the microscale, which causes quantifiable intervention in the charge conduction path, thereby affecting the overall resistance continuity and surface stability.

[0103] The density and distribution of the island-like structures are not theoretically derived or set values, but are directly measured sample by sample through scanning electron microscopy imaging combined with statistical algorithms. The changes in the tomography rate also correspond to the actual image presented by the integrity of the conductive signal in the conductive atomic force scanning area. This mode of mapping the differences in the microscopic state of the structure to the macroscopic electrical response makes the changes in the resistance value and the tomography rate between samples show a regular bivariate decreasing trend, without any abrupt changes or anomalous distributions. Especially under high density and coating control conditions, the spatial uniformity of the fracture islands is enhanced, which further decouples the conductive path and significantly shrinks the potential disturbance region. This structural state itself determines the synchronous decrease of the resistance and tomography rate indicators.

[0104] Therefore, each set of data from A1 to A5 in this table is not an isolated sample formed under discrete experimental conditions, but a system response result obtained under a set of experimental logic with continuous control variables and traceable formation mechanism; the influence of different interface buffer film states on the performance of conductive layer shows a closed correspondence between structural parameters, microscopic response and electrical performance, rather than an isolated distribution of results.

[0105] It should be noted that the data in Table 2 focuses on the correspondence between the density change of the fracture island structure and the interference phase response of the pattern structure layer; the fracture island is a micro-region solidification product during the condensation process of the interface buffer film, and its density is controlled by the combined effects of physical parameters such as polishing pressure, charge-induced configuration, and condensation rate of the alloy system.

[0106] During the structure formation process, the distribution of the number of fracture islands per unit area directly determines the electric field perturbation path configuration of the interface layer on the upper pattern structure, which in turn affects the spatial consistency of the optical interference phase after pattern etching. In the experiment, by systematically adjusting the induction factor, the formation density of fracture islands was gradually increased while maintaining the film thickness, etching depth, and encoding period. The corresponding pattern response was then quantitatively acquired.

[0107] Phase shift was measured using interferometry to assess the optical response of the etched pattern layer. The phase shift value per unit area was determined by comparing it with a theoretical reference phase. Distortion area was calculated based on the spatial error integral after image reconstruction, reflecting the spatial misalignment range of the coded pattern after disturbance in the interferometric path. As the density of fracture islands increased from 60 islands / μm... 2 Gradually increase to 180 / μm 2 The phase shift decreased from 0.28 rad to 0.12 rad, and the distortion area decreased from 8.1% to 2.4% simultaneously. This trend reflects the gradual enhancement of the interface fracture structure's ability to shield potential interference, enabling continuous improvement in the upper layer pattern in terms of etching accuracy and optical path integrity.

[0108] More importantly, this set of data is not an isolated sample comparison, but a structure-response sequence based on the same material system, unified construction process, and progressive variable conditions. The density distribution and spatial uniformity of the fracture islands not only affect the interfacial electrical properties, but also transmit stress, potential and interference offset signals to the upper optical structure through the mediating mechanism of charge field interference. Therefore, the phase response and pattern distortion changes have a clear structural causal chain. The data in the table show a reasonable and continuous decreasing relationship, which is a true reflection of the coupling behavior between structural variables and optical output.

[0109] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dielectric-free holographic optical element based on grinding and polishing parameters, characterized in that, The optical element comprises the following three layers in sequence: The first layer is the main conductive layer, which is composed of the following components in the following mass ratios: 40 parts of reduced graphene oxide, 22 parts of silver nanowires, 12 parts of polyvinyl alcohol composite dispersant, 25 parts of deionized water, and 1 part of interface stabilizer. The second layer is an interface buffer film, which is disposed between the main conductive layer and the patterned structure layer. It is composed of the following components in the following mass ratio: 80 parts gallium, 14 parts indium, 3 parts tin, 1 part tungsten nanoparticles, 1 part sodium acetate, and 1 part tributylphosphine. The third layer is a patterned structure layer, composed of the following components in the following mass ratios: 80 parts silicon nitride powder, 10 parts lithium borate, 6 parts potassium titanate, and 4 parts lead borosilicate glass flux. The main conductive layer is bonded together by homogenization and hot pressing to form a continuous conductive film layer, and the surface resistance of the main conductive layer is controlled within the range of 120 to 180 ohms per square meter. The interface buffer film is induced to condense by terminal polishing, forming multiple unconnected fractured island-shaped structural blocks. The boundaries of the fractured island-shaped structural blocks are discontinuously distributed, which is used to cut off the equipotential coupling between the main conductive layer and the underlying pattern structure. The pattern structure layer is spray-dried and sintered to form a subwavelength pattern coding substrate. The substrate has a pattern cross-section with a roughness Ra≤2nm, and a periodic structure is formed by ion beam etching.

2. The dielectric-free holographic optical element based on grinding and polishing parameters according to claim 1, characterized in that: The silver nanowires are dispersed in the main conductive layer in a coating phase formed by a polyvinyl alcohol composite dispersant. The silver nanowires have a diameter of 40 nanometers and a length of 30 micrometers. The overall silver content of the silver nanowires accounts for 22 parts of the total mass of the main conductive layer.

3. The dielectric-free holographic optical element based on grinding and polishing parameters according to claim 1, characterized in that: During the formation of the interface buffer film, the interface polishing temperature is controlled between 28°C and 38°C, so that the gallium-indium alloy system grows along the tungsten nanoparticle-induced region under charge drive, forming no less than 100 fractured island-like structural blocks per unit area, and the block size ranges from 0.3 to 1.8 micrometers.

4. The dielectric-free holographic optical element based on grinding and polishing parameters according to claim 1, characterized in that: The tungsten nanoparticles are coated with 0.3 parts of fluorinated polytrifluoroethylene to guide the formation of asymmetry in the potential distribution of the gallium-indium alloy system.

5. The dielectric-free holographic optical element based on grinding and polishing parameters according to claim 1, characterized in that: Before etching, the silicon nitride powder is spray-dried to control its particle size to D90≤300 nm, and then ion-beam etched to form a pattern coding structure with a period of 300 nm and a depth of 50 nm on the surface.

6. The dielectric-free holographic optical element based on grinding and polishing parameters according to claim 1, characterized in that: The main conductive layer and the interface buffer film are bonded to each other by a silane coupling agent, which is 3-fluoropropyltriethoxysilane and is used in an amount of 0.6 parts.

7. A dielectric-free holographic optical element fabrication process based on grinding and polishing parameters, characterized in that, include: Step S1, Preparation of the main conductive layer: Reduced graphene oxide, silver nanowires, polyvinyl alcohol composite dispersant, deionized water and interface stabilizer were sequentially added to a stirring container, and mechanical stirring and ultrasonic dispersion were combined until a stable and uniform dispersion was formed. The dispersion was distributed on the carrier configuration plane using a spin coating process, and a conductive film layer was constructed by hot pressing. The hot pressing temperature was set to 80°C and the hot pressing duration was 90 seconds. The formed conductive film layer was tested using a four-probe test method, and the output surface resistance value was limited to between 120 ohms per square and 180 ohms per square. Step S2, Construction of the interface buffer membrane: Gallium, indium, tin, tungsten nanoparticles, sodium acetate, and tributylphosphine were mixed sequentially according to a preset mass ratio, and a multi-component liquid-phase mixture was generated by hot melting. The obtained liquid phase mixture was spread evenly on the surface of the main conductive layer using a blade scraping method, followed by polishing-induced condensation treatment. The polishing pressure was set to 200 g / cm², and the interface temperature was controlled in the range of 28°C to 38°C. Guided by the distribution of tungsten nanoparticles, the gallium-indium alloy system undergoes a structural condensation process along the potential gradient direction, forming no fewer than 100 fractured island-like structural blocks with unconnected boundaries, each block having a size controlled between 0.3 micrometers and 1.8 micrometers. Step S3, Formation of the pattern structure layer: Silicon nitride powder, lithium borate, potassium titanate and lead borosilicate glass flux are mixed and the particle size of the resulting mixture is controlled to D90≤300 nanometers using a spray drying process. The dried material is subjected to a molding process and sintered at 1400°C for 4 hours to generate a structural layer. Mechanical polishing is performed on the surface of the sintered structural layer to achieve a surface roughness Ra of no more than 2 nanometers. Reactive ion etching is used to perform pattern coding on the surface area of ​​the structural layer. The etching parameters are set to a period of 300 nanometers and a depth of 50 nanometers to form a fixed coded pattern structure. Step S4, Structural Integration and Interface Sealing: The pattern structure layer with completed pattern etching is stacked face-to-face with the double-layer structure containing the interface buffer film. An interface plasma cleaning operation was performed in a nitrogen atmosphere, followed by a hot-press sealing operation with the following parameters: temperature 85°C, pressure 100 g / cm², and duration 120 seconds. A 3-fluoropropyltriethoxysilane coupling agent was introduced into the interlayer at a dosage of 0.6 parts. The coupling agent participated in the interfacial reaction during hot pressing to construct a bonded bridge chain structure.

8. The dielectric-free holographic optical element fabrication process based on grinding and polishing parameters according to claim 7, characterized in that: In the polishing-induced condensation treatment in step S2, a polishing lubricant consisting of 0.2 parts of fluorosilicone oil and 1.5 parts of glycerol ether is introduced into the liquid-phase mixture. Under the temperature control of 28°C to 38°C, the lubricant is continuously applied at a bidirectional linear scraping frequency of 60 times per minute for 90 seconds to induce the preferential deposition of gallium-indium alloy in the tungsten nanoparticle distribution area and form island-shaped structural blocks with a boundary fracture rate of not less than 85%.

9. The dielectric-free holographic optical element fabrication process based on grinding and polishing parameters according to claim 8, characterized in that: In the mechanical polishing step S3, a mirror polishing slurry composed of 0.02-micron cerium oxide and ammonium borate in a mass ratio of 10:1 is applied to the surface of the sintered pattern structure layer. Three cycles of mechanical polishing are continuously performed at a pressure of 120 g / cm² and a circular reciprocating trajectory of 90 times / minute. In the last cycle, 0.3 parts of aminosilane solution are introduced as a critical buffer to induce the formation of a passivation layer on the glass phase surface, thereby controlling the roughness Ra within the range of 1.5-2 nanometers.

Images