A method, device and electronic equipment for overall temperature control of DDR memory and SOC chip

Abstract

The application belongs to the field of high-integration SOC chips, and discloses a method and device for overall temperature control of DDR memory and an SOC chip and electronic equipment, comprising: obtaining a mapping relationship table of DDR grain refresh rate and temperature generated in advance; calling the DDR controller of the SOC chip through the DDR driver to obtain the current DDR grain refresh rate; determining the temperature corresponding to the current DDR grain refresh rate as the first temperature of the DDR memory based on the mapping relationship between the DDR grain refresh rate and the temperature in the mapping relationship table; obtaining the second temperature of the SOC chip from the temperature sensor in the SOC chip; determining the temperature control strategy to be taken based on the first temperature and the second temperature, and performing the overall temperature control operation of the DDR memory and the SOC chip according to the temperature control strategy. The application effectively reduces the overall temperature of the DDR memory and the SOC chip, and further reduces the overall power consumption of the DDR memory and the SOC chip.

Description

Technical Field

[0001] This invention belongs to the field of high-integration SOC chip technology, and specifically relates to a method, device and electronic equipment for overall temperature control of DDR memory and SOC chip. Background Technology

[0002] Highly integrated System-on-Chip (SoC) chips are the brains of various types of smart devices, from smartphones and wearable devices to smart medical devices and self-driving cars; SoC chips are ubiquitous. SoC chip designs incorporate embedded temperature sensors to monitor and control the chip's temperature, ensuring a balance between performance, power consumption, and temperature.

[0003] In the process of developing this invention, the inventors discovered that in various electronic devices with size constraints, such as terminals and watches, a System-on-a-Chip (SoC) chip and DDR memory (Double Data Rate Dynamic Random Access Memory) may be packaged together. However, both the SoC chip and DDR memory are power-consuming devices that generate a large amount of heat during operation, causing the temperature of both components to rise. This results in higher power consumption for both the SoC chip and DDR memory, and the increased temperature also affects their performance. Therefore, there is an urgent need to provide a method for overall temperature control of the DDR memory and the SoC chip. Summary of the Invention

[0004] The purpose of this invention is to regulate the overall temperature of DDR memory and the SOC chip. This allows for the inverse calculation of DDR memory temperature information using the temperature-dependent refresh rate of the DDR chip itself, without the need for additional temperature sensors on the DDR chip. This effectively reduces the overall temperature of the DDR memory and the SOC chip, thereby reducing their overall power consumption.

[0005] In a first aspect, embodiments of the present invention provide a method for overall temperature control of DDR memory and a SOC chip, applied to an electronic device in which DDR memory and a SOC chip are spatially integrated and packaged, wherein the SOC chip includes a DDR controller, and the method includes:

[0006] Obtain a pre-generated mapping table between DDR chip refresh rate and temperature. The process of establishing the mapping table includes: testing the DDR memory in a temperature-controlled environment, recording the actual refresh rate of the DDR chip at different temperatures, and forming a mapping relationship between the DDR chip refresh rate and the corresponding temperature.

[0007] The DDR driver calls the DDR controller of the SOC chip to obtain the current DDR chip refresh rate;

[0008] Based on the mapping relationship between DDR chip refresh rate and temperature in the mapping table, the temperature corresponding to the current DDR chip refresh rate is determined as the first temperature of the DDR memory;

[0009] The second temperature of the SOC chip is obtained from the temperature sensor in the SOC chip;

[0010] Based on the first temperature and the second temperature, a temperature control strategy to be adopted is determined, and the overall temperature control operation of the DDR memory and SOC chip is executed according to the temperature control strategy.

[0011] Optionally, determining the appropriate temperature control strategy based on the first and second temperatures, and executing the overall temperature control operation of the DDR memory and SOC chip according to the temperature control strategy, includes:

[0012] If the sum of the first temperature and the second temperature is greater than the first temperature threshold, a first temperature control command is sent to the internal components of the SOC chip. The first temperature control command is used to instruct the highest frequency of the internal components to be limited to less than the first frequency threshold, or to instruct the internal components to perform a core removal operation.

[0013] The DDR driver calls the DDR controller of the SOC chip to send a second temperature control command to the DDR memory. The second temperature control command is used to control the maximum frequency of the DDR memory to be less than a second frequency threshold.

[0014] Optionally, the method further includes:

[0015] Every preset time interval, the DDR driver calls the DDR controller of the SOC chip to obtain the DDR chip refresh rate again;

[0016] Based on the mapping relationship between DDR chip refresh rate and temperature in the mapping table, the temperature corresponding to the newly obtained DDR chip refresh rate is determined as the third temperature of the DDR memory.

[0017] The fourth temperature of the SOC chip is obtained from the temperature sensor in the SOC chip, and it is determined whether the sum of the third temperature and the fourth temperature is less than the target temperature.

[0018] If the sum of the third temperature and the fourth temperature is greater than the target temperature, a third temperature control instruction is sent to the internal components of the SOC chip, and the DDR controller of the SOC chip is called through the DDR driver to send a fourth temperature control instruction to the DDR memory until the sum of the third temperature and the fourth temperature is lower than the target temperature.

[0019] Optionally, determining the appropriate temperature control strategy based on the first and second temperatures, and executing the overall temperature control operation of the DDR memory and SOC chip according to the temperature control strategy, includes:

[0020] If the second temperature of the SOC chip is less than the second temperature threshold, but the first temperature of the DDR memory is higher than the third temperature threshold, a temperature reduction request actively sent by the DDR driver is received, wherein the second temperature threshold is less than the third temperature threshold.

[0021] In response to the temperature reduction request, the DDR controller of the SOC chip is invoked through the DDR driver to send a fifth temperature control instruction to the DDR memory. The fifth temperature control instruction is used to control the maximum frequency of the DDR memory to be less than the third frequency threshold.

[0022] Optionally, the method further includes:

[0023] Determine the current performance mode of the DDR memory;

[0024] If the current performance mode is benchmark mode, stop sending temperature control commands to the DDR controller.

[0025] Optionally, testing the DDR memory in a temperature-controlled environment and recording the actual refresh rate of the DDR chips at different temperatures to form a mapping relationship between the DDR chip refresh rate and the corresponding temperature includes:

[0026] In a temperature-controlled environment, the temperature of the DDR memory is adjusted multiple times according to a preset adjustment step size. Each time the temperature of the DDR memory is adjusted, the actual temperature of the DDR memory is measured through a temperature chamber, and the actual refresh rate of the DDR chip is obtained.

[0027] A mapping relationship is established between each actual temperature and the corresponding actual refresh rate to obtain a mapping table of DDR chip refresh rate and temperature.

[0028] Optionally, temperature sensors are pre-embedded at different locations in the SOC chip;

[0029] The step of obtaining the second temperature of the SOC chip from the temperature sensor in the SOC chip includes:

[0030] The temperature at different locations on the SOC chip is obtained from temperature sensors embedded in different locations on the SOC chip.

[0031] The second temperature of the SOC chip is determined based on the temperature at different locations of the SOC chip.

[0032] Secondly, embodiments of the present invention provide a device for overall temperature control of DDR memory and SOC chip, applied to electronic devices that spatially integrate DDR memory and SOC chip into a single package, wherein the SOC chip includes a DDR controller, and the device is specifically used to perform the following steps:

[0033] Obtain a pre-generated mapping table between DDR chip refresh rate and temperature. The process of establishing the mapping table includes: testing the DDR memory in a temperature-controlled environment, recording the actual refresh rate of the DDR chip at different temperatures, and forming a mapping relationship between the DDR chip refresh rate and the corresponding temperature.

[0034] The DDR driver calls the DDR controller of the SOC chip to obtain the current DDR chip refresh rate;

[0035] Based on the mapping relationship between DDR chip refresh rate and temperature in the mapping table, the temperature corresponding to the current DDR chip refresh rate is determined as the first temperature of the DDR memory;

[0036] The second temperature of the SOC chip is obtained from the temperature sensor in the SOC chip;

[0037] Based on the first temperature and the second temperature, a temperature control strategy to be adopted is determined, and the overall temperature control operation of the DDR memory and SOC chip is executed according to the temperature control strategy.

[0038] Thirdly, embodiments of the present invention provide an electronic device that spatially integrates DDR memory and a SOC chip in a package. The SOC chip includes a DDR controller, and the SOC chip executes the following steps via temperature control:

[0039] Obtain a pre-generated mapping table between DDR chip refresh rate and temperature. The process of establishing the mapping table includes: testing the DDR memory in a temperature-controlled environment, recording the actual refresh rate of the DDR chip at different temperatures, and forming a mapping relationship between the DDR chip refresh rate and the corresponding temperature.

[0040] The DDR driver calls the DDR controller of the SOC chip to obtain the current DDR chip refresh rate;

[0041] Based on the mapping relationship between DDR chip refresh rate and temperature in the mapping table, the temperature corresponding to the current DDR chip refresh rate is determined as the first temperature of the DDR memory;

[0042] The second temperature of the SOC chip is obtained from the temperature sensor in the SOC chip;

[0043] Based on the first temperature and the second temperature, a temperature control strategy to be adopted is determined, and the overall temperature control operation of the DDR memory and SOC chip is executed according to the temperature control strategy.

[0044] Fourthly, embodiments of the present invention provide a computer-readable storage medium that, when instructions in the computer-readable storage medium are executed by a temperature control drive of a SOC chip, enables an electronic device to perform the method described in any of the first aspects.

[0045] The technical solution provided in this invention first tests the DDR memory in a temperature-controlled environment, records the actual refresh rate of the DDR chips at different temperatures, and forms a mapping relationship between the DDR chip refresh rate and the corresponding temperature to pre-generate a mapping relationship table between the DDR chip refresh rate and temperature; then, the DDR driver calls the DDR controller of the SOC chip to obtain the current DDR chip refresh rate; based on the mapping relationship table between the DDR chip refresh rate and temperature, the temperature of the current DDR memory corresponding to the current DDR chip refresh rate is determined; and the current temperature of the SOC chip can be obtained from the temperature sensor in the SOC chip; finally, the current temperature of the DDR memory and the current temperature of the SOC chip are treated as a whole to determine the temperature control strategy to be adopted, and the overall temperature control operation of the DDR memory and the SOC chip is executed according to the temperature control strategy.

[0046] By regulating the overall temperature of the DDR memory and SOC chip, the temperature information of the DDR memory can be inferred from the temperature-related refresh rate of the DDR chip itself, without adding an additional temperature sensor to the DDR chip. This allows for effective temperature control of the DDR memory and SOC chip, thereby reducing overall power consumption and improving overall performance. Attached Figure Description

[0047] Figure 1 A schematic diagram of an overall architecture provided for an embodiment of the present invention;

[0048] Figure 2 A flowchart illustrating a method for overall temperature control of DDR memory and SOC chip provided in an embodiment of the present invention;

[0049] Figure 3for Figure 2 A flowchart of one implementation of S250;

[0050] Figure 4 for Figure 2 A flowchart of another implementation of S250. Detailed Implementation

[0051] The present invention will be described in detail below through embodiments.

[0052] Highly integrated System-on-Chip (SoC) chips are the brains of various types of smart devices, from smartphones and wearable devices to smart medical devices and self-driving cars; SoC chips are ubiquitous. SoC chip designs incorporate embedded temperature sensors to monitor and control the chip's temperature, ensuring a balance between performance, power consumption, and temperature.

[0053] In the process of developing this invention, the inventors discovered that in various electronic devices with size constraints, such as mobile phones and watches, a System-on-a-Chip (SoC) chip and DDR memory (Double Data Rate SDRAM) may be packaged together. However, both the SoC chip and DDR memory are power-consuming devices that generate a significant amount of heat during operation. This leads to increased temperatures in both components, resulting in higher power consumption for both the SoC chip and DDR memory. Furthermore, the increased temperature negatively impacts the performance of both the SoC chip and DDR memory.

[0054] Furthermore, when the SOC chip and DDR memory are spatially close, heat will be transferred between them, affecting each other's operation. Current technology does not consider the temperature impact of DDR memory on the SOC chip, nor does it consider the temperature impact of the SOC chip on the DDR memory. If the DDR memory affects the temperature of the SOC chip, it will impact the performance of the SOC chip; conversely, if the SOC chip affects the temperature of the DDR memory, it will also impact the performance of the DDR memory. Therefore, there is an urgent need to provide a method for overall temperature control of both the DDR memory and the SOC chip, that is, to control the temperature of the SOC chip and DDR memory as a whole.

[0055] The method for overall temperature control of DDR memory and SOC chip provided in this embodiment of the invention can be applied to electronic devices that integrate DDR memory and SOC chip in space. In practical applications, SOC and LPDDR can be spatially bound into a whole by packaging technologies such as POP or SIP.

[0056] POP stands for Package on Package, which is a technology that allows SOC chips and DDR memory to be packaged separately but with overlapping packages. The SOC chip and DDR memory are connected via pins.

[0057] SIP stands for System in a Package, which means that the SOC chip and DDR memory are packaged together.

[0058] The overall temperature control method for DDR memory and SOC chip in this invention can be used in electronic devices such as watches or mobile phones.

[0059] The present invention provides a method for overall temperature control of DDR memory and SOC chip, the core of which is:

[0060] 1. Treat DDR memory as one of the heat sources and include it in the SOC chip temperature control strategy.

[0061] 2. Without adding an additional temperature sensor to the DDR chip, the temperature information of the DDR memory can be deduced from the temperature-related refresh rate of the DDR chip itself. Furthermore, the SOC chip includes a DDR controller, which can periodically read the DDR chip refresh rate and transmit it to the SOC chip's temperature control driver to execute corresponding temperature control strategies.

[0062] 3. The temperature control driver executes corresponding temperature control strategies, including but not limited to:

[0063] (1) When the overall temperature of the SOC chip and DDR memory is too high, in order to reduce the overall temperature of the SOC chip and DDR memory as soon as possible, a request to limit the maximum frequency of DDR memory is sent to the DDR controller simultaneously. This is done to reduce the temperature of DDR memory by reducing the frequency of DDR memory. In addition, the current DDR chip refresh rate can be monitored in real time. By mapping the DDR chip refresh rate to temperature information, the temperature corresponding to the current DDR chip refresh rate can be determined, thereby ensuring that the temperature of DDR memory drops to the expected range.

[0064] (2) When the temperature of the SOC chip is still within the tolerance range, that is, the temperature of the SOC does not exceed the temperature threshold, but the DDR memory is severely limited in performance or is close to being unable to work properly due to excessive temperature, the DDR memory can actively request the SOC chip to reduce its own temperature through temperature control strategy.

[0065] To ensure clarity, the overall technical solution of this invention will be described in detail below with reference to the overall architecture diagram.

[0066] like Figure 1The diagram shows how SOC chips and DDR content are spatially bound together as a whole using packaging technologies such as SIP or POP. In this case, it is necessary to include the temperature control of DDR memory within the scope of SOC chip temperature control.

[0067] from Figure 1 As can be seen, temperature sensors can be set at different locations on the SOC chip. These multiple temperature sensors can be named temperature sensor 0, temperature sensor 1, ..., temperature sensor n, respectively. The value of n can be determined according to the specific design of the SOC chip. This embodiment of the invention does not specifically limit the value of n, that is, it does not limit the number of temperature sensors in the SOC chip. The temperature sensor at each location is used to measure the temperature at that location.

[0068] from Figure 1 It can also be seen that the SOC chip also runs temperature control driver software. This temperature control driver software can obtain temperature information from n temperature sensors to obtain the temperature of the SOC chip, and decide whether to perform temperature control management on the CPU and other internal components of the SOC chip according to the temperature control strategy. The specific implementation of temperature control management can be to limit the frequency of the internal components of the SOC chip or control the internal components of the SOC chip to perform core removal operations, so as to balance the temperature, performance and power consumption of the entire SOC chip.

[0069] Furthermore, the SOC chip also includes a DDR driver and a DDR controller, with the DDR controller bidirectionally connected to the DDR memory. DDR memory is a volatile storage device, and to ensure data is not lost, it needs to periodically (e.g., at the microsecond level) refresh operations on its internal storage cells. The refresh cycle is affected by temperature. Moreover, when DDR memory spends more time on refresh operations, read and write operations are limited, leading to performance degradation. Therefore, temperature control management of DDR memory is particularly important.

[0070] Taking LPDDR5 as an example, according to the LPDDR5 JEDEC standard protocol, the MR4 bit [4:0] of the mode register in the DDR chip (the DDR chip is the core storage unit that constitutes DDR memory) is defined as follows: when the DDR memory is at a reasonable temperature, a 1X refresh cycle is used, that is, the DDR storage unit needs to be refreshed once every 3.9us.

[0071] When the DDR temperature rises to a certain level, a shorter refresh cycle is used to refresh the DDR memory cells to ensure data integrity. For example, a 0.5X refresh cycle is used, meaning the refresh cycle is halved, specifically 0.5 × 3.9µs = 1.95µs, which means the number of refreshes doubles. Even worse, when the DDR temperature rises to an unacceptable level, all read and write operations will be rejected, and the DDR chips will need to dedicate all their time to refreshing to ensure data integrity.

[0072] As described above, the DDR chip refresh rate is related to the DDR memory temperature, and the DDR memory temperature can be deduced from the DDR chip refresh rate.

[0073] The following will explain how to perform overall temperature control on DDR memory and the SOC chip. This can be broken down into the following steps:

[0074] The first step is to obtain a mapping table of DDR chip refresh rate and temperature based on actual measurements in a temperature-controlled environment, since the relationship between DDR chip refresh rate and temperature may differ for different suppliers and models of DDR memory. Specifically, DDR memory is tested in a temperature-controlled environment, and the actual refresh rate of the DDR chips at different temperatures is recorded to establish a mapping relationship between DDR chip refresh rate and corresponding temperature.

[0075] The second step involves the DDR driver periodically calling the DDR controller interface to obtain the refresh rate information of the DDR memory's mode register MR4, thus obtaining the current DDR chip refresh rate. Then, using the mapping table between the DDR chip refresh rate and temperature obtained in the first step, the driver obtains the current DDR temperature corresponding to the current DDR chip refresh rate and sends a temperature control request to the temperature control driver.

[0076] The third step involves the temperature control driver combining the current internal temperature of the SOC chip with the current DDR temperature information obtained in the second step to determine a unified temperature control strategy and then executing the temperature control strategy.

[0077] Temperature control strategies include, but are not limited to:

[0078] (1) When the overall temperature of the SOC chip and DDR memory is too high, in order to reduce the overall temperature as quickly as possible, while sending instructions to the SOC internal components to limit the maximum frequency and remove the core, instructions to limit the maximum frequency of the DDR memory are sent to the DDR driver. In addition, by periodically acquiring DDR temperature information, the temperature of the SOC chip and DDR memory is managed to be within the target temperature range.

[0079] (2) When the temperature of the SOC chip is still within the tolerance range, but the temperature of the DDR memory is too high, the performance is severely limited or it is close to being unable to work normally, the DDR driver actively executes the temperature control strategy to reduce the temperature of the DDR memory.

[0080] (3) In benchmark mode, the temperature limiting factors are temporarily disabled to ensure that DDR is in its highest performance state. That is, in benchmark mode, the temperature of DDR is temporarily not controlled. Among them, the "benchmark mode" of DDR (Double Data Rate) memory usually refers to adjusting the memory frequency, voltage and other parameters to achieve higher performance.

[0081] It is evident that by differentiating between various scenarios such as performance benchmarking mode or user mode, and by invoking temperature control strategies driven by temperature control, performance, temperature, and power consumption can be effectively balanced, and the user experience can be improved.

[0082] The technical solution provided in this invention first tests the DDR memory in a temperature-controlled environment, records the actual refresh rate of the DDR chips at different temperatures, and forms a mapping relationship between the DDR chip refresh rate and the corresponding temperature to pre-generate a mapping relationship table between the DDR chip refresh rate and temperature; then, the DDR driver calls the DDR controller of the SOC chip to obtain the current DDR chip refresh rate; based on the mapping relationship table between the DDR chip refresh rate and temperature, the temperature of the current DDR memory corresponding to the current DDR chip refresh rate is determined; and the current temperature of the SOC chip can be obtained from the temperature sensor in the SOC chip; finally, the current temperature of the DDR memory and the current temperature of the SOC chip are treated as a whole to determine the temperature control strategy to be adopted, and the overall temperature control operation of the DDR memory and the SOC chip is executed according to the temperature control strategy.

[0083] By regulating the overall temperature of DDR memory and SOC chip, the overall temperature of DDR memory and SOC chip can be effectively reduced, thereby reducing the overall power consumption of DDR memory and SOC chip and improving the overall performance of DDR memory and SOC chip.

[0084] After a detailed description of the overall technical solution of the embodiments of the present invention, the following is a detailed description of a method, apparatus and electronic device for overall temperature control of DDR memory and SOC chip provided by the embodiments of the present invention.

[0085] like Figure 2 As shown in the figure, an embodiment of the present invention provides a method for overall temperature control of DDR memory and SOC chip, applied to an electronic device in which DDR memory and SOC chip are spatially integrated and packaged. The SOC chip includes a DDR controller. The method includes:

[0086] S210, obtain the pre-generated mapping table of DDR chip refresh rate and temperature.

[0087] The process of establishing the mapping table includes: testing DDR memory in a temperature-controlled environment, recording the actual refresh rate of DDR chips at different temperatures, and forming a mapping relationship between the refresh rate of DDR chips and the corresponding temperature.

[0088] Because the relationship between DDR chip refresh rate and temperature may differ for different suppliers and models of DDR memory, a pre-generated mapping table of DDR chip refresh rate and temperature is needed to quickly deduce DDR memory issues based on the DDR chip refresh rate in subsequent steps. Furthermore, to accurately obtain this mapping table, DDR memory can be tested in a temperature-controlled environment, recording the actual refresh rate of the DDR chips at different temperatures, thus establishing the mapping relationship between DDR chip refresh rate and corresponding temperature.

[0089] As one implementation of this invention, testing DDR memory in a temperature-controlled environment and recording the actual refresh rate of DDR chips at different temperatures to form a mapping relationship between DDR chip refresh rate and corresponding temperature may include the following steps:

[0090] In a temperature-controlled environment, the temperature of the DDR memory was adjusted multiple times according to a preset adjustment step size. Each time the temperature of the DDR memory was adjusted, the actual temperature of the DDR memory was measured through a temperature chamber, and the actual refresh rate of the DDR chips was obtained.

[0091] A mapping relationship is established between each actual temperature and the corresponding actual refresh rate, resulting in a mapping table of DDR chip refresh rate and temperature.

[0092] In this embodiment, the preset adjustment step size can be determined according to the actual situation, for example, it can be 0.5 degrees Celsius or 1 degree Celsius. This embodiment of the invention does not specifically limit the preset adjustment step size. Each time the temperature of the DDR memory is adjusted, the actual temperature of the DDR memory is measured by a temperature chamber, and the refresh rate of the DDR chip at this time is recorded. This allows for an accurate mapping relationship table between the DDR chip refresh rate and the temperature of the DDR memory, which helps to quickly and accurately deduce the temperature of the DDR memory based on the DDR chip refresh rate in subsequent steps.

[0093] The S220 uses the DDR driver to call the DDR controller of the SOC chip to obtain the current DDR chip refresh rate.

[0094] S230 determines the temperature corresponding to the current DDR chip refresh rate based on the mapping relationship between DDR chip refresh rate and temperature in the mapping table, and uses it as the first temperature of the DDR memory.

[0095] Specifically, the DDR driver periodically calls the DDR controller interface to obtain the refresh rate information of the DDR memory's mode register MR4, that is, to obtain the current DDR chip refresh rate. Then, through the mapping table between the DDR chip refresh rate and temperature, it obtains the current DDR temperature corresponding to the current DDR chip refresh rate. For clarity, the current DDR temperature can be referred to as the first temperature of the DDR memory.

[0096] S240 obtains a second temperature of the SOC chip from a temperature sensor in the SOC chip.

[0097] In practical applications, temperature sensors are embedded in different locations within the SOC chip.

[0098] At this point, obtaining the second temperature of the SOC chip from the temperature sensor in the SOC chip can include the following steps:

[0099] Temperatures at different locations on the SOC chip are obtained from temperature sensors embedded in different positions on the SOC chip.

[0100] The second temperature of the SOC chip is determined based on the temperature at different locations on the SOC chip.

[0101] Specifically, the highest temperature among the temperatures at different locations can be used as the current temperature of the SOC chip. Alternatively, depending on the actual situation, the average temperature of multiple locations can be used as the current temperature of the SOC chip; both are reasonable. This embodiment of the invention does not specifically limit the specific implementation method for calculating the second temperature of the SOC chip based on the temperatures at different locations. For clarity, the current temperature of the SOC chip can be referred to as the second temperature of the SOC chip.

[0102] S250 determines the appropriate temperature control strategy based on the first and second temperatures, and performs overall temperature control operations on the DDR memory and SOC chip according to the temperature control strategy.

[0103] The temperature control driver combines the primary temperature of the DDR memory with the secondary temperature of the SOC chip to determine a unified temperature regulation strategy and execute it. This allows for overall temperature control of both the DDR memory and the SOC chip without requiring additional temperature sensors on the DDR chip.

[0104] The technical solution provided in this invention first tests the DDR memory in a temperature-controlled environment, records the actual refresh rate of the DDR chips at different temperatures, and forms a mapping relationship between the DDR chip refresh rate and the corresponding temperature to pre-generate a mapping relationship table between the DDR chip refresh rate and temperature; then, the DDR driver calls the DDR controller of the SOC chip to obtain the current DDR chip refresh rate; based on the mapping relationship table between the DDR chip refresh rate and temperature, the temperature of the current DDR memory corresponding to the current DDR chip refresh rate is determined; and the current temperature of the SOC chip can be obtained from the temperature sensor in the SOC chip; finally, the current temperature of the DDR memory and the current temperature of the SOC chip are treated as a whole to determine the temperature control strategy to be adopted, and the overall temperature control operation of the DDR memory and the SOC chip is executed according to the temperature control strategy.

[0105] By regulating the overall temperature of the DDR memory and SOC chip, the temperature information of the DDR memory can be inferred from the temperature-related refresh rate of the DDR chip itself, without adding an additional temperature sensor to the DDR chip. This allows for effective temperature control of the DDR memory and SOC chip, thereby reducing overall power consumption and improving overall performance.

[0106] exist Figure 2 Based on the illustrated embodiment, as one implementation of this invention, in step S250, a temperature control strategy to be adopted is determined based on the first temperature and the second temperature, and the overall temperature control operation of the DDR memory and the SOC chip is executed according to the temperature control strategy, such as... Figure 3 As shown, it may include the following steps:

[0107] S251a: If the sum of the first temperature and the second temperature is greater than the first temperature threshold, a first temperature control command is sent to the internal components of the SOC chip.

[0108] The first temperature control command is used to indicate that the highest frequency of the internal component is limited to less than a first frequency threshold, or to indicate that the internal component performs a core removal operation.

[0109] The S252a, through the DDR driver, calls the DDR controller of the SOC chip to send a second temperature control command to the DDR memory.

[0110] The second temperature control command is used to control the maximum frequency of DDR memory to be less than the second frequency threshold.

[0111] Specifically, if the sum of the first and second temperatures exceeds the first temperature threshold, indicating that the overall temperature of the SOC chip and DDR memory is too high, a first temperature control command is sent to the internal components of the SOC chip, and a second temperature control command is simultaneously sent to the DDR memory to quickly reduce their overall temperature. This is done by lowering the maximum frequency of the internal components of the SOC chip or removing a core, thereby reducing the temperature of the SOC chip, and by lowering the frequency of the DDR memory, thereby reducing the overall temperature of the DDR memory and the SOC chip. This effectively reduces the overall temperature of the DDR memory and the SOC chip, thereby reducing the overall power consumption of the DDR memory and the SOC chip, and improving the overall performance of the DDR memory and the SOC chip.

[0112] It should be noted that the first temperature threshold, the first frequency threshold, and the second frequency threshold mentioned above can be determined according to the actual situation, and the embodiments of the present invention do not impose specific limitations on them.

[0113] exist Figure 3 Based on the illustrated embodiment, as one implementation of the present invention, the method may further include the following steps, namely steps a1 to a4:

[0114] Step a1: Every preset time interval, the DDR driver calls the DDR controller of the SOC chip to obtain the DDR chip refresh rate again.

[0115] Step a2: Based on the mapping relationship between DDR chip refresh rate and temperature in the mapping table, determine the temperature corresponding to the newly obtained DDR chip refresh rate, and use it as the third temperature of the DDR memory.

[0116] Step a3: Obtain the fourth temperature of the SOC chip from the temperature sensor in the SOC chip, and determine whether the sum of the third temperature and the fourth temperature is less than the target temperature.

[0117] Step a4: If the sum of the third temperature and the fourth temperature is greater than the target temperature, a third temperature control instruction is sent to the internal components of the SOC chip, and the DDR controller of the SOC chip is called through the DDR driver to send a fourth temperature control instruction to the DDR memory until the sum of the third temperature and the fourth temperature is lower than the target temperature.

[0118] In this implementation, during temperature control, the DDR chip refresh rate can be acquired at preset intervals (which can be determined based on actual conditions) to deduce the current temperature of the DDR memory (for clarity, this current temperature can be referred to as the third temperature). Simultaneously, the current temperature of the SOC chip is acquired (for clarity, this current temperature can be referred to as the fourth temperature), and the sum of the third and fourth temperatures is calculated to determine if it is less than the target temperature. If the sum of the third and fourth temperatures is less than the target temperature, it indicates that the overall temperature of the SOC chip and DDR memory has been controlled within the target range. If the sum of the third and fourth temperatures is greater than the target temperature, it indicates that the overall temperature of the SOC chip and DDR memory is still high. In this case, the temperature control strategy continues until the sum of the third and fourth temperatures is less than the target temperature.

[0119] The target temperature can be determined according to the actual situation, and the present invention does not specifically limit the magnitude of the target temperature.

[0120] As can be seen, this implementation method can effectively reduce the overall temperature of the DDR memory and SOC chip without adding a temperature sensor to the DDR memory, thereby reducing the overall power consumption of the DDR memory and SOC chip and improving the overall performance of the DDR memory and SOC chip.

[0121] exist Figure 2 Based on the illustrated embodiment, as one implementation of this invention, in step S250, a temperature control strategy to be adopted is determined based on the first temperature and the second temperature, and the overall temperature control operation of the DDR memory and the SOC chip is executed according to the temperature control strategy, such as... Figure 4 As shown, it may include the following steps:

[0122] S251b: If the second temperature of the SOC chip is lower than the second temperature threshold, but the first temperature of the DDR memory is higher than the third temperature threshold, it receives a temperature reduction request actively sent by the DDR driver.

[0123] The second temperature threshold is less than the third temperature threshold.

[0124] In response to a temperature reduction request, the S252b calls the DDR controller of the SOC chip via the DDR driver to send a fifth temperature control command to the DDR memory.

[0125] The fifth temperature control instruction is used to control the maximum frequency of DDR memory to be less than the third frequency threshold.

[0126] Specifically, when the SOC chip's temperature remains within its tolerance range (i.e., the SOC temperature has not exceeded the temperature threshold), but the DDR memory's performance is severely limited or nearing malfunction due to excessive temperature, the DDR memory can proactively request the SOC chip to lower its own temperature through a temperature control strategy. Furthermore, the DDR driver invokes the SOC chip's DDR controller to send a fifth temperature control command to the DDR memory. This fifth temperature control command can reduce the DDR memory's maximum frequency, i.e., control the DDR memory's maximum frequency to be lower than a third frequency threshold. The magnitude of the third frequency threshold can be determined based on actual conditions, and this embodiment of the invention does not impose a specific limitation on it.

[0127] As can be seen, this implementation method can effectively reduce the temperature of DDR memory, thereby effectively reducing the overall temperature of DDR memory and SOC chip, reducing the overall power consumption of DDR memory and SOC chip, and improving the overall performance of DDR memory and SOC chip.

[0128] exist Figure 2 Based on the illustrated embodiment, as one implementation of the present invention, the method for overall temperature control of DDR memory and SOC chip may further include the following steps, namely steps a1 and a2:

[0129] Step a1: Determine the current performance mode of the DDR memory.

[0130] Step a2: If the current performance mode is benchmark mode, stop sending temperature control commands to the DDR controller.

[0131] In this implementation, during the benchmarking mode, temperature limitations are temporarily disabled to ensure that the DDR memory operates at its highest performance level. That is, during benchmarking mode, temperature control of the DDR memory is temporarily suspended. The "benchmarking mode" for DDR (Double Data Rate) memory typically refers to adjusting parameters such as memory frequency and voltage to achieve higher performance.

[0132] Of course, in practical applications, it is also possible to determine whether to temporarily disable the temperature control of DDR memory based on other performance modes of DDR memory, or to adjust the cycle of temperature control of DDR memory, which are all reasonable.

[0133] It is evident that by differentiating between various scenarios such as performance benchmarking mode or user mode, and by invoking temperature control strategies driven by temperature control, performance, temperature, and power consumption can be effectively balanced, and the user experience can be improved.

[0134] This invention also provides a device for overall temperature control of DDR memory and SOC chip, applied to electronic devices that spatially integrate DDR memory and SOC chip in a package. The SOC chip includes a DDR controller, and the device is specifically used to perform the following steps:

[0135] Obtain a pre-generated mapping table between DDR chip refresh rate and temperature. The process of establishing the mapping table includes: testing the DDR memory in a temperature-controlled environment, recording the actual refresh rate of the DDR chip at different temperatures, and forming a mapping relationship between the DDR chip refresh rate and the corresponding temperature.

[0136] The DDR driver calls the DDR controller of the SOC chip to obtain the current DDR chip refresh rate;

[0137] Based on the mapping relationship between DDR chip refresh rate and temperature in the mapping table, the temperature corresponding to the current DDR chip refresh rate is determined as the first temperature of the DDR memory;

[0138] The second temperature of the SOC chip is obtained from the temperature sensor in the SOC chip;

[0139] Based on the first temperature and the second temperature, a temperature control strategy to be adopted is determined, and the overall temperature control operation of the DDR memory and SOC chip is executed according to the temperature control strategy.

[0140] This invention also provides an electronic device that spatially integrates DDR memory and a SOC chip in a package. The SOC chip includes a DDR controller, and the SOC chip executes the following steps via temperature control:

[0141] Obtain a pre-generated mapping table between DDR chip refresh rate and temperature. The process of establishing the mapping table includes: testing the DDR memory in a temperature-controlled environment, recording the actual refresh rate of the DDR chip at different temperatures, and forming a mapping relationship between the DDR chip refresh rate and the corresponding temperature.

[0142] The DDR driver calls the DDR controller of the SOC chip to obtain the current DDR chip refresh rate;

[0143] Based on the mapping relationship between DDR chip refresh rate and temperature in the mapping table, the temperature corresponding to the current DDR chip refresh rate is determined as the first temperature of the DDR memory;

[0144] The second temperature of the SOC chip is obtained from the temperature sensor in the SOC chip;

[0145] Based on the first temperature and the second temperature, a temperature control strategy to be adopted is determined, and the overall temperature control operation of the DDR memory and SOC chip is executed according to the temperature control strategy.

[0146] This invention also provides a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by the temperature control drive of a SOC chip, enables an electronic device to perform the method described in any of the first aspects.

[0147] The technical solution provided in this invention first tests the DDR memory in a temperature-controlled environment, records the actual refresh rate of the DDR chips at different temperatures, and forms a mapping relationship between the DDR chip refresh rate and the corresponding temperature to pre-generate a mapping relationship table between the DDR chip refresh rate and temperature; then, the DDR driver calls the DDR controller of the SOC chip to obtain the current DDR chip refresh rate; based on the mapping relationship table between the DDR chip refresh rate and temperature, the temperature of the current DDR memory corresponding to the current DDR chip refresh rate is determined; and the current temperature of the SOC chip can be obtained from the temperature sensor in the SOC chip; finally, the current temperature of the DDR memory and the current temperature of the SOC chip are treated as a whole to determine the temperature control strategy to be adopted, and the overall temperature control operation of the DDR memory and the SOC chip is executed according to the temperature control strategy.

[0148] By regulating the overall temperature of the DDR memory and SOC chip, the temperature information of the DDR memory can be inferred from the temperature-related refresh rate of the DDR chip itself, without adding an additional temperature sensor to the DDR chip. This allows for effective temperature control of the DDR memory and SOC chip, thereby reducing overall power consumption and improving overall performance.

[0149] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A method for overall temperature control of a DDR memory and an SOC chip, characterized in that, The method is applied to an electronic device in which a DDR memory is spatially integrated with a SOC chip, and the SOC chip includes a DDR controller. The method includes: obtaining a pre-generated mapping relationship table of a DDR particle refresh rate and temperature, wherein the mapping relationship table is established by adjusting the temperature of the DDR memory multiple times according to a preset adjustment step in a temperature control environment, and measuring the actual temperature of the DDR memory by a temperature box and obtaining the actual refresh rate of the DDR particle each time the temperature of the DDR memory is adjusted; and establishing a mapping relationship between each actual temperature and the actual refresh rate corresponding to the actual temperature to obtain the mapping relationship table of the DDR particle refresh rate and temperature; periodically calling the DDR controller interface of the SOC chip through a DDR driver to obtain the mode register MR4 refresh rate information of the DDR memory to obtain the current DDR particle refresh rate; determining the temperature corresponding to the current DDR particle refresh rate as the first temperature of the DDR memory based on the mapping relationship between the DDR particle refresh rate and the temperature in the mapping relationship table; obtaining the second temperature of the SOC chip from a temperature sensor in the SOC chip; based on the first temperature and the second temperature, determining a temperature control strategy to be taken, and performing overall temperature control operations of the DDR memory and the SOC chip according to the temperature control strategy, including: if the sum of the first temperature and the second temperature is greater than a first temperature threshold, sending a first temperature control instruction to an internal component of the SOC chip, the first temperature control instruction being used to instruct to limit the maximum frequency of the internal component to be less than a first frequency threshold, or to instruct the internal component to perform a core pulling operation; calling the DDR controller of the SOC chip through the DDR driver to send a second temperature control instruction to the DDR memory, the second temperature control instruction being used to control the maximum frequency of the DDR memory to be less than a second frequency threshold.

2. The method of claim 1, wherein, The method further includes: calling the DDR controller of the SOC chip through the DDR driver every preset time length to obtain the DDR particle refresh rate again; determining the temperature corresponding to the DDR particle refresh rate obtained again as the third temperature of the DDR memory based on the mapping relationship between the DDR particle refresh rate and the temperature in the mapping relationship table; obtaining the fourth temperature of the SOC chip from the temperature sensor in the SOC chip, and determining whether the sum of the third temperature and the fourth temperature is less than a target temperature; if the sum of the third temperature and the fourth temperature is greater than the target temperature, sending a third temperature control instruction to the internal component of the SOC chip, and calling the DDR controller of the SOC chip through the DDR driver to send a fourth temperature control instruction to the DDR memory until the sum of the third temperature and the fourth temperature is controlled to be lower than the target temperature.

3. The method of claim 1, wherein, The method further includes: If the second temperature of the SOC chip is less than a second temperature threshold, but the first temperature of the DDR memory is higher than a third temperature threshold, the second temperature threshold is less than the third temperature threshold, and the DDR drive actively sends a temperature reduction request, the temperature reduction request is received; In response to the temperature reduction request, the DDR controller of the SOC chip is called through the DDR drive, and a fifth temperature regulation instruction is sent to the DDR memory, the fifth temperature regulation instruction being used to control the highest frequency of the DDR memory to be less than a third frequency threshold.

4. The method of claim 1, wherein, The method further comprises: determining a current performance mode of the DDR memory; if the current performance mode is a running mode, stopping sending temperature regulation instructions to the DDR controller.

5. The method according to any one of claims 1 to 4, characterized in that, Different positions in the SOC chip are respectively pre-buried with temperature sensors; The second temperature of the SOC chip is obtained from the temperature sensors in the SOC chip, comprising: Respectively obtaining the temperatures of different positions of the SOC chip from the temperature sensors pre-buried in the different positions of the SOC chip; Based on the temperatures of different positions of the SOC chip, the second temperature of the SOC chip is determined.

6. A device for overall temperature control of a DDR memory and an SOC chip, characterized in that, The application is applied to an electronic device in which a DDR memory is integrated and packaged with a SOC chip in space, the SOC chip comprising a DDR controller, and the device is specifically used for performing the following steps: obtaining a pre-generated mapping relationship table of DDR particle refresh rate and temperature, wherein the establishment process of the mapping relationship table comprises: adjusting the temperature of the DDR memory multiple times according to a preset adjustment step in a temperature control environment, and measuring the actual temperature of the DDR memory through a temperature box and obtaining the actual refresh rate of the DDR particle each time the temperature of the DDR memory is adjusted; mapping each actual temperature and the actual refresh rate corresponding to the actual temperature to obtain the mapping relationship table of DDR particle refresh rate and temperature; obtaining the current DDR particle refresh rate by periodically calling the DDR controller interface of the SOC chip through the DDR drive to obtain the mode register MR4 refresh rate information of the DDR memory; determining the temperature corresponding to the current DDR particle refresh rate as the first temperature of the DDR memory based on the mapping relationship of DDR particle refresh rate and temperature in the mapping relationship table; obtaining the second temperature of the SOC chip from the temperature sensors in the SOC chip; based on the first temperature and the second temperature, determining a temperature regulation strategy to be taken, and performing the overall temperature regulation operation of the DDR memory and the SOC chip according to the temperature regulation strategy, comprising: if the temperature sum of the first temperature and the second temperature is greater than a first temperature threshold, sending a first temperature regulation instruction to an internal part of the SOC chip, the first temperature regulation instruction being used to instruct to limit the highest frequency of the internal part to be less than a first frequency threshold, or being used to instruct the internal part to perform a core pulling operation; The DDR controller of the SOC chip is called by a DDR driver, and a second temperature control instruction is sent to the DDR memory, the second temperature control instruction being used to control the maximum frequency of the DDR memory to be less than a second frequency threshold.

7. An electronic device, comprising: The electronic device integrates the DDR memory and the SOC chip in space, the SOC chip including a DDR controller, and the SOC chip performs the following steps through a temperature control driver: A mapping relationship table of DDR particle refresh rate and temperature is obtained, and the mapping relationship table is established by the following process: in a temperature control environment, the temperature of the DDR memory is adjusted multiple times according to a preset adjustment step, and the actual temperature of the DDR memory is measured by a temperature box and the actual refresh rate of the DDR particle is obtained each time the temperature of the DDR memory is adjusted; a mapping relationship is established between each actual temperature and the actual refresh rate corresponding to the actual temperature, and the mapping relationship table of DDR particle refresh rate and temperature is obtained; The DDR controller interface of the SOC chip is called periodically by a DDR driver to obtain the mode register MR4 refresh rate information of the DDR memory, and the current DDR particle refresh rate is obtained; Based on the mapping relationship of DDR particle refresh rate and temperature in the mapping relationship table, the temperature corresponding to the current DDR particle refresh rate is determined as the first temperature of the DDR memory; The second temperature of the SOC chip is obtained from a temperature sensor in the SOC chip; Based on the first temperature and the second temperature, a temperature control strategy to be taken is determined, and the overall temperature control operation of the DDR memory and the SOC chip is performed according to the temperature control strategy, including: If the sum of the first temperature and the second temperature is greater than a first temperature threshold, a first temperature control instruction is sent to internal components of the SOC chip, the first temperature control instruction being used to instruct the maximum frequency of the internal components to be less than a first frequency threshold, or being used to instruct the internal components to perform a core pulling operation; The DDR controller of the SOC chip is called by a DDR driver, and a second temperature control instruction is sent to the DDR memory, the second temperature control instruction being used to control the maximum frequency of the DDR memory to be less than a second frequency threshold.

8. A computer-readable storage medium, characterized in that, When the instructions in the computer readable storage medium are executed by the temperature control driver of the SOC chip, the electronic device can perform the method of any one of claims 1-5.

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