Speculative wake-up instruction dependency chain cancellation system, method, and related devices

Abstract

A speculative wake-up instruction dependency chain cancellation system, method, and related apparatus are disclosed. The instruction dependency chain cancellation system includes: a memory miss judgment module for determining whether the preceding instruction of the instruction to be executed can hit a memory access; a register number comparison module for comparing whether the source register number of the instruction to be executed is the same as the destination register number of the operand; and a cancellation processing module for notifying the issue queue module to clear the issue flag of the instruction to be executed and instructions that have a dependency relationship with the instruction to be executed when speculative wake-up fails. Compared with the prior art, this invention decouples long instruction dependency chains into multiple short dependencies by notifying the issue queue module to initiate the cancellation behavior of clearing issue flags in a time-sharing manner through the cancellation processing module. Without affecting performance, it reduces the timing critical path of the instruction during speculative wake-up cancellation by two register number comparison circuits.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a speculative wake-up instruction dependency chain cancellation system, method, and related equipment. Background Technology

[0002] High-performance superscalar processors typically employ out-of-order execution. This means that instructions are no longer executed sequentially according to the original program order, but are intelligently scheduled based on dependencies between instructions and the availability of execution units, improving execution efficiency. Data dependency between instructions refers to a situation where, during program execution, the result of one instruction is used by subsequent instructions; in this case, a data dependency exists between the two instructions. For example, if the source operand of an `add` instruction depends on the destination register of a `load` instruction, the processor hardware assumes that the input data for the `add` instruction comes from the result data of the `load` instruction. Even if the processor supports out-of-order execution, the execution of these two instructions must adhere to the original program sequence, ensuring the correct transfer and use of data between instructions.

[0003] Processor design, based on function and architecture, can generally be divided into several parts, including the front-end responsible for instruction fetching and decoding, the back-end responsible for scheduling and execution, and the memory access system responsible for memory access. Out-of-order execution is primarily implemented in the back-end, which typically consists of multiple pipeline stages such as renaming, dispatching, issuing, arbitration, read-reading, and execution. The main module in the issuing stage is the issue queue, which is the core component of out-of-order execution scheduling: when an instruction arrives at the issue queue after passing through the preceding pipelines, it is written into one of several entries in the issue queue. If the instruction depends on a preceding instruction and the preceding instruction has not yet completed and obtained a result, it will wait in the issue queue and will not be issued to the next pipeline stage. The issue queue will then select instructions without data dependencies in other entries for issuance.

[0004] Once the pre-instruction has finished executing and the result data has been calculated, the dependent instructions in the issue queue are notified that their source operands are ready and can be issued. This notification behavior is called wake-up. Specifically, when an instruction is executed by the execution unit and the result data is obtained, this result data is used by the register number comparison circuit to find all instructions in the issue queue that depend on this data, updating the state of the instructions in the queue. Source registers with the same number among these instructions are set to a valid state, allowing these instructions to be selected by the selection arbitration circuit and issued to the subsequent pipeline. The data from the source registers is obtained in the bypass network of the read-through stage before execution, such as... Figure 1 As shown, Figure 1 A schematic diagram illustrating the speculative wake-up process performed by a computer processor in a related technology.

[0005] Speculative wake-up, also known as predictive wake-up, is an optimization technique widely used in high-performance superscalar processors to reduce instruction stagnation in the pipeline. Speculative wake-up occurs when there are dependencies between instructions. Even if the preceding instruction has not yet completed and obtained its result data, it can be predicted based on the instruction type that it will complete in a few cycles. Therefore, all instructions in the issue queue that depend on and are waiting for that data are speculatively woken up and issued. This ensures that when the preceding instruction completes, the woken instruction has just reached the pre-execution read stage and obtained its result data, thus reducing the waiting cycle of the woken instruction in the issue queue and improving instruction execution efficiency. Taking a common high-performance processor pipeline design where the preceding instruction executes in a single cycle as an example, such as... Figure 2 and Figure 3 As shown, Figure 2 A spacetime diagram for a computer processor performing a normal wake-up in related technologies. Figure 3 The spatiotemporal diagram of speculative wake-up for computer processors in related technologies shows that the speculative wake-up mechanism reduces the delay of instructions by two cycles.

[0006] However, since speculative wake-up is speculative, it is prone to failure. For example, failure to compete for read access in the register file or a cache miss by the load instruction in the memory access unit can cause dependent instructions to fail to retrieve the source register data as expected during the read phase. Therefore, speculative wake-up is equipped with a cancellation mechanism to prevent the propagation of errors, such as... Figure 4 As shown, Figure 4 This is a space-time diagram illustrating the cancellation mechanism for speculative wake-up in computer processors of relevant technologies. If a pre-instruction fails to complete a contention during a register file read phase, it cancels the execution of all dependent instructions.

[0007] When designing a high-performance processor that needs to operate at high frequencies such as above 3GHz, the above solutions struggle to meet timing requirements when dealing with instruction dependency chains, especially those originating from load instructions. For example... Figure 5 As shown, Figure 5 This section describes the time-space graph of long instruction dependencies in computer processors, originating from the load instruction. In high-performance processor designs, the load instruction typically requires four execution cycles. This means that memory access hit information and result data are generated in the fourth execution phase. If a memory access miss occurs, a wake-up is predicted as incorrect. When the wake-up prediction in the second phase of load execution depends on its add instruction 1, so that add instruction 1 happens to retrieve the data written back by load in the subsequent read phase, a prediction window from T2 to T4 is generated. Within this window, a long instruction dependency chain is generated, such as... Figure 5The pipeline of four instructions within the window forms an instruction dependency chain originating from load. The correctness of the speculative wake-up behavior during this period is unknown until the memory access unit notifies of a memory hit at T4, at which point the wake-up behavior can be confirmed.

[0008] When a memory access miss occurs, the load instruction needs to find the add instruction 1 through the register number comparison circuit, preventing it from entering the next stage of the pipeline; similarly, add instruction 1 also needs to find the add instruction 2 through the register number comparison circuit, invalidating it; and so on. The dependency chain from the load instruction to the add instruction 3 requires three sequential comparison circuits. Furthermore, the initial memory access unit's miss detection circuit also requires some circuit logic resources. Therefore, the detection circuit and the three comparison circuits are serially combined into a combinational logic circuit completed within cycle T4. However, this circuit structure is extremely difficult for the design of a high-frequency processor. Figure 6 As shown, Figure 6 A schematic diagram of the circuit connection for canceling the instruction dependency chain during computer processor execution in related technologies.

[0009] Therefore, there is an urgent need for a new speculative wake-up instruction dependency chain cancellation system, method, and related equipment to solve the above-mentioned technical problems. Summary of the Invention

[0010] This invention provides a system, method, and related device for canceling instruction dependency chains for speculative wake-up, aiming to solve the timing problem of long instruction dependency chains when speculative wake-up fails, and improve the cancellation efficiency of speculative wake-up.

[0011] In a first aspect, a speculative wake-up instruction dependency chain cancellation system is provided, the instruction dependency chain cancellation system comprising a launch queue module, a selection arbitration module, a read module, an execution module, a speculative wake-up module, a pipelined register module, a register number comparison module, a memory access miss judgment module, and a cancellation processing module.

[0012] The launch queue module is used to store instructions to be executed.

[0013] The selection arbitration module is used to select an instruction to be executed from the transmission queue module in the current cycle and send it to the reading module;

[0014] The reading module is used to read the operands required in the pre-instruction of the received instruction to be executed, and send the instruction to be executed and the corresponding operands to the execution module.

[0015] The execution module is used to perform corresponding operations based on the received operands and the instruction to be executed;

[0016] The speculative wake-up module is used to speculatively wake up the instruction to be executed in the launch queue module based on the dependency relationship between the instruction to be executed and the preceding instruction in the launch queue module.

[0017] The pipeline register module is used to transfer the instruction to be executed between the launch queue module, the selection arbitration module, the read module, and the execution module;

[0018] The memory access miss determination module is used to determine whether the pre-instruction of the instruction to be executed in the reading module can hit the memory access.

[0019] The register number comparison module is used to compare whether the source register number of the instruction to be executed in the transmit queue module, the selection arbitration module, and the read module is the same as the destination register number of the operand;

[0020] The cancellation processing module is used to notify the launch queue module to clear the launch flag of the instruction to be executed and instructions that depend on the instruction to be executed when it is suspected that waking up the instruction to be executed has failed.

[0021] Preferably, the memory miss determination module is further configured to send the destination register number of the preceding instruction to the register number comparison module when the preceding instruction of the instruction to be executed fails to access memory.

[0022] Preferably, the register number comparison module is further configured to, when determining that the source register number of the instruction to be executed and the destination register number of the operand are the same, issue a termination signal to the pipeline register module to prevent the instruction to be executed from entering the execution module, and send the termination signal to the cancellation processing module.

[0023] Preferably, the cancellation processing module is further configured to read the destination register number of the instruction to be executed from the pipeline register module, and when receiving the termination signal sent by the register number comparison module, send the destination register number of the instruction to be executed corresponding to the termination signal to the register number comparison module.

[0024] Preferably, the register number comparison module is further used to compare whether the destination register number of the instruction to be executed is the same as the source register number of the instruction in the send queue module and the selection arbitration module. If they are the same, a cancellation flag is set for the corresponding instruction in the selection arbitration module and the send queue module. The destination register number of the instruction with the cancellation flag will be sent to the cancellation processing module in a subsequent cycle.

[0025] Preferably, the cancellation processing module is further configured to notify the launch queue module to clear the launch flag bit of an instruction with the cancellation flag bit.

[0026] Preferably, the register number comparison module includes a transmit queue comparison unit, a selection arbitration comparison unit, and a memory access miss comparison unit;

[0027] The transmit queue comparison unit is used to compare whether the source register number of the instruction in the transmit queue module is the same as the destination register number of the instruction to be executed. If they are the same, the cancellation flag is set for the corresponding instruction.

[0028] The selection arbitration comparison unit is used to compare whether the source register number of the instruction in the selection arbitration module is the same as the destination register number of the instruction to be executed. If they are the same, the cancellation flag is set for the corresponding instruction.

[0029] The memory miss comparison unit is used to compare whether the source register number of the instruction to be executed is the same as the destination register number of the operand. If so, the termination signal is issued to prevent the instruction to be executed from entering the execution module, and the termination signal is sent to the cancellation processing module.

[0030] Secondly, the present invention also provides a method for canceling speculative wake-up instruction dependency chains, the method being based on a speculative wake-up instruction dependency chain cancellation system as described in any of the above embodiments, the method comprising the following steps:

[0031] S1. Based on the dependency relationship between the instruction to be executed and the preceding instruction in the launch queue module, the instruction to be executed is speculatively woken up by the speculative wake-up module;

[0032] S2. When the memory access miss judgment module determines that the memory access miss of the preceding instruction of the instruction to be executed has occurred, the register number comparison module determines whether the source register number of the instruction to be executed is the same as the destination register number of the preceding instruction. If so, the instruction to be executed is suspected to have failed to wake up, and the cancellation processing module notifies the transmit queue module to clear the transmit flag bit of the instruction to be executed.

[0033] S3. The register number comparison module determines whether there is a source register number of an instruction in the transmit queue module and the selection arbitration module that is the same as the destination register number of the instruction to be executed. If so, the cancellation flag is set for the corresponding instruction in the transmit queue module and the selection arbitration module.

[0034] S4. The cancellation processing module notifies the launch queue module to clear the launch flag of the instruction with the cancellation flag.

[0035] Thirdly, the present invention also provides a computer device, including: a memory, a processor, and a speculative wake-up instruction dependency chain cancellation program stored in the memory and executable on the processor, wherein when the processor executes the speculative wake-up instruction dependency chain cancellation program, it implements the steps in the speculative wake-up instruction dependency chain cancellation method as described in the above embodiments.

[0036] Fourthly, the present invention also provides a computer-readable storage medium storing a speculative wake-up instruction dependency chain cancellation procedure, wherein the speculative wake-up instruction dependency chain cancellation procedure, when executed by a processor, implements the steps of the speculative wake-up instruction dependency chain cancellation method as described in any of the above embodiments.

[0037] Compared with existing technologies, this invention cancels the cancellation behavior of clearing the transmission flag bit by notifying the transmission queue module in time periods through the cancellation processing module. This decouples the long instruction dependency chain into multiple short dependencies, reduces its logic levels, and achieves the purpose of improving timing frequency. Without affecting performance, it reduces the timing critical path of the instruction when speculating on wake-up cancellation by two register number comparison circuits, effectively solving the timing bottleneck problem of long instruction dependency chains. Attached Figure Description

[0038] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0039] Figure 1 This is a schematic diagram illustrating the wake-up process performed by a computer processor in a related technology.

[0040] Figure 2 This is a spacetime diagram of a computer processor performing a normal wake-up in related technologies;

[0041] Figure 3 It is a spacetime diagram of the speculative wake-up process performed by the computer processor in the relevant technology;

[0042] Figure 4 This is a spacetime diagram of the computer processor's speculative wake-up cancellation mechanism in related technologies;

[0043] Figure 5 It is a spacetime graph of the long instruction dependency chain executed by the computer processor of the related technology, which originates from the load instruction;

[0044] Figure 6 This is a schematic diagram of the circuit connection for canceling the instruction dependency chain during computer processor execution, related to the technology.

[0045] Figure 7This is a schematic diagram of the structure of the speculative wake-up instruction dependency chain cancellation system provided in an embodiment of the present invention;

[0046] Figure 8 This is a schematic diagram of the framework for canceling speculative wake-up in the instruction dependency chain cancellation system provided in this embodiment of the invention.

[0047] Figure 9 This is a spatiotemporal diagram of the speculative wake-up cancellation process in the speculative wake-up instruction dependency chain cancellation system provided in this embodiment of the invention.

[0048] Figure 10 This is a flowchart of the method for canceling the instruction dependency chain for speculative wake-up provided in an embodiment of the present invention;

[0049] Figure 11 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0051] Example 1

[0052] Please refer to Figure 7 The present invention provides a speculative wake-up instruction dependency chain cancellation system 100, the instruction dependency chain cancellation system 100 including speculative wake-up module 01, issue queue module 02, selection arbitration module 03, read module 04, execution module 05, pipeline register module 06, register number comparison module 07, memory access miss judgment module 08, and cancellation processing module 09.

[0053] The launch queue module 02 is used to store instructions to be executed;

[0054] The selection arbitration module 03 is used to select an instruction to be executed from the transmission queue module 02 in the current cycle and send it to the reading module 04;

[0055] The reading module 04 is used to read the operands required by the received instruction to be executed in the preceding instructions, and send the instruction to be executed and the corresponding operands to the execution module 05; wherein, the operands are the execution results of the preceding instructions that have a dependency relationship. For example, the instruction to be executed A requires the operation A = A1 + A2, where A1 and A2 are the operands required by the instruction to be executed.

[0056] The execution module 05 is used to perform corresponding operations based on the received operands and the instruction to be executed. Specifically, the operand is a field of the assembly language instruction. It can be the operand itself, the operation address, or the calculation method of the operation address. The operand is the participant in the execution of the instruction, that is, the object of various operations, including the data that needs to be calculated or processed in the instruction.

[0057] The speculative wake-up module 01 is used to speculatively wake up the instruction to be executed in the launch queue module 02 based on the dependency relationship between the instruction to be executed and the preceding instruction in the launch queue module 02.

[0058] The pipeline register module 06 is used to transfer the instruction to be executed between the launch queue module 02, the selection arbitration module 03, the reading module 04, and the execution module 05.

[0059] In embodiments of the present invention, such as Figure 8 As shown, the pipeline register module 06 includes a pipeline register 061 between the transmit queue module 02 and the selection arbitration module 03, a pipeline register 062 between the selection arbitration module 03 and the readout module 04, and a pipeline register 063 between the readout module 04 and the execution module 05, etc. The pipeline registers realize the temporary storage and transmission of instructions to be executed.

[0060] The memory miss determination module 08 is used to determine whether the pre-instruction of the instruction to be executed in the reading module 04 can hit the memory access. The memory miss determination module 08 obtains the execution result of the pre-instruction through the execution module 05, and determines whether the memory access is hit based on the calculation result.

[0061] In this embodiment of the invention, the memory access miss judgment module is further configured to send the destination register number of the preceding instruction to the register number comparison module 07 when the preceding instruction of the instruction to be executed fails to access memory.

[0062] The register number comparison module 07 is used to compare whether the source register number of the instruction to be executed in the transmit queue module 02, the selection arbitration module 03, and the read module 04 is the same as the destination register number of the operand; the register number comparison module 07 is also used to send a termination signal to the pipeline register module 06 to prevent the instruction to be executed from entering the execution module 05 when it is determined that the source register number of the instruction to be executed and the destination register number of the operand (i.e., the destination register number of the preceding instruction) are the same, and to send the termination signal to the cancellation processing module 09.

[0063] In this embodiment of the invention, the register number comparison module 07 is further used to compare whether the destination register number of the instruction to be executed is the same as the source register number of the instruction in the send queue module 02 and the selection arbitration module 03. If they are the same, a cancellation flag is set for the corresponding instruction in the selection arbitration module 03 and the send queue module 02. The number of the instruction with the cancellation flag will be sent to the cancellation processing module 09 in a subsequent cycle.

[0064] In this embodiment of the invention, the register number comparison module 07 includes a transmit queue comparison unit 071, a selection arbitration comparison unit 072, and a memory access miss comparison unit 073.

[0065] The transmit queue comparison unit 071 is used to compare whether the source register number of the instruction in the transmit queue module 02 is the same as the destination register number of the instruction to be executed. If so, a cancellation flag is set for the corresponding instruction.

[0066] The selection arbitration comparison unit 072 is used to compare whether the source register number of the instruction in the selection arbitration module 03 is the same as the destination register number of the instruction to be executed. If so, a cancellation flag is set for the corresponding instruction.

[0067] The memory miss comparison unit 073 is used to compare whether the source register number of the instruction to be executed is the same as the destination register number of the operand. If so, a termination signal is issued to prevent the instruction to be executed from entering the execution module 05, and the termination signal is sent to the cancellation processing module 09.

[0068] The cancellation processing module 09 is used to notify the launch queue module 02 to clear the launch flag of the instruction to be executed and any instructions that depend on it, when it is suspected that waking up the instruction to be executed has failed. Specifically, the launch flag refers to a flag used during instruction launch to mark instructions that have been launched but whose final state has not yet been determined. Such instructions will not continue to be launched but will wait for subsequent control information to pop up and wake them up. This helps avoid instruction execution errors caused by data hazards. Clearing the launch flag of an instruction allows it to be relaunched at a later time.

[0069] In this embodiment of the invention, the cancellation processing module 09 is further configured to read the destination register number of the instruction to be executed from the pipeline register module 06, and upon receiving the termination signal sent by the register number comparison module 07, send the destination register number of the instruction to be executed corresponding to the termination signal to the register number comparison module 07. Specifically, after receiving the termination signal sent by the memory miss comparison unit 073, the cancellation processing module 09 sends the destination register number of the instruction to be executed to the issue queue comparison unit 071 and the selection arbitration comparison unit 072, respectively.

[0070] In this embodiment of the invention, the cancellation processing module 09 is further configured to notify the transmission queue module 02 to clear the transmission flag bit of the instruction with the cancellation flag bit.

[0071] For details, please refer to Figure 8 and Figure 9 In the deduced wake-up instruction dependency chain cancellation system 100, the output of the cancellation processing module 09 is connected to the input of the launch queue module 02, the input of the launch queue comparison unit 071, and the input of the selection arbitration comparison unit 072; the output of the launch queue module 02 is connected to the input of the launch queue comparison unit 071 and the input of the pipeline register 061; the output of the launch queue comparison unit 071 is connected to the input of the pipeline register 061; the output of the pipeline register 061 is connected to the input of the selection arbitration module 03; and the output of the selection arbitration module 03 is connected to the input of the selection arbitration comparison unit 072. The input terminal of module 2 is connected to the input terminal of pipeline register 062; the output terminal of selection arbitration comparison unit 072 is connected to the input terminal of pipeline register 062; the output terminal of pipeline register 062 is connected to the input terminal of reading module 04 and the input terminal of cancellation processing module 09; the output terminal of reading module 04 is connected to the input terminal of memory miss comparison unit 073 and the input terminal of pipeline register 063; the output terminal of memory miss comparison unit 073 is connected to the input terminal of pipeline register 063 and the input terminal of cancellation processing module 09; the memory miss judgment module 08 is connected to the input terminal of memory miss comparison unit 073.

[0072] Taking the longest instruction dependency chain load<- A1<- A2<- A3 as an example (the arrow's starting end depends on the arrow's pointing end, and A represents the addition instruction to be executed), the instruction flow in the issue queue module 02, the selection arbitration module 03, and the read module 04 is defined as pipeline 1, pipeline 2, and pipeline 3, respectively. When an instruction A1 to be executed in the issue queue module 02 is speculatively awakened by the load instruction in cycle T2, the issue queue module 02 sets its issue flag to 1, but does not retire it. Retirement means deallocation; that is, when an instruction enters the issue queue module 02, it is allocated and occupied in a table in the issue queue module 02. After the issue queue module 02 issues the instruction, because there is a possibility of re-issue, the instruction still exists in the table and will not be immediately deallocated (i.e., not retired). Instead, it needs to wait for the speculative awakening of the instruction to confirm that it is correct and will not be re-issued before it can be deallocated and resources released. The information of the instruction A1 is still recorded in the issue queue module 02. Instruction A1 arrives at pipeline 2 in cycle T3 and infers wake-up instruction A2. Then, instruction A1 arrives at pipeline 3 in cycle T4, and instruction A2 arrives at pipeline 2 and infers wake-up instruction A3 for launch queue module 02.

[0073] At this point, if the memory miss judgment module 08 detects a memory miss for the load instruction, it sends the destination register number of the load instruction (i.e., the pre-instruction of the instruction to be executed A1) to the memory miss comparison unit 073 of the register number comparison module 07 for comparison with the source register of instruction A1 in pipeline 3. If they are the same, a stop signal is issued to prevent the instruction in pipeline 3 from entering the next stage, and this information is simultaneously notified to the cancellation processing module 09. The cancellation processing module 09 then finds the recorded instruction A1 information in the issue queue module 02, clears its issue flag, and allows instruction A1 to be reissued at a later time. Secondly, the cancellation processing module 09 also needs to broadcast the destination register of instruction A1 to pipelines 1 and 2 (i.e., the issue queue module 02 and the selection arbitration module 03), and compares whether the source register numbers of the instructions in pipelines 1 and 2 are the same through the issue queue comparison unit 071 and the selection arbitration comparison unit 072 of the register number comparison circuit. If they are the same, it means that the instruction in the pipeline was speculatively awakened by instruction A1 and needs to be cancelled.

[0074] In this invention, after finding an instruction that needs to be cancelled, unlike the traditional approach which cancels it immediately within the same cycle, a cancellation flag is added to the instruction, and the cancellation action is not performed immediately. In this example, it is the cancellation flag for instruction A2. In subsequent cycles, the cancellation processing module 09 notifies the transmission queue module 02 to cancel the instruction. For example... Figure 9In the next cycle T5, instruction A2 enters pipeline 3, repeating the cancellation behavior of instruction A1 in pipeline 3 (i.e., clearing its emit flag and waiting to re-emitter in a later time step):

[0075] First, the register number comparison module 07 finds instruction A3, which is currently in pipeline 2 (based on the speculated wake-up principle, if instruction A2 is executed in two cycles, instruction A3 may also be found in pipeline 1) and sets its cancellation flag.

[0076] Secondly, the process cancels the instruction from entering the next stage of the pipeline and clears the issue flag of instruction A2 in the issue queue for subsequent re-issue. Similarly, instruction A3 will also be canceled in pipeline 3 at a later time, thus decoupling the previously serial long dependency chain of instructions into a pipelined form. Compared with the prior art, this invention reduces two register number comparison circuits on the critical path.

[0077] Please refer to Figure 9 , Figure 9 The spatiotemporal diagram for speculative wake-up cancellation provided in this embodiment of the invention, in the existing technical solution within the T4 cycle (see...) Figure 5 Previously, all cancellation actions would be completed serially through combinational logic circuits. However, this invention, by dividing the instruction cancellation actions into different cycles, can significantly reduce the number of combinational logic stages in a single cycle, greatly easing the pressure on circuit timing design and enabling the processor to operate at higher frequencies. Although the final cancellation action ends in cycle T6, compared to... Figure 5 Compared to the related technical solutions, the former has two more cycles, but this does not affect the processor's performance. This is because after the issue queue is notified to reissue, due to the memory access unit's processing of the missed instruction, the canceled instruction in the latter still needs more than two cycles before it can be issued.

[0078] Compared with the prior art, the present invention initiates the cancellation behavior of clearing the transmission flag bit by notifying the transmission queue module 02 in a time-segmented manner through the cancellation processing module 09, thereby decoupling the long instruction dependency chain into multiple short dependencies, reducing its logic levels, and achieving the purpose of improving timing frequency. Without affecting performance, the timing critical path of the instruction when speculating wake-up cancellation is reduced by two register number comparison circuits, effectively solving the timing bottleneck problem of long instruction dependency chain.

[0079] Example 2

[0080] This invention also provides a method for canceling speculative wake-up instruction dependency chains. This method is based on the speculative wake-up instruction dependency chain cancellation system 100 described in any of the above embodiments. Please refer to... Figure 10 , Figure 10This is a flowchart of the speculative wake-up instruction dependency chain cancellation method provided in an embodiment of the present invention, which includes:

[0081] The instruction dependency chain cancellation method includes the following steps:

[0082] S1. Based on the dependency relationship between the instruction to be executed and the preceding instruction in the launch queue module 02, the instruction to be executed is speculatively woken up by the speculative wake-up module 01;

[0083] S2. When the memory access miss judgment module 08 determines that the memory access miss of the preceding instruction of the instruction to be executed has occurred, the register number comparison module 07 determines whether the source register number of the instruction to be executed is the same as the destination register number of the preceding instruction. If so, the instruction to be executed is suspected to have failed to wake up, and the cancellation processing module 09 notifies the issue queue module 02 to clear the issue flag of the instruction to be executed.

[0084] S3. The register number comparison module 07 determines whether there is a source register number of an instruction in the transmit queue module 02 and the selection arbitration module 03 that is the same as the destination register number of the instruction to be executed. If so, the cancellation flag is set for the corresponding instruction in the transmit queue module 02 and the selection arbitration module 03.

[0085] S4. The cancellation processing module 09 notifies the launch queue module 02 to clear the launch flag bit of any instruction with the cancellation flag bit.

[0086] In this embodiment of the invention, clearing the launch flag bit means setting the flag bit used to indicate the launch status of the command (i.e., the launch flag bit) to a specific value, so as to indicate that the corresponding launch status changes from launched to pending launch. For example, when command A is launched, its launch flag bit is 1, which means that command A has been launched and command A is still recorded in the launch queue module 02. If the execution of command A needs to be cancelled later, its launch flag bit is cleared by changing 1 to 0, indicating that command A still needs to be launched again. Steps S3 and S4 can be repeated based on the dependency chain of the instruction to be executed. For example, taking the longest instruction dependency chain load<- A1<- A2<- A3 as an example (the starting end of the arrow depends on the pointing end of the arrow, and A represents the addition instruction to be executed), when the load instruction fails to hit memory access, and the source register number of the instruction to be executed A1 is consistent with the destination register number of the operand of the load instruction, then the instruction to be executed A1 is a speculative wake-up instruction. The cancellation processing module 09 needs to notify the issue queue module 02 to clear the issue flag of instruction A1 for re-issue at a later time. At the same time, the destination register number of instruction A1 is broadcast in the issue queue module 02 and the selection arbitration module 03 to determine whether there is an instruction in the issue queue module 02 and the selection arbitration module 03 whose source register number is consistent with the destination register number of instruction A1 (in this example, the source register number of instruction A2 is consistent with the destination register number of instruction A1). A cancellation flag is set for instruction A2 so that the cancellation processing module 09 can notify the issue queue module 02 to clear the issue flag of instruction A2 in a subsequent cycle. Similarly, instruction A3 is processed in subsequent cycles as instruction A2, thereby decoupling the entire long instruction dependency chain and canceling instructions A1, A2, and A3 successively in different cycles.

[0087] The speculative wake-up instruction dependency chain cancellation method is based on a module in the speculative wake-up instruction dependency chain cancellation system 100 as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0088] Example 3

[0089] This invention also provides a computer device, please refer to... Figure 11 , Figure 11 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a speculative wake-up instruction dependency chain cancellation program stored in the memory 302 and executable on the processor 301.

[0090] The processor 301 calls the speculative wake-up instruction dependency chain cancellation program stored in the memory 302 to execute the steps in the speculative wake-up instruction dependency chain cancellation method provided in this embodiment of the invention. Please refer to... Figure 10 Specifically, it includes the following steps:

[0091] S1. Based on the dependency relationship between the instruction to be executed and the preceding instruction in the launch queue module 02, the instruction to be executed is speculatively woken up by the speculative wake-up module 01;

[0092] S2. When the memory access miss judgment module 08 determines that the memory access miss of the preceding instruction of the instruction to be executed has occurred, the register number comparison module 07 determines whether the source register number of the instruction to be executed is the same as the destination register number of the preceding instruction. If so, the instruction to be executed is suspected to have failed to wake up, and the cancellation processing module 09 notifies the issue queue module 02 to clear the issue flag of the instruction to be executed.

[0093] S3. The register number comparison module 07 determines whether there is a source register number of an instruction in the transmit queue module 02 and the selection arbitration module 03 that is the same as the destination register number of the instruction to be executed. If so, the cancellation flag is set for the corresponding instruction in the transmit queue module 02 and the selection arbitration module 03.

[0094] S4. The cancellation processing module 09 notifies the launch queue module 02 to clear the launch flag bit of any instruction with the cancellation flag bit.

[0095] The computer device 300 provided in this embodiment of the invention includes a module in the speculative wake-up instruction dependency chain cancellation system 100 as described in the above embodiment, and can achieve the same technical effect. Refer to the description in the above embodiment, which will not be repeated here.

[0096] Example 4

[0097] This invention also provides a computer-readable storage medium storing a speculative wake-up instruction dependency chain cancellation program. When executed by a processor, the speculative wake-up instruction dependency chain cancellation program implements the steps of the speculative wake-up instruction dependency chain cancellation method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0098] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0099] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0100] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0101] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A speculative wake-up instruction dependency chain cancellation system, characterized in that, The instruction dependency chain cancellation system includes a launch queue module, a selection arbitration module, a read module, an execution module, a speculative wake-up module, a pipelined register module, a register number comparison module, a memory access miss judgment module, and a cancellation processing module. The launch queue module is used to store instructions to be executed. The selection arbitration module is used to select an instruction to be executed from the transmission queue module in the current cycle and send it to the reading module; The reading module is used to read the operands required in the pre-instruction of the received instruction to be executed, and send the instruction to be executed and the corresponding operands to the execution module. The execution module is used to perform corresponding operations based on the received operands and the instruction to be executed; The speculative wake-up module is used to speculatively wake up the instruction to be executed in the launch queue module based on the dependency relationship between the instruction to be executed and the preceding instruction in the launch queue module. The pipeline register module is used to transfer the instruction to be executed between the launch queue module, the selection arbitration module, the read module, and the execution module; The memory access miss determination module is used to determine whether the pre-instruction of the instruction to be executed in the reading module can hit the memory access. The register number comparison module is used to compare whether the source register number of the instruction to be executed in the transmit queue module, the selection arbitration module, and the read module is the same as the destination register number of the operand; The cancellation processing module is used to notify the launch queue module to clear the launch flag of the instruction to be executed and instructions that depend on the instruction to be executed when it is suspected that waking up the instruction to be executed has failed. The register number comparison module is also used to send a termination signal to the pipeline register module to prevent the instruction to be executed from entering the execution module when it is determined that the source register number of the instruction to be executed and the destination register number of the operand are the same, and to send the termination signal to the cancellation processing module. The cancellation processing module is also used to read the destination register number of the instruction to be executed from the pipeline register module, and when it receives the termination signal sent by the register number comparison module, it sends the destination register number of the instruction to be executed corresponding to the termination signal to the register number comparison module. The register number comparison module is also used to compare whether the destination register number of the instruction to be executed is the same as the source register number of the instruction in the launch queue module and the selection arbitration module. If they are the same, a cancellation flag is set for the corresponding instruction in the selection arbitration module and the launch queue module, and the destination register number of the instruction with the cancellation flag is sent to the cancellation processing module in subsequent cycles. The cancellation processing module is also used to notify the launch queue module to clear the launch flag bit of any instruction with the cancellation flag bit.

2. The instruction dependency chain cancellation system for speculative wake-up as described in claim 1, characterized in that, The memory miss determination module is also used to send the destination register number of the preceding instruction to the register number comparison module when the preceding instruction of the instruction to be executed cannot miss the memory access.

3. The instruction dependency chain cancellation system for speculative wake-up as described in claim 1, characterized in that, The register number comparison module includes a transmit queue comparison unit, a selection arbitration comparison unit, and a memory access miss comparison unit; The transmit queue comparison unit is used to compare whether the source register number of the instruction in the transmit queue module is the same as the destination register number of the instruction to be executed. If they are the same, the cancellation flag is set for the corresponding instruction. The selection arbitration comparison unit is used to compare whether the source register number of the instruction in the selection arbitration module is the same as the destination register number of the instruction to be executed. If they are the same, the cancellation flag is set for the corresponding instruction. The memory miss comparison unit is used to compare whether the source register number of the instruction to be executed is the same as the destination register number of the operand. If so, the termination signal is issued to prevent the instruction to be executed from entering the execution module, and the termination signal is sent to the cancellation processing module.

4. A method for canceling a speculative wake-up instruction dependency chain, characterized in that, The instruction dependency chain cancellation method is based on the speculative wake-up instruction dependency chain cancellation system as described in any one of claims 1-3, and the instruction dependency chain cancellation method includes the following steps: S1. Based on the dependency relationship between the instruction to be executed and the preceding instruction in the launch queue module, the instruction to be executed is speculatively woken up by the speculative wake-up module; S2. When the memory access miss judgment module determines that the memory access miss of the preceding instruction of the instruction to be executed has occurred, the register number comparison module determines whether the source register number of the instruction to be executed is the same as the destination register number of the preceding instruction. If so, the instruction to be executed is suspected to have failed to wake up, and the cancellation processing module notifies the transmit queue module to clear the transmit flag bit of the instruction to be executed. S3. Determine whether there is an instruction whose source register number is the same as the destination register number of the instruction to be executed in the transmit queue module and the selection arbitration module through the register number comparison module; if so, set the cancellation flag bit for the corresponding instruction in the transmit queue module and the selection arbitration module. S4. The cancellation processing module notifies the launch queue module to clear the launch flag of any instruction with a cancellation flag.

5. A computer device, characterized in that, include: The memory, the processor, and the speculative wake-up instruction dependency chain cancellation procedure stored in the memory and executable on the processor, wherein the processor, when executing the speculative wake-up instruction dependency chain cancellation procedure, implements the steps of the speculative wake-up instruction dependency chain cancellation method as described in claim 4.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a speculative wake-up instruction dependency chain cancellation procedure, which, when executed by a processor, implements the steps of the speculative wake-up instruction dependency chain cancellation method as described in claim 4.

Images