A high performance bus transmission security method and system

Abstract

The application relates to a high-performance bus transmission security guarantee method and system, which comprises a bus security unit, a host, a slave and a bus matrix group composed of multiple bus matrices; the bus security unit is connected between the host and the slave; the bus security unit uses a transmission time length counting module to perform error monitoring; the decoded slave port number is compared with a preconfigured slave port number to determine whether a slave port error occurs; and error processing at an operating system layer or a bus controller layer is performed when the error occurs. The application can independently act on the bus and the bus matrix group mechanism, can find loss or timeout error in the bus transmission process caused by register transient failure or abnormal flip of the register in a transparent manner of the bus, the host and the slave, can be independently mounted and used or integrated with the bus, has high flexibility and less additional hardware and software overhead.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of intelligent chips, and particularly relates to a high-performance bus transmission security guarantee method and system. BACKGROUND

[0002] In a high-performance chip bus system, transmission security guarantee is a multi-level comprehensive protection system that needs to be designed in coordination from the protocol, hardware and system three dimensions. In the bus arbitration and bus matrix group transmission scene, the existing security guarantee method is mainly based on a static protection mechanism, while the front-line technology is committed to building a dynamic and intelligent security protection system. At the protocol level, traditional bus security mainly relies on fixed encryption algorithms and static access control. Bus transmission data is usually encrypted using standard algorithms such as AES, and CRC check is used to guarantee data integrity, while basic access control is achieved through a master device ID whitelist. Security guarantee technology at the hardware level is developing towards dynamic and intelligent direction. Dynamic encryption technology effectively improves the anti-attack ability of the encryption system through key rotation and post-quantum encryption algorithms. The construction of the hardware trust chain becomes the key, and the device identity authentication based on PUF and the TEE security domain isolation provide a hardware-level trust foundation for bus transmission. The programmable monitoring unit embedded in the bus matrix can analyze the transmission behavior pattern in real time, identify abnormal traffic through machine learning algorithms, and realize the transition from passive protection to active defense. The application of these technologies significantly improves the security baseline of the bus system. System-level security needs to consider the balance between performance and security. In the bus arbitration strategy, a security weight factor is introduced, and the device security level is included in the arbitration priority calculation to ensure low-latency transmission of critical security transactions. At the same time, through dynamic remapping of address space and labeled routing mechanism, flexible configuration and security isolation of the transmission path are realized.

[0003] Bus transmission anomalies can have serious cascading effects on the chip and the entire computing system. The consequences can be analyzed from three dimensions of function, performance, and reliability. At the functional level, transmission errors can cause critical data loss or instruction execution errors. For example, data anomalies on the memory access bus can cause the processor to read incorrect instructions or operands, which can cause application crashes or even system-level deadlocks. In safety-critical areas such as autonomous driving or medical devices, such anomalies can directly endanger personal safety. Deadlocks or livelocks caused by bus contention can disable the multi-core cooperation mechanism of the entire chip, and multiple processing units can be stuck in a state of resource contention. This systemic paralysis often requires hardware reset to recover. From a performance perspective, bus anomalies can significantly increase system latency and reduce throughput. When the bus matrix detects transmission errors, it usually needs to start a retransmission mechanism or wait for arbitration timeout, which introduces additional clock cycle overhead. In cache coherence protocols, bus transaction anomalies can trigger unnecessary cache line invalidation operations, causing a sharp rise in subsequent memory access delays. For real-time systems such as 5G baseband or industrial control, such delay fluctuations can directly cause the system to fail to meet timing constraints, causing task timeouts. More seriously, some bus errors can be mistakenly propagated and amplified. For example, a faulty DMA transmission can contaminate a large block of memory, and subsequent error correction operations will consume a lot of computing resources. In terms of reliability, the long-term accumulation of bus transmission anomalies can accelerate system aging and shorten chip life. Continuous bus contention and retransmission can cause related circuits to be in a high-load state, increasing power consumption and heat, which in turn affects transistor stability. Certain physical layer anomalies such as signal integrity degradation can cause metal migration effects, causing permanent damage to bus lines. In safety-critical scenarios, undetected hidden bus errors can lurk for a long time and eventually erupt at critical moments. This "silent failure" mode poses a great threat to system reliability. More alarmingly, maliciously constructed bus anomalies can be used as an entry point for hardware attacks. Through carefully designed error injection, security protection can be bypassed, and encryption keys or critical configuration registers can be stolen or tampered with.

[0004] In traditional high-performance bus transmission, when the master port initiates a transmission, it sends the selected slave port address. This address is decoded by combinational logic into a one-hot bit selection signal, which serves as the slave port selection signal. This signal is then sent to the bus matrix, which buffers the slave port selection signal along with other transmission signals from the master port. After arbitration and delay, the matrix selects the appropriate slave port based on the selected signal and completes the transmission. However, if the register buffering the slave port selection signal experiences a transient failure causing an abnormal flip, the transmission will be sent to the wrong slave port without triggering any alarms. This can lead to the fetching or writing of abnormal data, resulting in serious consequences. Existing technologies for high-performance bus security are solutions implemented independently at the software or hardware level. Furthermore, hardware-level solutions are often based on hardware redundancy rather than focusing on anomaly detection. Based on the above problems, this invention can detect and resolve transmission errors at both the hardware and software levels by starting from the perspective of the bus transmission mechanism itself, based on the specific exception type and its source. It can also independently operate on the bus and its bus matrix group mechanism, and detect transient failures caused by registers and loss or timeout errors in the bus transmission process caused by abnormal flips in a transparent manner for the bus, master and slave. It can be used independently or on the bus, has high flexibility and low additional hardware and software overhead, and is suitable for embedded chip design scenarios that require a high degree of hardware and software resource integration to improve chip performance. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention proposes a high-performance bus transmission security assurance method and system, the method comprising:

[0006] Step S1: Send the address information to the bus security unit and the bus matrix group;

[0007] Step S2: The decoding circuit decodes the address information into slave port and matrix selection signals, sends them to the bus matrix group to select the corresponding bus matrix and slave port, and sends them to the encoding circuit.

[0008] Step S3: The encoding circuit encodes the selection signal and sends it to the bus matrix group; the bus matrix group performs bit concatenation between the encoded selection signal and the address signal sent from the master port.

[0009] Step S4: Transmit based on the selected slave port and bus matrix; perform bit splitting on the bit-concatenated signal to obtain the encoded selection signal, and send it together with its own slave port number to the decoding circuit; send the address signal obtained by bit splitting to the slave device;

[0010] Step S5: The decoding circuit decodes the encoded selection signal and compares it with the pre-configured slave port number to determine if the slave port is consistent. If not, proceed to the next step; otherwise, it determines that the transmission is completed normally, and the slave responds to the monitoring counter corresponding to the slave port with a received signal. The monitoring counter compares the monitoring counter with the timeout threshold. If it exceeds the threshold, a transmission timeout error is reported and the monitoring counter is cleared. If no received signal is received, the counting continues until the loss threshold is reached, and a transmission loss error is reported.

[0011] Step S6: Send an error report to the operating system and / or send a bus error to the bus controller based on the error information; The operating system updates the number of timeout errors and / or the number of lost errors based on the error report and the type of execution involved, and triggers a system-level error response and / or reconfigures the address range and slave port mapping relationship based on the number of timeout errors and / or lost errors of the slave port; The bus controller performs a bus matrix reset in response to the bus error reset enable.

[0012] Furthermore, the transmission duration counting module in the bus security unit sets a monitoring counter for each slave port; when the master port initiates a transmission, in response to the counting trigger signal from the master, the monitoring counter in the bus security unit corresponding to that slave port starts counting, and the transmission duration is used to check whether there is a transmission timeout error or transmission loss error.

[0013] Furthermore, the monitoring threshold is configurable. After the bus security unit is enabled, the operating system writes the monitoring threshold into the register in the transmission duration counting module. The monitoring threshold includes a timeout threshold and a loss threshold, which are used to monitor transmission duration errors and transmission loss errors, respectively. The loss threshold is greater than the timeout threshold.

[0014] Furthermore, when the master port initiates a transmission via the bus, it encodes the selected slave port number and sends it to the slave port along with the transmission data. When the slave port receives the transmission data, it decodes the encoded slave port number and verifies it against its own preset number to determine whether a slave port error has occurred during the transmission.

[0015] Furthermore, the transmission request may originate from the operating system or from the application layer.

[0016] Furthermore, the operating system triggers system-level error responses and / or reconfigures the address range and slave port mapping based on the number of timeout errors and / or loss errors on the slave port; and reconfigures the correspondence between the slave port and the slave based on this reconfiguration operation;

[0017] Specifically, the steps include the following:

[0018] Step S11: The host determines the execution type of the transmission request; the execution type includes time-sensitive, loss-sensitive, reliability-sensitive, or other types;

[0019] Step S12: When the operating system receives an error report, it updates the number of timeout errors and / or lost errors on the slave port based on the execution body type. Specifically, it obtains the execution body corresponding to the transmission request and its corresponding execution body type based on the master port number, address information, and / or slave port number of the transmission error; it updates the number of timeout errors and / or lost errors based on the execution body type and error type; it pre-sets a correspondence table between the execution body type, error type, and update methods for the number of timeout errors and / or lost errors, obtains the update method by querying the correspondence table, and updates the number of timeout errors and / or lost errors based on the obtained update method.

[0020] Step S13: Determine whether the timeout error and / or data loss error exceed the tolerance threshold. If so, proceed to the next step.

[0021] Step S14: Trigger a system-level error response and / or reconfigure the address and slave port mapping relationship based on the number of timeout errors and / or loss errors on the slave port; and reconfigure the correspondence between the slave port and the slave device based on the reconfiguration operation;

[0022] The reconfiguration of the address and slave port mapping relationship based on the number of timeout errors and / or loss errors of the slave port specifically involves: obtaining the first mapping relationship between the address range involved in the slave port with the most timeout errors and / or loss errors and the slave port; obtaining the second mapping relationship between the address range involved in the slave port with the fewest timeout errors and / or loss errors and the slave port; and swapping the first mapping relationship and the second mapping relationship for reconfiguration.

[0023] A high-performance bus transmission security system is provided to implement the aforementioned high-performance bus transmission security method. The system includes a bus security unit, a master unit, slave units, and a bus matrix group composed of multiple bus matrices.

[0024] The bus security unit connects the host and slave devices; the bus security unit includes a transmission duration counting module, an address decoding circuit, an address mapping management circuit, an encoding circuit, a decoding circuit, an error reporting module, and a register;

[0025] The bus security unit sends the address information from the bus to the address decoding circuit to cooperate with the address mapping management circuit for decoding, and sends the decoded matrix / slave port selection signal to the bus matrix group and the encoding circuit.

[0026] The encoding circuit encodes the matrix / slave port selection signal to obtain the encoded port selection signal, which is then sent to the bus matrix group.

[0027] The decoding circuit receives the encoded port selection signal and the current slave port selection signal from the bus matrix group, compares the decoded slave port number with the pre-configured slave port number to determine whether the slave port is consistent. If they are inconsistent, a slave port error is determined to have occurred. When an error occurs, the error information is sent to the error reporting module and register.

[0028] The register receives and stores the configuration information for the bus security unit, and records the error information after the bus security unit detects an error;

[0029] The transmission duration counting module includes multiple monitoring counters, each of which corresponds to a master port and / or a slave port;

[0030] The bus matrix group is used to select the bus matrix and slave port based on the matrix / slave port selection signal, and to perform data transmission based on the selected slave port.

[0031] A high-performance bus transmission security assurance digital logic is provided, which is used to implement the above-mentioned high-performance bus transmission security assurance method.

[0032] A high-performance bus transmission security chip is provided, which is used to implement the above-mentioned high-performance bus transmission security method.

[0033] A high-performance bus transmission security protection circuit is provided, which is used to implement the above-mentioned high-performance bus transmission security protection method.

[0034] The beneficial effects of this invention include:

[0035] (1) It operates independently on the bus and its bus matrix group mechanism, and discovers the loss or timeout error in the bus transmission process caused by the transient failure of the register or its abnormal flip through the bus, master and slave in a transparent manner. It can be used independently or integrated with the bus, and has high flexibility and less additional hardware and software overhead.

[0036] (2) By reporting the discovered hardware-level errors to the operating system and bus controller layers through error reporting, a layered error handling mechanism is provided, which in turn supports the analysis of bus transmission errors at the operating system level. Based on the analysis results, the system-level error response and / or port reconfiguration opportunity is provided to the operating system layer and application layer execution entities. Through the reconfiguration of chip mapping logic, a better bus routing method is provided for important execution entities that are time-sensitive, loss-sensitive, and reliability-sensitive. Without replacing the main hardware, the reliability of the chip is improved, providing a strong guarantee for bus transmission and adapting to different functional safety requirements. Attached Figure Description

[0037] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to unduly limit the invention. In the drawings:

[0038] Figure 1 A schematic diagram of the high-performance bus transmission security assurance method provided by the present invention.

[0039] Figure 2 This is a schematic diagram of the high-performance bus transmission security system provided by the present invention.

[0040] Figure 3 This is a schematic diagram of the bus matrix structure provided by the present invention.

[0041] Figure 4 This is a schematic diagram of the error reporting module structure provided by the present invention. Detailed Implementation

[0042] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The illustrative embodiments and descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0043] This invention proposes a high-performance bus transmission security assurance method, as shown in the appendix. Figure 1 As shown, the method includes:

[0044] Step S1: Send address information from the master port; specifically: the host sends the address information to the bus security unit and then sends it to the bus matrix group through the master port;

[0045] Preferably, a monitoring counter is set for each slave port in the transmission duration counting module of the bus security unit; when the master port initiates a transmission, in response to the counting trigger signal from the host, the monitoring counter in the bus security unit corresponding to that slave port starts counting, and the transmission duration is used to check whether there is a bus transmission timeout or loss; the monitoring threshold is configurable, the operating system writes the monitoring threshold into a register, and after the bus security unit is enabled, the monitoring threshold in the register is written into the transmission duration counting module;

[0046] Preferably, the monitoring thresholds include a timeout threshold and a loss threshold, which are used to count transmission duration and transmission loss, respectively; the loss threshold is greater than the timeout threshold; the setting of the monitoring thresholds is related to the security requirements of the chip. When the chip requires high security, the timeout threshold and loss threshold are set to a lower value; otherwise, a relatively lenient setting can be made.

[0047] Alternative: Set monitoring thresholds individually for each slave port based on the slave type mapped to the port; when different slave types have different security requirements or time sensitivities, the monitoring thresholds can be set differently, but such settings will result in more on-chip resource overhead.

[0048] Preferred method: Trigger system-level error response and / or reconfigure address range and slave port mapping based on the number of timeout errors and / or loss errors of the slave port; and reconfigure the correspondence between the slave port and the slave based on the reconfiguration information; the specific reconfiguration timing can be one of the following: on a periodic basis, before the master port sends address information, after receiving an error report, or during bus matrix group idle time;

[0049] Specifically, the steps include the following:

[0050] Step S11: The host determines the execution type of the transmission request; the execution type includes time-sensitive, loss-sensitive, reliability-sensitive, and other types.

[0051] Preferably, the transmission request originates from the operating system or from the application layer;

[0052] Preferred execution types include: user processes / threads, kernel threads, interrupt handlers, DMA controllers, system calls, and hardware accelerators. Generally, user processes are set to a general type because time-sensitive and loss-sensitive events in applications may initiate transmission requests in other execution types. Therefore, even for executions with high security requirements, such as vehicle control, no special consideration is needed. Other execution types also have similar issues, which will not be elaborated here. Of course, the execution type can be refined in one step according to the protection requirements, thus setting differentiated execution types for application-level executions to provide differentiated security protections.

[0053] Step S12: When the operating system receives an error report, it updates the number of timeout errors and / or loss errors from the port based on the execution type.

[0054] Step S13: Determine whether the timeout error and / or data loss error exceed the tolerance threshold. If so, proceed to the next step.

[0055] Preferred: The tolerance threshold is a preset value; the tolerance threshold can be set to a large value, and can be further combined with other operating system monitoring data for joint settings; since the mapping relationship between the address range and the slave port is relatively fixed after configuration, and for time-sensitive and timeout-sensitive execution entities, their bus routing method can be regarded as logically fixed, and security can be achieved by remapping to break this inherent logical limitation.

[0056] Step S14: Trigger a system-level error response and / or reconfigure the address and slave port mapping relationship based on the number of timeout errors and / or loss errors on the slave port; and reconfigure the correspondence between the slave port and the slave device based on the reconfiguration information;

[0057] Preferred: Sending information that the error condition has exceeded the tolerance level to the operating system, such as the system-level error management unit in the operating system, and generating a system interrupt or system reset, slave port module-level reset, or reconfiguring the slave port based on the number of timeout errors and / or loss errors of the slave port;

[0058] The reconfiguration of address and slave port mapping based on the number of timeout errors and / or lost errors of slave ports specifically involves: obtaining the first mapping relationship between the address range and slave ports involved in the slave port with the most timeout errors and / or lost errors; obtaining the second mapping relationship between the address range and slave ports involved in the slave port with the fewest timeout errors and / or lost errors; and swapping the mapping relationships of the two for reconfiguration; that is, establishing a mapping relationship between the address range in the first mapping relationship and the slave ports in the second mapping relationship, and establishing a mapping relationship between the address range in the second mapping relationship and the slave ports in the first mapping relationship; this reconfiguration method is suitable for situations with low tolerance but small reconfiguration effort, requiring less configuration overhead and time;

[0059] The above describes the reconfiguration of the number of timeout errors and the number of lost errors respectively. However, since some lost errors are caused by timeout errors, the two can be considered together by weighted summation, and a unified exchange based on their weighted summation count can be performed.

[0060] Preferred methods include: reconfiguring mapping and correspondence relationships through dynamic remapping of registers on interconnect buses that support software-programmable address decoding, dynamic redirection of the MMU / IOMMU of CPUs or I / O devices that support virtual address translation, and reconfiguration of PCIeBAR that supports dynamic address allocation for PCIe devices.

[0061] The dynamic remapping via registers specifically involves: determining the configuration register for control address mapping in the bus matrix; writing a command to the control register to unbind the old address range from the slave port; and writing the base address and address range of the new address range to achieve dynamic configuration of the address range to the slave port.

[0062] Preferred approach: After reconfiguration is complete, trigger the synchronization barrier and verify the effectiveness of the new mapping through test access.

[0063] The dynamic redirection via MMU / IOMMU specifically involves: updating the page table of the MMU / IOMMU, mapping the virtual address to a new address range to correspond with different slave ports, and refreshing the TLB to invalidate the old address range translation cache;

[0064] The dynamic address allocation via PCIe device specifically involves: disabling the device by closing the device response through the PCI configuration space; modifying the BAR register by writing the base address of the new address range to point to the new slave port address; and reallocating the address space.

[0065] The reconfiguration of the correspondence between the slave port and the slave device based on the reconfiguration information specifically involves: sending a global abort signal through the bus arbitrator to clear all incomplete transmission requests associated with the slave port; modifying the control register of the slave port in the bus matrix to point to the new address range; and resetting the slave devices involved in the reconfiguration operation.

[0066] The restart of the bus matrix group specifically refers to: partially restarting the bus matrix group, re-enabling and reconfiguring the relevant parts of the bus matrix;

[0067] Step S2: The decoding circuit decodes the address information into a one-hot code as the slave port and matrix selection signal; it sends the slave port and matrix selection signal to the bus matrix group to select the corresponding bus matrix and slave port, and sends it to the encoding circuit at the same time;

[0068] Preferably, before proceeding to step S2, the host sends a transmission start signal to the corresponding monitoring counter;

[0069] Preferably, the one-hot code uses N bits to represent N different states, where only one bit is 1 and the rest are 0, for bit port selection;

[0070] Step S3: The encoding circuit encodes the slave port and matrix selection signals and sends them to the bus matrix group; the bus matrix group performs bit concatenation of the encoded slave port and / or matrix signals with the address signals sent from the master port.

[0071] Preferred: Each slave port is assigned a binary code that is unique to both the matrix number and the slave port number, based on the selected encoding type;

[0072] Step S4: The bus matrix group selects the bus matrix and slave port based on the slave port and matrix selection signals received from the decoding circuit; at the same time, it performs bit splitting on the received bit-concatenated encoded slave port and / or matrix signals and address signals to obtain the encoded matrix and / or slave port selection signals, and sends them together with its own slave port number (i.e., the current slave port number) to the decoding circuit; the address signal obtained from the bit splitting is sent to the slave device.

[0073] Preferred configuration: After the bus matrix group is enabled, the slave port number information is obtained and the slave port is pre-configured; while performing bit splitting, the selected slave port obtains the pre-configured slave port number information and sends it to the decoding circuit.

[0074] Preferred method: Read the slave port number information from the bus controller;

[0075] Preferred configuration: When a transmission signal is received from the bus matrix at the port, a bit splitting operation is triggered on the received bit-concatenated signal, splitting it into an address signal and an encoded slave port selection signal;

[0076] Step S5: Determine if a port error has occurred; if yes, proceed to the next step; otherwise, confirm that the transmission was completed normally.

[0077] The process of determining whether a slave port error has occurred is as follows: receiving a pre-configured slave port number sent by the slave port; the decoding circuit decodes the received encoded slave port / matrix selection signal; and compares the decoded slave port number with the pre-configured slave port number to determine whether the slave port is consistent. If they are inconsistent, a slave port error is determined to have occurred.

[0078] Preferred configuration: When the master port initiates a transmission via the bus, it encodes all selected slave port numbers and sends them to the slave ports together via the bus; when the slave port receives the transmitted data, it decodes the encoded slave port number and verifies it against its own preset number to determine whether a slave port error has occurred during transmission.

[0079] Preferred configuration: When the transmission from the slave port is completed normally, the slave device responds with a received signal to the monitoring counter corresponding to the slave port. Based on the received signal, the monitoring counter value is compared with the timeout threshold. If the timeout threshold is exceeded, a transmission timeout error is reported; at the same time, the monitoring counter is cleared. However, if the slave port does not receive a signal, the monitoring counter of the master port cannot be cleared due to the lack of signal. The monitoring counter continues to count until the loss threshold is reached, and a transmission loss error is reported.

[0080] Step S6: The error management module and registers receive the reported error information; the registers record the error information; the error management module sends an error report to the operating system and / or sends a bus error to the bus controller based on the information in the registers;

[0081] Preferably, the error information includes the master port number, address information, and slave port number where the transmission error occurred;

[0082] Preferred configuration: The error management module sends error reports when reporting conditions are met; the reporting conditions are: meeting the sending cycle requirement, register being full, and receiving enable information for each error report;

[0083] Preferably: the error management module sends an error report to the operating system by initiating an interrupt request; the operating system analyzes the error report to perform error handling; the bus controller re-enables the bus matrix in response to the bus error to perform a bus matrix reset; further: the bus controller has a built-in counter threshold, and re-enables the bus when the number of timeout errors and / or the number of data loss reaches the counter threshold;

[0084] The operating system analyzes the error report to perform error handling, specifically: the operating system records the number of timeout errors and / or the number of lost errors for each slave port; upon receiving the error report, the operating system updates the recorded number of timeout errors and / or the number of lost errors for each slave port based on the master port number, address information and / or slave port number and error type transmitted in the error report.

[0085] The update of the recorded number of timeout errors and / or number of lost errors corresponding to the slave port specifically involves: obtaining the execution body corresponding to the transmission request and its corresponding execution body type based on the master port number, address information, and / or slave port number of the transmission error; and updating the number of timeout errors and / or number of lost errors based on the execution body type and error type.

[0086] The update of timeout error count and / or lost error count based on execution body type and error type involves: pre-setting a correspondence table between execution body type, error type, and update methods for timeout error count and / or lost error count; obtaining the update method by querying the correspondence table; and performing the update based on the obtained update method. An example correspondence table is shown in the table below.

[0087] Table 1: Correspondence between execution type, error type, and update methods for timeout error count and / or missing error count;

[0088]

[0089] Of course, the granularity of the above updates can be configured according to the chip's aging level, usage frequency, and usage scenario; the example above is a unit update granularity.

[0090] This invention proposes a high-performance bus transmission security assurance method and system, wherein the system is used to implement the above method steps; as shown in the appendix. Figure 2 As shown, the high-performance bus transmission security system includes a bus security unit, a master unit, a slave unit, and a bus matrix group consisting of multiple bus matrices;

[0091] The bus security unit connects the host and slave devices; the bus security unit includes a transmission duration counting module, an address decoding circuit, an address mapping management circuit, an encoding circuit, a decoding circuit, an error reporting module, and a register;

[0092] Preferably, the bus security unit is integrated into the bus integration checker for use, or it is connected between the host and slave as a separate module in the form of a bus security unit by being mounted next to the bus port;

[0093] The bus security unit sends the address information from the bus to the address decoding circuit to cooperate with the address mapping management circuit for decoding, and sends the decoded matrix / slave port selection signal to the bus matrix group and the encoding circuit.

[0094] The encoding circuit encodes the matrix / slave port selection signal to obtain the encoded port selection signal, which is then sent to the bus matrix group.

[0095] The decoding circuit receives the encoded port selection signal and the current slave port selection signal from the bus matrix group, compares the decoded slave port number with the pre-configured slave port number to determine whether the slave port is consistent. If they are inconsistent, a slave port error is determined to have occurred. When an error occurs, the error information is sent to the error reporting module and register.

[0096] The transmission duration counting module includes multiple monitoring counters, each corresponding to a master port and / or a slave port; it is used to count the transmission duration when a counting trigger signal (transmission start signal) is received from the master, and to stop counting when a received signal (transmission delivery signal) is received from the slave; in the event of a timeout or loss, it sends a timeout or loss error to the error reporting module and register;

[0097] The bus matrix group is used to select the bus matrix and slave port based on the matrix / slave port selection signal, and to perform data transmission based on the selected slave port.

[0098] The register receives and stores the configuration information for the bus security unit, and records the error information after the bus security unit detects an error;

[0099] Preferred configuration: The address mapping management module is used to manage the address mapping. Based on the reconfiguration information, it provides management for the specific address mapping of the bus matrix. When the address range and slave port mapping relationship are reconfigured, the configuration information in the address mapping management module is modified based on the reconfiguration information, and the address decoding and connection allocation between the bus slave port and the sub-module are performed according to the configuration information of the address mapping management module.

[0100] As attached Figure 3As shown, each bus matrix in the bus matrix group contains multiple master ports and multiple slave ports, which are connected through the bus matrix group; it also includes a bit splicing module, a bus buffer / interaction module, and a bit splitting module; when the master port initiates a transmission, it splices the received encoded matrix / slave port selection signal with the address signal; the spliced ​​signal is sent into the bus matrix and sent to the selected slave port through the bus buffer / interaction module; after receiving the spliced ​​signal, the slave port performs bit splitting on the received address signal, splitting it into an address signal and an encoded matrix / slave port selection signal, and decodes the encoded matrix / slave port selection signal based on the slave port number pre-configured for the slave port to obtain the encoded slave port matrix / slave port selection signal for slave port error judgment;

[0101] Preferred configuration: Handling conflicts or caching data through a bus caching / interaction module, enabling concurrent management of multiple masters and slaves;

[0102] As attached Figure 4 As shown, the error reporting module receives error information and error reporting enable information, and sends the error report to the operating system or the bus error to the bus controller based on the error reporting enable information.

[0103] Preferably, the error report enable information comes from the bus controller or the operating system;

[0104] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of programming language, including assembly or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but does not necessarily, correspond to a file in a file system. A program can be stored as part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to said program, or in multiple co-located files (e.g., a file storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on a single computer or on multiple computers located at a single site or distributed across multiple sites and interconnected by a communications network.

[0105] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0106] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0107] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0108] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A high-performance bus transmission security assurance method, characterized in that, Include: Step S1: Send the address information to the bus security unit and the bus matrix group; Step S2: The decoding circuit decodes the address information into slave port and matrix selection signals, sends them to the bus matrix group to select the corresponding bus matrix and slave port, and sends them to the encoding circuit. Step S3: The encoding circuit encodes the selection signal and sends it to the bus matrix group; The bus matrix group performs bit-by-bit concatenation between the encoded selection signal and the address signal sent from the master port; Step S4: Transmit based on the selected slave port and bus matrix; perform bit splitting on the bit-concatenated signal to obtain the encoded selection signal, and send it together with its own slave port number to the decoding circuit; send the address signal obtained by bit splitting to the slave device; Step S5: The decoding circuit decodes the encoded selection signal and compares it with the pre-configured slave port number to determine if the slave port is consistent. If not, proceed to the next step; otherwise, it determines that the transmission is completed normally, and the slave responds to the monitoring counter corresponding to the slave port with a received signal. The monitoring counter compares the monitoring counter with the timeout threshold. If it exceeds the threshold, a transmission timeout error is reported and the monitoring counter is cleared. If no received signal is received, the counting continues until the loss threshold is reached, and a transmission loss error is reported. Step S6: Send an error report to the operating system and / or send a bus error to the bus controller based on the error information; The operating system updates the number of timeout errors and / or lost errors based on the error report and the type of execution involved, and triggers system-level error response and / or reconfigures address range and slave port mapping based on the number of timeout errors and / or lost errors from the slave port. The bus controller performs a bus matrix reset in response to a bus error reset enable.

2. The high-performance bus transmission security assurance method according to claim 1, characterized in that, The transmission duration counting module in the bus security unit sets a monitoring counter for each slave port. When the master port initiates a transmission, in response to the counting trigger signal from the master, the monitoring counter in the bus security unit corresponding to that slave port starts counting, and the transmission duration is used to check whether there is a transmission timeout error or transmission loss error.

3. The high-performance bus transmission security assurance method according to claim 2, characterized in that, The monitoring threshold is configurable. After the bus security unit is enabled, the operating system writes the monitoring threshold into the register in the transmission duration counting module. The monitoring threshold includes a timeout threshold and a loss threshold, which are used to monitor transmission duration errors and transmission loss errors, respectively. The loss threshold is greater than the timeout threshold.

4. The high-performance bus transmission security assurance method according to claim 3, characterized in that, When the master port initiates a transmission via the bus, it encodes the selected slave port number and sends it to the slave port along with the transmission data. When the slave port receives the transmission data, it decodes the encoded slave port number and verifies it against its own preset number to determine whether a slave port error has occurred during the transmission.

5. The high-performance bus transmission security assurance method according to claim 4, characterized in that, The transmission request originates from the operating system or from the application layer.

6. The high-performance bus transmission security assurance method according to claim 5, characterized in that, The operating system triggers a system-level error response and / or reconfigures the address range and slave port mapping based on the number of timeout errors and / or loss errors on the slave port; and reconfigures the correspondence between the slave port and the slave based on the reconfiguration operation; Specifically, the steps include the following: Step S11: The host determines the execution type of the transmission request; the execution type includes time-sensitive, loss-sensitive, reliability-sensitive, or other types; Step S12: When the operating system receives an error report, it updates the number of timeout errors and / or the number of lost errors on the slave port based on the execution type; Specifically, this involves: obtaining the execution body corresponding to the transmission request and its corresponding execution body type based on the main port number, address information, and / or port number of the transmission error; and updating the number of timeout errors and / or the number of lost errors based on the execution body type and error type. A pre-defined mapping table is set up between execution type, error type, and update method for timeout error count and / or lost error count. The update method is obtained by querying the mapping table, and the timeout error count and / or lost error count are updated based on the obtained update method. Step S13: Determine whether the timeout error and / or data loss error exceed the tolerance threshold. If so, proceed to the next step. Step S14: Trigger system-level error response and / or reconfigure address and slave port mapping based on the number of timeout errors and / or loss errors on the slave port; And based on this reconfiguration operation, the mapping between the slave port and the slave device is reconfigured; The reconfiguration of the address and slave port mapping relationship based on the number of timeout errors and / or lost errors of the slave port specifically involves: obtaining the address range involved in the slave port with the most timeout errors and / or lost errors and the first mapping relationship between the slave port and the slave port; obtaining the address range involved in the slave port with the fewest timeout errors and / or lost errors and the second mapping relationship between the slave port and the slave port. Swap the first and second mapping relationships for reconfiguration.

7. A high-performance bus transmission security system, characterized in that, The high-performance bus transmission security system is used to implement the high-performance bus transmission security method as described in any one of claims 1-6; the system includes a bus security unit, a master unit, a slave unit, and a bus matrix group composed of multiple bus matrices; The bus security unit connects the host and slave devices; the bus security unit includes a transmission duration counting module, an address decoding circuit, an address mapping management circuit, an encoding circuit, a decoding circuit, an error reporting module, and a register; The bus security unit sends the address information from the bus to the address decoding circuit, which works with the address mapping management circuit to perform decoding, and sends the decoded matrix / slave port selection signal to the bus matrix group and the encoding circuit. The encoding circuit encodes the matrix / slave port selection signal to obtain the encoded port selection signal, which is then sent to the bus matrix group. The decoding circuit receives the encoded port selection signal and the current slave port selection signal from the bus matrix group, compares the decoded slave port number with the pre-configured slave port number to determine whether the slave port is consistent. If they are inconsistent, a slave port error is determined to have occurred. And when an error occurs, the error information is sent to the error reporting module and registers; The register receives and stores the configuration information for the bus security unit, and records the error information after the bus security unit detects an error; The transmission duration counting module contains multiple monitoring counters, each corresponding to a master port and / or a slave port; The bus matrix group is used to select the bus matrix and slave port based on the matrix / slave port selection signal, and to perform data transmission based on the selected slave port.

8. A high-performance bus transmission security chip, characterized in that, The high-performance bus transmission security chip is used to implement the high-performance bus transmission security method as described in any one of claims 1-6.

9. A high-performance bus transmission security protection circuit, characterized in that, The high-performance bus transmission security protection circuit is used to implement the high-performance bus transmission security protection method according to any one of claims 1-6.

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