Bit error rate determination method, data recovery method, device, equipment and medium

Abstract

The invention discloses a bit error rate determination method, a data recovery method and device, equipment and a medium, and relates to the technical field of flash memories. And based on the mark mapping relationship, determining target initial mark data corresponding to the target mark address. And then based on the target initial labeled data and the labeled data to be compared, calculating to obtain a labeled bit error rate of the labeled data. Error codes in the physical page are uniformly distributed, so that the marked error rate between the target initial marked data and the marked data to be compared can be used as the error rate of the physical page, and the marked error rate can be used for determining whether the rereading voltage meets the requirement or not in the data recovery process so as to assist the data recovery process. And the marked bit error rate is obtained by comparing the target initial marked data with the to-be-compared marked data, and compared with a traditional technology of calculating the bit error rate through all data of a physical page, the method is high in calculation speed and high in efficiency, so that the duration of a data recovery process can be shortened, and the data recovery efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of flash memory technology, and in particular to a method for determining a bit error rate, a data recovery method, an apparatus, a device, and a medium. Background Art

[0002] Flash memory chips are widely used today, offering excellent properties such as high speed and non-volatility. Data is stored internally in the form of electrical charge. During actual use, the amount of stored charge fluctuates due to various internal and external conditions. If this variation accumulates to a certain level, accessing the flash memory using the default read operation may result in incorrect data.

[0003] If a silent read fails, a data recovery process is performed to re-determine the flash memory's read voltage. During this data recovery process, the flash memory chip's original manufacturer typically provides a reread table. This table is then traversed to recover the data, attempting to read at the voltages in the table. The bit error rate is calculated after each read until the bit error rate meets the requirements. Related technologies typically calculate the bit error rate by comparing all data stored in the flash memory's physical pages with the original data. This is time-consuming and inefficient, resulting in a long and inefficient data recovery process. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method for determining a bit error rate, a data recovery method, an apparatus, a device, and a medium, which can quickly and efficiently determine the bit error rate of a flash memory, thereby reducing the time required for the data recovery process and improving the efficiency of data recovery.

[0005] According to a method for determining a bit error rate according to an embodiment of the first aspect of the present application, the method is applied to a flash memory, and the method includes: In response to detecting that a first read operation on the flash memory fails, obtaining a reread voltage and an operation address in the first read operation; Determining a target tag address corresponding to the operation address in the first read operation based on a pre-generated tag mapping relationship; wherein the tag mapping relationship records a correspondence between multiple operation addresses and multiple tag addresses; performing a second read operation on the flash memory based on the target tag address and the reread voltage to obtain tag data to be compared from a physical page of the flash memory; Based on the tag mapping relationship, determining the target initial tag data corresponding to the target tag address; wherein the tag mapping relationship further records the correspondence between multiple initial tag data and multiple tag addresses; A marking error rate of the marking data is calculated based on the target initial marking data and the target marking data.

[0006] The bit error rate determination method according to the embodiment of the present application has at least the following beneficial effects: When the bit error rate determination method of the embodiment of the present application detects that a first read operation on a flash memory fails, indicating that the flash memory data cannot be properly read using the default voltage of the flash memory, a reread voltage and the operation address in the first read operation are obtained. Based on a pre-generated tag mapping relationship, a target tag address corresponding to the operation address in the first read operation is determined. A second read operation is performed on the flash memory based on the target tag address and the reread voltage to obtain tag data to be compared from a physical page of the flash memory. Based on the tag mapping relationship, target initial tag data corresponding to the target tag address is determined. A tag bit error rate of the tag data is then calculated based on the target initial tag data and the tag data to be compared. Since the bit errors within a physical page are uniformly distributed, the tag bit error rate between the target initial tag data and the tag data to be compared can be used as the bit error rate of the physical page. The tag bit error rate can be used to determine whether the reread voltage meets the requirements during data recovery, thereby assisting the data recovery process. The mark bit error rate is obtained by comparing the target initial mark data with the mark data to be compared. Compared with the traditional technology that calculates the bit error rate through all the data of the physical page, the mark bit error rate calculation speed of this application is fast and efficient, which can reduce the duration of the data recovery process and improve the efficiency of data recovery.

[0007] According to some embodiments of the present application, before acquiring the reread voltage and the operation address in the first read operation in response to detecting that the first read operation on the flash memory fails, the method further includes: In response to detecting a write operation to the flash memory, obtaining an operation address of the write operation; Calculating a tag address based on the operation address of the write operation; generating the initial marking data; Establishing the mapping relationship between the initial tag data, the operation address of the write operation and the tag address to obtain the tag mapping relationship; The initial tag data is written into the tag address of the flash memory.

[0008] According to some embodiments of the present application, the calculating the tag address based on the operation address of the write operation includes: The offset address is calculated based on an address calculation formula, and the tag address is obtained based on the operation address of the write operation and the offset address; the address calculation formula is: L=(chip_no*pages_per_chip+block_no*pages_per_block+page_no)*Large_prime%page_length; Wherein, L is the offset address, chip_no is the flash memory number, pages_per_chip is the total number of physical pages in the flash memory, block_no is the physical block number in the operation address of the write operation, pages_per_block is the total number of physical pages in the physical block, page_no is the physical page number in the operation address of the write operation, large_prime is a preset prime number, and page_length is the length of the physical page.

[0009] According to some embodiments of the present application, obtaining the reread voltage includes: obtaining a read voltage of the first read operation; The re-read voltage is obtained from a preset re-read voltage table based on the read voltage, wherein the re-read voltage is greater than or less than the read voltage of the first read operation.

[0010] According to some embodiments of the present application, the calculating the tag address based on the operation address of the write operation includes: determining a physical page to be written based on an operation address of the write operation; The tag address is randomly generated based on the physical page to be written; wherein the tag address is within the physical page to be written.

[0011] A second aspect of the present application provides a data recovery method, which is applied to a flash memory. The method includes the bit error rate determination method as described in any one of the first aspect of the present application; Also includes: Detecting the marking bit error rate; When it is detected that the marked bit error rate is less than the preset bit error threshold, the reread voltage is used as a target read voltage of the flash memory, and the first read operation is re-performed on the flash memory based on the target read voltage to obtain first target recovered data; The first target recovery data is corrected by an error correction code module to obtain second target recovery data.

[0012] According to some embodiments of the present application, after detecting the mark bit error rate, the method further includes: When it is detected that the mark error rate is greater than or equal to the preset error threshold, the reread voltage is updated, and the process jumps to performing a second read operation on the flash memory based on the mark address and the reread voltage to obtain target mark data from the physical page of the flash memory.

[0013] A third aspect of the present application provides a device for determining a bit error rate, which is applied to a flash memory. The device includes: a first acquiring module, configured to acquire a reread voltage and an operation address in response to detecting that a first read operation on the flash memory fails; A first determining module is configured to determine a target tag address corresponding to an operation address in the first read operation based on a pre-generated tag mapping relationship, wherein the tag mapping relationship records a correspondence between a plurality of operation addresses and a plurality of tag addresses; a second acquisition module, configured to perform a second read operation on the flash memory based on the target tag address and the reread voltage, so as to acquire tag data to be compared from a physical page of the flash memory; A second determining module is configured to determine target initial tag data corresponding to the target tag address based on the tag mapping relationship; wherein the tag mapping relationship further records a correspondence between a plurality of initial tag data and a plurality of tag addresses; The calculation module is used to calculate the marking error rate of the marked data based on the target initial marked data and the marked data to be compared.

[0014] An embodiment of the fourth aspect of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the bit error rate determination method described in any one of the embodiments of the first aspect, or the data recovery method described in any one of the embodiments of the second aspect.

[0015] The fifth aspect embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the bit error rate determination method described in any one of the first aspect embodiments, or the data recovery method described in any one of the second aspect embodiments.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present application is further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 This is a flowchart of the steps of the method for determining the bit error rate according to an embodiment of the present application; Figure 2 This is a flowchart of a step before step S110 of the method for determining the bit error rate according to an embodiment of the present application; Figure 3 A schematic diagram of a sub-process of the data recovery method according to an embodiment of the present application; Figure 4 A schematic diagram of a specific flow chart of the data recovery method according to an embodiment of the present application; Figure 5 This is a module block diagram of a bit error rate determination device according to an embodiment of the present application; Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0019] In the description of this application, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0020] In the description of this application, "several" means more than one, "plurality" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0021] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0022] In the description of this application, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples.

[0023] NAND Flash chips are widely used today, offering excellent properties such as high speed and non-volatility. Data is stored internally in the form of electrical charge. During actual use, various internal and external conditions can cause the amount of stored charge to fluctuate. If this variation accumulates to a certain level, accessing the flash memory using the default read operation may result in incorrect data. Generally, NAND Flash manufacturers allow for adjustment of the read voltage used to determine the cell state. This adjustment can help recover the correct data, a process known as read retry. During use, NAND Flash products can experience fluctuations in the number of electrons within the cell due to internal and external environmental conditions, making it impossible to retrieve correct data using the default read voltage. Manufacturers typically provide multiple read retry methods to adjust the read voltage to recover data.

[0024] If a silent read fails, a data recovery process is performed to re-determine the flash memory's read voltage. During the data recovery process, the flash memory chip's original manufacturer typically provides a reread table. This table is traversed to recover the data, and attempts are made to read at the voltage in the reread table. The bit error rate is calculated after each read until the bit error rate meets the requirements. Related technologies typically compare all data stored in the flash memory's physical pages with the original data when calculating the bit error rate. This is time-consuming and inefficient, resulting in a long and inefficient data recovery process and very high data read latency.

[0025] Based on this, the present application provides a bit error rate determination method, data recovery method, device, equipment and medium, which can quickly determine the bit error rate of the flash memory with high efficiency, thereby reducing the duration of the data recovery process, improving the efficiency of data recovery, and thus reducing the delay in data reading of the flash memory.

[0026] The first embodiment of the present application provides a method for determining a bit error rate. The method for determining a bit error rate in the embodiment of the present application can be applied to a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, etc. The server can be configured as an independent physical server, or as a server cluster or distributed system composed of multiple physical servers. It can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application that implements the method for determining a bit error rate, etc., but is not limited to the above forms.

[0027] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments in which tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media, including storage devices.

[0028] Reference Figure 1 , Figure 1 The method for determining the bit error rate according to the embodiment of the present application is applied to a flash memory and includes but is not limited to steps S110 to S150.

[0029] Step S110 , in response to detecting that the first read operation on the flash memory fails, obtaining a reread voltage and an operation address in the first read operation; It is worth noting that the operation address in the first read operation refers to the data read address, which can indicate the specific location of the data to be read. The operation address in the first read operation can be used to determine the physical page of the data to be read. For example, the operation address in the first read operation includes the flash memory number, physical page number, and physical block number.

[0030] It should be noted that an error correction code (ECC) module is provided in the flash memory or the system in which the flash memory is applied. When the first read operation is performed, the flash memory is read based on the operation address in the first read operation to obtain the read data, and then the error correction code module performs error correction verification on the read data. When the error correction code module determines that the read data cannot pass the error correction verification, that is, the verification fails, it is deemed that the first read operation has failed.

[0031] It should be noted that the Error Correction Code (ECC) module is the core reliability engine of the NAND Flash storage system. Its function is to detect and correct bit errors caused by physical mechanisms (charge leakage, read / write interference, noise, etc.) in real time by adding redundant check information to the data.

[0032] Step S120: determining a target tag address corresponding to the operation address in the first read operation based on a pre-generated tag mapping relationship; wherein the tag mapping relationship records a correspondence between a plurality of operation addresses and a plurality of tag addresses; In some embodiments, the tag mapping relationship records the correspondence between each physical page and the tag address. When the operation address in the first read operation is obtained, the physical page corresponding to the first read operation is determined, and then the tag address corresponding to the physical page is determined from the tag mapping relationship as the target tag address, thereby obtaining the target tag address.

[0033] Step S130 , performing a second read operation on the flash memory based on the target tag address and the reread voltage to obtain tag data to be compared from the physical page of the flash memory; It should be noted that the tag data is pre-stored in the tag address corresponding to the physical page. Therefore, in step S130, a second read operation is performed on the flash memory based on the target tag address and the reread voltage to obtain the tag data to be compared from the physical page indicated by the operation address of the first read operation.

[0034] Step S140: determining target initial tag data corresponding to the target tag address based on the tag mapping relationship; wherein the tag mapping relationship further records the correspondence between the plurality of initial tag data and the plurality of tag addresses; Step S150 : calculating a marking error rate of the marked data based on the target initial marked data and the marked data to be compared.

[0035] Specifically, the target initial marked data is compared with the marked data to be compared one by one to obtain the marked bit error rate. Exemplarily, the target initial marked data is compared with the marked data to be compared one by one to obtain the number of erroneous bits in the marked data to be compared, and the number of erroneous bits is divided by the total number of bits in the target initial marked data to obtain the marked bit error rate.

[0036] It is worth noting that the bit error rate determination method of the embodiment of the present application, through the above-mentioned steps S110 to S150, when it is detected that the first read operation on the flash memory fails, it means that the data of the flash memory cannot be read normally at the default voltage of the flash memory, so the reread voltage and the operation address in the first read operation are obtained, and based on the pre-generated tag mapping relationship, the target tag address corresponding to the operation address in the first read operation is determined. A second read operation is performed on the flash memory based on the target tag address and the reread voltage to obtain the tag data to be compared from the physical page of the flash memory, and based on the tag mapping relationship, the target initial tag data corresponding to the target tag address is determined. Then, based on the target initial tag data and the tag data to be compared, the tag bit error rate of the tag data is calculated. Since the bit errors within the physical page are evenly distributed, the tag bit error rate between the target initial tag data and the tag data to be compared can be used as the bit error rate of the physical page. The tag bit error rate can be used to determine whether the reread voltage meets the requirements during the data recovery process, thereby assisting the data recovery process. The mark bit error rate is obtained by comparing the target initial mark data with the mark data to be compared. Compared with the traditional technology that calculates the bit error rate based on the entire data of the physical page, the mark bit error rate calculation method of the present application is fast and efficient. It reduces the decoding time consumption of the invalid error correction code module, thereby reducing the length of the data recovery process, improving the efficiency of data recovery, and thus reducing the delay of data reading in the flash memory.

[0037] In some embodiments, reference Figure 2 , Figure 2 This is a flowchart of a step before step S110 of the bit error rate determination method according to an embodiment of the present application. Before step S110, steps S210 to S250 may also be included.

[0038] Step S210, in response to detecting a write operation to the flash memory, obtaining an operation address of the write operation; It's worth noting that a write operation is used to write data to the flash memory. The write operation address includes the flash memory number, physical page number, and physical block number. The flash memory number refers to the flash memory chip number.

[0039] Step S220, calculating a tag address based on the operation address of the write operation; In some embodiments, step S220 specifically includes step S221 and step S222.

[0040] Step S221, determining the physical page to be written based on the operation address of the write operation; Step S222 : randomly generating a tag address based on the physical page to be written; wherein the tag address is within the physical page to be written.

[0041] For example, the physical page to which the data to be stored is written is determined using the physical block number and physical page number in the write operation address, and then the tag address is determined on that physical page. For example, after the data to be stored is written, the remaining storage space of the physical page to which the data to be stored is written can be determined, and an address that matches a preset length can be randomly selected from the remaining storage space as the tag address. It is worth noting that the preset length is less than the length of the data to be stored.

[0042] Step S230, generating initial marking data; It is worth noting that the initial tag data can be a randomly generated sequence, and the data length of the initial tag data is equal to the preset length. In this way, different tag data can be written to each physical page, ensuring the randomness of the tag data within the physical block. In some embodiments, the preset length is 200 bits.

[0043] Step S240, establishing a mapping relationship between the initial tag data, the operation address of the write operation and the tag address to obtain a tag mapping relationship; In some embodiments, the tag mapping relationship is obtained by recording the initial tag data, the correspondence between the operation address of the write operation, and the tag address. In other embodiments, the tag mapping relationship is obtained by recording the correspondence between the initial tag data, the physical page indicated by the operation address of the write operation, and the tag address. Generating the tag mapping relationship facilitates determining the target tag address corresponding to the operation address in the first read operation in step S120 and also facilitates determining the target initial tag data corresponding to the target tag address in step S140.

[0044] Step S250: writing the initial tag data into the tag address of the flash memory.

[0045] It is worth noting that the bit error rate determination method of the embodiment of the present application, through steps S210 to S250, when performing a write operation, not only writes the data to be stored to the physical page of the flash memory, but also writes the initial mark data to the physical page, and establishes a mapping relationship between the initial mark data, the operation address of the write operation and the mark address, and obtains a mark mapping relationship, so that when the data recovery process needs to be performed, the bit error rate of the physical page can be quickly evaluated based on the initial mark data.

[0046] In some embodiments, step S220 specifically includes: The offset address is calculated based on the address calculation formula, and the tag address is obtained based on the operation address and the offset address of the write operation. The address calculation formula is: L=(chip_no*pages_per_chip+block_no*pages_per_block+page_no)*Large_prime%page_length; Where L is the offset address, chip_no is the flash memory number in the operation address of the write operation, pages_per_chip is the total number of physical pages in the flash memory, block_no is the physical block number in the operation address of the write operation, pages_per_block is the total number of physical pages in the physical block, page_no is the physical page number in the operation address of the write operation, large_prime is a preset prime number, and page_length is the length of the physical page.

[0047] It is worth noting that the offset address is calculated using the address calculation formula, and then the operation address of the write operation and the offset address are added to obtain the tag address. For example, the operation address of the write operation is added to the offset address to obtain the tag address. In this way, the tag address corresponding to each physical page is different, which can avoid the data distribution in the physical block not meeting the randomization requirements. In other embodiments, the same purpose can be achieved by writing different tag data in each physical page. A similar purpose can also be achieved by splitting the tag data into sequences of smaller lengths and writing them to different offset addresses in the physical page.

[0048] It should be noted that the length of the marker data is smaller than the length of the corresponding data to be stored. According to the characteristics of flash memory, the bit errors in a page are basically evenly distributed, so the bit errors of the entire physical page can be evaluated by the bit errors of the marker data.

[0049] In some embodiments, obtaining the re-read voltage in step S110 may include step S111 and step S112 .

[0050] Step S111, obtaining a read voltage of a first read operation; Step S112 : obtaining a re-read voltage from a preset re-read voltage table based on the read voltage, wherein the re-read voltage is greater than or less than the read voltage of the first read operation.

[0051] It is worth noting that each flash memory chip is preset with a reread voltage table. The read voltage for the first read operation is generally the default read voltage of the flash memory chip. If the first read operation fails, it indicates that the read voltage of the first read operation cannot read data, so the read voltage needs to be changed. The reread voltage is obtained from the preset reread voltage table. The reread voltage is not the same as the read voltage. It should be noted that the reread voltage table records multiple voltages and can be preset by the flash memory chip manufacturer or by those skilled in the art based on actual conditions.

[0052] The second embodiment of the present application provides a data recovery method. The data recovery method is applied to a flash memory, and the data recovery method includes the bit error rate determination method of the first embodiment. Figure 3 , Figure 3 This is a schematic diagram of a sub-process of the data recovery method according to an embodiment of the present application. Figure 3 The illustrated process includes steps S310 to S330.

[0053] Step S310, detecting the mark bit error rate; Step S320, when it is detected that the marked bit error rate is less than a preset bit error threshold, using the reread voltage as a target read voltage of the flash memory, and re-performing the first read operation on the flash memory based on the target read voltage to obtain first target recovered data; It should be noted that the preset error threshold can be set according to the error correction code module. When the marked error rate is less than the preset error threshold, the error correction code module can correct the data. When the marked error rate is greater than or equal to the preset error threshold, the error correction code module cannot correct the data.

[0054] Step S330: Correct the first target recovered data using an error correction code module to obtain second target recovered data.

[0055] In some embodiments, reference Figure 4 , Figure 4 This is a schematic diagram of a specific flow chart of the data recovery method according to an embodiment of the present application. Figure 4 The illustrated process includes steps S110 to S150, and also includes steps S310 to S330. Specifically, the mark bit error rate is first calculated through steps S110 to S150, and then the second target recovery data is obtained through steps S310 to S330, thereby realizing the data recovery process. In this process, the mark bit error rate is obtained by comparing the target initial mark data with the mark data to be compared. Compared with the traditional technology of calculating the bit error rate based on the entire data of the physical page, the mark bit error rate calculation speed of the present application is fast and efficient, thereby reducing the duration of the data recovery process and improving the efficiency of data recovery.

[0056] In some embodiments, after detecting the mark bit error rate in step S310, the following steps are further included: When it is detected that the mark error rate is greater than or equal to the preset error threshold, the reread voltage is updated and the process jumps to step S130 to perform a second read operation on the flash memory based on the mark address and the reread voltage to obtain the mark data to be compared from the physical page of the flash memory.

[0057] Specifically, if the marked bit error rate is greater than or equal to the preset bit error threshold, it indicates that the current reread voltage does not meet the requirements, and therefore the reread voltage needs to be updated. For example, a new voltage is selected from the reread voltage table as the new reread voltage, and the process jumps to step S130. The reread voltage table is traversed in this manner, with a new voltage selected as the new reread voltage each time the table is executed, until the marked bit error rate is less than the preset bit error threshold. When every voltage in the reread voltage table is selected and the marked bit error rate is still greater than or equal to the preset bit error threshold, an error alarm is generated and sent to the relevant terminal.

[0058] It should be noted that, since the data recovery method of the second embodiment includes the bit error rate determination method of the first embodiment, the specific implementation methods and beneficial effects of the bit error rate determination method of the first embodiment are applicable to the data recovery method of the second embodiment.

[0059] The third aspect of the present application provides a bit error rate determination device, which is applied to a flash memory. Figure 5 , Figure 5 This is a block diagram of a bit error rate determination device according to an embodiment of the present application. The bit error rate determination device includes: A first acquisition module 510 is configured to acquire a reread voltage and an operation address in the first read operation in response to detecting that the first read operation on the flash memory fails; A first determining module 520 is configured to determine a target tag address corresponding to an operation address in the first read operation based on a pre-generated tag mapping relationship, wherein the tag mapping relationship records a correspondence between multiple operation addresses and multiple tag addresses; A second acquisition module 530 is configured to perform a second read operation on the flash memory based on the target tag address and the reread voltage to obtain tag data to be compared from a physical page of the flash memory; A second determining module 540 is configured to determine target initial tag data corresponding to a target tag address based on the tag mapping relationship; wherein the tag mapping relationship further records a correspondence between a plurality of initial tag data and a plurality of tag addresses; The calculation module 550 is configured to calculate a marking error rate of the marked data based on the target initial marked data and the marked data to be compared.

[0060] The bit error rate determination device of the third embodiment of the present application is used to perform the bit error rate determination method of the first embodiment. When executing the method, when it is detected that the first read operation on the flash memory fails, it indicates that the data of the flash memory cannot be normally read using the default voltage of the flash memory. Therefore, a reread voltage and the operation address in the first read operation are obtained. Based on a pre-generated tag mapping relationship, a target tag address corresponding to the operation address in the first read operation is determined. A second read operation is performed on the flash memory based on the target tag address and the reread voltage to obtain the tag data to be compared from the physical page of the flash memory. Based on the tag mapping relationship, the target initial tag data corresponding to the target tag address is determined. Then, based on the target initial tag data and the tag data to be compared, a tag bit error rate of the tag data is calculated. Since the bit errors within the physical page are uniformly distributed, the tag bit error rate between the target initial tag data and the tag data to be compared can be used as the bit error rate of the physical page. The tag bit error rate can be used to determine whether the reread voltage meets the requirements during data recovery, thereby assisting the data recovery process. The mark bit error rate is obtained by comparing the target initial mark data with the mark data to be compared. Compared with the traditional technology that calculates the bit error rate through all the data of the physical page, the mark bit error rate calculation speed of this application is fast and efficient, which can reduce the duration of the data recovery process and improve the efficiency of data recovery.

[0061] It should be noted that the specific implementation of the bit error rate determination device is basically the same as the specific implementation of the bit error rate determination method in the above embodiment, and will not be repeated here. On the premise of meeting the requirements of the embodiment of this application, the bit error rate determination device can also be provided with other functional modules to implement the bit error rate determination method in the above embodiment.

[0062] In a fourth aspect, an embodiment of the present application provides an electronic device comprising a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the bit error rate determination method of the above embodiment. The electronic device can be any smart terminal, such as a tablet computer or an in-vehicle computer.

[0063] In one embodiment, referring to Figure 6 , Figure 6 The hardware structure of the electronic device according to the embodiment of the present application is shown. The electronic device includes: The processor 601 may be implemented as a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application. The memory 602 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 602 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 602 and is called by the processor 601 to execute the bit error rate determination method of the first embodiment of the present application or the data recovery method of the second embodiment of the present application; Input / output interface 603, used to implement information input and output; Communication interface 604, used to implement communication interaction between this device and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WiFi, Bluetooth, etc.); Bus 605 , which transmits information between various components of the device (e.g., processor 601 , memory 602 , input / output interface 603 , and communication interface 604 ); The processor 601 , the memory 602 , the input / output interface 603 and the communication interface 604 are connected to each other in communication within the device via a bus 605 .

[0064] The fifth aspect of the present application is a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the bit error rate determination method of the first aspect or the data recovery method of the second aspect.

[0065] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0066] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0067] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0068] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0069] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0070] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0071] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0072] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the above units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0073] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0074] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0075] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: various media that can store programs, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0076] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A method for determining a bit error rate, characterized in that: Applied to flash memory, the method includes: In response to detecting that a first read operation on the flash memory fails, obtaining a reread voltage and an operation address in the first read operation; Determining a target tag address corresponding to the operation address in the first read operation based on a pre-generated tag mapping relationship; wherein the tag mapping relationship records a correspondence between multiple operation addresses and multiple tag addresses; performing a second read operation on the flash memory based on the target tag address and the reread voltage to obtain tag data to be compared from a physical page of the flash memory; Based on the tag mapping relationship, determining the target initial tag data corresponding to the target tag address; wherein the tag mapping relationship further records the correspondence between multiple initial tag data and multiple tag addresses; A marking error rate of the marked data is calculated based on the target initial marked data and the marked data to be compared.

2. The method for determining the bit error rate according to claim 1, wherein: Before acquiring the reread voltage and the operation address in the first read operation in response to detecting that the first read operation on the flash memory fails, the method further includes: In response to detecting a write operation to the flash memory, obtaining an operation address of the write operation; Calculating a tag address based on the operation address of the write operation; generating the initial marking data; Establishing a mapping relationship between the initial tag data, the operation address of the write operation, and the tag address to obtain the tag mapping relationship; The initial tag data is written into the tag address of the flash memory.

3. The method for determining the bit error rate according to claim 2, wherein: The calculating of the tag address based on the operation address of the write operation includes: The offset address is calculated based on an address calculation formula, and the tag address is obtained based on the operation address of the write operation and the offset address; the address calculation formula is: L=(chip_no*pages_per_chip+block_no*pages_per_block+page_no)*Large_prime%page_length; Wherein, L is the offset address, chip_no is the flash memory number, pages_per_chip is the total number of physical pages in the flash memory, block_no is the physical block number in the operation address of the write operation, pages_per_block is the total number of physical pages in the physical block, page_no is the physical page number in the operation address of the write operation, large_prime is a preset prime number, and page_length is the length of the physical page.

4. The method for determining the bit error rate according to claim 1, wherein: The obtaining of the reread voltage includes: obtaining a read voltage of the first read operation; The re-read voltage is obtained from a preset re-read voltage table based on the read voltage, wherein the re-read voltage is greater than or less than the read voltage of the first read operation.

5. The method for determining the bit error rate according to claim 2, wherein: The calculating of the tag address based on the operation address of the write operation includes: determining a physical page to be written based on an operation address of the write operation; The tag address is randomly generated based on the physical page to be written; wherein the tag address is within the physical page to be written.

6. A data recovery method, characterized in that: Applied to flash memory, the method comprises the bit error rate determination method according to any one of claims 1 to 5; Also includes: Detecting the marking bit error rate; When it is detected that the marked bit error rate is less than a preset bit error threshold, the reread voltage is used as a target read voltage of the flash memory, and the first read operation is re-performed on the flash memory based on the target read voltage to obtain first target recovered data; The first target recovery data is corrected by an error correction code module to obtain second target recovery data.

7. The data recovery method according to claim 6, characterized in that: After detecting the mark bit error rate, the method further includes: When it is detected that the mark error rate is greater than or equal to the preset error threshold, the reread voltage is updated, and the process jumps to performing a second read operation on the flash memory based on the mark address and the reread voltage to obtain the mark data to be compared from the physical page of the flash memory.

8. A bit error rate determination device, characterized in that: Applied to flash memory, the device comprises: a first acquiring module, configured to acquire a reread voltage and an operation address in response to detecting that a first read operation on the flash memory fails; A first determining module is configured to determine a target tag address corresponding to an operation address in the first read operation based on a pre-generated tag mapping relationship, wherein the tag mapping relationship records a correspondence between a plurality of operation addresses and a plurality of tag addresses; a second acquisition module, configured to perform a second read operation on the flash memory based on the target tag address and the reread voltage, so as to acquire tag data to be compared from a physical page of the flash memory; A second determining module is configured to determine target initial tag data corresponding to the target tag address based on the tag mapping relationship; wherein the tag mapping relationship further records a correspondence between a plurality of initial tag data and a plurality of tag addresses; The calculation module is used to calculate the marking error rate of the marked data based on the target initial marked data and the marked data to be compared.

9. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements the bit error rate determination method according to any one of claims 1 to 5, or the data recovery method according to any one of claims 6 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for determining the bit error rate according to any one of claims 1 to 5 or the method for recovering the data according to any one of claims 6 to 7 is implemented.

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