Performance acceleration analysis method, system and storage medium for test cases

Abstract

This invention relates to the field of test case analysis technology, and particularly to a method, system, and storage medium for accelerating the performance analysis of test cases. The invention runs test cases comprising multiple instructions using a simulator. When a test case executes to a preset interval, it acquires instruction information corresponding to each instruction within that interval. This instruction information includes the instruction type, operands, and calculation result. Based on a first preset rule, it determines whether each instruction within the preset interval has dependencies, obtaining instruction dependency statistics. Based on a second preset rule, it divides the test case into multiple read-only memory (ROM) files and multiple random access memory (RAM) files. These ROM files and RAM files are run in parallel. The test cases are analyzed based on the instruction dependency statistics and the execution results to obtain the analysis results. Compared with existing technologies, this invention provides faster and more effective test case analysis.

Description

Technical Field

[0001] This invention relates to the field of test case analysis technology, and in particular to a method, system and storage medium for accelerating the performance analysis of test cases. Background Technology

[0002] As a key tool in software and hardware development, CPU simulators primarily function to simulate the core behaviors of a target CPU, such as instruction execution, register interaction, and memory access, without requiring real hardware. This supports cross-architecture program execution and debugging, reduces hardware dependency costs, and accelerates the verification process for new architectures or new features.

[0003] QEMU, an open-source CPU simulator, is capable of simulating CPUs with various architectures. By accurately modeling key components of the target CPU, such as its instruction set, registers, and memory management, it can reproduce the operating characteristics of different CPU architectures well in a simulation environment, providing strong support for cross-platform software development, system debugging, and other tasks.

[0004] The plugin interface provided by the QEMU simulator enables users to extend functionality. Through this interface, users can develop plugins to analyze running test cases under different architectures, such as counting the number of instructions and printing instruction execution paths. These functions are very helpful for software performance optimization and program error troubleshooting.

[0005] However, the plugins included with the QEMU simulator are often quite basic and cannot meet the needs of RISC-V architecture test case analysis. The RISC-V architecture is modular and scalable, and its test case analysis often requires more complex functions, such as statistically analyzing the execution cycle of specific instructions and monitoring privilege level switching. Existing simulator plugins lack effective support in these areas and cannot meet the testing requirements of the RISC-V architecture.

[0006] Therefore, there is an urgent need for a new method, system, and storage medium for accelerating the performance analysis of test cases to solve the above-mentioned technical problems. Summary of the Invention

[0007] This invention provides a method, system, and storage medium for accelerating the performance analysis of test cases, aiming to improve the efficiency and effectiveness of test case analysis.

[0008] In a first aspect, the present invention provides a method for accelerating the performance analysis of test cases, the method comprising the following steps:

[0009] S1. Run test cases containing multiple instructions using a simulator. When the test cases reach a preset interval, obtain the instruction information corresponding to each instruction within the preset interval. The instruction information includes the instruction type, operands, and calculation result.

[0010] S2. Based on the first preset rule, determine whether each instruction in the preset interval has a dependency according to the instruction information, and obtain the instruction dependency statistics result;

[0011] S3. Based on the second preset rule, the test cases are divided into multiple read-only memory files and multiple random access memory files; the multiple read-only memory files and multiple random access memory files are run in parallel to obtain the running results;

[0012] S4. Analyze the test cases based on the instruction dependency statistics and the execution results to obtain the analysis results.

[0013] Preferably, the first preset rule is: determining whether the operands of each instruction within the preset interval are the same as the calculation result corresponding to at least one executed instruction within the preset range.

[0014] If so, then record the dependency relationship between the instruction and the executed instruction.

[0015] Preferably, in step S3, the second preset rule is:

[0016] S31. Based on the basic block vector generation tool, run the test cases once and collect the feature points of the test cases to obtain the test case feature file;

[0017] S32. Analyze and sample the use case feature file based on the simulation point tool to obtain a cutting point file; wherein, the cutting point file includes multiple specified cutting positions;

[0018] S33. The simulator runs the test case again and cuts the test case according to the cut point file to obtain multiple read-only memory files and multiple random access memory files.

[0019] Preferably, step S33 includes the following sub-steps:

[0020] S331. Determine whether the current simulator's instruction for running the test case has reached the specified cutting position of the cutting point file: if yes, proceed to step S332; if no, the simulator continues to run the next instruction of the test case.

[0021] S332. Query all current register information from the simulator and store all current register information sequentially into a new read-only memory file; Query the current memory information from the simulator and store the current memory information into a new random access memory file;

[0022] S333. Determine whether the simulator has completed running all the specified cutting positions in the cutting point file: if yes, output the multiple read-only memory files and multiple random access memory files; if no, the simulator runs the next instruction of the test case and returns to step S331.

[0023] Secondly, the present invention also provides a performance acceleration analysis system for test cases, the performance acceleration analysis system for test cases comprising:

[0024] The execution module is used to run test cases containing multiple instructions through a simulator. When the test cases are executed to a preset interval, the module obtains the instruction type, operands, and calculation result corresponding to each instruction within the preset interval.

[0025] The statistics module is used to determine whether each instruction within the preset interval has a dependency based on a first preset rule, and to obtain the instruction dependency statistics result.

[0026] The segmentation module is used to segment the test cases into multiple read-only memory files and multiple random access memory files based on a second preset rule; and to run multiple read-only memory files and multiple random access memory files in parallel to obtain the running results.

[0027] The analysis module is used to analyze the test cases based on the instruction dependency statistics and the execution results, and obtain analysis results.

[0028] Preferably, the first preset rule is: determining whether the operands of each instruction within the preset interval are the same as the calculation result corresponding to at least one executed instruction within the preset range.

[0029] If so, then record the dependency relationship between the instruction and the executed instruction.

[0030] Preferably, in the segmentation module, the second preset rule is:

[0031] The test cases are run once using a basic block vector generation tool, and the feature points of the test cases are collected to obtain a test case feature file.

[0032] The use case feature file is analyzed and sampled using a simulation point tool to obtain a cutting point file; wherein, the cutting point file includes multiple specified cutting positions;

[0033] The simulator runs the test cases again and cuts the test cases according to the cut point file to obtain multiple read-only memory files and multiple random access memory files.

[0034] Preferably, the segmentation module further includes the following sub-units:

[0035] The judgment unit is used to determine whether the instruction of the simulator running the test case has reached the specified cutting position of the cutting point file: if yes, it jumps to the query unit; if no, the simulator continues to run the next instruction of the test case.

[0036] The query unit is used to query all current register information from the simulator and store all current register information sequentially into a new read-only memory file; and to query current memory information from the simulator and store current memory information into a new random access memory file.

[0037] The output unit is used to determine whether the simulator has completed running all the specified cutting positions in the cutting point file: if yes, it outputs multiple read-only memory files and multiple random access memory files; if no, the simulator runs the next instruction of the test case and returns to the determination unit.

[0038] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a performance acceleration analysis program for test cases stored in the memory and executable on the processor, wherein when the processor executes the performance acceleration analysis program for test cases, it implements the steps in the performance acceleration analysis method for test cases as described in any of the above embodiments.

[0039] Fourthly, the present invention also provides a computer-readable storage medium storing a performance acceleration analysis program for test cases, wherein the performance acceleration analysis program for test cases, when executed by a processor, implements the steps in the performance acceleration analysis method for test cases as described in any of the above embodiments.

[0040] Compared to existing technologies, this invention runs test cases containing multiple instructions using a simulator. When a test case reaches a preset interval, it acquires instruction information for each instruction within that interval. This instruction information includes instruction type, operands, and calculation results. Based on a first preset rule, it determines whether each instruction within the preset interval has dependencies, obtaining instruction dependency statistics. Based on a second preset rule, the test case is divided into multiple read-only memory (ROM) files and multiple random access memory (RAM) files. These ROM files and RAM files are run in parallel to obtain execution results. The test cases are then analyzed based on the instruction dependency statistics and execution results to obtain analysis results. This invention can count the number of instructions of different types and determine the dependencies between instructions, obtaining instruction dependency statistics. This allows for analysis based on the instruction dependency statistics to aid chip optimization. Furthermore, for large test cases, the limited speed of the simulator results in long execution times. The second preset rule allows large test cases to be divided into multiple representative ROM files and RAM files. When analyzing test cases, the performance of the ROM files and RAM files is first analyzed to equivalently represent the performance of the large test cases. Furthermore, multiple read-only memory files and random access memory files can be run in parallel, which greatly reduces the running time. Attached Figure Description

[0041] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0042] Figure 1 This is a flowchart of the performance acceleration analysis method for test cases provided in the embodiments of the present invention;

[0043] Figure 2 This is a schematic diagram of the performance acceleration analysis system for test cases provided in this embodiment of the invention;

[0044] Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0046] Example 1

[0047] Please refer to Figure 1This invention provides a method for accelerating the performance analysis of test cases, the method comprising the following steps:

[0048] S1. Run test cases containing multiple instructions through a simulator. When the test cases are executed to a preset interval, obtain the instruction information corresponding to each instruction within the preset interval. The instruction information includes the instruction type, operands, and calculation result.

[0049] In this embodiment of the invention, the simulator is a QEMU (Quick Emulator) simulator. The preset range can be any range from the start instruction to the end instruction set in the test case. For example, when the simulator runs the test case and reaches the start instruction, it starts recording the instruction information (including the start instruction) corresponding to the instruction until it runs to the end instruction. The size of the preset range can be set according to the actual situation.

[0050] S2. Based on the first preset rule, determine whether each instruction in the preset interval has a dependency according to the instruction information, and obtain the instruction dependency statistics result.

[0051] In this embodiment of the invention, the first preset rule is: to determine whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range; if so, to record the dependency relationship between the instruction and the executed instruction. The preset range refers to the n executed instructions preceding the current instruction, with a maximum value of 64. For example, determining whether the operand of the current instruction is the same as the calculation result of the 64 executed instructions preceding it.

[0052] Specifically, when optimizing for a test case, it's essential to understand the number of instructions, instruction types, and dependencies between them. This is achieved by counting the number of instructions of different types and identifying their dependencies. After determining these dependencies, it becomes clear which instruction pair appears most frequently in the test case. For example, if the addition instruction appears most often, subsequent chip design can focus on optimizing the addition module to improve test case performance.

[0053] S3. Based on the second preset rule, the test cases are divided into multiple read-only memory files and multiple random access memory files; multiple read-only memory files and multiple random access memory files are run in parallel to obtain the running results.

[0054] In this embodiment of the invention, in step S3, the second preset rule is:

[0055] S31. Using the Basic Block Vector Generation Tool, run the test cases once completely and collect the feature points of the test cases to obtain a test case feature file. The Basic Block Vector Generation Tool is a tool used to statistically analyze and quantify the execution behavior of basic blocks during program execution, generating "basic block vectors" (i.e., feature points). The Basic Block Vector Generation Tool monitors the program execution flow using instrumentation technology, records the execution count of each basic block, and ultimately forms feature points reflecting program behavior, thus obtaining a test case feature file with multiple feature points.

[0056] S32. The use case feature file is analyzed and sampled using a Simpoint tool to obtain a cut-off point file. This cut-off point file includes multiple specified cut-off locations. The Simpoint tool analyzes the basic block vectors generated by the use case feature file during runtime, dividing the entire execution process into several behaviorally similar "stages," and selecting the most representative stages (called "Simpoints"). Each stage is defined by a specified cut-off location. These stages accurately reflect the overall execution characteristics of the program, avoiding ineffective simulation of redundant or repetitive execution parts.

[0057] S33. The simulator runs the test case again and segments the test case according to the segmentation point file to obtain multiple read-only memory files (BootROM files) and multiple random access memory files (MainRAM files). The read-only memory files store all register information at the moment the slice is generated. The random access memory files store all memory information at the moment the slice is generated; both are used to restore the runtime.

[0058] For example, a large test case (with a particularly large number of instructions), such as 3 billion instructions, needs to run for a period of time. A basic block vector generation tool is used to identify its feature points, and then a simulated point tool is used to segment it into six parts (the number of segments and the specified segmentation positions can be manually set). The first part starts with 0 instructions, the second with 500 million instructions, and so on. Finally, six sets of slice files are obtained, each with one read-only memory file and one random access memory file, for a total of twelve files.

[0059] Step S33 includes the following sub-steps:

[0060] S331. Determine whether the current simulator's instruction for running the test case has reached the specified cutting position of the cutting point file: if yes, proceed to step S332; if no, the simulator continues to run the next instruction of the test case.

[0061] S332. Query all current register information from the simulator and store all current register information sequentially into a new read-only memory file; Query the current memory information from the simulator and store the current memory information into a new random access memory file;

[0062] S333. Determine whether the simulator has completed running all the specified cutting positions in the cutting point file: if yes, output the multiple read-only memory files and multiple random access memory files; if no, the simulator runs the next instruction of the test case and returns to step S331.

[0063] S4. Analyze the test cases based on the instruction dependency statistics and the execution results to obtain the analysis results.

[0064] Compared to existing technologies, this invention runs test cases containing multiple instructions using a simulator. When a test case reaches a preset interval, it acquires instruction information for each instruction within that interval. This instruction information includes instruction type, operands, and calculation results. Based on a first preset rule, it determines whether each instruction within the preset interval has dependencies, obtaining instruction dependency statistics. Based on a second preset rule, the test case is divided into multiple read-only memory (ROM) files and multiple random access memory (RAM) files. These ROM files and RAM files are run in parallel to obtain execution results. The test cases are then analyzed based on the instruction dependency statistics and execution results to obtain analysis results. This invention can count the number of instructions of different types and determine the dependencies between instructions, obtaining instruction dependency statistics. This allows for analysis based on the instruction dependency statistics to aid chip optimization. Furthermore, for large test cases, the limited speed of the simulator results in long execution times. The second preset rule allows large test cases to be divided into multiple representative ROM files and RAM files. When analyzing test cases, the performance of the ROM files and RAM files is first analyzed to equivalently represent the performance of the large test cases. Furthermore, multiple read-only memory files and random access memory files can be run in parallel, which greatly reduces the running time.

[0065] Example 2

[0066] This invention also provides a performance acceleration analysis system for test cases. Please refer to [link / reference]. Figure 2 , Figure 2This is a schematic diagram of the performance acceleration analysis system 200 for test cases provided in this embodiment of the invention, which includes:

[0067] 201. Execution module, used to run test cases including multiple instructions through a simulator. When the test cases are executed to a preset interval, the module obtains the instruction type, operands and calculation results corresponding to each instruction in the preset interval.

[0068] In this embodiment of the invention, the simulator is a QEMU (Quick Emulator) simulator. The preset range can be any range from the start instruction to the end instruction set in the test case. For example, when the simulator runs the test case and reaches the start instruction, it starts recording the instruction information (including the start instruction) corresponding to the instruction until it runs to the end instruction. The size of the preset range can be set according to the actual situation.

[0069] 202. The statistics module is used to determine whether each instruction in the preset interval has a dependency based on the first preset rule, and to obtain the instruction dependency statistics result.

[0070] In this embodiment of the invention, the first preset rule is: to determine whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range; if so, the dependency relationship between the instruction and the executed instruction is recorded.

[0071] 203. A segmentation module, used to segment the test cases into multiple read-only memory files and multiple random access memory files based on a second preset rule; and to run multiple read-only memory files and multiple random access memory files in parallel to obtain the running results.

[0072] In this embodiment of the invention, the second preset rule in the segmentation module 203 is:

[0073] The test cases are run once using a basic block vector generation tool, and the feature points of the test cases are collected to obtain a test case feature file.

[0074] The use case feature file is analyzed and sampled using a simulation point tool to obtain a cutting point file; wherein, the cutting point file includes multiple specified cutting positions;

[0075] The simulator runs the test cases again and cuts the test cases according to the cut point file to obtain multiple read-only memory files and multiple random access memory files.

[0076] In this embodiment of the invention, the segmentation module 203 further includes the following sub-units:

[0077] 2031. Judgment unit, used to determine whether the instruction of the simulator running the test case has reached the specified cutting position of the cutting point file: if yes, then jump to query unit 2032; if no, then the simulator continues to run the next instruction of the test case;

[0078] 2032. A query unit, configured to query all current register information from the simulator and sequentially store all current register information into a new read-only memory file; and query current memory information from the simulator and store the current memory information into a new random access memory file;

[0079] 2033. Output unit, used to determine whether the simulator has completed running all the specified cutting positions in the cutting point file: if yes, output multiple read-only memory files and multiple random access memory files; if no, the simulator runs the next instruction of the test case and returns to the judgment unit 2031.

[0080] 204. Analysis module, used to analyze the test cases based on the instruction dependency statistics and the execution results, and obtain analysis results.

[0081] The performance acceleration analysis system 200 for test cases can implement the steps in the performance acceleration analysis method for test cases as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0082] Example 3

[0083] This invention also provides a computer device, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a performance acceleration analysis program for test cases stored in the memory 302 and capable of running on the processor 301.

[0084] The processor 301 calls the performance acceleration analysis program for test cases stored in the memory 302, and executes the steps in the performance acceleration analysis method for test cases provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps:

[0085] S1. Run test cases containing multiple instructions through a simulator. When the test cases are executed to a preset interval, obtain the instruction information corresponding to each instruction within the preset interval. The instruction information includes the instruction type, operands, and calculation result.

[0086] In this embodiment of the invention, the simulator is a QEMU (Quick Emulator) simulator. The preset range can be any range from the start instruction to the end instruction set in the test case. For example, when the simulator runs the test case and reaches the start instruction, it starts recording the instruction information (including the start instruction) corresponding to the instruction until it runs to the end instruction. The size of the preset range can be set according to the actual situation.

[0087] S2. Based on the first preset rule, determine whether each instruction in the preset interval has a dependency according to the instruction information, and obtain the instruction dependency statistics result.

[0088] In this embodiment of the invention, the first preset rule is: to determine whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range; if so, to record the dependency relationship between the instruction and the executed instruction. The preset range refers to the n executed instructions preceding the current instruction, with a maximum value of 64. For example, determining whether the operand of the current instruction is the same as the calculation result of the 64 executed instructions preceding it.

[0089] Specifically, when optimizing for a test case, it's essential to understand the number of instructions, instruction types, and dependencies between them. This is achieved by counting the number of instructions of different types and identifying their dependencies. After determining these dependencies, it becomes clear which instruction pair appears most frequently in the test case. For example, if the addition instruction appears most often, subsequent chip design can focus on optimizing the addition module to improve test case performance.

[0090] S3. Based on the second preset rule, the test cases are divided into multiple read-only memory files and multiple random access memory files; multiple read-only memory files and multiple random access memory files are run in parallel to obtain the running results.

[0091] In this embodiment of the invention, in step S3, the second preset rule is:

[0092] S31. Using the Basic Block Vector Generation Tool, run the test cases once completely and collect the feature points of the test cases to obtain a test case feature file. The Basic Block Vector Generation Tool is a tool used to statistically analyze and quantify the execution behavior of basic blocks during program execution, generating "basic block vectors" (i.e., feature points). The Basic Block Vector Generation Tool monitors the program execution flow using instrumentation technology, records the execution count of each basic block, and ultimately forms feature points reflecting program behavior, thus obtaining a test case feature file with multiple feature points.

[0093] S32. The use case feature file is analyzed and sampled using a Simpoint tool to obtain a cut-off point file. This cut-off point file includes multiple specified cut-off locations. The Simpoint tool analyzes the basic block vectors generated by the use case feature file during runtime, dividing the entire execution process into several behaviorally similar "stages," and selecting the most representative stages (called "Simpoints"). Each stage is defined by a specified cut-off location. These stages accurately reflect the overall execution characteristics of the program, avoiding ineffective simulation of redundant or repetitive execution parts.

[0094] S33. The simulator runs the test case again and segments the test case according to the segmentation point file to obtain multiple read-only memory files (BootROM files) and multiple random access memory files (MainRAM files). The read-only memory files store all register information at the moment the slice is generated. The random access memory files store all memory information at the moment the slice is generated; both are used to restore the runtime.

[0095] For example, a large test case (with a particularly large number of instructions), such as 3 billion instructions, needs to run for a period of time. A basic block vector generation tool is used to identify its feature points, and then a simulated point tool is used to segment it into six parts (the number of segments and the specified segmentation positions can be manually set). The first part starts with 0 instructions, the second with 500 million instructions, and so on. Finally, six sets of slice files are obtained, each with one read-only memory file and one random access memory file, for a total of twelve files.

[0096] Step S33 includes the following sub-steps:

[0097] S331. Determine whether the current simulator's instruction for running the test case has reached the specified cutting position of the cutting point file: if yes, proceed to step S332; if no, the simulator continues to run the next instruction of the test case.

[0098] S332. Query all current register information from the simulator and store all current register information sequentially into a new read-only memory file; Query the current memory information from the simulator and store the current memory information into a new random access memory file;

[0099] S333. Determine whether the simulator has completed running all the specified cutting positions in the cutting point file: if yes, output the multiple read-only memory files and multiple random access memory files; if no, the simulator runs the next instruction of the test case and returns to step S331.

[0100] S4. Analyze the test cases based on the instruction dependency statistics and the execution results to obtain the analysis results.

[0101] The computer device 300 provided in this embodiment of the invention can implement the steps in the performance acceleration analysis method of the test cases in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0102] Example 4

[0103] This invention also provides a computer-readable storage medium storing a performance acceleration analysis program for test cases. When executed by a processor, the performance acceleration analysis program for test cases implements the various processes and steps in the performance acceleration analysis method for test cases provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0104] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer programs or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0105] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0106] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0107] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A method for accelerating the performance analysis of test cases, characterized in that, The performance acceleration analysis method includes the following steps: S1. Run test cases containing multiple instructions using a simulator. When the test cases reach a preset interval, obtain the instruction information corresponding to each instruction within the preset interval. The instruction information includes the instruction type, operands, and calculation result. S2. Based on the first preset rule, determine whether each instruction in the preset interval has a dependency according to the instruction information, and obtain the instruction dependency statistics result; S3. Based on the second preset rule, the test cases are divided into multiple read-only memory files and multiple random access memory files; the multiple read-only memory files and multiple random access memory files are run in parallel to obtain the running results; S4. Analyze the test cases based on the instruction dependency statistics and the execution results to obtain the analysis results; The first preset rule is: to determine whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range. If so, then record the dependency relationship between the instruction and the executed instruction; In step S3, the second preset rule is: S31. Based on the basic block vector generation tool, run the test cases once and collect the feature points of the test cases to obtain the test case feature file; S32. Analyze and sample the use case feature file based on the simulation point tool to obtain a cutting point file; wherein, the cutting point file includes multiple specified cutting positions; S33. The simulator runs the test case again and cuts the test case according to the cut point file to obtain multiple read-only memory files and multiple random access memory files.

2. The performance acceleration analysis method for test cases as described in claim 1, characterized in that, Step S33 includes the following sub-steps: S331. Determine whether the current simulator's instruction for running the test case has reached the specified cutting position of the cutting point file: if yes, proceed to step S332; if no, the simulator continues to run the next instruction of the test case. S332. Query all current register information from the simulator and store all current register information sequentially into a new read-only memory file; Query the current memory information from the simulator and store the current memory information into a new random access memory file; S333. Determine whether the simulator has completed running all the specified cutting positions in the cutting point file: if yes, output the multiple read-only memory files and multiple random access memory files; if no, the simulator runs the next instruction of the test case and returns to step S331.

3. A performance acceleration analysis system for test cases, characterized in that, The performance acceleration analysis system for the test cases includes: The execution module is used to run test cases containing multiple instructions through a simulator. When the test cases are executed to a preset interval, the module obtains the instruction type, operands, and calculation result corresponding to each instruction within the preset interval. The statistics module is used to determine whether each instruction within the preset interval has a dependency based on a first preset rule, and to obtain the instruction dependency statistics result. The segmentation module is used to segment the test cases into multiple read-only memory files and multiple random access memory files based on a second preset rule; and to run multiple read-only memory files and multiple random access memory files in parallel to obtain the running results. The analysis module is used to analyze the test cases based on the instruction dependency statistics and the execution results, and obtain analysis results; The first preset rule is: to determine whether the operand of each instruction within the preset interval is the same as the calculation result corresponding to at least one executed instruction within the preset range. If so, then record the dependency relationship between the instruction and the executed instruction; In the segmentation module, the second preset rule is: The test cases are run once using a basic block vector generation tool, and the feature points of the test cases are collected to obtain a test case feature file. The use case feature file is analyzed and sampled using a simulation point tool to obtain a cutting point file; wherein, the cutting point file includes multiple specified cutting positions; The simulator runs the test cases again and cuts the test cases according to the cut point file to obtain multiple read-only memory files and multiple random access memory files.

4. The performance acceleration analysis system for test cases as described in claim 3, characterized in that, The segmentation module further includes the following sub-units: The judgment unit is used to determine whether the instruction of the simulator running the test case has reached the specified cutting position of the cutting point file: if yes, it jumps to the query unit; if no, the simulator continues to run the next instruction of the test case. The query unit is used to query all current register information from the simulator and sequentially store all current register information into a new read-only memory file; The simulator is used to query the current memory information and store the current memory information into a new random access memory file. The output unit is used to determine whether the simulator has completed running all the specified cutting positions in the cutting point file: if yes, it outputs multiple read-only memory files and multiple random access memory files; if no, the simulator runs the next instruction of the test case and returns to the determination unit.

5. A computer device, characterized in that, include: The system includes a memory, a processor, and a performance acceleration analysis program for test cases stored in the memory and executable on the processor. When the processor executes the performance acceleration analysis program for the test cases, it implements the steps in the performance acceleration analysis method for test cases as described in any one of claims 1-2.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a performance acceleration analysis program for test cases, which, when executed by a processor, implements the steps of the performance acceleration analysis method for test cases as described in any one of claims 1-2.

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