A graphics processing unit signal compatible device, method and computer storage medium

Abstract

The application relates to a graphics processing unit signal compatibility device, method and computer storage medium. The device comprises a control controller, a processor, an interconnection expander, at least one graphics processing unit and at least one resistance array; wherein the controller is connected with the processor and the at least one resistance array respectively, the at least one resistance array is connected with the at least one graphics processing unit and the interconnection expander respectively, the interconnection expander is connected with the processor, and the at least one graphics processing unit corresponds to the at least one resistance array in one-to-one correspondence; the electrical parameters corresponding to the graphics processing are acquired, and the resistance array is configured; the interconnection expander detects the resistance array, and transmits detection data to the controller; and the controller controls the enabling state of the target graphics processing unit according to the detection result. Through the device, different graphics processing units can be compatible, and signal transmission stability can be improved.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to a signal compatibility device, method, and computer storage medium for a graphics processing unit. Background Technology

[0002] With the development of information technology and artificial intelligence, the amount of storage, computing, and interactive data that data centers need to process is constantly increasing. PCIe, as the core interconnect bus within servers, provides high-speed data transmission between devices such as GPUs, network interface cards (NICs), and storage. Because PCIe uses a point-to-point link approach, PCIe Bridges or PCIe Switches are typically introduced into the system to improve flexibility and scalability, allowing multiple downstream devices to be connected to the same root port. In multi-GPU server architectures, PCIe Switch solutions have become the mainstream design, alleviating the problem of limited physical CPU channels and supporting the collaborative access of multiple GPUs, high-speed networks, and storage devices through port expansion, thereby meeting the bandwidth and interconnect efficiency requirements of deep learning and large-scale model training.

[0003] While existing PCIe switch architectures offer advantages in channel resource allocation and multi-device interconnection, they still have significant shortcomings. Different GPUs vary in electrical characteristics, protocol implementation, clock tolerance, and power-saving states. Fixed hardware link designs struggle to be compatible with all specifications, easily leading to signal attenuation, overshoot, link training failures, or performance degradation. Furthermore, factors such as manufacturing process, PCB impedance, and batch consistency further affect signal quality, making systems more prone to bit errors, card drops, or system crashes in mixed deployments. Moreover, changing GPU models often requires reconfiguring the hardware topology, increasing operational complexity and cluster deployment costs. This means that while striving for compatibility with more devices, the overall stability and reliability of the system are actually weakened. Summary of the Invention

[0004] Therefore, it is necessary to provide a signal compatibility device, method, and storage medium that can be compatible with different graphics processing units and improve signal transmission stability in order to address the above-mentioned technical problems.

[0005] In a first aspect, a signal compatibility device for a graphics processing unit is provided, comprising:

[0006] The controller, processor, interconnect expander, at least one graphics processing unit, and at least one resistor array;

[0007] The controller is connected to the processor and at least one resistor array, the at least one resistor array is connected to at least one graphics processing unit and an interconnect expander, the interconnect expander is connected to the processor, and the at least one graphics processing unit corresponds one-to-one with the at least one resistor array.

[0008] The controller acquires the electrical parameters corresponding to the graphics processing and configures the resistor array. The interconnect extender detects the resistor array and transmits the detection data to the controller. The controller controls the activation status of the target graphics processing unit based on the detection results.

[0009] Secondly, a signal compatibility method for a signal compatibility device applied to a graphics processing unit is provided, comprising:

[0010] The controller obtains the identifier of the target graphics processing unit through the processor;

[0011] The controller queries the corresponding target graphics processing unit in the preset database based on the identifier and obtains its electrical parameters;

[0012] The controller transmits electrical parameters to the resistor array corresponding to the target graphics processing unit, adjusts the electrical parameters, and configures the resistor array according to the adjusted electrical parameters.

[0013] Error detection of the resistor array is performed through the interconnect extender, and the detection data is transmitted to the controller.

[0014] The controller generates detection results based on the detection data and controls the activation status of the target graphics processing unit based on the detection results.

[0015] Thirdly, a computer-readable storage medium is provided, on which a computer program is stored, wherein when the computer program is executed by a processor, the signal compatibility method for a graphics processing unit described in the second aspect is implemented.

[0016] By implementing the aforementioned graphics processing unit signal compatibility device, method, and computer storage medium, an adaptive matching of the electrical characteristics of different graphics processing units is achieved by introducing a programmable resistor array between the CPU and GPU, and by utilizing the controller's dynamic parameter scheduling and the interconnect expander's real-time bit error detection. This fundamentally eliminates problems such as signal mismatch, increased bit error rate, and system instability caused by traditional fixed impedance designs. Since the controller uses the I²C bus to send parameters to the resistor array with low latency and low power consumption, the system can complete the matching configuration simply through software-level database updates when replacing or adding GPUs, without rewiring or replacing hardware components, significantly reducing maintenance costs and improving expansion flexibility. Simultaneously, the high-bandwidth link provided by the interconnect expander via the PCIe bus ensures high-speed data transmission, and its built-in detection and feedback loops enable the system to continuously monitor link quality during operation and dynamically reconfigure the resistor array or automatically shield abnormal GPUs when necessary, thereby achieving link self-optimization and self-recovery and improving overall reliability. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This application provides a structural diagram of a signal compatibility device for a graphics processing unit.

[0019] Figure 2 A flowchart illustrating a signal compatibility method for a graphics processing unit provided in this application embodiment;

[0020] Figure 3 This is a diagram showing the internal structure of a computer device in an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0022] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0023] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] In one embodiment, such as Figure 1 As shown, a signal compatibility device for a graphics processing unit is provided, comprising:

[0025] The controller, processor, interconnect expander, at least one graphics processing unit, and at least one resistor array;

[0026] The controller is connected to the processor and at least one resistor array, the at least one resistor array is connected to at least one graphics processing unit and an interconnect expander, the interconnect expander is connected to the processor, and the at least one graphics processing unit corresponds one-to-one with the at least one resistor array.

[0027] The electrical parameters corresponding to the graphics processing are obtained and the resistor array is configured. The interconnect extender detects the resistor array and transmits the detection data to the controller. The controller controls the activation status of the target graphics processing unit based on the detection results.

[0028] Among them, the processor (Central Processing Unit, CPU) refers to the computing core that executes the operating system and applications, and is responsible for data processing, task scheduling and bus management; the controller (Control Manager) refers to the hardware logic unit located on the motherboard, which is responsible for monitoring the status of various components in the system, acquiring parameters, issuing configurations and controlling the working status. It is usually implemented as a baseboard controller (BMC) or a dedicated FPGA / ASIC.

[0029] A high-speed chip is a communication controller with high-speed data processing capabilities, typically a PCIe switch or similar device, used to expand the number of channels and perform link control and data forwarding. A graphics processing unit (GPU) is a processor with powerful parallel computing capabilities, used for graphics rendering, deep learning inference, and large-scale computing tasks. A programmable resistor array is an array of adjustable resistors used to adjust the impedance matching of high-speed signal links, compensate for signal attenuation or reflection problems, and achieve compatible connections between devices with different electrical characteristics. An I²C bus (Inter-Integrated Circuit) is a low-speed serial communication bus used for short-distance control signal exchange between chips, featuring device address identification and multi-master / multi-slave mechanisms, suitable for parameter retrieval and configuration communication between the controller and the resistor array. A PCIe bus (Peripheral Component Interconnect Express, PCIe) is a high-speed serial communication standard used for high-bandwidth data exchange with graphics processing units and interconnects, supporting point-to-point direct connection, hierarchical topology, and hot-plug functionality.

[0030] Specifically, the controller connects to at least one resistor array via an I²C bus and to the processor via a PCIe bus, enabling the reading of configuration commands and parameters for the resistor arrays. Each resistor array connects to its corresponding graphics processing unit (GPU) via an I²C bus, allowing for precise tuning of the GPU's electrical characteristics. The interconnect expander connects to the processor via a PCIe bus, forming a high-speed data channel. Simultaneously, the interconnect expander connects to each GPU via a PCIe bus, facilitating high-speed data forwarding. Each GPU corresponds to its specific resistor array, thus achieving independent impedance matching and signal compensation at the physical level.

[0031] During operation, the controller first obtains the set of electrical parameters corresponding to the target graphics processing unit (GPU) through the processor. Then, it uses the I²C bus to send the retrieved parameters to the corresponding resistor array and instructs it to complete the programming configuration. After configuration, the interconnect expander continuously monitors the signal quality on the PCIe link, performs real-time detection, and returns the detection data to the controller via PCIe. The controller generates a link quality assessment report based on the detection results, and then controls the enabling or disabling of the target GPU to ensure that the GPU is only allowed to operate when the link meets a preset threshold. By constructing a collaborative interconnection based on both I²C and PCIe buses between the controller, processor, interconnect expander, GPU, and resistor array, closed-loop control of real-time acquisition, precise configuration, and dynamic matching of the GPU's operating impedance is achieved. This significantly improves the integrity and stability of signal transmission, reduces reflections and noise caused by impedance mismatch, and thus improves the overall performance and reliability of the system. Simultaneously, the high-speed detection of the resistor array by the interconnect expander and the feedback of the results to the controller enable the system to immediately disable the corresponding GPU when abnormal resistance values ​​or failures are detected, preventing the continued propagation of erroneous signals and achieving fault self-protection. The structure also features modular scalability, enabling synchronous matching of multiple signals by adding resistor array units or graphics processing units without altering the core circuitry.

[0032] In one embodiment, the device further includes a memory connected to the controller for storing a preset database.

[0033] The memory refers to a non-volatile storage medium connected to the controller. It is electrically interconnected with the controller, which serves as the core control unit, through an internal data bus or dedicated interface. It is used to persistently store a preset database containing information such as device configuration parameters, operating instruction sets, and status thresholds. The preset database is a set of structured data stored in the memory, containing pre-configured rules, parameters, mapping relationships, or other key information, used to support the controller's decision-making, querying, or computational functions.

[0034] Specifically, by tightly coupling the memory and controller and storing a preset database, the device can quickly complete data queries, rule matching, or control command generation without frequent access to external storage or networks, thereby significantly improving system response speed and operating efficiency. The presence of the preset database allows the device to handle complex logic locally, reducing reliance on external resources, thus lowering power consumption and improving system stability and reliability. Furthermore, this architecture supports flexible expansion; for example, the device's behavior can be adjusted by updating instructions or parameters in the preset database without changing the hardware circuitry, thereby reducing upgrade costs and improving adaptability and scalability.

[0035] In one embodiment, the apparatus further includes a cluster data synchronization hardware unit connected to the controller, which is used to exchange the controller's data information with other servers in the server cluster via a network.

[0036] The cluster data synchronization hardware unit refers to a dedicated hardware module, typically composed of a network interface controller (NIC), a data buffer, and related data processing circuitry. Its function is to enable efficient data interaction between the controller and other servers in the server cluster. A server cluster refers to a collection of servers interconnected by a high-speed network. These servers work together to provide high availability, high performance, or load-balanced computing capabilities, and typically employ a distributed architecture to ensure system redundancy and scalability.

[0037] Specifically, the cluster data synchronization hardware unit is directly coupled to the controller via a high-speed network interface (such as an Ethernet port or Fibre Channel), typically employing a dedicated data bus or high-speed serial communication link to ensure low-latency and high-throughput data transmission. The controller establishes connections with other servers in the external server cluster through the network interface of this cluster data synchronization hardware unit. By integrating the cluster data synchronization hardware unit, the device can efficiently synchronize or interact with data information in the controller and other servers in the server cluster, thereby achieving data consistency and collaborative working capabilities in the distributed system. This significantly improves the system's scalability and fault tolerance. For example, if a node in the server cluster fails, the controller can quickly synchronize data to other available nodes through the cluster data synchronization hardware unit, thus ensuring the continuity of system services. Simultaneously, the hardware acceleration function of this unit reduces the computational burden on the controller, improving the efficiency and reliability of data transmission.

[0038] In one embodiment, the apparatus further includes a programmable logic device connected to the interconnect extender for taking over some timing control, logic operations, and computational processing of the interconnect extender.

[0039] Programmable logic devices (PLDs) are hardware components whose internal logic functions can be configured through programming. These include Field-Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Their function is to implement specific timing control, logic operations, or data processing tasks. Timing control refers to the precise management of the clock signals, trigger signals, or data transmission timing of hardware operations to ensure the efficiency and accuracy of the coordinated operation of various components.

[0040] Specifically, programmable logic devices (PLDs) are directly coupled to interconnect expanders via high-speed interconnect interfaces (such as AXI buses, PCIe channels, or dedicated parallel / serial buses) to ensure low-latency and high-bandwidth data transmission and control signal interaction. As auxiliary processing units of interconnect expanders, PLDs receive input signals (such as control commands or data streams) from the interconnect expanders and perform timing control, logical operations, or computational processing tasks through their internal configurable logic units.

[0041] By coupling programmable logic devices (PLDs) with interconnect extenders, the device significantly improves system flexibility and processing efficiency. The configurable nature of PLDs allows for dynamic functional adjustments based on specific application requirements. For example, reprogramming can implement new timing control strategies or logic operation rules to adapt to diverse application scenarios, such as real-time protocol conversion in smart IoT devices or optimizing data flow management in high-performance computing systems. By taking over some of the timing control, logic operation, and computational processing tasks from the interconnect extenders, PLDs effectively offload the controller's computational load, reducing system latency and improving the parallelism and real-time performance of data processing. Simultaneously, this design enhances the device's scalability and maintainability. For instance, updating the firmware or logic configuration of the PLDs allows for rapid adaptation to new hardware interfaces or protocol standards, thereby extending the device's lifespan and enhancing its market competitiveness.

[0042] In one embodiment, such as Figure 2 As shown, a signal compatibility method for a graphics processing unit is provided, applicable to any graphics processing unit signal compatibility device. The method includes:

[0043] S100: The controller obtains the identifier of the target graphics processing unit through the processor;

[0044] S200: The controller queries the corresponding target graphics processing unit in the preset database according to the identifier and obtains its electrical parameters;

[0045] S300: The controller transmits electrical parameters to the resistor array corresponding to the target graphics processing unit, adjusts the electrical parameters, and configures the resistor array according to the adjusted electrical parameters;

[0046] S400: Performs bit error detection on the resistor array via the interconnect extender and transmits the detection data to the controller;

[0047] S500: The controller generates detection results based on the detection data and controls the activation status of the target graphics processing unit based on the detection results.

[0048] Among them, electrical parameters refer to the operating parameters of the target graphics processing unit, such as voltage, current, power or frequency, which directly affect its performance and stability; detection data refers to the raw data generated during the error detection process, reflecting the integrity or error status of data transmission;

[0049] Specifically, the processor interconnects with the interconnect extender via the peripheral component interconnect bus, and the interconnect extender then connects to the graphics processing unit (GPU) via the corresponding PCIe channel, thus constructing a complete high-speed data path. In this link, the resistor array located between the GPU and the interconnect extender has its electrical characteristics adjusted by the controller. The controller accesses a preset database via the I²C bus, identifies the device identifier of the target GPU, and reads its corresponding electrical parameters, such as drive strength, impedance requirements, and clock jitter tolerance. Subsequently, it programs and configures the resistor array corresponding to the target GPU according to these parameters to meet the signal transmission requirements of the current GPU. After the electrical configuration is completed, the interconnect extender continuously performs error detection on the signal link and reports the detection results to the controller via the PCIe path. The controller then determines whether the current link is stable, whether the startup conditions have been met, and controls the enabling or disabling state of the GPU. Through this dynamic signal matching mechanism based on the cooperation of the I²C and PCIe dual buses, it can effectively accommodate electrical differences between GPUs from different manufacturers and batches, improving the reliability and stability of the interconnect link. This also provides fundamental support for subsequent automatic deployment, elastic expansion, and intelligent operation and maintenance, exhibiting excellent system scalability and engineering feasibility. By introducing a configurable resistor array and combining the controller's dynamic parameter scheduling with the interconnect extender's link detection, adaptive matching of the electrical characteristics of different graphics processing units is achieved, effectively avoiding signal mismatch and link instability issues present in traditional fixed impedance designs. Since the controller can retrieve the electrical parameters of the target graphics processing unit from a preset database via the integrated circuit bus and configure the resistor array in real time, the system can maintain stable operation even when graphics processing units of different models and batches are deployed together, significantly improving hardware compatibility and flexibility. Simultaneously, the interconnect extender's continuous bit error detection and feedback mechanism enables the system to dynamically optimize and self-recover during operation, further enhancing overall reliability. Relying on the high-bandwidth transmission channel provided by the peripheral component interconnect bus, efficient interconnection of multiple graphics processing units can be achieved while ensuring signal quality, meeting the stringent requirements of artificial intelligence training and high-performance computing for stability, bandwidth, and latency.

[0050] In one embodiment, the controller queries the corresponding target graphics processing unit in a preset database based on an identifier and obtains its electrical parameters, including:

[0051] If no corresponding target graphics processing unit is found in the preset database, the preset intermediate electrical parameter is obtained as the electrical parameter.

[0052] If a corresponding target graphics processing unit exists in the preset database, its corresponding electrical parameters are obtained.

[0053] Among them, the preset intermediate value electrical parameters refer to a set of predefined general electrical parameters (such as default values ​​for voltage, current or frequency) used as alternative parameters to ensure the normal operation of the device when a specific electrical parameter corresponding to the identifier of the target graphics processing unit cannot be found in the preset database.

[0054] Specifically, the controller queries a preset database to prioritize obtaining specific electrical parameters corresponding to the identifier, thereby optimizing the performance and energy efficiency of the target graphics processing unit (GPU). When no matching parameter exists in the database, a preset intermediate electrical parameter is used as the default configuration, ensuring stable operation even when faced with unknown or newly added GPUs. By querying the preset database based on the identifier of the target GPU to obtain the corresponding electrical parameters and dynamically handling the presence or absence of matching parameters, the controller enables precise configuration and efficient operation of the GPU, significantly improving the system's adaptability and operational efficiency. For example, it allows for rapid adaptation to new GPUs in dynamically expanding cloud computing environments. This dynamic parameter acquisition and configuration method not only reduces the risk of configuration failure due to missing parameters but also enhances the system's compatibility and robustness through universal intermediate parameters. It is suitable for heterogeneous computing or scenarios with frequent hardware updates, such as dynamic resource allocation in artificial intelligence training or edge computing.

[0055] In one embodiment, the electrical parameters include resistance parameters and equalization parameters. The controller transmits the electrical parameters to a resistor array corresponding to the target graphics processing unit, adjusts the electrical parameters, and configures the resistor array according to the adjusted electrical parameters, including:

[0056] In response to the existence of a corresponding target graphics processing unit in the preset database, a resistor array is configured based on the corresponding resistance parameters and equalization parameters of the target graphics processing unit.

[0057] If no corresponding target graphics processing unit is found in the preset database, preset intermediate electrical parameters are obtained. The preset intermediate electrical parameters include: intermediate resistance parameters and intermediate equalization parameters.

[0058] according to:

[0059] ;

[0060] The calculated voltage output is converted to obtain the optimal resistance parameters; where V inV is the input voltage. out For the output voltage, R eq Z0 represents the intermediate resistance parameter, and Z0 is the transmission line impedance.

[0061] The resistor array is configured based on the preferred resistor parameters and the intermediate value equalization parameters.

[0062] Among them, resistance parameters refer to the resistance values ​​or resistor network configuration parameters associated with the target graphics processing unit, used to adjust the resistor array to match the electrical requirements of the graphics processing unit. Equalization parameters refer to parameters used to optimize signal transmission or circuit performance, typically involving signal equalization (such as pre-emphasis or de-emphasis settings) to reduce signal distortion or noise interference. Intermediate value resistance parameters and intermediate value equalization parameters refer to the resistance values ​​and equalization settings in the preset intermediate electrical parameters, respectively, used as default configurations to handle cases where no matching parameters are found in the database.

[0063] Specifically, the controller retrieves specific resistance and equalization parameters that match the target graphics processing unit (GPU) identifier by querying a preset database in memory. These parameters are typically obtained through actual measurements based on the GPU's specifications (such as rated voltage, current, or signal bandwidth requirements). For example, precise measurements of the GPU's voltage, current, and signal response under different workloads are performed using laboratory testing equipment to generate database entries containing resistance values ​​and equalization settings. If matching parameters exist in the database, the controller directly transmits these measured parameters to the resistor array, adjusting its resistor network and equalization circuitry to ensure the GPU operates under optimal electrical conditions. This includes, for example, compensating for high-frequency signal attenuation by setting specific pre-emphasis values. If no matching parameters exist in the database, the controller uses preset intermediate electrical parameters, including intermediate resistance and equalization parameters. These intermediate values ​​are also based on empirical data derived from measurements of the general electrical characteristics of various GPUs. For example, statistical analysis of the impedance and signal transmission characteristics of common GPU models determines default resistance values ​​(e.g., 50Ω) and equalization settings (e.g., median pre-emphasis coefficient) suitable for most scenarios.

[0064] Subsequently, the controller uses the formula Calculate the output voltage, where V in R is the actual input voltage measured by a voltmeter (e.g., 1.2V). eq Z0 is the intermediate resistance value (e.g., 50Ω), and Z0 is the transmission line impedance measured by a network analyzer (e.g., 50Ω). For a specific example, assume the measured value is V... in =1.2V, R eq =50Ω, Z0=50Ω, substitute into the formula to calculate: V out= (1.2 × 50) / (50 + 50) = 1.2 × 0.5 = 0.6V. Based on this output voltage, the controller further transforms the voltage-to-resistance mapping table (built based on measurement data) to obtain the optimal resistance parameters, such as adjusting the resistor array to 45Ω to match the target output voltage. At the same time, it combines intermediate equalization parameters (such as a pre-emphasis coefficient of 0.5) to configure the equalization circuit of the resistor array to optimize signal integrity. This method of parameter acquisition and formula transformation based on measurement not only ensures the accuracy of resistor array configuration, but also reduces the risk of configuration failure due to missing parameters by dynamically adapting measurement data. In addition, by combining measurement data and formula calculation, the reliability of signal transmission and circuit operating efficiency are optimized, signal distortion and power consumption are reduced, making it particularly suitable for complex application scenarios requiring high-precision signal processing.

[0065] In one embodiment, bit error detection of the resistor array is performed via an interconnect extender, and the detected data is transmitted to the controller, including:

[0066] If a corresponding target graphics processing unit exists in the preset database and the link training is completed, the link bit error rate is detected.

[0067] If the link bit error rate is less than the preset bit error threshold, the electrical parameters corresponding to the target graphics processing unit are used as preferred parameters and uploaded to the controller to update the preset database and adjust the configuration parameters of the resistor array according to the electrical parameters.

[0068] In response to a link bit error rate greater than or equal to a preset threshold, the resistance parameters are kept unchanged, and a fine-tuning loop of equalization parameters is executed to obtain at least one equalization parameter. Bit error rate detection is performed based on this parameter to obtain a set of detection results. The equalization parameter corresponding to the lowest bit error rate point in the set of detection results is selected as the electrical parameter, uploaded to the controller, the preset database is updated, and the configuration parameters of the resistor array are adjusted according to the electrical parameter.

[0069] If the target graphics processing unit does not exist in the preset database and the link training is completed, the link bit error rate is detected.

[0070] If the link bit error rate is less than the preset bit error threshold, the electrical parameters corresponding to the target graphics processing unit are used as preferred parameters and uploaded to the controller to update the preset database and adjust the configuration parameters of the resistor array according to the electrical parameters.

[0071] In response to a link bit error rate greater than or equal to a preset threshold, the equalization parameter fine-tuning loop is executed while keeping the resistance parameters unchanged to obtain at least one equalization parameter. Bit error rate detection is then performed based on this parameter to obtain a set of detection results. The equalization parameter corresponding to the lowest bit error rate point in this set of detection results is selected as the electrical parameter, uploaded to the controller, and the configuration parameters of the resistor array are adjusted according to the electrical parameter.

[0072] Bit error detection refers to the process of evaluating link transmission quality by detecting erroneous bits in data transmission, typically using the bit error rate (BER) as a quantitative metric. Link training refers to the process of synchronizing and optimizing the sender and receiver during data transmission link establishment through protocol handshakes or signal adjustments, such as adaptive equalization or voltage regulation to ensure stable communication. The link BER refers to the proportion of erroneous bits to the total transmitted bits when transmitting data on a specific link, used to measure the reliability of link transmission. A preset BER threshold is a pre-defined upper limit for the BER, used to determine whether the link transmission quality meets performance requirements; for example, it might be set to 10. -12 Equalization parameter fine-tuning loop refers to an iterative process of adjusting equalization parameters (such as pre-emphasis or de-emphasis coefficients) by testing different parameter combinations multiple times to optimize signal transmission quality.

[0073] Specifically, after link training is completed, the link bit error rate (BER) is detected by the interconnect extender. The detection data comes from error statistics in actual data transmission, such as measuring the link BER using a BER tester (e.g., the BERTScope BSX series). When the corresponding parameters for the target graphics processing unit exist in the preset database and the BER is lower than the preset BER threshold, the controller confirms the current electrical parameters (including resistance parameters and equalization parameters) as the preferred parameters, uploads them to the database, and adjusts the resistor array configuration accordingly to ensure the graphics processing unit operates under optimal electrical conditions. If the BER is higher than or equal to the threshold, the method keeps the resistance parameters unchanged and starts a fine-tuning loop for the equalization parameters. Different equalization parameters are tested iteratively (e.g., gradually adjusting the pre-emphasis coefficient from 0.3 to 0.7, in increments of 0.1). After each test, a set of BER data is generated through BER detection, and the equalization parameter with the lowest BER is selected as the preferred electrical parameter. The database is then updated, and the resistor array configuration is adjusted. For cases where the corresponding parameter is not found in the database, the method also detects the bit error rate after link training. If it is below the threshold, the current electrical parameters are directly updated in the database as preferred parameters, and the resistor array is configured. If it is above the threshold, the same equalization parameter fine-tuning loop is executed, optimizing the parameters and updating the configuration based on the detection results. For a specific example, assume the link bit error rate detection value is 10. -10 The preset threshold is 10. -12The method obtains a set of bit error rate data by fine-tuning the cyclic test equalization parameters (e.g., 0.3 corresponds to 10). -9 0.5 corresponds to 10 -11 0.7 corresponds to 10 -10 The method optimizes signal integrity by selecting 0.5 as the preferred equalization parameter. This approach, based on real-time error detection and dynamic parameter optimization, not only reduces the risk of transmission errors caused by initial parameter mismatch through measurement-driven parameter adjustment, but also significantly improves signal transmission efficiency and stability through fine-tuning loops. It is particularly suitable for high-performance computing environments, such as dynamic link optimization for GPU clusters in data centers. Furthermore, by automating the error detection and parameter optimization process, this method reduces the complexity and time cost of manual intervention, providing efficient and reliable technical support for complex graphics processing tasks, while also offering flexible adaptability for new device integration or link performance improvements.

[0074] In one embodiment, the controller generates a detection result based on the detection data and controls the activation state of the target graphics processing unit based on the detection result, including:

[0075] If the link error rate is less than the preset error threshold in response to the detection result, the target graphics processing unit is enabled.

[0076] If the link error rate in response to the detection result is greater than or equal to the preset error threshold, the target graphics processing unit is controlled to be disabled.

[0077] The "enabled" state refers to the target graphics processing unit (GPU) being activated and operating normally, allowing it to perform data processing or computational tasks. The "disabled" state refers to the target GPU being paused or disabled, typically used to prevent erroneous data processing or system instability caused by poor link quality.

[0078] Specifically, the controller first generates a detection result based on the detection data provided by the interconnect extender (e.g., real-time statistics of error bits transmitted through a bit error rate tester). This result includes a specific numerical value of the link bit error rate, which reflects the data transmission reliability of the target graphics processing unit under the current link configuration. If the detection result shows that the link bit error rate is lower than a preset bit error threshold (e.g., 10), the controller will then proceed with the detection. -12 This indicates that the link transmission quality meets the system performance requirements. The controller then activates the target graphics processing unit, allowing it to perform graphics processing or computation tasks normally, ensuring efficient system operation. If the detection result shows that the link bit error rate is higher than or equal to the preset bit error threshold (e.g., 10), it indicates that the link transmission quality meets the system performance requirements. The controller then activates the target graphics processing unit, allowing it to perform graphics processing or computation tasks normally, ensuring efficient system operation. -10 ≥10 -12This indicates a high risk of errors in the link transmission, which could lead to data processing errors or system instability. The controller then disables the target graphics processing unit, suspending its operation to prevent error propagation. By assessing link quality in real time and making corresponding decisions, the risk of system performance degradation or data corruption caused by link errors is effectively reduced. Through automated detection and state control mechanisms, the complexity and time cost of manual intervention are significantly reduced, providing efficient and reliable technical support for complex graphics processing tasks. Simultaneously, it offers flexible adaptability for stable system operation in scenarios of dynamic expansion or fluctuating link quality.

[0079] In one embodiment, controlling the activation state of the target graphics processing unit based on the detection result by the controller further includes:

[0080] In response to the target graphics processing unit being enabled, the controller periodically acquires the operating status data of the target graphics processing unit, which includes power consumption data and signal transmission rate.

[0081] Based on the operating status data, the performance index of the target graphics processing unit is calculated. The performance index is calculated using the formula P=S / W, where P is the performance index, S is the signal transmission rate, and W is the power consumption data.

[0082] If the performance index is greater than or equal to the preset performance threshold, the target graphics processing unit is kept in the enabled state and the current electrical parameters are recorded to the preset database.

[0083] If the performance index is less than the preset performance threshold, the interconnect extender is triggered to perform secondary error detection and generate secondary detection results.

[0084] In response to the link error rate being less than the preset error threshold in the secondary detection result, the target graphics processing unit is kept in the enabled state and the equalization parameters are fine-tuned. New preferred equalization parameters are generated through the equalization parameter fine-tuning loop, the preset database is updated, and the resistor array configuration is adjusted according to the updated preferred equalization parameters.

[0085] If the link error rate is greater than or equal to the preset error threshold in response to the secondary detection result, the target graphics processing unit is controlled to enter a disabled state, and a warning signal is generated by the controller to notify other servers in the server cluster.

[0086] Among them, the operational status data refers to the real-time data generated by the target graphics processing unit during operation, including power consumption data (e.g., real-time power consumption in watts) and signal transmission rate (e.g., data transmission speed in Gbps), used to evaluate its performance and stability; performance indicators are used to measure the balance between signal transmission efficiency and power consumption of the target graphics processing unit, reflecting its operational efficiency; preset performance thresholds refer to the pre-set lower limit of performance indicators, used to determine whether the target graphics processing unit meets the requirements for efficient operation; secondary bit error rate detection refers to the additional bit error rate detection performed by the interconnect extender when the performance indicators are not met, used to further verify link quality and provide data support for configuration optimization; warning signals are signals generated by the controller and sent to the server cluster through the cluster data synchronization hardware unit when the target graphics processing unit is disabled due to excessively high link bit error rate, used to notify other servers to coordinate system operation.

[0087] Specifically, the controller obtains real-time power consumption (e.g., 50W) and transmission rate (e.g., 100Gbps) from the GPU's monitoring interface. Based on this data, the controller calculates performance metrics using the formula P=S / W, for example, P=100 / 50=2Gbps / W. If the performance metric is higher than a preset performance threshold (e.g., 1.5Gbps / W), it indicates that the GPU is operating efficiently, and the controller records the current electrical parameters to a preset database. If the performance metric is lower than the threshold, the controller triggers the interconnect extender to perform secondary bit error rate detection, generating secondary detection results through a bit error rate tester. If the secondary detection results show that the link bit error rate is lower than a preset threshold (e.g., 100Gbps / W), the controller determines the performance. −12 The method generates new optimal equalization parameters through a fine-tuning loop of equalization parameters (e.g., adjusting the pre-emphasis coefficient from 0.5 to 0.6 in 0.05 steps), updates the database, and adjusts the resistor array configuration to optimize signal transmission quality. If the bit error rate exceeds a threshold, the controller disables the GPU and generates a warning signal through the cluster data synchronization hardware unit to notify the server cluster to coordinate task allocation. By monitoring operational status and evaluating performance indicators, combined with secondary bit error detection and parameter optimization, the method not only effectively improves the signal transmission efficiency and energy efficiency of the graphics processing unit but also enhances the system's coordination and fault tolerance in a cluster environment through the warning mechanism.

[0088] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described graphics processing unit signal compatibility method embodiments when it is run.

[0089] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0090] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both, such as Figure 3 As shown, to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the above description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0091] The above provides a detailed description of a signal compatibility method for a graphics processing unit provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A signal compatibility device for a graphics processing unit, characterized in that, include: The controller, processor, interconnect expander, at least one graphics processing unit, and at least one resistor array; The controller is connected to the processor and the at least one resistor array, the at least one resistor array is connected to the at least one graphics processing unit and the interconnect expander, the interconnect expander is connected to the processor, the at least one graphics processing unit corresponds one-to-one with the at least one resistor array, and the resistor array is composed of multiple adjustable resistors; The controller acquires the electrical parameters corresponding to the target graphics processing unit and configures its corresponding resistor array. The interconnect extender detects the resistor array and transmits the detection data to the controller. The controller controls the activation state of the target graphics processing unit according to the detection results. The resistor array completes the programming configuration according to the retrieval parameters issued by the controller.

2. The signal compatibility device for a graphics processing unit according to claim 1, characterized in that, The device also includes a memory connected to the controller for storing a preset database.

3. The signal compatibility device for a graphics processing unit according to claim 1, characterized in that, The device further includes a cluster data synchronization hardware unit, which is connected to the controller and is used to exchange the controller's data information with other servers in the server cluster via a network.

4. The signal compatibility device for a graphics processing unit according to claim 1, characterized in that, The device further includes a programmable logic device connected to the interconnect extender, which is used to take over some timing control, logic operations and computational processing of the interconnect extender.

5. A method for signal compatibility of a graphics processing unit, applied to the signal compatibility device of a graphics processing unit as described in any one of claims 1-4, characterized in that, The method includes: The controller obtains the identifier of the target graphics processing unit through the processor; The controller queries the corresponding target graphics processing unit in the preset database based on the identifier and obtains its electrical parameters; The controller transmits the electrical parameters to the resistor array corresponding to the target graphics processing unit, adjusts the electrical parameters, and configures the resistor array according to the adjusted electrical parameters. The interconnect extender performs bit error detection on the resistor array and transmits the detection data to the controller. The controller generates detection results based on the detection data and controls the activation status of the target graphics processing unit based on the detection results.

6. A signal compatibility method for a graphics processing unit according to claim 5, characterized in that, The step of querying the target graphics processing unit corresponding to the identifier in the preset database through the controller and obtaining its electrical parameters includes: If the target graphics processing unit does not exist in the preset database, then preset electrical parameters are obtained; If a corresponding target graphics processing unit exists in the preset database, its corresponding electrical parameters are obtained.

7. A signal compatibility method for a graphics processing unit according to claim 5, characterized in that, The electrical parameters include resistance parameters and equalization parameters. The step of transmitting the electrical parameters to the resistor array corresponding to the target graphics processing unit via the controller, adjusting the electrical parameters, and configuring the resistor array according to the adjusted electrical parameters includes: In response to the existence of a corresponding target graphics processing unit in the preset database, the resistor array is configured based on the corresponding resistance parameters and equalization parameters of the target graphics processing unit. In response to the absence of a corresponding target graphics processing unit in the preset database, preset intermediate electrical parameters are obtained, including: intermediate resistance parameters and intermediate equalization parameters; according to: ； The voltage output is calculated and converted to obtain the optimal resistance parameters, where V in V is the input voltage. out For the output voltage, R eq Z0 represents the intermediate resistance parameter, and Z0 is the transmission line impedance. The resistor array is configured according to the preferred resistor parameters and the intermediate value equalization parameters.

8. A signal compatibility method for a graphics processing unit according to claim 7, characterized in that, The process of performing bit error detection on the resistor array via the interconnect extender and transmitting the detection data to the controller includes: If the target graphics processing unit exists in the preset database and the link training is completed, the link bit error rate is detected. In response to the link bit error rate being less than a preset bit error threshold, the electrical parameters corresponding to the target graphics processing unit are used as preferred parameters and uploaded to the controller to update the preset database and adjust the configuration parameters of the resistor array according to the electrical parameters; In response to the link bit error rate being greater than or equal to a preset threshold, the resistor parameters are kept unchanged, and a fine-tuning loop of equalization parameters is executed to obtain at least one equalization parameter. Bit error rate detection is then performed based on the equalization parameter to obtain a set of detection results. The equalization parameter corresponding to the lowest bit error rate point is selected from the set of detection results as the electrical parameter, uploaded to the controller, the preset database is updated, and the configuration parameters of the resistor array are adjusted according to the electrical parameter. If the target graphics processing unit does not exist in the preset database and the link training is completed, the link bit error rate is detected. In response to the link bit error rate being less than a preset bit error threshold, the electrical parameters corresponding to the target graphics processing unit are used as preferred parameters and uploaded to the controller to update the preset database and adjust the configuration parameters of the resistor array according to the electrical parameters; In response to the link bit error rate being greater than or equal to the preset threshold, the equalization parameter fine-tuning loop is executed while keeping the resistor parameters unchanged to obtain at least one equalization parameter. Bit error rate detection is then performed based on the equalization parameter to obtain a set of detection results. The equalization parameter corresponding to the lowest bit error rate point is selected from the set of detection results as the electrical parameter and uploaded to the controller. The configuration parameters of the resistor array are then adjusted according to the electrical parameter.

9. A signal compatibility method for a graphics processing unit according to claim 8, characterized in that, The step of generating a detection result based on the detection data through the controller, and controlling the activation state of the target graphics processing unit based on the detection result, includes: If the link error rate of the detection result is less than a preset error threshold, the target graphics processing unit is controlled to be enabled. If the link error rate of the detection result is greater than or equal to a preset error threshold, the target graphics processing unit is controlled to be disabled.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 5 to 9.

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