A control method and related apparatus

Abstract

The application discloses a control method and related device, relates to the technical field of memory-computing integrated chips, and comprises the following steps: determining the stable time length of each sampling bit line of an analog-digital conversion module; determining the activation time of each sampling bit line based on the stable time length of each sampling bit line, wherein the activation time of the sampling bit line is at least earlier than the sampling start time of the sampling bit line by the corresponding stable time length; controlling the activation of each sampling bit line at the activation time of each sampling bit line; and controlling the closing of the sampling bit line after the sampling of the analog-digital conversion module is completed. The application controls the activation of the sampling bit line at least by the corresponding stable time length before the sampling of the sampling bit line, so that the sampling bit line is ensured to be stable before sampling, wherein the activation time is determined based on the sampling time of each sampling bit line and the stable time length, and the sampling bit line is controlled to be closed in time after sampling is completed, so that the time length of the sampling bit line in the activated state is shortened, and therefore, the redundant energy consumption is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory-computing integrated chips, and in particular to a control method and related device. BACKGROUND

[0002] The memory-computing integrated chip array based on analog signals utilizes the physical relationship of current, voltage and resistance in the storage array to perform calculation on the input analog signals, and then converts the analog signals of the calculation results output by the storage array into digital signals through an analog-to-digital conversion module (ADC) to output the calculation results. In order to ensure the sampling stability of the ADC, all bit lines connected with the ADC are usually activated at the beginning of the calculation task, that is, the entire storage array is opened, and sampling is started after all bit lines are stabilized until sampling of all bit lines is completed.

[0003] When the entire storage array is opened, current will flow through each storage cell, and energy consumption will be generated on each storage cell according to the calculation formula of current work power. Therefore, the energy consumption of the entire matrix will continue until the calculation results on all bit lines are sampled by the ADC. In the case of sampling multiple bit lines by a single analog-to-digital conversion module in time sequence, since the entire storage array is opened, that is, the bit lines not sampled are in an activated state waiting to be sampled, there is a large amount of redundant energy consumption. SUMMARY

[0004] In view of the above problems, the present application provides a control method and related device to achieve the purpose of reducing the redundant energy consumption of the storage matrix. The specific scheme is as follows:

[0005] The first aspect of the present application provides a control method, comprising:

[0006] determining the stable time length of each sampling bit line of the analog-to-digital conversion module based on the calculation task;

[0007] determining the activation time of each sampling bit line based on the stable time length of each sampling bit line, the activation time of the sampling bit line being at least ahead of the sampling start time of the sampling bit line by the corresponding stable time length;

[0008] controlling to activate each sampling bit line at the activation time of each sampling bit line, and controlling to close the sampling completed sampling bit line after the analog-to-digital conversion module completes sampling of the sampling bit line.

[0009] In a possible implementation, determining the stable time length of each sampling bit line of the analog-to-digital conversion module comprises:

[0010] determining the weight value of each storage cell on each sampling bit line based on the calculation task;

[0011] Determine the stable time length of each sampling bit line based on the weight value of each corresponding storage unit.

[0012] In a possible implementation, determine the activation time of each sampling bit line based on the stable time length of each sampling bit line, including:

[0013] Take the initial time as the activation time of the starting sampling bit line with a sampling sequence of 1;

[0014] If the standard deviation of the stable time length of each sampling bit line is greater than a preset standard deviation threshold:

[0015] After adjusting the sampling sequence of the sampling bit line corresponding to the maximum stable time length to 1, determine the sampling sequence of each target sampling bit line except the starting sampling bit line based on the standard sampling sequence configured by the computing task;

[0016] Delay the initial time by the stable time length of the starting sampling bit line to obtain the sampling start time of the starting sampling bit line;

[0017] Determine the sampling start time of each target sampling bit line based on the sampling start time of the starting sampling bit line, the sampling sequence of each target sampling bit line, and the sampling time length of the analog-to-digital conversion module;

[0018] Advance the sampling start time of each target sampling bit line by the corresponding stable time length to obtain the activation time of each target sampling bit line.

[0019] In a possible implementation, determine the sampling start time of each target sampling bit line based on the sampling start time of the starting sampling bit line, the sampling sequence of each target sampling bit line, and the sampling time length of the analog-to-digital conversion module, including:

[0020] Determine the cumulative sampling time length of the analog-to-digital conversion module before the target sampling bit line based on the sampling time length of the analog-to-digital conversion module and the sampling sequence of the target sampling bit line;

[0021] Delay the sampling start time of the starting sampling bit line by the corresponding cumulative sampling time length to obtain the sampling start time of the target sampling bit line.

[0022] In a possible implementation, determine the activation time of each sampling bit line based on the stable time length of each sampling bit line, and further include:

[0023] If the standard deviation of the stable time length of each sampling bit line is not greater than the standard deviation threshold, take the standard sampling sequence of each sampling bit line configured by the computing task as the sampling sequence of each sampling bit line;

[0024] delay the initial moment by the maximum stable duration to obtain a sampling start moment of the initial sampling bit line;

[0025] starting from the initial moment, sequentially determine the activation moment of each target sampling bit line except the initial sampling bit line with the sampling duration of the analog-digital conversion module as a time interval.

[0026] In a possible implementation, the control method further includes:

[0027] control the analog-digital conversion module to start sampling each sampling bit line in sequence according to the corresponding sampling timing sequence starting from the sampling start moment of the initial sampling bit line.

[0028] The second aspect of the present application provides a control device, including:

[0029] a stable duration determination unit configured to determine the stable duration of each sampling bit line of the analog-digital conversion module based on a computing task;

[0030] an activation moment determination unit configured to determine the activation moment of each sampling bit line based on the stable duration of each sampling bit line, the activation moment of the sampling bit line being at least ahead of the sampling start moment of the sampling bit line by the corresponding stable duration;

[0031] a bit line control unit configured to control each sampling bit line to be activated at the activation moment of each sampling bit line, and control the sampling bit line to be closed after the analog-digital conversion module completes sampling on the sampling bit line.

[0032] The third aspect of the present application provides a computer program product, including computer readable instructions, when the computer readable instructions run on an electronic device, the electronic device implements the control method of the first aspect or any implementation manner of the first aspect.

[0033] The fourth aspect of the present application provides an electronic device, including at least one processor and a memory connected with the processor, wherein:

[0034] the memory is configured to store a computer program;

[0035] the processor is configured to execute the computer program, so that the electronic device can implement the control method of the first aspect or any implementation manner of the first aspect.

[0036] The fifth aspect of the present application provides a memory-computing integrated chip, including a memory array, an analog-digital conversion module and a controller, the controller is configured to:

[0037] determine the stable duration of each sampling bit line of the analog-digital conversion module based on a computing task;

[0038] determine an activation time of each of the sampling bit lines based on the stable time length of each of the sampling bit lines, the activation time of the sampling bit line being at least in advance of the sampling start time of the sampling bit line by the corresponding stable time length;

[0039] control the activation of each of the sampling bit lines at the activation time of each of the sampling bit lines, and control the closing of the sampling bit line after the sampling of the sampling bit line by the analog-digital conversion module is completed.

[0040] According to the technical solution, the control method and the related device provided by the present application determine the stable time length of each sampling bit line of the analog-digital conversion module based on the computing task, wherein the sampling bit line is a bit line in the storage array connected to the analog-digital conversion module; determine the activation time of each sampling bit line based on the stable time length of each sampling bit line, the activation time of the sampling bit line being at least in advance of the sampling start time of the sampling bit line by the corresponding stable time length; control the activation of each of the sampling bit lines at the activation time of each of the sampling bit lines, and control the closing of the sampling bit line after the sampling of the sampling bit line by the analog-digital conversion module is completed. The present application controls the activation of the sampling bit line at least in advance of the corresponding stable time length before starting the sampling of each sampling bit line, so as to ensure that the sampling bit line is stable before sampling, wherein the activation time is determined based on the sampling time of each sampling bit line and the stable time length, and the sampling bit line is closed in time after the sampling is completed, so as to shorten the time length of the sampling bit line in the activated state, thereby reducing the redundant energy consumption. BRIEF DESCRIPTION OF DRAWINGS

[0041] The above and other features, advantages, and aspects of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

[0042] Figure 1 An example of a matrix operation effect diagram of a storage array is shown;

[0043] Figure 2 A structure diagram of an integrated storage and computing chip provided by an embodiment of the present application is shown;

[0044] Figure 3 A flow diagram of a control method provided by an embodiment of the present application is shown;

[0045] Figure 4 A flow diagram of another control method provided by an embodiment of the present application is shown;

[0046] Figure 5 A specific structure diagram of an integrated storage and computing chip provided by an embodiment of the present application is shown;

[0047] Figure 6 A control effect schematic diagram provided for an embodiment of the present application;

[0048] Figure 7 Another control effect schematic diagram provided for an embodiment of the present application;

[0049] Figure 8 A structure schematic diagram of a control device provided for an embodiment of the present application;

[0050] Figure 9 A structure schematic diagram of an electronic device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0051] The embodiments of the present application will be described in detail below with the accompanying drawings. The terms used in the embodiment part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0052] The embodiments of the present application will be described below with the accompanying drawings. It is known to those skilled in the art that the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems as technology develops and new scenarios appear.

[0053] The terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, and this is only a way of distinguishing the objects with the same attributes in the description of the embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that the processes, methods, systems, products or devices containing a series of units do not have to be limited to those units, but can include other units not clearly listed or inherent to these processes, methods, products or devices.

[0054] In the storage array in the storage-computing integrated chip, the storage units are arranged in a cross array form, the rows are connected to word lines, and the columns are connected to bit lines. Each cross point is a programmable storage unit (such as a memristor RRAM, a floating gate transistor NOR Flash, etc.). The threshold voltage or resistance value of the storage unit can be adjusted to represent different weight values, realizing the storage of analog matrix data. In the matrix computing scenario, the computing task is Y = XW, wherein, is a weight parameter, is an input, , The specific computing task can be referred to in Figure 1 The left matrix computing formula. Figure 1 An example of a matrix operation effect schematic diagram of a storage array is shown inFigure 1 As shown, the storage array is an n×m interleaved array. The physical quantities in each storage cell represent weight parameters, thus forming the matrix parameters. The physical quantity in the storage cell at the intersection of the i-th row and j-th column represents... For example, the physical quantity in the storage cell at the intersection of the 3rd row and 3rd column represents... .

[0055] Under the aforementioned computational tasks, the in-memory computing chip converts digital signals into digital signals via a digital-to-analog converter (DAC). ~ After being converted into analog voltage or current, it is applied to each row word line. Analog operations are then performed using the physical quantities stored in the memory cells on each column bit line. Finally, an analog-to-digital converter (ADC) converts the analog operation results on each bit line into digital signals. ~ Output the results of the calculation.

[0056] It should be noted that after an analog signal is input into the memory array, current flows through each memory cell on the bit lines and finally reaches the connected ADC. The time delay from the start of bit line activation and word line signal input until the signal reaches the ADC and stabilizes is called the "bit line settling time." In some in-memory computing chips, the array settling time can even be longer than the ADC's sampling time. To ensure sampling stability, the ADC can only begin sampling after the bit line settling time has elapsed. Therefore, existing control methods turn on the entire memory array at the start of the computation task, that is, activate all bit lines at the start of the computation task, and begin sampling after all bit lines have stabilized.

[0057] When the entire memory array is turned on, current flows through each memory cell, and according to the formula for calculating the power done by current, each memory cell consumes energy. Therefore, the energy consumption of the entire matrix continues until the calculation results on all bit lines are sampled by the ADC. When a single analog-to-digital converter samples multiple bit lines sequentially, since the entire memory array is turned on, that is, the unsampled bit lines are in an active state waiting to be sampled, there is a large amount of redundant energy consumption.

[0058] To address the aforementioned problems, embodiments of this application provide a control method and related apparatus. The control method and related apparatus of this application will be described in detail below with reference to the accompanying drawings.

[0059] Reference Figure 2 , Figure 2 This is a schematic diagram of the structure of a memory computing chip provided in an embodiment of this application, as shown below. Figure 2As shown, the storage-computation integrated chip includes a controller, a storage array, and an analog-digital conversion module, wherein the storage array includes a plurality of storage units arranged in a cross array form, a row connection word line for inputting an analog signal, a column connection bit line for outputting an analog operation result, and the analog-digital conversion module has at least one quantity for converting the analog operation result output by the corresponding bit line into a digital signal. The controller is used for activation control of the word line and the bit line, and connection conduction of the bit line and the corresponding analog-digital conversion module. It should be noted that, according to the type of the storage unit, the controller controls the activation of the word line and the bit line and the conduction of the analog-digital conversion module by different specific control methods.

[0060] Referring to Figure 3 , Figure 3 A flowchart of a control method provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, a data processing method provided by an embodiment of the present application can include S301 to S303, which will be described in detail below. Figure 3

[0061] S301, based on a computing task, determining a stable time length of each sampling bit line of an analog-digital conversion module.

[0062] In this embodiment, the stable time length of the bit line refers to the time required from the activation of the word line to the bit line signal reaching a sampleable stable state.

[0063] In a possible embodiment, the method for obtaining the stable time length of the sampling bit line includes:

[0064] Based on the computing task, the weight values of each storage unit on each sampling bit line are determined. Based on the weight values of the corresponding storage units, the stable time length of each sampling bit line is determined. In different circuit structures, the weight values of each storage unit on the sampling bit line have different influences on the stable time length. The mapping relationship between the stable time length and the weight values can be constructed in advance according to the specific circuit structure, so as to determine the stable time length based on the mapping relationship.

[0065] It should be noted that when determining the stable time length of each sampling bit line of the analog-digital conversion module, the stable time length can also be adjusted according to the current array external environment. Optionally, the stable time length influence coefficient under various external environment parameters can be calibrated in advance, the stable time length influence coefficient is determined according to the real-time external environment parameter, and the stable time length is corrected based on the stable time length influence coefficient, so as to improve the accuracy of the stable time length.

[0066] S302, based on the stable time length of each sampling bit line, determining the activation time of each sampling bit line.

[0067] In this embodiment, the activation time of the sampling bit line is at least ahead of the sampling start time of the sampling bit line by the corresponding stable time length. ​

[0068] S303, control the activation time of each sampling bit line, activate each sampling bit line, and control the sampling completed sampling bit line to be closed after the analog-to-digital conversion module completes sampling on the sampling bit line.

[0069] From the above technical solution, it can be seen that the control method provided by the embodiment of the application determines the stable time length of each sampling bit line of the analog-to-digital conversion module; based on the stable time length of each sampling bit line, the activation time of each sampling bit line is determined, and the activation time of the sampling bit line is at least ahead of the sampling start time of the sampling bit line by the corresponding stable time length; control the activation time of each sampling bit line, activate each sampling bit line, and control the sampling completed sampling bit line to be closed after the analog-to-digital conversion module completes sampling on the sampling bit line. Before sampling on the sampling bit line, the application controls the activation of the sampling bit line at least ahead of the corresponding stable time length, ensures that the sampling bit line reaches stability before sampling, wherein the activation time is determined based on the sampling time of each sampling bit line and the stable time length, and the sampling completed sampling bit line is controlled to be closed in time, thus shortening the time length of the sampling bit line in the activated state, thereby reducing the redundant energy consumption.

[0070] Based on the above embodiment, see Figure 4 , Figure 4 The flowchart of another control method provided by the embodiment of the application is shown in Figure 4 S302 is shown, that is, based on the stable time length of each sampling bit line, the activation time of each sampling bit line is determined, as shown in Figure 4 The method specifically includes S401-S410, which will be described in detail below. Based on the stable time length of each sampling bit line, the activation time of each sampling bit line includes:

[0071] S401, the initial time is taken as the activation time of the starting sampling bit line with a sampling sequence of 1.

[0072] In this embodiment, the initial time is determined based on the computing task, for example, in response to receiving a computing task, the computing task is immediately started to be executed, and the starting sampling bit line with a sampling sequence of 1 is activated.

[0073] S402, determine whether the standard deviation of the stable time length of each sampling bit line is greater than a preset standard deviation threshold.

[0074] In this embodiment, the standard deviation of the stable time length of each sampling bit line is first calculated. The standard deviation can reflect the consistency of the stable time length of all sampling bit lines. When the standard deviation is not greater than the standard deviation threshold, the consistency of the stable time length of the sampling bit line is high, and the distribution fluctuation is low. When the standard deviation of the stable time length of the sampling bit line is greater than the standard deviation threshold, it indicates that the consistency of the stable time length of each sampling bit line is low, and there is a large stable time length fluctuation.

[0075] S403, if yes, adjust the sampling time sequence of the sampling bit line corresponding to the maximum stable time length to 1, and determine the sampling time sequence of each target sampling bit line except the starting sampling bit line based on the standard sampling time sequence configured by the calculation task.

[0076] In this embodiment, the maximum stable time length is the maximum value of the stable time lengths of all sampling bit lines.

[0077] When the standard deviation of the stable time length of the sampling bit line is greater than the standard deviation threshold, the standard sampling time sequence configured by the calculation task is obtained, the maximum stable time length is obtained, and the sampling time sequence of the sampling bit line corresponding to the maximum stable time length is adjusted to 1, that is, the sampling time sequence of the sampling bit line corresponding to the maximum stable time length is advanced to the first bit, and the sampling bit line with time sequence k is denoted as Lk, and the sampling bit line corresponding to the maximum stable time length is denoted as L1.

[0078] S404, delay the initial time by the stable time length of the starting sampling bit line to obtain the sampling start time of the starting sampling bit line.

[0079] In this embodiment, the initial time is denoted as t1, and the stable time length of the starting sampling bit line is denoted as w1, then the sampling start time C1 of the starting sampling bit line is obtained by delaying t1 by w1, for example, the initial time is 0, and w1=160ns, then the 160ns is the sampling start time of the starting sampling bit line.

[0080] S405, based on the sampling time length of the analog-to-digital conversion module and the sampling time sequence of the target sampling bit line, determine the cumulative sampling time length of the analog-to-digital conversion module before the target sampling bit line.

[0081] In this embodiment, the sampling time sequence of the target sampling bit line minus 1 is the number of sampling bit lines that have been sampled before the target sampling bit line, that is, the total number of times of sampling of the analog-to-digital conversion module. Taking the target sampling bit line as the sampling bit line Lk with time sequence k as an example, the cumulative sampling time length of the analog-to-digital conversion module before the target sampling bit line is Sk=(k-1)xd, where d represents the sampling time length of one sampling.

[0082] S406, delay the sampling start time of the starting sampling bit line by the corresponding cumulative sampling time length to obtain the sampling start time of the target sampling bit line.

[0083] In this embodiment, taking the target sampling bit line as the sampling bit line Lk with time sequence k as an example, the sampling start time Ck of the target sampling bit line is C1+Sk.

[0084] S405~ S406 is a specific implementation method for determining the sampling start time of the target sampling bit line based on the sampling start time of the starting sampling bit line, the sampling time sequence of each target sampling bit line, and the sampling time length of the analog-to-digital conversion module.

[0085] S407, advance the sampling start time of each target sampling bit line by a corresponding stable time length to obtain the activation time of each target sampling bit line.

[0086] Taking the above example, the sampling start time of the target sampling bit line is Ck, that is, the target sampling bit line is sampled at time Ck, and the activation time of the target sampling bit line is tk=Ck-wk.

[0087] S408, if not, the standard sampling timing of each sampling bit line configured by the calculation task is used as the sampling timing of each sampling bit line.

[0088] In this embodiment, when the standard deviation is not greater than the standard deviation threshold value, the consistency of the stable time length of the sampling bit line is higher, and the distribution volatility is lower, and the standard sampling timing is directly used as the sampling timing of each sampling bit line.

[0089] S409, delay the initial time by the maximum stable time length to obtain the sampling start time of the starting sampling bit line.

[0090] S410, starting from the initial time, determine the activation time of each target sampling bit line except the starting sampling bit line in sequence with the sampling time length of the analog-to-digital conversion module as the time interval.

[0091] In this embodiment, the activation time of each sampling bit line is an arithmetic sequence with the standard sampling timing as the order position, the initial time as the starting value, and the time interval as the difference value. Moreover, the sampling start time of each sampling bit line is an arithmetic sequence with the standard sampling timing as the order position, the sampling start time obtained by delaying the initial time by the maximum stable time length as the starting value, and the sampling time length as the difference value.

[0092] For example, the maximum stable time length is 160ns and the sampling time length is 20ns, the initial time is 0, the activation time of each sampling bit line is [0, 20ns, 40ns, 60ns, 80ns, 100ns…], and the sampling start time of each sampling bit line is [160, 180ns, 200ns, 220ns, …], that is, when the sampling bit line starts sampling, 8 columns of sampling bit lines are activated in advance.

[0093] As can be seen from the above technical solution, the control method provided in this application uses the initial time as the activation time of the starting sampling bit line with a sampling timing of 1. When the standard deviation of the stable duration of each sampling bit line is greater than the standard deviation threshold, the timing of the sampling bit line with the longest stable duration is adjusted to the first position. The initial time is delayed after the stable duration of the starting sampling bit line to obtain the sampling start time of the starting sampling bit line. For each target sampling bit line, the time after the stable duration of the starting sampling bit line and the accumulated sampling duration is used as the sampling start time. The activation time obtained by further advancing the corresponding stable duration must be after the initial time. Furthermore, the target sampling bit line is activated at this activation time, ensuring that the sampling bit line has reached its stable duration when the sampling start time is reached. This achieves sampling stability and reduces the sampling waiting time after reaching the stable duration, thereby reducing redundant energy consumption.

[0094] Furthermore, if the standard deviation of the stable duration of each sampling bit line is not greater than the standard deviation threshold, the initial time is delayed by the maximum stable duration to obtain the sampling start time of the initial sampling bit line. Thus, the activation time of each target sampling bit line arranged in an arithmetic progression is obtained directly according to the sampling duration as the time interval. This achieves the activation of each sampling bit line at equal intervals, thereby ensuring sampling stability while reducing computational complexity.

[0095] Based on the above embodiments, the control method provided in this application further includes: controlling the analog-to-digital conversion module to sample each sampling bit line sequentially according to the corresponding sampling timing, starting from the sampling start time of the initial sampling bit line. That is, controlling the mode conversion module to sample the sampling bit lines sequentially according to the sampling timing, while maintaining a consistent sampling clock throughout.

[0096] Figure 5 This is a schematic diagram of the specific structure of a memory computing chip provided in an embodiment of this application, as shown below. Figure 5 As shown, the in-memory computing chip includes a controller, a memory array, a bit line activation control circuit, and a bit line switching control circuit. The A line, also known as the word line, connects to the input of a row of memory cells; the B line, also known as the bit line, connects to the output of a column of memory cells; and the C line, also known as the activation control line, connects to the control terminal of a column of memory cells. Figure 5 As shown, line A and line B form an orthogonal or non-orthogonal array, and line C is parallel to line B.

[0097] The bit line activation control circuit controls the activation state of the corresponding B line through the C line. The B line in the activation state is used to output the analog settlement result of the analog signal input to the A line. Specifically, by giving a high voltage V1 on the C line, each storage unit connected in series with the corresponding B line is opened, and current can flow through the storage unit for analog signal operation. By giving a low voltage V2 on the C line, each storage unit connected in series with the corresponding B line is opened and closed, and current cannot flow through the storage unit, or the current flowing through the storage unit will be much smaller than the current when the storage unit is opened.

[0098] The bit line switching circuit connects the bit line connected with the switching analog-digital conversion module through a switch, and realizes the conduction of the analog-digital conversion module and the corresponding sampling bit line at each sampling start time.

[0099] In this embodiment, the controller is configured to determine the stable time length of each sampling bit line of the analog-digital conversion module based on the calculation task. Based on the stable time length of each sampling bit line, the activation time of each sampling bit line is determined. The controller controls the activation of each sampling bit line at the activation time of each sampling bit line, and controls the closing of the sampling bit line after the sampling of the analog-digital conversion module on the sampling bit line is completed. Furthermore, the controller controls the analog-digital conversion module to start sampling each sampling bit line in sequence according to the corresponding sampling time sequence from the start sampling time of the start sampling bit line.

[0100] Since the activation time of the sampling bit line is at least ahead of the sampling start time of the sampling bit line by the corresponding stable time length, the C line is at a high voltage V1, and the corresponding storage unit has energy consumption. When the C line is at a low voltage V2, the energy consumption in the corresponding storage unit can be ignored. Therefore, by controlling the activation of each sampling bit line at the activation time of each sampling bit line by the controller, and controlling the closing of the sampling bit line after the sampling of the analog-digital conversion module on the sampling bit line is completed, a part of the C line can be in an open state, and the other part of the C line can be in a closed state. Reducing the redundant energy consumption in the overall storage array during the execution of the calculation task. Furthermore, by controlling the timely closing of the sampling bit line after the sampling of the analog-digital conversion module is completed by the controller, the redundant energy consumption is further reduced.

[0101] Taking the stable time length of each sampling bit line as 160ns and the sampling time length as 20nm as an example, the controller controls the activation of one sampling bit line every 20nm after the activation of the first sampling bit line. When the analog-digital converter starts sampling the sampling bit line, the number of sampling bit lines opened in advance = array stable time length / ADC sampling time length = 8, that is, 8 columns of storage units are opened in advance.

[0102] Further, the two parts of the control circuit jointly receive control of a programmable controller: keep both linkage, perform a variety of array opening and ADC sampling following strategy, the size of the opening array is controllable, and too many columns are not opened to make the current flow through the storage unit for a long time, and the sampling time is too long, causing energy loss. Ensure that the time of array opening is advanced, so that the part of the array is opened before sampling enough time to reach stability.

[0103] Figure 6 A control effect diagram provided by an embodiment of the present application, because the weight values stored in each storage unit in the storage array are different, the lengths of the bit line stabilization time of each bit line are different. Therefore, when the controller controls the advance activation of the sampling bit line, the activation time is determined based on the stabilization time of each sampling bit line. In the case of longer stabilization time, the number of sampling bit lines opened in advance is larger, and vice versa. As shown in Figure 6 , the stabilization time of the current sampling bit line L2 and the sampling bit line after it is shorter, so only 1 column of bit line after L2 needs to be opened in advance. The stabilization time of the current sampling bit line L6 and the sampling bit line after it is longer, so 3 columns of bit line after L6 need to be opened in advance, so as to ensure that the signal has reached stability when the 3 columns of bit line are sampled.

[0104] It can be seen that for the part of the array with shorter stabilization time, the number of opened columns is reduced, thereby reducing the current and power consumption. For the part of the array with longer stabilization time, the number of opened columns is increased, thereby ensuring the stability and accuracy of the output signal when the ADC is sampled.

[0105] Figure 7 Another control effect diagram provided by an embodiment of the present application is shown in Figure 7 , in the case where the number of analog-to-digital conversion modules is multiple, each analog-to-digital conversion module is controlled. Taking the example of the analog-to-digital conversion modules including ADC-1 and ADC-2, the current opening array L{ADC-1} of ADC-1 (framed by a dashed line) includes the current sampling line L2 of ADC-1 and 2 columns of un-sampled lines opened in advance, and the current opening array L{ADC-2} of ADC-2 (framed by a dashed line) includes the current sampling line L6 of ADC-2 and 2 columns of un-sampled lines opened in advance.

[0106] It can be seen that when the number of analog-to-digital conversion modules is multiple, each analog-to-digital conversion module corresponds to a current opening array. After sampling starts, the current opening array includes the current sampling bit line and at least one sampling bit line after the current sampling bit line in time sequence.

[0107] Please refer to Figure 8 , Figure 8 A structure diagram of a control device provided by an embodiment of the present application is shown inFigure 8 The control device 800 includes:

[0108] The stable duration determination unit 801 is configured to determine the stable duration of each sampling bit line of the analog-to-digital conversion module based on the calculation task.

[0109] The activation time determination unit 802 is configured to determine the activation time of each sampling bit line based on the stable duration of each sampling bit line, wherein the activation time of the sampling bit line is at least ahead of the sampling start time of the sampling bit line by the corresponding stable duration.

[0110] The bit line control unit 803 is configured to control the activation of each sampling bit line at the activation time of each sampling bit line, and control the closing of the sampling bit line after the analog-to-digital conversion module completes sampling on the sampling bit line.

[0111] In a possible implementation, when the stable duration determination unit is used to determine the stable duration of each sampling bit line of the analog-to-digital conversion module, the stable duration determination unit is specifically configured to:

[0112] determine the weight value of each storage unit on each sampling bit line based on the calculation task;

[0113] determine the stable duration of each sampling bit line based on the weight value of the corresponding storage unit.

[0114] In a possible implementation, when the activation time determination unit is used to determine the activation time of each sampling bit line based on the stable duration of each sampling bit line, the activation time determination unit is specifically configured to:

[0115] take the initial time as the activation time of the starting sampling bit line with a sampling sequence of 1;

[0116] If the standard deviation of the stable duration of each sampling bit line is greater than a preset standard deviation threshold:

[0117] after adjusting the sampling sequence of the sampling bit line corresponding to the maximum stable duration to 1, determine the sampling sequence of each target sampling bit line except the starting sampling bit line based on the standard sampling sequence configured by the calculation task;

[0118] delay the initial time by the stable duration of the starting sampling bit line to obtain the sampling start time of the starting sampling bit line;

[0119] determine the sampling start time of the target sampling bit line based on the sampling start time of the starting sampling bit line, the sampling sequence of each target sampling bit line, and the sampling duration of the analog-to-digital conversion module;

[0120] The sampling start time of each target sampling bit line is advanced by a corresponding stable time length to obtain an activation time of each target sampling bit line.

[0121] In a possible implementation, the activation time determination unit is configured to determine the sampling start time of the target sampling bit line based on the sampling start time of the starting sampling bit line, the sampling time sequence of each target sampling bit line, and the sampling time length of the analog-digital conversion module, and specifically configured to:

[0122] determine a cumulative sampling time length of the analog-digital conversion module before the target sampling bit line based on the sampling time length of the analog-digital conversion module and the sampling time sequence of the target sampling bit line;

[0123] delay the sampling start time of the starting sampling bit line by a corresponding cumulative sampling time length to obtain the sampling start time of the target sampling bit line.

[0124] In a possible implementation, the activation time determination unit is configured to determine the activation time of each sampling bit line based on the stable time length of each sampling bit line, and specifically further configured to:

[0125] if the standard deviation of the stable time length of each sampling bit line is not greater than the standard deviation threshold, set the standard sampling time sequence of each sampling bit line configured by the calculation task as the sampling time sequence of each sampling bit line;

[0126] delay the initial time by the maximum stable time length to obtain the sampling start time of the starting sampling bit line;

[0127] start from the initial time, and sequentially determine the activation time of each target sampling bit line except the starting sampling bit line with the sampling time length of the analog-digital conversion module as a time interval.

[0128] In a possible implementation, the control device further includes:

[0129] The sampling control unit is configured to control the analog-digital conversion module to start sampling each sampling bit line in sequence according to the corresponding sampling time sequence at the sampling start time of the starting sampling bit line.

[0130] The embodiments of the present application further provide an electronic device. Figure 9 A structural schematic diagram suitable for implementing the electronic device in the embodiments of the present application is shown. The electronic device in the embodiments of the present application can include but is not limited to a fixed terminal such as a mobile phone, a notebook computer, a PDA (personal digital assistant), a PAD (tablet computer), a desktop computer, and the like. Figure 9 The electronic device shown is only an example, and should not bring any limitation to the functions and use range of the embodiments of the present application.

[0131] As shown in Figure 9 The electronic device can include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 901 that can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 902 or loaded into a random access memory (RAM) 903 from a storage device 908. In a state in which the electronic device is powered on, various programs and data required for operation of the electronic device are also stored in the RAM 903. The processing device 901, the ROM 902, and the RAM 903 are connected to each other through a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0132] In general, the following devices can be connected to the I / O interface 905: input devices 906 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 907 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 908 including, for example, a memory card, a hard disk, etc.; and communication devices 909. The communication devices 909 can allow the electronic device to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 9 An electronic device having various devices is shown, but it is understood that all of the shown devices are not required to be implemented or possessed. More or fewer devices can be alternatively implemented or possessed.

[0133] The embodiments of the present application also provide a computer program product including computer readable instructions, which, when executed on an electronic device, cause the electronic device to implement any of the control methods provided by the embodiments of the present application.

[0134] The embodiments of the present application also provide a computer readable storage medium carrying one or more computer programs, which, when executed by an electronic device, can cause the electronic device to implement any of the control methods provided by the embodiments of the present application.

[0135] In addition, it should be noted that the apparatus embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., they can be located in one place, or distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments. In addition, the connection relationship between the modules in the apparatus embodiments provided by the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0136] Those skilled in the art can clearly understand that the application can be implemented by means of software plus necessary universal hardware, and of course can also be implemented by means of dedicated hardware including special integrated circuit, special CPU, special memory, special component, etc. Generally, any function completed by computer program can be easily implemented by corresponding hardware, and the specific hardware structure for implementing the same function can also be various, such as analog circuit, digital circuit or special circuit, etc. However, for the application, software program implementation is a better embodiment. Based on such understanding, the technical solution of the application or the part of the application which makes contribution to the prior art can be embodied in the form of software product, which is stored in readable storage medium, such as computer floppy disk, U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., and includes a plurality of instructions for making a computer device (which can be personal computer, training device or network device, etc.) execute the method described in various embodiments of the application.

[0137] In the above embodiments, the implementation can be achieved by software, hardware, firmware or any combination thereof, entirely or partially. When implemented by software, the implementation can be achieved in the form of a computer program product, entirely or partially.

[0138] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the flow or function described in the embodiments of the application is generated entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer, training device or data center to another website, computer, training device or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be stored by a computer or a data storage device such as a training device, a data center, etc. integrated with one or more available media sets. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

Claims

1. A control method, characterized in that, include: Based on the computational task, the stabilization time of each sampling bit line of the analog-to-digital conversion module is determined; Based on the stable duration of each of the sampling bit lines, the activation time of each of the sampling bit lines is determined, and the activation time of the sampling bit line is at least the corresponding stable duration earlier than the sampling start time of the sampling bit line. At the activation time of each of the sampling bit lines, each sampling bit line is activated, and after the analog-to-digital conversion module has completed sampling of the sampling bit lines, the sampling bit lines that have completed sampling are turned off.

2. The control method according to claim 1, characterized in that, The determination of the stabilization time of each sampling bit line of the analog-to-digital conversion module includes: Based on the computational task, the weight values ​​of each storage unit on each of the sampling bit lines are determined. The stable duration of each sampling bit line is determined based on the weight values ​​of each corresponding storage unit.

3. The control method according to claim 2, characterized in that, The determination of the activation time of each sampling bit line based on the stability duration of each sampling bit line includes: The initial time is used as the activation time of the starting sampling bit line with sampling timing 1; If the standard deviation of the stability duration of each of the sampling bit lines is greater than the preset standard deviation threshold: After adjusting the sampling timing of the sampling bit line corresponding to the maximum stable duration to 1, the sampling timing of each target sampling bit line other than the initial sampling bit line is determined based on the standard sampling timing configured for the computing task. The sampling start time of the initial sampling bit line is obtained by delaying the initial time by the stabilization time of the initial sampling bit line. The sampling start time of the target sampling bit line is determined based on the sampling start time of the starting sampling bit line, the sampling timing of each target sampling bit line, and the sampling duration of the analog-to-digital conversion module. The activation time of each target sampling bit line is obtained by advancing the sampling start time of each target sampling bit line by the corresponding stabilization time.

4. The control method according to claim 3, characterized in that, The determination of the sampling start time of the target sampling bit line based on the sampling start time of the initial sampling bit line, the sampling timing of each target sampling bit line, and the sampling duration of the analog-to-digital conversion module includes: Based on the sampling duration of the analog-to-digital conversion module and the sampling timing of the target sampling bit line, the cumulative sampling duration of the analog-to-digital conversion module before the target sampling bit line is determined; The sampling start time of the target sampling bit line is obtained by delaying the sampling start time of the starting sampling bit line by the corresponding cumulative sampling duration.

5. The control method according to claim 3, characterized in that, The step of determining the activation time of each sampling bit line based on the stability duration of each sampling bit line further includes: If the standard deviation of the stable duration of each of the sampling bit lines is not greater than the standard deviation threshold, the standard sampling timing of each of the sampling bit lines configured in the computing task shall be used as the sampling timing of each of the sampling bit lines. The sampling start time of the initial sampling bit line is obtained by delaying the initial time by the maximum stable duration. Starting from the initial moment, the activation time of each target sampling bit line, excluding the initial sampling bit line, is determined sequentially, with the sampling duration of the analog-to-digital conversion module as the time interval.

6. The control method according to any one of claims 3 to 5, characterized in that, The control method further includes: The analog-to-digital conversion module is controlled to start sampling each sampling bit line sequentially according to the corresponding sampling timing, starting at the sampling start time of the initial sampling bit line.

7. A control device, characterized in that, include: The stability duration determination unit is used to determine the stability duration of each sampling bit line of the analog-to-digital conversion module based on the computation task. An activation time determination unit is used to determine the activation time of each of the sampling bit lines based on the stability duration of each of the sampling bit lines, wherein the activation time of the sampling bit line is at least the corresponding stability duration earlier than the sampling start time of the sampling bit line. The bit line control unit is used to activate each of the sampling bit lines at the activation time of each of the sampling bit lines, and to control the sampling bit lines that have completed sampling to be turned off after the analog-to-digital conversion module has completed sampling.

8. An electronic device, characterized in that, The electronic device includes at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is used to execute the computer program to enable the electronic device to implement the control method as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, Includes computer-readable instructions that, when executed on a memory, cause the memory to implement the control method as described in any one of claims 1 to 6.

10. A memory computing chip, characterized in that, The in-memory computing chip includes a storage array, an analog-to-digital converter module, and a controller, wherein the controller is used for: Based on the computational task, the stable duration of each sampling bit line of the analog-to-digital conversion module is determined; Based on the stable duration of each of the sampling bit lines, the activation time of each of the sampling bit lines is determined, and the activation time of the sampling bit line is at least the corresponding stable duration earlier than the sampling start time of the sampling bit line. At the activation time of each of the sampling bit lines, each sampling bit line is activated, and after the analog-to-digital conversion module has completed sampling of the sampling bit lines, the sampling bit lines that have completed sampling are turned off.

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