Quantum bit partitioning, circuit adjustment method and apparatus, medium and product

Abstract

The application discloses a quantum bit partitioning and circuit adjusting method, device, medium and product, the method comprises the following steps: according to the topology structure of physical quantum bits in a quantum chip, adopting a hierarchical partitioning method to perform hierarchical partitioning on the physical quantum bits; performing quality evaluation on all quantum bit partitions in each layer to obtain partition evaluation results of all quantum bit partitions in each layer; and according to the partition evaluation results and the complexity of quantum circuits, allocating quantum bit partitions to quantum circuits in a parallel quantum circuit set. According to the topology structure of physical quantum bits in a quantum chip, the connectivity of each physical quantum bit is determined, the physical quantum bits are partitioned hierarchically according to the connectivity, all possible effective partitions are retained, quality evaluation is performed on all quantum bit partitions in each layer, and according to the partition evaluation results and the complexity of quantum circuits, the optimal unoccupied quantum bit partition is allocated to the current quantum circuit.

Description

Technical Field

[0001] This invention relates to the field of quantum technology, and in particular to a method, apparatus, medium, and product for partitioning quantum bits and adjusting circuits. Background Technology

[0002] Parallel processing technology for multiple quantum computing tasks is a novel approach to quantum computing task processing. Compared to mainstream single-quantum computing task processing techniques, this technology can manage and optimize the concurrent execution of multiple quantum computing tasks. First, it manages and schedules multiple quantum computing tasks to determine the task combinations for combined execution. Then, it performs qubit partitioning and mapping, allocating the necessary hardware resources to the quantum circuits corresponding to each task. Finally, a scheduling algorithm determines the execution time of the quantum circuits. This fully utilizes hardware resources, enabling the combined execution of multiple quantum circuits to improve the throughput of quantum hardware and enhance task processing efficiency for multiple quantum computing tasks.

[0003] Currently, the qubit partitioning mapping method in parallel processing techniques for multiple quantum computing tasks achieves qubit partitioning by continuously merging qubit partition nodes with the largest reward function to construct a structure tree. However, each partition node can only participate in the merge once, directly losing a large number of potentially effective partitions. This results in a homogeneous final partitioning result, failing to provide diverse hardware resource options for quantum circuits of varying complexity and limiting the adaptability of multi-circuit parallelism. Alternatively, instead of pre-dividing qubit partitions, qubit partitions are dynamically generated based on the quantum computing task. This process sacrifices more time complexity and introduces a greedy approach during partition generation, failing to obtain globally optimal partitioning results for multiple quantum computing tasks. Therefore, existing qubit partitioning mapping methods suffer from insufficient partition diversity and global optimality. Summary of the Invention

[0004] This invention provides a method, apparatus, medium, and product for qubit partitioning and circuit adjustment, which can solve the problems of insufficient partition diversity and global optimality in existing qubit partitioning and mapping methods, thereby improving the processing efficiency of quantum computing tasks.

[0005] To achieve the above objectives, embodiments of the present invention provide a quantum bit partitioning method, comprising:

[0006] Based on the topological structure of the physical qubits in the quantum chip, a hierarchical partitioning method is adopted to partition the physical qubits into hierarchical partitions. The hierarchical partitioning method is a partitioning strategy that divides the physical qubits in the quantum chip into a qubit partition layer by layer according to the hierarchical progressive logic and the connectivity of the qubits in the topological structure of the physical qubits.

[0007] The quality of all qubit partitions in each layer is evaluated to obtain the partition evaluation results of all qubit partitions in each layer;

[0008] Based on the partition evaluation results and the complexity of the quantum circuit, the qubit partitions are assigned to the quantum circuits in the parallel quantum circuit set.

[0009] As an improvement to the above scheme, the step of partitioning the physical qubits into hierarchical partitions based on the topological structure of the physical qubits in the quantum chip includes:

[0010] The topological structure of the physical qubits in the quantum chip is obtained. Based on the topological structure, a hierarchical partitioning method is adopted to divide each physical qubit in the quantum chip into a single qubit partition and classify all single qubit partitions into a single bit layer.

[0011] Starting from the single-bit layer, according to the connectivity of the qubits in the topology, the corresponding bit layers are constructed layer by layer in increasing order of bit number until all physical qubits are divided into a single qubit partition, thus completing the hierarchical partitioning of the physical qubits.

[0012] As an improvement to the above scheme, the step of constructing corresponding bit layers layer by layer according to the connectivity of qubits in the topology and in ascending order of bit number until all physical qubits are divided into a single qubit partition, thereby completing the hierarchical partitioning of the physical qubits, includes:

[0013] All single-qubit partitions in the single-qubit layer are combined in pairs, and each pair of combinations with the connectivity of the topological structure is taken as a two-qubit partition. All two-qubit partitions are classified into a two-qubit layer.

[0014] A three-qubit layer is obtained by combining two-qubit partitions with the same qubits in the two-qubit layer.

[0015] If all physical qubits are not assigned to a single qubit partition, then the next qubit layer is obtained by combining the qubits according to the qubit partitions of the current qubit layer in ascending order of the number of qubits, until all physical qubits are assigned to a single qubit partition, thus completing the hierarchical partitioning of the physical qubits.

[0016] As an improvement to the above scheme, the step of performing quality evaluation on all qubit partitions in each layer to obtain the partition evaluation results for all qubit partitions in each layer includes:

[0017] The quality of all qubit partitions in each layer is evaluated according to the quality evaluation formula, and the partition evaluation results are sorted from largest to smallest to obtain the partition evaluation results of all qubit partitions in each layer.

[0018] As an improvement to the above scheme, the step of allocating the qubit partitions to the quantum circuits in the parallel quantum circuit set based on the partition evaluation results and the complexity of the quantum circuits includes:

[0019] The quantum circuits in the parallel quantum circuit set are sorted according to their complexity.

[0020] The quantum bit partitions are assigned to the quantum circuits in sequence according to the partition evaluation results and sorting results.

[0021] As an improvement to the above scheme, the step of allocating the qubit partitions to the quantum circuit according to the partition evaluation results and sorting results includes:

[0022] Based on the partition evaluation and sorting results, the optimal qubit partition in the bit layer corresponding to the current quantum circuit to be allocated is selected according to the number of qubits required for the current quantum circuit to be allocated.

[0023] If the optimal qubit partition is already occupied by the preceding quantum circuit, then the second-best qubit partition in the corresponding bit layer is selected.

[0024] If all qubit partitions in the corresponding bit layer are occupied by the preceding quantum circuit, then the second-best qubit partition in the corresponding bit layer is selected again for the previously allocated quantum circuit, and the occupied best qubit partition is released.

[0025] Then, the optimal qubit partition is assigned to the currently unassigned quantum circuit until all quantum circuits in the parallel quantum circuit set are assigned to the qubit partition.

[0026] As an improvement to the above scheme, before considering the partitioning evaluation results and the complexity of the quantum circuit, the method further includes:

[0027] The quantum computing tasks in the task list are combined and evaluated to obtain the set of parallel quantum circuits for the quantum computing tasks.

[0028] As an improvement to the above scheme, the step of combining and evaluating the quantum computing tasks in the task list to obtain the set of parallel quantum circuits for the quantum computing tasks includes:

[0029] The quantum computing task at the top of the task list is used as the benchmark task. Other quantum computing tasks in the task list are evaluated in combination and then sorted from largest to smallest according to the evaluation results.

[0030] The quantum circuit corresponding to the benchmark task is added to the parallel quantum circuit set. If the number of qubits in the parallel quantum circuit set is less than a preset threshold, the quantum circuits corresponding to other quantum computing tasks are sequentially selected from the sorted task list and added to the parallel quantum circuit set until the number of qubits in the parallel quantum circuit set is not less than the preset threshold.

[0031] To achieve the above objectives, embodiments of the present invention provide a quantum circuit adjustment method, comprising:

[0032] Each quantum circuit in the parallel quantum circuit set is executed independently, and the independent execution result of each quantum circuit is obtained;

[0033] According to the execution timing scheme of the parallel quantum circuit set, all quantum circuits in the parallel quantum circuit set are executed in a merged manner to obtain the merged execution result of each quantum circuit;

[0034] Based on the independent execution results and the merged execution results, the execution mode of the quantum circuits in the parallel quantum circuit set is adjusted.

[0035] As an improvement to the above scheme, adjusting the execution mode of the parallel quantum circuit cluster based on the independent execution results and the combined execution results includes:

[0036] Statistically analyze the probability distribution of qubit states in the independent execution results and combined execution results of each quantum circuit;

[0037] The difference between the probability distribution of the merged execution result and the probability distribution of the independent execution result is calculated to obtain the fidelity loss of the merged execution.

[0038] If the fidelity loss is greater than a preset fidelity threshold, then each quantum circuit in the parallel quantum circuit set is executed independently.

[0039] If the fidelity loss is not greater than the preset fidelity threshold, then all quantum circuits in the parallel quantum circuit set are merged and executed.

[0040] To achieve the above objectives, embodiments of the present invention provide a quantum bit partitioning device, comprising:

[0041] A quantum bit partitioning module is used to partition the physical quantum bits in the quantum chip according to the topological structure of the physical quantum bits using a hierarchical partitioning method; wherein, the hierarchical partitioning method is a partitioning strategy that divides the physical quantum bits in the quantum chip into a quantum bit partition layer by layer according to the connectivity relationship of the quantum bits in the topological structure of the physical quantum bits, following a hierarchical progressive logic.

[0042] The bit partition evaluation module is used to evaluate the quality of all qubit partitions in each layer and obtain the partition evaluation results of all qubit partitions in each layer.

[0043] A quantum circuit allocation module is used to allocate the qubit partitions to the quantum circuits in the parallel quantum circuit set based on the partition evaluation results and the complexity of the quantum circuits.

[0044] To achieve the above objectives, embodiments of the present invention provide a quantum circuit adjustment device, comprising:

[0045] The independent execution module is used to execute each quantum circuit in the parallel quantum circuit set independently and obtain the independent execution result of each quantum circuit.

[0046] The line merging execution module is used to merge and execute all quantum lines in the parallel quantum circuit set according to the execution timing scheme of the parallel quantum circuit set, and obtain the merged execution result of each quantum circuit.

[0047] The line execution adjustment module is used to adjust the execution mode of the quantum circuits in the parallel quantum circuit set according to the independent execution results and the combined execution results.

[0048] To achieve the above objectives, embodiments of the present invention provide a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the above-described qubit partitioning method or the above-described quantum circuit adjustment method.

[0049] To achieve the above objectives, embodiments of the present invention also provide a computer-readable storage medium, the computer-readable storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to execute the above-described qubit partitioning method or the above-described quantum circuit adjustment method.

[0050] To achieve the above objectives, embodiments of the present invention also provide a computer program product, which is stored in a storage medium and executed by at least one processor to implement the steps of the above-described quantum bit partitioning method or the steps of the above-described quantum circuit adjustment method.

[0051] Compared with existing technologies, the present invention discloses a quantum bit partitioning, circuit adjustment method, apparatus, medium, and product. This method partitions the physical qubits in a quantum chip according to their topological structure using a hierarchical partitioning approach. It then performs quality evaluation on all qubit partitions in each layer to obtain partition evaluation results. Based on the partition evaluation results and the complexity of the quantum circuits, it allocates the qubit partitions to the quantum circuits in a parallel quantum circuit set. By determining the connectivity of each physical qubit based on its topological structure, performing hierarchical partitioning based on this connectivity, retaining all possible valid partitions, evaluating the quality of all qubit partitions in each layer, and allocating the optimal unoccupied qubit partition to the current quantum circuit based on the partition evaluation results and the complexity of the quantum circuits, this invention solves the problems of insufficient partition diversity and global optimality in existing quantum bit partitioning mapping methods, thereby improving the processing efficiency of quantum computing tasks. Attached Figure Description

[0052] Figure 1 This is a flowchart illustrating a quantum bit partitioning method provided in an embodiment of the present invention;

[0053] Figure 2 This is a flowchart of a parallel processing method for a quantum computing task provided in an embodiment of the present invention;

[0054] Figure 3 This is a schematic flowchart of a quantum circuit adjustment method provided in an embodiment of the present invention;

[0055] Figure 4 This is a framework diagram of a parallel processing mechanism for quantum computing tasks provided in an embodiment of the present invention;

[0056] Figure 5 This is a schematic diagram of the structure of a quantum bit partitioning device provided in an embodiment of the present invention;

[0057] Figure 6 This is a schematic diagram of the structure of a quantum circuit adjustment device provided in an embodiment of the present invention;

[0058] Figure 7 This is a schematic diagram of the structure of a terminal device provided in an embodiment of the present invention. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] It should be noted that the terms "comprising" and "specific" in this invention, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0061] Please see Figure 1 , Figure 1 This is a flowchart illustrating a quantum bit partitioning method provided in an embodiment of the present invention. The quantum bit partitioning method includes:

[0062] S11, Based on the topological structure of the physical qubits in the quantum chip, the physical qubits are divided into hierarchical partitions using a hierarchical partitioning method; wherein, the hierarchical partitioning method is a partitioning strategy that divides the physical qubits in the quantum chip into a qubit partition layer by layer according to the hierarchical progressive logic and the connectivity relationship of the qubits in the topological structure of the physical qubits.

[0063] S12, perform quality evaluation on all qubit partitions in each layer to obtain the partition evaluation results of all qubit partitions in each layer;

[0064] S13, Based on the partition evaluation results and the complexity of the quantum circuit, assign the qubit partitions to the quantum circuits in the parallel quantum circuit set.

[0065] For example, the physical qubit topology of the quantum chip is obtained (clarifying the physical connectivity between each physical qubit). Each qubit is treated as a partition, forming a single-qubit layer. Based on the physical connectivity between physical qubits, all pairs of connected qubits are combined into a partition, forming a double-qubit layer. This process is repeated until all physical qubits are grouped into a partition, forming a full-qubit layer, thus completing the hierarchical partitioning of physical qubits. Each partition satisfies the following: uniqueness (no duplicate partitions within the same layer); connectivity (all qubits within a partition are physically connected); and integrity (all physical qubits are covered within each partition). The quality of all qubit partitions in each layer is evaluated based on key parameters of the physical qubits (average fidelity of qubit measurements and average fidelity of quantum gate operations between any two connected qubits). All qubit partitions within the same layer are sorted from highest to lowest quality evaluation result. This sorting result represents the partition evaluation result for that layer, thus obtaining the partition evaluation result for all qubit partitions in each layer. The hierarchical partitioning of this invention covers partitions with different numbers of bits, which can adapt to the resource requirements of different quantum circuits and provide diverse choices and quantitative guidance for the partitioning allocation of parallel quantum circuit sets, so as to ensure the efficiency and fidelity of quantum circuit execution.

[0066] It should be noted that the above steps S11-S12 can be regarded as the preliminary preparation work in the parallel processing mechanism of quantum computing tasks. They are offline operations and do not need to be repeated each time a quantum computing task is processed in parallel. Specifically, the qubit hierarchical partitioning only needs to be repeated when the physical qubit topology in the quantum chip changes, and the hierarchical evaluation is repeated after the fidelity information is updated.

[0067] Specifically, step S11 includes:

[0068] S111, Obtain the topological structure of the physical qubits in the quantum chip, and adopt a hierarchical partitioning method according to the topological structure to divide each physical qubit in the quantum chip into a single qubit partition, and classify all single qubit partitions into a single bit layer;

[0069] S112, starting from the single-bit layer, according to the connectivity of the qubits in the topology, the corresponding bit layers are constructed layer by layer in increasing order of bit number until all physical qubits are divided into a single qubit partition, thus completing the hierarchical partitioning of the physical qubits.

[0070] like Figure 2 As shown, Figure 2 This is a flowchart of a parallel processing method for a quantum computing task provided by an embodiment of the present invention, such as... Figure 2The illustrated qubit hierarchical partitioning section obtains the physical qubit topology from the bottom layer of the quantum chip, then assigns each qubit as a partition to a single-qubit layer. Based on the single-qubit layer, all partitions within that layer are paired, and combinations with connectivity are assigned as partitions to a two-qubit layer, determined by the connectivity of the physical qubit topology. When constructing a three-qubit layer, partitions with identical qubits in the two-qubit layers are directly combined. Subsequent layer construction simply involves combining partitions from the previous layer, until all qubits are grouped into a single partition, thus completing the qubit hierarchical partitioning. Each partition within a layer must be unique.

[0071] More specifically, step S112 includes:

[0072] S1121, All single-qubit partitions in the single-qubit layer are combined in pairs, and each pair of combinations with the connectivity of the topological structure is taken as a two-qubit partition, and all two-qubit partitions are classified into a two-qubit layer.

[0073] S1122, Combine the two-qubit partitions with the same qubits in the two-qubit layer to obtain a three-qubit layer;

[0074] S1123, if all physical qubits are not divided into one qubit partition, then the next qubit layer is obtained by combining the qubit partitions of the current qubit layer in ascending order of the number of qubits, until all physical qubits are divided into one qubit partition, thus completing the hierarchical partitioning of the physical qubits.

[0075] For example, suppose there is a simple quantum chip containing 5 qubits, labeled as follows: , , , , In its topology and , Connected, and , Connected, and Connected, and Connected, It is not connected to any other qubits. The process of partitioning and stratifying qubits:

[0076] Single-bit layer: partitioned into { }、{ }、{ }、{ }、{ };

[0077] Two-bit layer: Based on connectivity, the combinations with connectivity are { , }、{ , }、{ , This forms three two-bit partitions;

[0078] Three-bit layer: In two-bit layer { , }and{ , } have the same number of qubits , combined to form { , , } partition; { , }and{ , } have the same number of qubits , combined to form { , , } partition.

[0079] Four-bit layer: { , , }and{ , , } There are multiple identical qubits that can be combined to form { , , , } partition.

[0080] Five-qubit layer: Ultimately, all qubits are combined into { , , , , } partition.

[0081] Specifically, step S12 includes:

[0082] The quality of all qubit partitions in each layer is evaluated according to the quality evaluation formula, and the partition evaluation results are sorted from largest to smallest to obtain the partition evaluation results of all qubit partitions in each layer.

[0083] For example, a quality assessment is performed on all qubit partitions in each layer, and the partitions are sorted from largest to smallest based on the quality assessment results, where the quality assessment includes the connectivity of the qubits in the partition. Average fidelity of quantum bit measurement and the average fidelity of quantum gate operations on any two connected qubits. Because quality assessment is performed at the same level (i.e., with the same number of qubits), The number of edges in the corresponding partition in the topology graph / Number of qubits in the corresponding partition express, A larger value indicates a tighter physical connection between the qubits, while fidelity can be obtained from random benchmark tests. The quality assessment formula is as follows:

[0084] .

[0085] Specifically, step S13 includes:

[0086] S131, Sort the quantum circuits in the parallel quantum circuit set according to the complexity of the quantum circuits;

[0087] S132, the quantum bit partitions are assigned to the quantum circuit in sequence according to the partition evaluation results and sorting results.

[0088] For example, the set of parallel quantum circuits is sorted according to the complexity of the quantum circuits, and the quantum bit partitions are assigned to the quantum circuits sequentially according to the partition evaluation results and the sorting results. The complexity of the quantum circuit is determined by the number of multi-qubit gates in the quantum circuit. Number of qubits used in quantum circuits The formula for characterizing the complexity of a quantum circuit is as follows:

[0089] ,

[0090] In the formula, The complexity of the quantum circuit.

[0091] In this embodiment of the invention, lines with higher complexity are given priority to obtain the optimal partition of the corresponding layer, so as to avoid high-quality resources being occupied by simple tasks.

[0092] More specifically, step S132 includes:

[0093] S1321, Based on the partition evaluation results and sorting results, select the optimal qubit partition in the bit layer corresponding to the current quantum circuit to be allocated by the number of qubits required for the current quantum circuit to be allocated;

[0094] S1322, If the optimal qubit partition has been occupied by the preceding quantum circuit, then the suboptimal qubit partition in the corresponding bit layer is selected;

[0095] S1323, If all qubit partitions in the corresponding bit layer have been occupied by the preceding quantum circuit, then select the second-best qubit partition in the corresponding bit layer for the previously allocated quantum circuit and release the occupied best qubit partition.

[0096] S1324, then allocate the optimal qubit partition to the currently unallocated quantum circuit until all quantum circuits in the parallel quantum circuit set are allocated to the qubit partition.

[0097] For example, when allocating partitions, first clarify the requirements for each quantum circuit: based on the number of qubits required for the quantum circuit, determine which partition to select from the corresponding layer (e.g., for a circuit requiring 2 qubits, select a partition from the two-qubit layer); then allocate partitions sequentially according to circuit complexity: the circuit with the highest complexity is selected first, and the optimal result is evaluated from the corresponding layer (i.e., The largest, unoccupied partition is allocated and marked as used. This process is repeated for each sorted quantum line. If a line cannot find an unoccupied optimal partition in its corresponding layer (e.g., the optimal partition is occupied by a more complex line, and the suboptimal and sub-suboptimal partitions are also occupied), the process backtracks to the previous line, changes its originally allocated optimal partition to a suboptimal partition, and releases the original optimal partition to the current line. If this is still insufficient, the process continues backtracking to the previous line until the current line finds an available partition, ensuring that all lines are allocated a partition.

[0098] It should be noted that the number of bits required for a quantum circuit strictly corresponds to the partitioning and layering, ensuring that the quantum circuit can operate normally within the allocated partition. The problem of insufficient partitions is solved by backtracking and adjustment, ensuring that all parallel quantum circuits can obtain a usable partition and avoiding tasks from stalling due to lack of resources.

[0099] Furthermore, before evaluating the partitioning results and the complexity of the quantum circuit, the method further includes:

[0100] S1301, Perform a combined evaluation of the quantum computing tasks in the task list to obtain a set of parallel quantum circuits for the quantum computing tasks.

[0101] Specifically, the step of combining and evaluating the quantum computing tasks in the task list to obtain the set of parallel quantum circuits for the quantum computing tasks includes:

[0102] The quantum computing task at the top of the task list is used as the benchmark task. Other quantum computing tasks in the task list are evaluated in combination and then sorted from largest to smallest according to the evaluation results.

[0103] The quantum circuit corresponding to the benchmark task is added to the parallel quantum circuit set. If the number of qubits in the parallel quantum circuit set is less than a preset threshold, the quantum circuits corresponding to other quantum computing tasks are sequentially selected from the sorted task list and added to the parallel quantum circuit set until the number of qubits in the parallel quantum circuit set is not less than the preset threshold.

[0104] For example, the quantum computing tasks that are at the top of the queue in the task list. As a benchmark task, other quantum tasks in the task list are compared. Perform a combined evaluation and sort from largest to smallest. The corresponding quantum circuits are added to the parallel quantum circuit set, provided that the number of parallel quantum circuits is less than a preset threshold. Under the premise of continuously selecting quantum circuits corresponding to quantum computing tasks from the sorted task list and adding them to the parallel quantum circuit set, where Set as To reduce the crosstalk caused by dense use of qubits, This refers to the number of physical qubits in the quantum chip. Understandably, the preset threshold can be set according to other requirements.

[0105] The combined evaluation formula is as follows:

[0106] ,

[0107] In the formula, To combine the evaluation results, This represents the number of quantum computing tasks in the task list; This is the current task's sequence number in the task list; This indicates the depth of the quantum circuit corresponding to the quantum computing task.

[0108] It should be noted that the task at the top of the queue from the list of quantum computing tasks to be processed is selected as the baseline task to ensure the priority of task processing, and the first to arrive is processed, which conforms to the conventional task scheduling logic. At the same time, the line depth of the baseline task (which reflects the complexity of the task, and the greater the depth, the longer the task execution time) is used as a reference to select tasks with high compatibility with it, so as to reduce decoherence error during parallel processing.

[0109] Furthermore, after allocating the qubit partitions to the quantum circuits in the parallel quantum circuit set, the method further includes:

[0110] The SABRE algorithm is used to map the quantum circuit to the corresponding quantum bit partition and to the quantum chip's quantum bit partition.

[0111] For example, the qubit partitioning mapping module uses a swap-based bidirectional heuristic search algorithm (SABRE) to map qubits from quantum circuits to corresponding partitions; simultaneously, it asynchronously executes the SABRE algorithm to map qubits from quantum circuits to the entire physical qubit partition. In essence, qubit mapping maps logical qubits (virtual bits defined in the circuit code) in a quantum circuit to physical qubits (bits actually existing in the hardware) on the quantum chip. The core logic of the SABRE algorithm is to find the optimal swap gate (qubit swapping operation) through bidirectional search (looking forward several steps and backward through historical operations), ensuring that logical bits match the connection relationships of physical bits without changing the circuit logic, while minimizing the number of swap gates (swap gates increase circuit depth and introduce errors). For example, mapping the quantum circuit to the corresponding qubit partitions involves using the assigned partitions as the scope and employing the SABRE algorithm to map the logical bits of the circuit to the physical bits within the partitions, ensuring that all quantum gates in the circuit can be executed on physical bits (i.e., the two physical bits of a gate operation must be connected). Mapping the quantum circuit to the qubit partitions of the quantum chip involves simultaneously executing the main mapping within the partition and initiating an independent SABRE algorithm process. This process uses the entire physical bit set of the quantum chip as the scope and employs the SABRE algorithm to map the logical bits of the circuit to the physical bits within the partitions, generating a full-bit-level mapping scheme.

[0112] This invention uses the SABRE algorithm to map lines to allocated partitions, ensuring that lines can be executed according to schedule in a set of parallel tasks, avoiding line failures due to physical bit disconnections; asynchronous full-bit mapping is performed, and a mapping table for independent execution is prepared in advance, so that when it is determined that independent execution is required, there is no need to recalculate, saving time costs; bidirectional heuristic search is used to reduce the number of SWAP gates, avoiding the increase in line depth and decrease in fidelity caused by too many SWAP gates, which meets the high fidelity requirements of quantum computing tasks.

[0113] See Figure 3 , Figure 3 This is a flowchart illustrating a quantum circuit adjustment method provided in an embodiment of the present invention. The quantum circuit adjustment method includes:

[0114] S21, each quantum circuit in the parallel quantum circuit set is executed independently to obtain the independent execution result of each quantum circuit;

[0115] S22, according to the execution timing scheme of the parallel quantum circuit set, all quantum circuits in the parallel quantum circuit set are executed in a merged manner to obtain the merged execution result of each quantum circuit;

[0116] S23, Based on the independent execution results and the combined execution results, adjust the execution mode of the quantum circuits in the parallel quantum circuit cluster.

[0117] For example, a single line in the parallel quantum circuit set is executed in hardware independently (other lines are not executed for the time being), repeated s times, and the qubit state of each execution is recorded. The frequency of each state is then calculated. It is understood that during independent execution, only the current line is loaded, and other lines in the parallel set are not loaded to avoid crosstalk, measurement interference, etc., ensuring that the frequency reflects the true probability distribution when the line is interference-free. All lines in the parallel quantum circuit set are executed in hardware simultaneously, also repeated s times, and the qubit state of the current line is recorded in each execution, calculating the frequency of each state. It is understood that during combined execution, a strict synchronous measurement strategy (after inserting an ID gate) must be followed to ensure consistency with the subsequent formal parallel execution environment, so that the frequency reflects the actual probability distribution when the line is interfered with. The actual probability distribution and the true probability distribution are compared to adjust the execution method of the quantum lines in the parallel quantum circuit set. The embodiments of the present invention can capture uncharacterizable errors such as crosstalk and measurement interference through actual execution comparison; differentiated judgment of different lines ensures the parallel efficiency of most lines while avoiding unreliable results due to merging of individual lines; by setting a small s, effective samples are obtained while avoiding excessive hardware resource consumption, which meets the requirements of efficient quantum computing.

[0118] Specifically, step S23 includes:

[0119] S231, Calculate the probability distribution of the qubit states in the independent execution results and the combined execution results of each quantum circuit;

[0120] S232, calculate the difference between the probability distribution of the merged execution result and the probability distribution of the independent execution result to obtain the fidelity loss of the merged execution;

[0121] S233, if the fidelity loss is greater than the preset fidelity threshold, then each quantum circuit in the parallel quantum circuit set is executed independently.

[0122] S234, if the fidelity loss is not greater than the preset fidelity threshold, then all quantum circuits in the parallel quantum circuit set are merged and executed.

[0123] For example, the quantum circuits in the parallel quantum circuit set are executed separately. Second-rate, The value can be set between 50 and 60 to obtain each quantum circuit. The measurement results, wherein the number of executions The number of executions should be set much lower than the normal number, taking into account both sample validity and time cost; then the quantum circuits should be executed in combination. This time, each quantum circuit was obtained in the same way. The measurement results were analyzed; the results of independent and combined execution of each quantum circuit were statistically analyzed separately. Probability distribution of states of a quantum bit and Based on the probability distribution of the results of independent execution. Based on this, the probability distribution of the merged execution results is calculated. and The gap To represent the fidelity loss during merge execution, compare the differences. Compared with the preset fidelity threshold ,like If the result is positive, it means that the fidelity of the quantum circuit is affected during the merged execution, and it needs to be executed independently; otherwise, the merged execution continues. This is an empirical constant that can be obtained through testing in a benchmark quantum circuit. This enables flexible adjustment of the parallelism of the quantum circuit, ensuring high fidelity in the parallel processing of quantum computing tasks.

[0124] The fidelity loss formula is as follows:

[0125] ,

[0126] In the formula, The first in the independent execution result The probability distribution of a quantum bit state; For the merged execution result, the first The probability distribution of a quantum bit state.

[0127] Furthermore, before independently executing each quantum circuit in the parallel quantum circuit set, the method further includes:

[0128] S201, Determine the baseline execution timing of the parallel quantum circuit set based on the depth of each quantum circuit in the parallel quantum circuit set;

[0129] S202, based on the reference execution timing, insert a quantum ID gate at the front end of a quantum circuit that is shorter than the reference execution timing to obtain the execution timing scheme of the parallel quantum circuit set.

[0130] For example, comparing the depth of each quantum circuit in a parallel quantum circuit set. , at maximum depth Based on the quantum circuit, insert at the front end of other quantum circuits respectively The quantum ID gate (no-operation), in which To correspond to the depth of quantum circuits, the execution of lower-depth quantum circuits is delayed, and the measurement operations of each quantum circuit are synchronized, reducing the interference of the measurement operation of one quantum circuit on the fidelity of other quantum circuits.

[0131] like Figure 2 As shown, in one specific implementation, the topological structure of the physical qubits in the quantum chip is first defined. Based on the topological structure, a hierarchical partitioning method (such as building from single-qubit layers to multi-qubit layers) is used to divide the physical qubits into different "qubit hierarchical partitions," covering partition combinations with different numbers of qubits and connectivity characteristics to adapt to diverse quantum circuit requirements. For each partition, a comprehensive quality score is calculated from dimensions such as connectivity, measurement fidelity, and quantum gate operation fidelity. Sort the partitions within the same level according to their scores, output the tiered evaluation results, and for the list of quantum computing tasks to be processed, select the top-ranked task as the task benchmark. Use the combined evaluation formula to calculate the combined evaluation results of other tasks and the benchmark task. ,according to Quantum computing tasks are screened, and a set of parallel quantum circuits is generated to enable adapted tasks to collaborate and run in parallel, improving efficiency. Based on the hierarchical evaluation results (ranking high-quality partitions), each circuit in the parallel quantum circuit set is assigned a qubit partition with a corresponding bit size and quality, allowing the circuit to run on adapted hardware resources. Using algorithms such as SABRE, the logical qubits of the circuit are mapped to the physical qubits of the assigned partitions, generating a master (for merged execution) and backup (for independent execution) mapping table, bridging the logic and hardware. For the mapped quantum circuits, independent execution (single-circuit run, measuring basic fidelity) and merged execution (multi-circuit parallel run, measuring collaborative effect) are performed respectively. The fidelity loss of the two execution methods is compared. ,like Selecting to merge and execute improves processing efficiency; if Then, independent execution ensures fidelity and enables flexible scheduling. This embodiment of the invention, while ensuring computational quality, maximizes the efficiency advantages of quantum parallel computing and adapts to the diverse needs of quantum computing tasks.

[0132] like Figure 4 As shown, Figure 4 This is a framework diagram of a parallel processing mechanism for quantum computing tasks provided by an embodiment of the present invention. Figure 4 It includes four modules: a quantum computing task parallel management module, a quantum bit partitioning and mapping module, a quantum circuit scheduling and execution module, and a quantum circuit flexible parallel module. The logical relationships between the modules are as follows: Figure 4As shown, the functions of each module are described below: Quantum Computing Task Parallel Management Module: Responsible for managing and scheduling the list of quantum computing tasks, combining them to obtain a set of parallel quantum circuits; Quantum Bit Partitioning and Mapping Module: Responsible for dividing physical qubits during the preparation phase, providing qubit partitions for the set of parallel quantum circuits; Quantum Computing Task Parallel Processing Phase: Responsible for allocating partitions and mapping qubits to quantum circuits; Quantum Circuit Scheduling and Execution Module: Responsible for scheduling the start time of each quantum circuit in the set of parallel quantum circuits; Quantum Circuit Flexible Parallelism Module: Responsible for inserting independent execution of quantum circuits when merging execution of quantum circuits, comparing the results of merging and independent execution, and flexibly adjusting the execution of quantum circuits.

[0133] This invention provides a quantum circuit adjustment method that independently executes each quantum circuit in a parallel quantum circuit set to obtain an independent execution result for each quantum circuit. Based on the execution timing scheme of the parallel quantum circuit set, all quantum circuits in the set are executed in a merged manner to obtain a merged execution result for each quantum circuit. The execution mode of the quantum circuits in the parallel quantum circuit set is adjusted based on the independent execution results and the merged execution results. By comparing actual execution results, the method can directly capture the impact of difficult-to-quantize errors such as crosstalk and decoherence on fidelity, optimizing the parallel strategy from the execution stage, and ultimately ensuring the high fidelity requirements of parallel processing of multiple quantum computing tasks.

[0134] See Figure 5 , Figure 5 This is a schematic diagram of the structure of a quantum bit partitioning device 10 provided in an embodiment of the present invention. The quantum bit partitioning device 10 includes:

[0135] The quantum bit partitioning module 11 is used to partition the physical quantum bits in the quantum chip according to the topological structure of the physical quantum bits using a hierarchical partitioning method; wherein, the hierarchical partitioning method is a partitioning strategy that divides the physical quantum bits in the quantum chip into a quantum bit partition layer by layer according to the connectivity relationship of the quantum bits in the topological structure of the physical quantum bits, following a hierarchical progressive logic.

[0136] The bit partition evaluation module 12 is used to evaluate the quality of all qubit partitions in each layer and obtain the partition evaluation results of all qubit partitions in each layer.

[0137] The quantum circuit allocation module 13 is used to allocate the quantum bit partitions to the quantum circuits in the parallel quantum circuit set according to the partition evaluation results and the complexity of the quantum circuits.

[0138] Furthermore, the quantum bit partitioning device 10 also includes:

[0139] The quantum task combination module is used to combine and evaluate quantum computing tasks in the task list to obtain a set of parallel quantum circuits for the quantum computing tasks.

[0140] Furthermore, the quantum bit partitioning device 10 also includes:

[0141] The quantum bit mapping module is used to map the quantum circuit to the corresponding quantum bit partition using the SABRE algorithm, and to map the quantum circuit to the quantum bit partition of the quantum chip.

[0142] The quantum bit partitioning device 10 provided in this embodiment of the invention can realize all the processes of the quantum bit partitioning method of the above embodiments. The functions and technical effects of each module in the device are the same as the functions and technical effects of the quantum bit partitioning method of the above embodiments, and will not be repeated here.

[0143] See Figure 6 , Figure 6 This is a schematic diagram of the structure of a quantum circuit adjustment device 20 provided in an embodiment of the present invention. The quantum circuit adjustment device 20 includes:

[0144] The independent execution module 21 is used to independently execute each quantum circuit in the parallel quantum circuit set and obtain the independent execution result of each quantum circuit.

[0145] The line merging execution module 22 is used to merge and execute all quantum lines in the parallel quantum circuit set according to the execution timing scheme of the parallel quantum circuit set, and obtain the merged execution result of each quantum circuit.

[0146] The line execution adjustment module 23 is used to adjust the execution mode of the quantum circuits in the parallel quantum circuit set according to the independent execution results and the combined execution results.

[0147] Furthermore, the quantum circuit adjustment device 20 also includes:

[0148] The execution timing determination module is used to determine the reference execution timing of the parallel quantum circuit set based on the depth of each quantum circuit in the set; and to insert quantum ID gates at the front end of quantum circuits with execution times smaller than the reference execution timing based on the reference execution timing to obtain the execution timing scheme of the parallel quantum circuit set.

[0149] The quantum circuit adjustment device 20 provided in this embodiment of the invention can realize all the processes of the quantum circuit adjustment method of the above embodiments. The functions and technical effects of each module in the device are the same as the functions and technical effects of the quantum circuit adjustment method of the above embodiments, and will not be repeated here.

[0150] See Figure 7 , Figure 7 This is a schematic diagram of the structure of a terminal device 30 provided in an embodiment of the present invention. The terminal device 30 of this embodiment includes: a processor 31, a memory 32, and a computer program stored in the memory 32 and executable on the processor 31. When the processor 31 executes the computer program, it implements the steps in the above-described quantum bit partitioning method embodiment, or the steps in the above-described quantum circuit adjustment method embodiment. Alternatively, when the processor 31 executes the computer program, it implements the functions of each module in the above-described quantum bit partitioning device embodiment, or the functions of each module in the above-described quantum circuit adjustment device embodiment.

[0151] For example, the computer program may be divided into one or more modules, which are stored in the memory 32 and executed by the processor 31 to complete the present invention. The one or more modules may be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the terminal device 30.

[0152] The terminal device 30 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. The terminal device 30 may include, but is not limited to, a processor 31 and a memory 32. Those skilled in the art will understand that the schematic diagram is merely an example of the terminal device 30 and does not constitute a limitation on the terminal device 30. It may include more or fewer components than shown, or combine certain components, or use different components. For example, the terminal device 30 may also include input / output devices, network access devices, buses, etc.

[0153] The processor 31 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. The processor 31 is the control center of the terminal device 30, connecting all parts of the terminal device 30 via various interfaces and lines.

[0154] The memory 32 can be used to store the computer programs and / or modules. The processor 31 implements various functions of the terminal device 30 by running or executing the computer programs and / or modules stored in the memory 32 and calling the data stored in the memory 32. The memory 32 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory 32 may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0155] If the modules integrated in the terminal device 30 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by the processor 31, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0156] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0157] This invention also provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the quantum bit partitioning method or the quantum circuit adjustment method of the above embodiments.

[0158] Furthermore, embodiments of the present invention also provide a computer program product, which is stored in a storage medium and executed by at least one processor to implement the steps of the quantum bit partitioning method of the above embodiments, or the steps of the quantum circuit adjustment method of the above embodiments.

[0159] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for partitioning quantum bits, characterized in that, include: The topological structure of the physical qubits in the quantum chip is obtained. Based on the topological structure, a hierarchical partitioning method is adopted to divide each physical qubit in the quantum chip into a single qubit partition and classify all single qubit partitions into a single bit layer. Starting from the single-qubit layer, according to the connectivity of qubits in the topology, the corresponding qubit layers are constructed layer by layer in ascending order of the number of qubits until all physical qubits are divided into one qubit partition, thus completing the hierarchical partitioning of the physical qubits; wherein, the hierarchical partitioning method is a partitioning strategy that divides the physical qubits in the quantum chip into one qubit partition layer by layer according to the hierarchical progressive logic and the connectivity of qubits in the topology of the physical qubits. The quality of all qubit partitions in each layer is evaluated to obtain the partition evaluation results of all qubit partitions in each layer; Based on the partition evaluation results and the complexity of the quantum circuit, the quantum bit partitions are assigned to the quantum circuits in the parallel quantum circuit set.

2. The quantum bit partitioning method as described in claim 1, characterized in that, Starting from the single-qubit layer, according to the connectivity of qubits in the topology, the corresponding qubit layers are constructed layer by layer in ascending order of the number of qubits until all physical qubits are divided into a single qubit partition, thus completing the hierarchical partitioning of the physical qubits, including: All single-qubit partitions in the single-qubit layer are combined in pairs, and each pair of combinations with the connectivity of the topological structure is taken as a two-qubit partition. All two-qubit partitions are classified into a two-qubit layer. A three-qubit layer is obtained by combining two-qubit partitions with the same qubits in the two-qubit layer. If all physical qubits are not assigned to a single qubit partition, then the next qubit layer is obtained by combining the qubits according to the qubit partitions of the current qubit layer in ascending order of the number of qubits, until all physical qubits are assigned to a single qubit partition, thus completing the hierarchical partitioning of the physical qubits.

3. The quantum bit partitioning method as described in claim 1, characterized in that, The quality evaluation of all qubit partitions in each layer, resulting in partition evaluation results for all qubit partitions in each layer, includes: The quality of all qubit partitions in each layer is evaluated according to the quality evaluation formula, and the partition evaluation results are sorted from largest to smallest to obtain the partition evaluation results of all qubit partitions in each layer.

4. The quantum bit partitioning method as described in claim 1, characterized in that, The process of allocating qubit partitions to quantum circuits in the parallel quantum circuit set based on the partition evaluation results and the complexity of the quantum circuit includes: The quantum circuits in the parallel quantum circuit set are sorted according to their complexity. The quantum bit partitions are assigned to the quantum circuits in sequence according to the partition evaluation results and sorting results.

5. The quantum bit partitioning method as described in claim 4, characterized in that, The step of allocating the qubit partitions to the quantum circuit according to the partition evaluation results and sorting results includes: Based on the partition evaluation and sorting results, the optimal qubit partition in the bit layer corresponding to the current quantum circuit to be allocated is selected according to the number of qubits required for the current quantum circuit to be allocated. If the optimal qubit partition is already occupied by the preceding quantum circuit, then the second-best qubit partition in the corresponding bit layer is selected; If all qubit partitions in the corresponding bit layer are occupied by the preceding quantum circuit, then the second-best qubit partition in the corresponding bit layer is selected again for the previously allocated quantum circuit, and the occupied best qubit partition is released. Then, the optimal qubit partition is assigned to the currently unassigned quantum circuit until all quantum circuits in the parallel quantum circuit set are assigned to the qubit partition.

6. The quantum bit partitioning method as described in claim 1, characterized in that, Before assessing the partitioning results and the complexity of the quantum circuit, the method further includes: The quantum computing tasks in the task list are combined and evaluated to obtain the set of parallel quantum circuits for the quantum computing tasks.

7. The quantum bit partitioning method as described in claim 6, characterized in that, The combined evaluation of quantum computing tasks in the task list to obtain the set of parallel quantum circuits for the quantum computing tasks includes: The quantum computing task at the top of the task list is used as the benchmark task. Other quantum computing tasks in the task list are evaluated in combination and then sorted from largest to smallest according to the evaluation results. The quantum circuit corresponding to the benchmark task is added to the parallel quantum circuit set. If the number of qubits in the parallel quantum circuit set is less than a preset threshold, the quantum circuits corresponding to other quantum computing tasks are sequentially selected from the sorted task list and added to the parallel quantum circuit set until the number of qubits in the parallel quantum circuit set is not less than the preset threshold.

8. A quantum circuit adjustment method, characterized in that, include: Each quantum circuit in the parallel quantum circuit set is executed independently, and the independent execution result of each quantum circuit is obtained; According to the execution timing scheme of the parallel quantum circuit set, all quantum circuits in the parallel quantum circuit set are executed in a merged manner to obtain the merged execution result of each quantum circuit; Statistically analyze the probability distribution of qubit states in the independent execution results and combined execution results of each quantum circuit; The difference between the probability distribution of the merged execution result and the probability distribution of the independent execution result is calculated to obtain the fidelity loss of the merged execution. If the fidelity loss is greater than a preset fidelity threshold, then each quantum circuit in the parallel quantum circuit set is executed independently. If the fidelity loss is not greater than the preset fidelity threshold, then all quantum circuits in the parallel quantum circuit set are merged and executed.

9. A quantum bit partitioning device, characterized in that, include: A qubit partitioning module is used to acquire the topological structure of physical qubits in a quantum chip. Based on the topological structure, a hierarchical partitioning method is adopted to divide each physical qubit in the quantum chip into a single qubit partition, and all single qubit partitions are classified into single-qubit layers. Starting from the single-qubit layer, according to the connectivity of qubits in the topological structure, the corresponding bit layers are constructed layer by layer in ascending order of the number of qubits until all physical qubits are divided into a single qubit partition, thus completing the hierarchical partitioning of physical qubits. The hierarchical partitioning method is a strategy that divides physical qubits in the quantum chip into qubit partitions layer by layer according to the connectivity of qubits in the topological structure of physical qubits, following a hierarchical progressive logic. The bit partition evaluation module is used to evaluate the quality of all qubit partitions in each layer and obtain the partition evaluation results of all qubit partitions in each layer. A quantum circuit allocation module is used to allocate the qubit partitions to the quantum circuits in the parallel quantum circuit set based on the partition evaluation results and the complexity of the quantum circuits.

10. A quantum circuit adjustment device, characterized in that, include: The independent execution module is used to execute each quantum circuit in the parallel quantum circuit set independently and obtain the independent execution result of each quantum circuit. The line merging execution module is used to merge and execute all quantum lines in the parallel quantum circuit set according to the execution timing scheme of the parallel quantum circuit set, and obtain the merged execution result of each quantum circuit. The line execution adjustment module is used to statistically analyze the probability distribution of qubit states in the independent execution results and the combined execution results of each quantum line. The difference between the probability distribution of the merged execution result and the probability distribution of the independent execution result is calculated to obtain the fidelity loss of the merged execution; if the fidelity loss is greater than a preset fidelity threshold, each quantum circuit in the parallel quantum circuit set is executed independently; if the fidelity loss is not greater than the preset fidelity threshold, all quantum circuits in the parallel quantum circuit set are merged and executed.

11. A terminal device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the qubit partitioning method as described in any one of claims 1-7, or the quantum circuit adjustment method as described in claim 8.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein, when the computer program is executed, it controls the device containing the computer-readable storage medium to perform the quantum bit partitioning method as described in any one of claims 1-7, or the quantum circuit adjustment method as described in claim 8.

13. A computer program product, characterized in that, The computer program product is stored in a storage medium and is executed by at least one processor to implement the quantum bit partitioning method as described in any one of claims 1-7, or the quantum circuit adjustment method as described in claim 8.

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