An lpddr5 read training method and system for eliminating fine delay and coarse delay errors

Abstract

The application aims to provide an LPDDR5 Read Training method and system for eliminating fine delay and coarse delay error, which comprises the following steps: scanning a unit interval of read training; obtaining a position of a scanned eye diagram boundary; and adjusting a calibration delay line according to the position of the eye diagram boundary. The application can avoid the influence of the error caused by the inequality between 1UI of the fine delay and 1UI of the coarse delay as much as possible without affecting the correctness of the Read Training.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to an LPDDR5 Read Training method and system for eliminating fine delay and coarse delay errors. BACKGROUND

[0002] In LPDDR5, the DQ[15:0] returned by the grain needs to be sampled by the returned RDQS clock, but because the frequency is very high and the period is very small, the delay of RDQS must be trained for each DQ, so as to ensure that RDQS can correctly sample all DQs. Coarse Delay and Fine Delay are generally designed to adjust the delay of RDQS (the clock after the delay is called RxClk). The Coarse Delay is realized by digital logic, so one unit is 1 UI (1 UI represents half of the RDQS period). The Fine Delay is realized by analog LCDL, and one unit is 1 / 64 UI. In addition, LPDDR5 is a double-edge sampling serial port, and due to some reasons, the rising edge clock (RDQS_C) and the falling edge clock (RDQS_T) must maintain the consistency of the Coarse Delay when sampling, so they share the Coarse Delay configuration. Taking the IO of a certain DQ as the description object, the Training process generally first performs Delay Training on RDQS_C, and at the same time, the common Coarse Delay of RDQS_C and RDQS_T is also trained, and then the Fine Delay of RDQS_T is trained.

[0003] Figure 2 The midpoint of the RxClk_c eye diagram obtained after the left dashed line Training is on the right, and the delay corresponding to this point can make RDQS_C correctly sample the corresponding DQ, but because the Fine Delay is too close to the 2UI position of the LCDL, it is easy to cause the RDQS_T to be backfilled to a position exceeding 2UI during the Training, resulting in Training failure, and it may also cause Retrain failure, so the Fine Delay is generally backfilled to a position close to 1UI. Figure 2The state in the code requires carrying over 1 UI from FineDelay to CoarseDelay. This allows for the adjustment of FineDelay from 1.9 UI to 0.9 UI. In Read Training, CoarseDelay is implemented using digital logic, with one unit being 1 UI. The precision of CoarseDelay is based on the clock output of the PHYPLL, and the clock jitter is very small, essentially considered to be error-free. FineDelay, on the other hand, is implemented using an analog LCDL, with one unit being 1 / 64 UI. Its precision is affected by PVT, the LCDL Clibration algorithm, the linearity of the LCDL, and the LCDL's structural design itself. For this reason, 1 UI of LCDL is not equal to 1 UI of CoarseDelay. Summary of the Invention

[0004] The purpose of this invention is to provide an LPDDR5 Read Training method and system that eliminates fine delay and coarse delay errors. This method can avoid the impact of the error caused by the unequal 1UI of Fine Delay and Coarse Delay without affecting the correctness of Read Training.

[0005] An LPDDR5 Read Training method for eliminating fine-grained and coarse-grained delay errors includes:

[0006] Scan and read the unit interval of training;

[0007] Obtain the position of the scanned eye map boundary;

[0008] Adjust the calibration delay line according to the position of the eye diagram boundary.

[0009] Preferably, the unit interval for scanning and reading training includes:

[0010] A single scan reads a unit interval from the training data.

[0011] Preferably, obtaining the location of the scanned eye diagram boundary includes:

[0012] Scan the left boundary of the eye diagram within the 0-1 unit interval;

[0013] If the left boundary of the eye diagram is not found in the 0-1 unit interval, adjust the parameters of the delay line and continue scanning;

[0014] If the left boundary of the eye diagram is found in the 0-1 unit interval, continue scanning to find the right boundary.

[0015] Preferably, the calibration delay line includes a coarse delay line and a fine delay line.

[0016] Preferably, adjusting the calibration delay line according to the position of the eye diagram boundary includes:

[0017] Determine the points in the eye diagram based on the position of the eye diagram boundary;

[0018] Determine whether to adjust the fine delay line or the coarse delay line based on the position of the point in the eye diagram.

[0019] Preferably, determining whether to adjust the fine delay line or the coarse delay line based on the position of the point in the eye diagram includes:

[0020] If the left boundary of the eye diagram is not detected in the 0-1 unit interval, the coarse delay line is carried over by 1, and the fine delay line is accumulated again starting from 0.

[0021] If the left boundary of the eye diagram is found in the 0-1 unit interval, the coarse delay line remains unchanged, and the fine delay line continues to accumulate to the 1-2 unit interval until the right boundary of the eye diagram is found.

[0022] Preferably, adjusting the calibration delay line according to the position of the eye diagram boundary further includes:

[0023] The range of the LCDL Delay set at the left boundary of the eye diagram is controlled according to the standard range of the eye diagram, which belongs to (0UI, 1UI);

[0024] The range of the LCDL Delay set at the right boundary of the eye diagram is controlled according to the standard range of the eye diagram, which belongs to (1UI, 2UI).

[0025] According to the standard range of the eye diagram, the set of midpoints of the left and right boundaries of the eye diagram belongs to (0.5UI, 1.5UI).

[0026] An LPDDR5 Read Training system for eliminating fine-grained and coarse-grained delay errors includes:

[0027] The scanning module is used to scan and read unit intervals of training data.

[0028] The judgment module is used to obtain the position of the scanned eye diagram boundary;

[0029] The calibration module is used to adjust the calibration delay line according to the position of the eye diagram boundary.

[0030] An electronic device includes a chip, a processor, and a memory, the memory storing computer program code including computer instructions, wherein, when the chip executes the computer instructions, the electronic device performs an LPDDR5 Read Training method to eliminate fine-grained and coarse-grained delay errors.

[0031] A computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor of an electronic device, cause the processor to perform an LPDDR5 Read Training method for eliminating fine-grained and coarse-grained delay errors.

[0032] The beneficial effects of this invention are as follows: 1. This invention requires the Read Training eye diagram to appear within the 2UI range of an LCDL, thereby avoiding the need for Fine Delay to perform borrow or carry operations on Coarse Delay when backfilling the final delay configuration; 2. This invention uses the Read Training algorithm of Fine Delay to determine whether to carry over to Coarse Delay by finding the left boundary. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of an LPDDR5 Read Training method algorithm for eliminating fine-grained and coarse-grained delay errors according to the present invention.

[0036] Figure 2 A diagram illustrating a prior art approach to performing a Delay Scan on RDQS_C.

[0037] Figure 3 Figure 2 illustrates a prior art scheme for performing a Delay Scan on RDQS_C.

[0038] Figure 4 This is an eye diagram error that may occur during Training RDQS_C in the prior art of this invention;

[0039] Figure 5 A diagram illustrating the delay backfill skew that may occur during Training RDQS_C in the prior art of this invention;

[0040] Figure 6Two figures illustrate the delay backfilling skew situation that may occur during Training RDQS_C in the prior art of this invention;

[0041] Figure 7 This is a diagram showing the effect of the algorithm used in this invention in dealing with the delay backfill skew situation that may occur when Training RDQS_C;

[0042] Figure 8 This is a diagram showing the effect of the algorithm used in this invention in dealing with the second case of delay backfilling skew that may occur when Training RDQS_C;

[0043] Figure 9 This is a schematic diagram of the hardware structure of an electronic device according to the present invention. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0045] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0046] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0047] Figure 2The dashed line on the right represents the point in the eye diagram of RxClk_c obtained after training. The delay corresponding to this point allows RDQS_C to correctly sample the corresponding DQ. However, because the Fine Delay is too close to the 2UI position of LCDL, it can easily cause RDQS_T to have to be backfilled to a position beyond 2UI, leading to training failure and potentially retraining failure. Therefore, the Fine Delay should generally be backfilled to a position closer to 1UI. Figure 2 The state in the code requires carrying over 1 UI from FineDelay to CoarseDelay. This allows for the adjustment of FineDelay from 1.9 UI to 0.9 UI. In Read Training, CoarseDelay is implemented using digital logic, with one unit being 1 UI. The precision of CoarseDelay is based on the clock output of the PHYPLL, and the clock jitter is very small, essentially considered to be error-free. FineDelay, on the other hand, is implemented using an analog LCDL, with one unit being 1 / 64 UI. Its precision is affected by PVT, the LCDL Clibration algorithm, the linearity of the LCDL, and the LCDL's structural design itself. For this reason, 1 UI of LCDL is not equal to 1 UI of CoarseDelay.

[0048] This invention requires the Read Training eye diagram to appear within a 2UI range of an LCDL, thereby avoiding the need for Fine Delay to perform borrow or carry operations on Coarse Delay for the final delay configuration backfill; this invention determines whether to carry Fine Delay to Coarse Delay Read Training algorithm by finding whether the left boundary is found.

[0049] Example 1

[0050] A method for eliminating fine-grained and coarse-grained delay errors in LPDDR5 Read Training, referenced Figure 1 ,include:

[0051] S100, scans and reads the unit interval of training;

[0052] In this embodiment of the invention, a unit interval is 1 UI. 1 UI (Unit Interval) represents the duration of one bit cycle in timing. Specifically, 1 UI refers to the duration of one bit of information, equal to the reciprocal of the data transmission cycle, i.e., 1 / data rate. For example, if the data rate is 1 Gbps, then 1 UI is approximately 1 nanosecond. In digital communication and signal integrity analysis, 1 UI is used to measure parameters such as jitter and eye diagram width. As the transmission rate increases, the duration of 1 UI decreases. For example, if the code rate doubles, the duration of 1 UI will be halved.

[0053] S200, obtain the position of the scanned eye diagram boundary;

[0054] An eye diagram visually reflects signal distortion, inter-symbol interference (ISI), and noise interference by superimposing signal waveforms across multiple symbol periods. A larger eye opening indicates stronger noise immunity and lower ISI, thus resulting in better system performance.

[0055] S300, adjusts the calibration delay line according to the position of the eye diagram boundary.

[0056] LCDL delay refers to the delay time of the Local Calibration Delay Line (LCD). In DDR memory, a delay line is a hardware module used to adjust the delay of signals to meet timing requirements. LCDL delay specifically refers to the delay time of the LCD, which is calibrated during initialization. It primarily adjusts the phase of the data signal (DQ) and data strobe signal (DQS) to ensure they are sampled or written to memory at the correct clock edge. The delay line is used to adjust the phase of the data signal (DQ) and data strobe signal (DQS) to ensure they are sampled or written to memory at the correct clock edge. Due to variations in voltage and temperature, the delay effect of the delay line can change; this phenomenon is called drift. LCDL uses a PVT compensation mechanism to detect and compensate for drift, ensuring that the delay value remains consistent under different conditions.

[0057] Preferably, in step S100, the unit interval for scanning and reading training includes:

[0058] A single scan reads a unit interval from the training data.

[0059] If the actual delay of LCDL is greater than the calculated delay due to the influence of PVT, then the right boundary of the Rxclk eye diagram will appear earlier. In high-speed communication interfaces, the eye diagram width is already very small; reducing the range of the eye diagram may make training more difficult and also leads to inaccuracies in backfilling delay. Figure 4 As shown. InFigure 2 In the algorithm shown, the final backfill uses the 1UI carry-over of Fine Delay (i.e., LCDL Delay) to Coarse Delay as the final Delay configuration backfill. This may result in the backfilled delay configuration not necessarily being in the exact center of the actual eye diagram, but rather having a deviation. If the eye diagram is too small, this carry adjustment may reveal that the backfilled delay configuration is incorrect. Regarding... Figure 2 and Figure 3 The possible consequences of the above-mentioned practices are as follows: Figure 5 and Figure 6 As shown.

[0060] Preferably, in step S200, obtaining the position of the scanned eye diagram boundary includes:

[0061] Scan the left boundary of the eye diagram within the 0-1 unit interval;

[0062] If the left boundary of the eye diagram is not found in the 0-1 unit interval, adjust the parameters of the delay line and continue scanning;

[0063] If the left boundary of the eye diagram is found in the 0-1 unit interval, continue scanning to find the right boundary.

[0064] Preferably, the calibration delay line includes a coarse delay line and a fine delay line.

[0065] In this embodiment of the invention, Fine Delay and Coarse Delay are respectively a fine delay line and a coarse delay line. Fine Delay allows for fine-tuning of the delay and is mainly used for precise adjustments. Its adjustment range is small, making it suitable for scenarios requiring precise control of the delay time. Coarse Delay performs coarse-tuning of the delay and is mainly used for rough adjustments. Its adjustment range is large, making it suitable for scenarios requiring rapid setting of the delay time. Fine Delay has a smaller adjustment range, suitable for precise adjustments; while Coarse Delay has a larger adjustment range, suitable for rapid adjustments. Fine Delay is used when precise control of the delay time is required; Coarse Delay is used when rapid setting of the delay time is required.

[0066] Preferably, S300, adjusting the calibration delay line according to the position of the eye diagram boundary includes:

[0067] S310, Determine the points in the eye diagram based on the position of the eye diagram boundary;

[0068] S320 determines whether to adjust the fine delay line or the coarse delay line based on the position of the point in the eye diagram.

[0069] If the left boundary of the eye diagram is not found during the scanning of LCDL's 0~1UI, then the Coarse Delay is carried over by 1, and the Fine Delay (LCDL Delay) is pushed back to 0. If the left boundary of the eye diagram is found during the scanning of 0~1UI, then the Coarse remains unchanged, and Fine continues to push the next 1UI~2UI positions until the right boundary is found.

[0070] Preferably, refer to Figure 1 Determining whether to adjust the fine or coarse delay line based on the position of the point in the eye diagram includes:

[0071] If the left boundary of the eye diagram is not detected in the 0-1 unit interval, the coarse delay line is carried over by 1, and the fine delay line is accumulated again starting from 0.

[0072] If the left boundary of the eye diagram is found in the 0-1 unit interval, the coarse delay line remains unchanged, and the fine delay line continues to accumulate to the 1-2 unit interval until the right boundary of the eye diagram is found.

[0073] During the Read Training scan of the six UIs, the fine delay of LCDL's 2UI is not always fully scanned. Instead, if the left boundary of the eye diagram is not found during the scanning of LCDL's 0-1UI, the CoarseDelay is carried over by 1, and the Fine Delay (LCDL Delay) is reset to 0. If the left boundary of the eye diagram is found during the scanning of 0-1UI, the Coarse remains unchanged, and Fine continues to advance the positions of the next 1UI-2UI until the right boundary is found.

[0074] Preferably, adjusting the calibration delay line according to the position of the eye diagram boundary further includes:

[0075] The range of the LCDL Delay set at the left boundary of the eye diagram is controlled according to the standard range of the eye diagram, which belongs to (0UI, 1UI);

[0076] The range of the LCDL Delay set at the right boundary of the eye diagram is controlled according to the standard range of the eye diagram, which belongs to (1UI, 2UI).

[0077] According to the standard range of the eye diagram, the set of midpoints of the left and right boundaries of the eye diagram belongs to (0.5UI, 1.5UI).

[0078] Since the standard eye diagram has a range of 1 UI, according to the algorithm described in the patent, the range of the LCDL Delay set corresponding to the left boundary is (0 UI, 1 UI), and the range of the LCDL Delay set corresponding to the right boundary is (1 UI, 2 UI); therefore, the range of the set of midpoints of the left and right boundaries is (0.5 UI, 1.5 UI).

[0079] In this embodiment of the invention, the midpoint of the trained eye diagram is guaranteed to be between (0.5UI, 1.5UI), eliminating the need for carry or borrow processing for Fine Delay and Coarse Delay during final backfilling. This avoids the impact of errors caused by the unequal 1UI of Fine Delay and Coarse Delay.

[0080] In a preferred embodiment, if LCDL is x UIs greater than 2UI, the judgment in the algorithm remains the same: if the left boundary of the eye diagram is not scanned during the scanning of the 0-1 UIs of LCDL, then Fine Delay carries over and increments by 1 to Coarse Delay; if the left boundary is scanned, then no carry is made.

[0081] Example 2

[0082] An LPDDR5 Read Training system for eliminating fine-grained and coarse-grained delay errors includes:

[0083] The scanning module is used to scan and read unit intervals of training data.

[0084] The judgment module is used to obtain the position of the scanned eye diagram boundary;

[0085] The calibration module is used to adjust the calibration delay line according to the position of the eye diagram boundary.

[0086] Figure 7 and Figure 8 The algorithm used in this invention is described in the face of Figure 4 , Figure 5 and Figure 6 The algorithm's performance in the scenario shown in the diagram.

[0087] If still in Figure 4 and Figure 5 In the mid-eye diagram scenario, the delay of LCDL will be directly backfilled to 0.9UI, i.e., Coarse=3UI, Fine=0.9UI. This method's eye diagram range does not include the transition of LCDL from 2UI to 0UI, thus avoiding a hole in the middle of the RxClk Eye and preventing... Figure 3This method also avoids the carry-over handling of Coarse Delay by Fine Delay during backfilling, thus preventing... Figure 5 For details of the issues shown, please see [link / reference]. Figure 7 .

[0088] If still in Figure 5 In the middle eye diagram scenario, the LCDL delay will be directly backfilled to 1.1UI, i.e., Coarse = 1UI, Fine = 1.1UI. This method avoids the borrowing process of Fine Delay on Coarse Delay during backfilling, thus preventing... Figure 5 For details of the issues shown, please see [link / reference]. Figure 8 .

[0089] Example 3

[0090] An electronic device includes a chip, a processor, and a memory, the memory storing computer program code including computer instructions. When the chip executes the computer instructions, the electronic device performs an LPDDR5 Read Training method to eliminate fine-grained and coarse-grained delay errors.

[0091] refer to Figure 9 The electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, memory 22, input device 23, and output device 24 are coupled together via connectors, which may include various interfaces, transmission lines, or buses, etc., and are not limited in this embodiment of the invention. It should be understood that in the various embodiments of the invention, coupling refers to mutual connection through a specific method, including direct connection or indirect connection through other devices, such as through various interfaces, transmission lines, buses, etc.

[0092] The processor 21 can be one or more graphics processing units (GPUs). If the processor 21 is a GPU, the GPU can be a single-core GPU or a multi-core GPU. Optionally, the processor 21 can be a processor group composed of multiple GPUs, with the multiple processors coupled to each other via one or more buses. Optionally, the processor can also be other types of processors, etc., and this embodiment of the invention is not limited thereto.

[0093] The memory 22 can be used to store computer program instructions, as well as various types of computer program code, including program code for executing the present invention. Optionally, the memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), which is used for related instructions and data.

[0094] Input device 23 is used to input data and / or signals, and output device 24 is used to output data and / or signals. Output device 24 and input device 23 can be independent devices or an integrated device.

[0095] Example 4

[0096] A computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor of an electronic device, cause the processor to perform an LPDDR5 Read Training method for eliminating fine-grained and coarse-grained delay errors.

[0097] This invention requires the Read Training eye diagram to appear within a 2UI range of an LCDL, thereby avoiding the need for Fine Delay to perform borrow or carry operations on Coarse Delay for the final delay configuration backfill; this invention determines whether to carry Fine Delay to Coarse Delay Read Training algorithm by finding whether the left boundary is found.

[0098] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for eliminating fine-grained and coarse-grained delay errors in LPDDR5 Read Training, characterized in that, include: Scan and read the unit interval of training; Obtain the position of the scanned eye map boundary; Adjust the calibration delay line according to the position of the eye diagram boundary; The calibration delay line includes a coarse delay line and a fine delay line; adjusting the calibration delay line according to the position of the eye diagram boundary includes: determining the point in the eye diagram according to the position of the eye diagram boundary; and determining whether to adjust the fine delay line or the coarse delay line according to the position of the point in the eye diagram. The step of determining whether to adjust the fine delay line or the coarse delay line based on the position of the point in the eye diagram includes: if the left boundary of the eye diagram is not scanned in the 0-1 unit interval, the coarse delay line is carried over by 1, and the fine delay line is accumulated again starting from 0; if the left boundary of the eye diagram is scanned in the 0-1 unit interval, the coarse delay line remains unchanged, and the fine delay line continues to accumulate to the 1-2 unit interval until the right boundary of the eye diagram is found. The adjustment of the calibration delay line according to the position of the eye diagram boundary further includes: controlling the range of the LCDLDelay set of the left boundary of the eye diagram to be (0UI, 1UI) according to the standard range of the eye diagram; controlling the range of the LCDLDelay set of the right boundary of the eye diagram to be (1UI, 2UI) according to the standard range of the eye diagram; and controlling the range of the set of midpoints of the left and right boundaries of the eye diagram to be (0.5UI, 1.5UI) according to the standard range of the eye diagram.

2. The LPDDR5 Read Training method for eliminating fine and coarse delay errors according to claim 1, characterized in that, The unit interval for the scanning and reading training includes: one unit interval in a single scanning and reading training session.

3. The LPDDR5 Read Training method for eliminating fine and coarse delay errors according to claim 1, characterized in that, The process of obtaining the position of the scanned eye diagram boundary includes: scanning the left boundary of the eye diagram in the 0-1 unit interval; if the left boundary of the eye diagram is not scanned in the 0-1 unit interval, adjusting the parameters of the delay line and continuing to scan; if the left boundary of the eye diagram is scanned in the 0-1 unit interval, continuing to scan to find the right boundary.

4. An LPDDR5 Read Training system for eliminating fine-grained delay and coarse-grained delay errors, applied to the LPDDR5 Read Training method for eliminating fine-grained delay and coarse-grained delay errors as described in claim 1, characterized in that, include: The scanning module is used to scan and read unit intervals of training data. The judgment module is used to obtain the position of the scanned eye diagram boundary; The calibration module is used to adjust the calibration delay line according to the position of the eye diagram boundary.

5. An electronic device, characterized in that, include: A chip, a processor, and a memory, the memory being used to store computer program code, the computer program code including computer instructions, wherein, when the chip executes the computer instructions, the electronic device performs an LPDDR5ReadTraining method for eliminating fine-grained and coarse-grained delay errors as claimed in any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which includes program instructions that, when executed by a processor of an electronic device, cause the processor to perform an LPDDR5 ReadTraining method for eliminating fine-grained and coarse-grained delay errors as described in any one of claims 1 to 3.

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