An etching method and semiconductor processing apparatus

Abstract

The application provides an etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The etching method is designed to solve the problem that necking phenomenon is easily formed on the top of an etching material layer in a metal hard mask etching process. The etching method comprises the following steps: providing a semiconductor device, wherein the semiconductor device comprises an etching material layer, a metal hard mask layer, an oxidation layer, an anti-reflection layer and a patterned photoresist layer which are sequentially stacked; performing a first etching step to etch the anti-reflection layer with the photoresist layer as a mask and expose the oxidation layer; and performing a deposition step to form a first carbon-containing sacrificial layer on the top of the anti-reflection layer and a second carbon-containing sacrificial layer on the top of the oxidation layer, wherein the thickness of the first carbon-containing sacrificial layer is greater than the thickness of the second carbon-containing sacrificial layer. The application can improve the remaining amount of the anti-reflection layer thickness, so that the anti-reflection layer still has a remaining amount in the subsequent etching step, thereby preventing the round corner morphology of the anti-reflection layer from being transferred to the etching material layer to form the necking phenomenon.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to an etching method and semiconductor process equipment. Background Technology

[0002] As chip integration increases, the critical dimensions of semiconductor devices are becoming smaller and the patterns are becoming denser, leading to increasingly higher requirements for the accuracy of pattern transfer. To improve the accuracy of pattern transfer, related technologies employ a metal hard mask with high etching selectivity to transfer patterns to the etch material layer. Specifically, a metal hard mask, an oxide layer, an anti-reflective layer, and a photoresist layer are sequentially disposed on the etch material layer. First, the anti-reflective layer and the oxide layer are etched downwards using the photoresist layer as a mask to transfer the pattern to the metal hard mask; then, the metal hard mask is used as a mask again for further etching downwards.

[0003] As semiconductor manufacturing processes continue to advance and the precision of pattern transfer increases, thinner photoresist and anti-reflective layers are often required. However, advanced processes correspond to thicker and more complex etching material layers, often necessitating thicker metal hard masks. This results in almost no remaining photoresist and anti-reflective layers during the etching process of the metal hard mask. Furthermore, because the photoresist used to form the photoresist layer is relatively soft, its top becomes rounded after plasma bombardment. This morphology, further transferred through the anti-reflective layer, oxide layer, and metal hard mask, causes a "neckback" phenomenon at the top of the etched material layer. Summary of the Invention

[0004] The first objective of this invention is to provide an etching method to solve the technical problem that a "neckback" phenomenon is easily formed at the top of the etched material layer in the metal hard mask etching process.

[0005] The etching method provided by this invention includes:

[0006] A semiconductor device is provided, the semiconductor device comprising an etch material layer, a metal hard mask layer, an oxide layer, an anti-reflection layer and a patterned photoresist layer stacked sequentially;

[0007] In the first etching step, the antireflective layer is etched using the photoresist layer as a mask, exposing the oxide layer; and

[0008] In the deposition step, a first carbon-containing sacrificial layer is formed on top of the anti-reflective layer and a second carbon-containing sacrificial layer is formed on top of the oxide layer, wherein the thickness of the first carbon-containing sacrificial layer is greater than the thickness of the second carbon-containing sacrificial layer.

[0009] Furthermore, prior to the first etching step, a photoresist layer modification step is included to modify the photoresist layer to reduce the linewidth roughness of the photoresist layer.

[0010] Furthermore, the photoresist layer modification step includes: a photoresist layer residual adhesive removal step, which removes the protrusions on the sidewall of the photoresist layer;

[0011] The upper radio frequency power is 100-400W and the lower radio frequency power is 0; the process gas is a CF gas, and the flow rate of the CF gas is between 100-140 sccm.

[0012] Furthermore, the photoresist layer modification step further includes: a photoresist layer curing step, which cures the photoresist layer;

[0013] The upper radio frequency power is 700-1200W and the lower radio frequency power is 0; the process gas is HBr gas, and the flow rate of the HBr gas is between 130-170 sccm.

[0014] Furthermore, in the first etching step, the upper radio frequency power is 500-1500W, and the lower radio frequency power is 30-100W.

[0015] Further, after the deposition step, a second etching step is included, in which the second carbon-containing sacrificial layer and the oxide layer are etched using the anti-reflection layer as a mask; wherein the process gas is a mixture of CF4 and CHF3, and the flow rate ratio of CF4 gas to CHF3 gas is (0.5~5):1.

[0016] Furthermore, after the second etching step, a main etching step is included, which etches the metal hard mask layer; wherein the process pressure is between 5 and 20 mtorr.

[0017] Furthermore, after the main etching step, the process includes an over-etching step to partially etch the etching material layer; wherein the dilution gas includes N2 or He.

[0018] Furthermore, after the etching step, the process includes: smoothing the surface of the oxide layer.

[0019] The beneficial effects of the etching method of this invention are:

[0020] In this etching method, a deposition step is added after the etching step of the anti-reflective layer. Since the top of the anti-reflective layer is unobstructed, while the top of the oxide layer is obstructed by the anti-reflective layer, the carbon-containing sacrificial layer can more easily contact the top of the anti-reflective layer during deposition. This results in the formation of a thicker first carbon-containing sacrificial layer on top of the anti-reflective layer, and a thinner second carbon-containing sacrificial layer on top of the oxide layer. Utilizing the thickness difference of the carbon-containing sacrificial layers formed in these two locations increases the remaining thickness of the anti-reflective layer. This allows the first carbon-containing sacrificial layer to offset the etching amount in subsequent etching steps, reducing the consumption of the anti-reflective layer. This ensures that some anti-reflective layer remains in the next etching stage, preventing the rounded corner morphology of the anti-reflective layer from being transferred to the oxide layer and further to the etching material layer, thus preventing a "neckback" phenomenon at the top of the etching material layer.

[0021] The second objective of this invention is to provide a semiconductor process apparatus to solve the technical problem that a "neckback" phenomenon is easily formed at the top of the etched material layer in the metal hard mask etching process.

[0022] The semiconductor process equipment provided by the present invention includes a process chamber, an air intake assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller includes at least one processor and at least one memory. The memory stores a computer program, which, when executed by the processor, implements the above-described etching method.

[0023] The beneficial effects of the semiconductor process equipment of this invention are:

[0024] This semiconductor process equipment can implement the above etching method, and accordingly, it has all the advantages of the above etching method, which will not be elaborated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0026] Figure 1 A cross-sectional view of the structure of a semiconductor device manufactured according to an etching method provided by the relevant technology at each step;

[0027] Figure 2 A flowchart of the etching method provided in an embodiment of the present invention;

[0028] Figure 3A cross-sectional view of the structure of a semiconductor device manufactured by the etching method provided in an embodiment of the present invention at each step;

[0029] Figure 4 A flowchart of another etching method provided in an embodiment of the present invention;

[0030] Figure 5 The etching method provided in this embodiment of the invention shows the relationship between the upper radio frequency power and the remaining thickness of the anti-reflection layer in the first etching step;

[0031] Figure 6 The etching method provided in this embodiment of the invention shows the relationship between the lower radio frequency power and the remaining thickness of the anti-reflection layer in the first etching step;

[0032] Figure 7 The graph showing the relationship between the CF4 / CHF3 ratio and the remaining thickness of the anti-reflection layer in the second etching step of the etching method provided in this embodiment of the invention;

[0033] Figure 8 This is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] 101' - Photoresist layer; 102' - Anti-reflective layer; 103' - Oxide layer; 104' - Metal hard mask layer; 105' - Etching material layer;

[0036] 101 - Photoresist layer; 102 - Anti-reflective layer; 103 - Oxide layer; 104 - Metal hard mask layer; 105 - Etching material layer;

[0037] 501 - First carbon-containing sacrificial layer; 502 - Second carbon-containing sacrificial layer;

[0038] 100 - Plasma; 200 - Semiconductor process equipment; 20 - Process chamber; 20A - Inlet assembly; 20B - Upper electrode assembly; 20C - Lower electrode assembly; 20D - Evacuation assembly;

[0039] 21-RF coil; 22-Wafer carrier; 23-Upper RF power supply; 24-Lower RF power supply; 25-Upper matching unit; 26-Lower matching unit. Detailed Implementation

[0040] To improve the accuracy of pattern transfer, related technologies use a metal hard mask with high etching selectivity to transfer patterns to the etched material layer. Figure 1 The following is a cross-sectional view of the structure of a semiconductor device manufactured according to the etching method provided by the relevant technology, showing the specific steps:

[0041] The morphology before etching is shown in (a). After photolithography processes such as development and fixing, the photoresist layer 101' forms a line pattern with a horizontal top and vertical sidewalls.

[0042] Using photoresist layer 101' as a mask, the pattern is transferred to antireflective layer 102'. Since the photoresist used to form photoresist layer 101' is relatively soft, its top will become rounded after plasma bombardment. Furthermore, due to the actual linewidth control requirements, there will still be a certain proportion of over-etching time when it comes into contact with oxide layer 103' to meet the linewidth requirements. At this time, photoresist layer 101' will be completely consumed, and the top rounded corner shape will be transferred to antireflective layer 102', as shown in (b).

[0043] Using the anti-reflective layer 102' as a mask, the oxide layer 103' is etched downwards. Since this step does not have a high etching selectivity for the anti-reflective layer 102', the anti-reflective layer 102' will also suffer some loss. The morphology of the etched semiconductor device is shown in (c).

[0044] Using the anti-reflective layer 102' as a mask, the metal hard mask layer 104' is etched downwards. Because the anti-reflective layer 102' has rounded corners at the top, inherited from the photoresist layer 101', the edges of the anti-reflective layer 102' are completely etched first during the etching process of the metal hard mask layer 104', while the middle portion remains. As the etching process continues, the oxide layer 103' will form rounded corners at the edges and a relatively flat middle portion, creating a "shoulder" shape. Influenced by this shape, a tilted morphology will appear on the sidewalls of the metal hard mask layer 104', as shown in (d).

[0045] Over-etching is performed to ensure that the metal hard mask layer 104' is fully opened. At this time, the etching material layer 105' is consumed to some extent, as shown in (e).

[0046] The etching material layer 105' is etched. In this step, the tilted topography of the metal hard mask layer 104' is transferred to the etching material layer 105', thereby forming a "neckback" phenomenon at the top of the etching material layer 105', which seriously affects the sidewall topography of the etching material layer 105'.

[0047] Therefore, the purpose of this invention is to provide an etching method and semiconductor process equipment to solve the technical problem that a "neck-down" phenomenon is easily formed at the top of the etched material layer during the etching process of metal hard masks.

[0048] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0049] Figure 2 This is a flowchart of the etching method provided in this embodiment. Figure 2 As shown, this embodiment provides an etching method, including:

[0050] Step S100: Provide a semiconductor device. For example... Figure 3 As shown in (a), the semiconductor device includes an etch material layer 105, a metal hard mask layer 104, an oxide layer 103, an anti-reflection layer 102, and a patterned photoresist layer 101, which are stacked sequentially.

[0051] In the aforementioned semiconductor device, the metal hard mask layer 104 is located on top of the etching material layer 105 and is used to prevent the pattern on the photoresist layer 101 from being damaged due to pattern miniaturization. It can be formed by chemical vapor deposition or spin coating and can be made of inorganic thin film materials such as TiN (titanium nitride), SiN (silicon nitride), and SiO2 (silicon dioxide). The oxide layer 103 is located on top of the metal hard mask layer 104 and is used to prevent short circuits and the flow of current between circuits to improve the stability and performance of the device. It can be made of SiO2. The anti-reflection layer 102 is located on top of the oxide layer 103 and is used to reduce light reflection during photolithography and suppress interference between incident and reflected light to generate standing waves, thereby improving light transmission efficiency. The photoresist layer 101 is located on top of the anti-reflection layer 102 and is formed by developing and fixing a relatively soft photoresist to create a line pattern. Its top is horizontal and its sidewalls are vertical.

[0052] Step S300: First etching step, as follows Figure 3 As shown in (b), the anti-reflection layer 102 is etched using the photoresist layer 101 as a mask, exposing the oxide layer 103.

[0053] In this step, the upper surface of the oxide layer 103 is used as the etching stop surface. Typically, when the longitudinal etching contacts the oxide layer 103, the longitudinal etching stops, and only the lateral etching is performed to increase the window spacing dimension (B1). However, in order to meet the linewidth and over-etching requirements, etching continues for a certain period of time after the longitudinal etching stops. This step is crucial for controlling B1 and the remaining thickness of the anti-reflective layer 102. Increasing the etching time or increasing the amount of etching gas introduced can effectively increase B1, but it will reduce the remaining thickness of the anti-reflective layer 102, resulting in insufficient thickness of the anti-reflective layer 102.

[0054] Specifically, in the first etching step, the up-frequency power can be 500 to 1500W.

[0055] By increasing the up-frequency power, the lateral etching depth can be enhanced, sidewall consumption can be increased, and the window spacing dimension B1 of the anti-reflection layer 102 can be increased, such as... Figure 5As shown, with the increase of the upper radio frequency power (the horizontal axis in the figure is from left to right), the window spacing size B1 of the anti-reflection layer 102 increases linearly.

[0056] As the lateral etching depth is increased, the longitudinal consumption of the anti-reflective layer 102 will decrease accordingly, thus increasing the remaining thickness of the anti-reflective layer 102. However, when the up-frequency power increases to a certain level, due to the rounded corners of the anti-reflective layer 102, the remaining thickness of the anti-reflective layer 102 becomes insensitive to changes in the up-frequency power, which is reflected in... Figure 5 The curve showing the change in the remaining thickness of the intermediate anti-reflective layer 102 is as follows: it first increases linearly, and then fluctuates around a certain value.

[0057] Specifically, as the lateral etching increases, the lateral dimension B2 of the anti-reflective layer 102 decreases. Due to the rounded corners of the anti-reflective layer 102, the lateral etching at the top of the anti-reflective layer 102 consumes the thickness of the anti-reflective layer 102. As can be seen from the above analysis, the increased lateral etching leads to a decrease in the longitudinal etching, which in turn reduces the longitudinal consumption of the anti-reflective layer 102. Thus, the increase in the thickness of the anti-reflective layer 102 due to the decrease in longitudinal etching and the decrease in the thickness of the anti-reflective layer 102 due to the increase in lateral etching can cancel each other out, resulting in a phenomenon where the remaining thickness of the anti-reflective layer 102 is insensitive after the up-frequency power increases to a certain level.

[0058] Alternatively, in the first etching step, the lower radio frequency power can be set to 30-100W.

[0059] By reducing the lower radio frequency power, the bombardment of the antireflective layer 102 by the plasma can be weakened, thereby reducing the consumption of the photoresist layer 101 and the antireflective layer 102. Simultaneously, the etching environment of the process chamber is cleaner, reducing the amount of polymer deposited on the sidewalls and bottom of both the photoresist layer 101 and the antireflective layer 102, thus reducing the protection of the sidewalls and increasing the window spacing dimension B1. Specifically, as follows... Figure 6 As shown, with the decrease of the upper radio frequency power (the horizontal axis in the figure is from right to left), the remaining thickness of the anti-reflection layer 102 and the window spacing dimension B1 both increase.

[0060] Step S500: Deposition step, such as Figure 3 As shown in (c), a first carbon-containing sacrificial layer 501 is formed on top of the anti-reflective layer 102 and a second carbon-containing sacrificial layer 502 is formed on top of the oxide layer 103, wherein the thickness of the first carbon-containing sacrificial layer 501 is greater than the thickness of the second carbon-containing sacrificial layer 502.

[0061] By adding a deposition step after the etching step of the antireflective layer 102, since the top of the antireflective layer 102 is not obstructed around it, while the top of the oxide layer 103 is obstructed around it by the antireflective layer 102, the carbon-containing sacrificial layer can more easily contact the top of the antireflective layer 102 during the deposition process, so that a thicker first carbon-containing sacrificial layer 501 is formed on the top of the antireflective layer 102, and a second carbon-containing sacrificial layer 502 with a thickness less than the first carbon-containing sacrificial layer 501 is formed on the top of the oxide layer 103. By utilizing the thickness difference of the carbon-containing sacrificial layer formed in the two locations mentioned above, the remaining thickness of the anti-reflective layer 102 can be increased. This allows the etching amount to be offset by the first carbon-containing sacrificial layer 501 in subsequent etching steps, thereby reducing the consumption of the anti-reflective layer 102. This ensures that some of the anti-reflective layer 102 remains in the next etching step, preventing the rounded corner morphology of the anti-reflective layer 102 from being transferred to the oxide layer 103 and further to the etching material layer 105, thus preventing a "neck" phenomenon from forming at the top of the etching material layer 105.

[0062] It should be noted that, in this embodiment, the thickness direction can be referenced. Figure 3 As indicated by the corresponding arrows in (a), the thickness of the device structure represents the dimension in the thickness direction.

[0063] In this embodiment, the thickness of the first carbon-containing sacrificial layer 501 is 3 to 5 times the thickness of the second carbon-containing sacrificial layer 502.

[0064] By limiting the thickness of the first carbon-containing sacrificial layer 501 and the second carbon-containing sacrificial layer 502 to the above-mentioned range, the first carbon-containing sacrificial layer 501 has sufficient thickness to reduce the weakening effect of subsequent etching processes.

[0065] Figure 4 A flowchart of another etching method provided in this embodiment. For example... Figure 4 As shown, before the first etching step, there is also a step S200: photoresist layer 101 modification step, which modifies the photoresist layer 101 to reduce the linewidth roughness of the photoresist layer 101.

[0066] After photolithography, the sidewall boundaries of the photoresist layer 101 are not completely smooth; they are typically uneven or rough. During etching, the pattern of the photoresist layer 101 is transferred downwards layer by layer, and this roughness gradually amplifies, making the sidewall boundaries even more uneven. In this step S200, by modifying the photoresist layer 101, the linewidth roughness of the photoresist layer 101 can be reduced, making the sidewalls of the photoresist layer 101 smoother, thereby reducing the adverse effects on pattern transfer accuracy during etching.

[0067] The above-mentioned photoresist layer 101 modification step may include: a photoresist layer 101 residual adhesive removal step, removing the protrusions on the sidewall of the photoresist layer 101; wherein, the upper RF power is 100-400W and the lower RF power is 0; the process gas is a CF gas, and the flow rate of the CF gas is between 100-140sccm.

[0068] In this step, using only the upper radio frequency and not the lower radio frequency can prevent the plasma from bombarding the photoresist layer 101 and deforming it, thereby reducing the impact on the sidewalls of the photoresist layer 101. At the same time, using CF-type gas can etch the protrusions on the sidewalls of the photoresist layer 101, passivating or smoothing the relatively sharp protrusions to achieve a smoothing effect, thereby reducing the linewidth roughness of the photoresist layer 101.

[0069] Furthermore, by limiting the upper radio frequency power within the aforementioned range, it is possible to avoid insufficient dissociation of the etching gas due to excessively low upper radio frequency power, which would prevent the insufficient etching of the protrusions on the sidewalls of the photoresist layer 101. On the other hand, it is also possible to avoid excessive etching of the photoresist layer 101 due to excessively high upper radio frequency power, which would increase the dissociation and thus increase the sidewall spacing B3 (see reference). Figure 3 (a) and reducing the thickness of photoresist layer 101.

[0070] Specifically, in the photoresist layer 101 residual adhesive removal step, the upper radio frequency power can be 300W.

[0071] The above-mentioned photoresist layer 101 modification step may further include: a photoresist layer 101 curing step, curing the photoresist layer 101; wherein, the upper RF power is 700-1200W and the lower RF power is 0; the process gas is HBr (hydrogen bromide) gas, and the flow rate of HBr gas is between 130-170 sccm.

[0072] In this step, HBr gas is used to generate vacuum ultraviolet (VUV) light within the process chamber, inducing polymer chain rearrangement. This VUV light then reacts chemically with the photoresist layer 101, modifying it, smoothing its edge morphology, generating a dense and hard cross-linked layer, and curing the surface. This improves the etching resistance of the photoresist layer 101, making it easier to maintain its original morphology during etching and reducing deformation. Using only the upper radio frequency (RF) and not the lower RF prevents excessive loss to the photoresist layer 101. Furthermore, by maintaining the upper RF power within this higher range, HBr can dissociate more, ensuring sufficient contact with the photoresist layer 101 and enhancing the curing effect.

[0073] By limiting the flow rate of HBr gas within the above range, on the one hand, it is possible to avoid weakening the curing effect due to insufficient HBr gas flow rate, and on the other hand, it is possible to avoid waste due to excessive HBr gas flow rate.

[0074] In this embodiment, the CF-type gas used in the photoresist layer 101 residual adhesive removal step can be CF4 (carbon tetrafluoride), and its flow rate can be increased from the original 80 sccm to 120 sccm; the HBr gas used in the photoresist layer 101 curing step can be increased from the original 100 sccm to 150 sccm.

[0075] Increasing the flow rate of CF gas in the photoresist layer 101 residual adhesive removal step and increasing the flow rate of HBr gas in the photoresist layer 101 curing step also helps stabilize the ignition and prevent extinguishing.

[0076] Please continue to refer to Figure 4 In this embodiment, after the deposition step, step S600 may be included: a second etching step, in which the second carbon-containing sacrificial layer 502 and oxide layer 103 are etched using the anti-reflection layer 102 as a mask; wherein the process gas is a mixture of CF4 and CHF3 (trifluoromethane), and the ratio of the flow rate of CF4 gas to the flow rate of CHF3 gas is (0.5~5):1.

[0077] In this step, the oxide layer 103 to be etched is typically made of materials such as OX (oxide), SiN (silicon nitride), and SiON (silicon oxynitride). Generally, the oxide layer 103 is thin and the etching time is short. However, in this embodiment, because a second carbon-containing sacrificial layer 502 is formed on top of the oxide layer 103 in step S500, a longer time is required to first open the second carbon-containing sacrificial layer 502 before etching the oxide layer 103 below. The etched device structure is as follows: Figure 3 As shown in (d) in the figure.

[0078] By increasing the proportion of CHF3 gas within a certain range, the increased C / F ratio introduces more carbon into the process chamber, resulting in more carbon-containing byproducts adhering to the surface of the anti-reflective layer 102. This protects the anti-reflective layer 102 and reduces its consumption during subsequent etching processes. Figure 7 As shown, when the proportion of CHF3 gas increases (the horizontal axis in the figure is from right to left), the remaining thickness of the anti-reflective layer 102 increases, while having little impact on the sidewall angle of the oxide layer 103.

[0079] Specifically, the total flow rates of CF4 gas and CHF3 gas remain constant. For example, in the initial stage, the flow rate of CF4 gas is 100 sccm and the flow rate of CHF3 gas is 20 sccm. When the flow rate of CHF3 gas increases to 80 sccm, the flow rate of CF4 gas decreases to 40 sccm.

[0080] More specifically, in the second etching step, the process pressure can be controlled at 5-20 mtorr, the upper RF power at 300-600W to generate plasma, and the lower RF power at 20-80W; the temperature of the electrostatic chuck is 35°C, and the etching time is 20-40s.

[0081] Please continue to refer to Figure 4 After the second etching step, step S700 can be included: main etching step, etching the metal hard mask layer 104, wherein the process pressure is 5 to 20 mtorr.

[0082] In this embodiment, the material of the metal hard mask layer 104 is specifically TiN.

[0083] By reducing the process pressure during the etching of the metal hard mask layer 104, the impact of plasma can be reduced, thereby increasing its mean free path. This intensifies plasma bombardment and enhances etching anisotropy, resulting in straighter sidewalls during the etching process of the metal hard mask layer 104. Consequently, it is easier to maintain the bottom window spacing when the etched morphology of the metal hard mask layer 104 is transmitted downwards. Therefore, compared to a tilted morphology, a vertical morphology of the metal hard mask layer 104 is more likely to increase its bottom window spacing.

[0084] Specifically, in the main etching step, 50–150 sccm of Cl2 (chlorine) is introduced as the etching gas, and 10–50 sccm of CH4 is introduced to form carbon-containing byproducts on the surface of the antireflective layer 102, thus providing protection for the antireflective layer 102 in this step. 50–200 sccm of N2 (nitrogen) or Ar (argon) is introduced as the carrier gas and dilution gas. Simultaneously, the process pressure is controlled at 5–20 mtorr, the upper RF power at 500–1000 W to generate plasma, and the lower RF power at 10–50 W. Furthermore, the electrostatic chuck temperature is 35°C, the etching time is 10–30 s, and etching is stopped when the etch material layer 105 is exposed.

[0085] Please continue to refer to Figure 4 After the main etching step, step S800 may be included: In the next etching step, partial etching of the etching material layer 105 is performed, wherein the dilution gas includes N2 or He, and the etched device structure is as follows: Figure 3 As shown in (e) in the diagram.

[0086] This over-etching step enables partial etching of the etch material layer 105, ensuring the complete opening of the metal hard mask layer 104. By selecting N2 or He as the dilution gas in the over-etching step, the bombardment effect of the dilution gas can be reduced. Since the over-etching step lasts for a short time, it has almost no impact on the window spacing, only slightly reducing the thickness of the anti-reflection layer 102. This ensures that after the over-etching step, the anti-reflection layer 102 remains, protecting the sidewall morphology of the oxide layer 103 and the metal hard mask layer 104 from lateral sputtering. This prevents the metal hard mask layer 104 from developing a tilted morphology and the etch material layer 105 from forming a "neck" phenomenon during subsequent etching of the etch material layer 105.

[0087] Specifically, in the over-etching step, 10–50 sccm of Cl2 is introduced as the etching gas, and 50–150 sccm of N2 or Ar is introduced as the carrier gas and dilution gas. Simultaneously, the process pressure is controlled at 5–15 mtorr, the upper RF power at 500–1000 W to generate plasma, and the lower RF power at 10–40 W. Furthermore, the electrostatic chuck temperature is 35°C, and the etching time is 5–15 s.

[0088] Please continue to refer to Figure 4 In this embodiment, after the etching step, step S900 may be included: smoothing the upper surface of the oxide layer 103.

[0089] By smoothing the upper surface of the oxide layer 103, the residues adhering to the upper surface of the oxide layer 103 can be removed, thereby ensuring the cleanliness of the upper surface of the oxide layer 103 and avoiding adverse effects of the residues on subsequent processes.

[0090] In this embodiment, after step S800, an anti-reflective layer 102 remains on the upper surface of the oxide layer 103, such as... Figure 3 As shown in (e), this portion of the anti-reflective layer 102 can be removed by a dry etching process. Specifically, in step S900, 100–200 sccm of O2 (oxygen) is introduced as the etching gas, and 10–40 sccm of N2 is introduced as the protective gas. Simultaneously, the process pressure is controlled at 5–15 mtorr, the upper RF power at 800–1300 W to generate plasma, and the lower RF power at 0 to prevent plasma bombardment of the bottom of the window. Furthermore, the electrostatic chuck temperature is 45°C, the etching time is 40–60 s, and etching is stopped when the oxide layer 103 is over-etched by 50% to ensure that any residue on the upper surface of the oxide layer 103 is completely removed. The device structure after etching is shown below. Figure 3 As shown in (f), at this time, the upper surface of the oxide layer 103 is flat, and the oxide layer 103 has good perpendicularity to the sidewall of the metal hard mask layer 104.

[0091] Figure 8 This is a schematic diagram of the structure of a semiconductor process equipment 200 provided in an embodiment of the present invention. Figure 8 As shown, this embodiment also provides a semiconductor process apparatus 200, including a process chamber 20, an air intake assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C, and a controller. The controller includes at least one processor and at least one memory, in which a computer program is stored. When the computer program is executed by the processor, it implements the above-described etching method.

[0092] The semiconductor process equipment 200 is capable of performing the above-mentioned etching method. Accordingly, the semiconductor process equipment 200 has all the advantages of the above-mentioned etching method, which will not be elaborated here.

[0093] For example, the controller can be a host computer or a slave computer. The controller can open the valve of the inlet assembly 20A to introduce the corresponding process gas into the process chamber 20; the controller can also control the flow rate of the process gas by controlling the opening degree of the valve of the inlet assembly 20A. The controller can also control the evacuation assembly 20D to evacuate the process chamber 20, for example, by controlling the valve opening degree of the evacuation assembly 20D or the speed of the evacuation pump, to control the pressure inside the process chamber 20 and remove reaction byproducts.

[0094] The upper electrode assembly 20B may include an RF coil 21, an upper RF power supply 23, and an upper matching unit 25. The controller is also used to control the upper RF power supply 23 to provide upper RF power to the RF coil 21 through the upper matching unit 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma 100.

[0095] The lower electrode assembly 20C may include a wafer carrier 22, a lower RF power supply 24, and a lower matching unit 26. The controller is also configured to control the lower RF power supply 24 to provide lower RF power to the wafer carrier 22 through the lower matching unit 26 to provide RF bias. The wafer carrier 22 may be an electrostatic chuck, a mechanical chuck, or a vacuum suction chuck.

[0096] The semiconductor process equipment 200 in this application embodiment can be an inductively coupled plasma device or a capacitively coupled plasma device. This application embodiment does not limit the type of semiconductor process equipment 200.

[0097] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

[0098] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0099] In the above embodiments, descriptions of directions such as "up", "down", "left", "right", and "side" are all based on the accompanying drawings.

[0100] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An etching method, characterized in that, include: A semiconductor device is provided, the semiconductor device comprising an etch material layer (105), a metal hard mask layer (104), an oxide layer (103), an anti-reflection layer (102), and a patterned photoresist layer (101) stacked sequentially. The photoresist layer (101) modification step modifies the photoresist layer (101) to reduce the linewidth roughness of the photoresist layer (101); the photoresist layer (101) modification step includes: a photoresist layer (101) residual adhesive removal step, which removes the protrusions on the sidewall of the photoresist layer (101); wherein, the upper RF power is 100-400W and the lower RF power is 0; the process gas is a CF gas, and the flow rate of the CF gas is between 100-140sccm; In the first etching step, the antireflective layer (102) is etched using the photoresist layer (101) as a mask, exposing the oxide layer (103); in the first etching step, the upper radio frequency power is 500-1500W, and the lower radio frequency power is 30-100W; and In the deposition step, a first carbon-containing sacrificial layer (501) is formed on top of the anti-reflective layer (102), and a second carbon-containing sacrificial layer (502) is formed on top of the oxide layer (103), wherein the thickness of the first carbon-containing sacrificial layer (501) is greater than the thickness of the second carbon-containing sacrificial layer (502).

2. The etching method according to claim 1, characterized in that, The photoresist layer (101) modification step further includes: a photoresist layer (101) curing step, which cures the photoresist layer (101). The upper radio frequency power is 700-1200W and the lower radio frequency power is 0; the process gas is HBr gas, and the flow rate of the HBr gas is between 130-170 sccm.

3. The etching method according to claim 1, characterized in that, Following the deposition step, a second etching step is included, in which the second carbon-containing sacrificial layer (502) and the oxide layer (103) are etched using the antireflective layer (102) as a mask; wherein the process gas is a mixture of CF4 and CHF3, and the ratio of the flow rate of CF4 gas to the flow rate of CHF3 gas is (0.5~5):

1.

4. The etching method according to claim 3, characterized in that, Following the second etching step, the process includes a main etching step, which etches the metal hard mask layer (104); wherein the process pressure is between 5 and 20 mtorr.

5. The etching method according to claim 4, characterized in that, Following the main etching step, the process includes an over-etching step to partially etch the etching material layer (105); wherein the dilution gas includes N2 or He.

6. The etching method according to claim 5, characterized in that, After the etching step, the surface of the oxide layer (103) is planarized.

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