Deep silicon etching method and semiconductor process apparatus
By employing a step-by-step deep silicon etching method with different etching steps using oxygen-containing gas and varying lower electrode power, the problems of depth micro-load effect and mask layer loss were solved. This approach achieved consistency in isolation trench depth and optimization of mask layer height, thereby improving the electrical performance and yield of DRAM products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INTEGRATED CIRCUIT EQUIPMENT INNOVATION CENTER CO LTD
- Filing Date
- 2025-06-17
- Publication Date
- 2026-05-22
AI Technical Summary
In the existing technology, the deep silicon etching method has a depth micro-load effect when forming isolation trenches, which leads to inconsistent isolation trench depths, affecting the electrical properties and yield of the product. At the same time, it increases the wear of the mask layer during etching, resulting in insufficient effective height of the mask layer, which easily leads to defects such as AA tipping or wire breakage.
A two-step deep silicon etching method is adopted. The first and second cycles use different lower electrode power and protective gas. The first cycle forms a protective layer in the upper trench section, and the second cycle uses oxygen-containing gas to enhance oxidation deposition in the lower trench section, thereby balancing the etching rate and reducing mask layer consumption.
It effectively reduces the micro-load effect of the isolation groove depth, improves the consistency of the isolation groove depth, ensures the effective height of the mask layer, reduces AA tipping and wire breakage defects, and improves the electrical properties and yield of the product.
Smart Images
Figure CN120749016B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a deep silicon etching method and semiconductor process equipment. Background Technology
[0002] With the rapid development of technology, Dynamic Random Access Memory (DRAM), as an important container for storing and exchanging data, faces increasingly higher performance requirements. As a key structure within the DRAM memory array, the active array (AA) requires isolation trenches with a depth of at least 200nm to ensure stable electrical performance and yield. Within the active array, differences in pattern density exist between different regions of the isolation trenches. The deep silicon etching process generates a depth micro-load effect, leading to inconsistent trench depths and affecting the morphological accuracy of the isolation trenches and AA, ultimately impacting the product's electrical performance and yield.
[0003] In related technologies, the duty cycle of the lower electrode power in the etching step is generally increased to reduce the depth micro-load effect. However, this operation will also increase the etching loss of the mask layer in the etching step, resulting in insufficient effective height at the end of the mask layer, which in turn causes the AA to suffer from head clipping, and in severe cases, even wire breakage defects, and still cannot guarantee the electrical properties and yield of the product.
[0004] Therefore, how to simultaneously reduce the depth micro-load effect and ensure the effective height of the mask layer in order to improve the electrical properties and yield of the product is an urgent problem to be solved. Summary of the Invention
[0005] The purpose of this invention is to provide a deep silicon etching method and semiconductor process equipment to solve the technical problem in related technologies that cannot simultaneously reduce the micro-load effect of the isolation trench depth and ensure the effective height of the mask layer, thus affecting the electrical properties and yield of the product.
[0006] To address the aforementioned problems, this invention provides a deep silicon etching method, comprising a first cycle step and a second cycle step. Both the first cycle step and the second cycle step include an etching step for etching trenches on a silicon substrate, a removal step for removing byproducts, and a deposition step for forming a protective layer on the sidewalls of the trenches. The protective gas used in the deposition step of the second cycle step includes an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than the lower electrode power of the deposition step of the first cycle step.
[0007] Optionally, the lower electrode power of the deposition step in the first cycle step is 0, and the lower electrode power of the deposition step in the second cycle step is 10 to 80 W.
[0008] Optionally, the lower electrode power of the deposition step in the second cycle step is 30-60W.
[0009] Optionally, the flow rate of the oxygen-containing gas in the deposition step of the second cycle step is 200-300 sccm.
[0010] Optionally, in the second cycle step, the etching step, the removal step, and the deposition step are executed sequentially.
[0011] Optionally, in the first cyclic step, the etching step, the deposition step, and the removal step are executed sequentially, wherein the process gas in the removal step includes a fluorocarbon gas.
[0012] Optionally, the first loop step may be repeated 2 to 4 times.
[0013] Optionally, the second loop step is repeated 11 to 15 times.
[0014] Optionally, before performing the first cyclic step, a pre-removal step is first performed to remove the oxide layer on the surface of the silicon substrate.
[0015] The present invention also provides a semiconductor process apparatus, comprising: a process chamber, a carrier substrate, an upper radio frequency power supply, a lower radio frequency power supply, and a controller, wherein,
[0016] The support base is used to support the silicon substrate;
[0017] The upper radio frequency power supply is used to apply upper electrode power to the process chamber;
[0018] The lower radio frequency power supply is used to apply lower electrode power to the support base;
[0019] The controller includes a memory and a processor. The memory stores computer instructions, and the processor executes the deep silicon etching method described above by executing the computer instructions.
[0020] In the deep silicon etching method provided by this invention, the deposition step of the second cycle uses oxygen-containing gas as a protective gas, and the lower electrode power applied in the deposition step of the second cycle is greater than the lower electrode power in the deposition step of the first cycle. When the deposition step of the second cycle is executed, its lower electrode power can attract more oxygen-containing gas into the lower trench section, thereby enhancing the micro-loading effect of the oxygen-containing gas on the silicon sidewalls and bottom walls of the lower trench section. This results in a thicker protective layer being deposited on the trench sidewalls and bottom walls of the first region with a larger isolation trench CD, correspondingly slowing down the etching rate of the first region in the second cycle. In the first and second regions of the lower trench section, the deposition rate of the deposition step corresponds to the etching rate of the etching step, thereby balancing the overall etching rate of the lower trench section, optimizing the depth micro-loading effect, and improving the depth consistency of the isolation trench.
[0021] Meanwhile, the deposition step in the second cycle uses oxygen-containing gas as a protective gas. The oxygen-containing gas forms a protective layer through the silicon oxide sidewall and silicon bottom wall. The application of the lower electrode power will not increase the consumption of the mask layer in the deposition step. Thus, while reducing the micro-load of the isolation trench depth and improving the consistency of the isolation trench depth, it also reduces the consumption of the mask layer and ensures the effective height of the mask layer. This improves the morphological accuracy of the formed isolation trench and AA, reduces defects such as AA tipping or even wire breakage, and improves the electrical properties and yield of the product. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0023] Figure 1 This is a target etching topography image of an active array in a DRAM.
[0024] Figure 2a The image shows the etching topography of the isolation trench along the direction perpendicular to AA, obtained by the first deep silicon etching method provided by the relevant technology.
[0025] Figure 2b The image shows the etching morphology of the isolation trench along the AA direction, obtained by the first deep silicon etching method provided by the relevant technology.
[0026] Figure 3 The image shows the etching topography of an active array obtained using a second deep silicon etching method provided by related technologies, in which the ends of AA are subjected to a clipping phenomenon.
[0027] Figure 4A flowchart illustrating the first and second cycle steps in the deep silicon etching method provided in this embodiment of the invention;
[0028] Figure 5a For deep silicon etching methods in Figure 4 The electron microscope image of the etching morphology of the isolation trench along the AA direction is obtained under the cyclic process shown, without optimizing the number of cycles in the first cycle step and the deposition step in the second cycle step.
[0029] Figure 5b For deep silicon etching methods in Figure 4 The electron microscope image of the etching morphology of the isolation trench along the AA direction obtained under the cyclic process shown, without optimizing the number of cycles in the first cycle step and the deposition step in the second cycle step.
[0030] Figure 6a Electron micrograph of the etching morphology of the isolation trench along the direction perpendicular to AA, obtained by the first deep silicon etching method provided in the embodiment of the present invention;
[0031] Figure 6b An electron microscope image of the etching morphology of the isolation trench along the AA direction obtained by the first deep silicon etching method provided in the embodiment of the present invention;
[0032] Figure 7a Electron micrograph of the etching morphology of the isolation trench along the direction perpendicular to AA, obtained by the second deep silicon etching method provided in the embodiment of the present invention;
[0033] Figure 7b Electron micrograph of the etching morphology of the isolation trench along the AA direction obtained by the second deep silicon etching method provided in the embodiment of the present invention;
[0034] Figure 8 This is a schematic diagram of a semiconductor process equipment provided in an embodiment of the present invention.
[0035] Explanation of reference numerals in the attached figures:
[0036] 10-Mask layer; 11-Opening; 20-Silicon substrate; 21-Isolation trench; 211-Upper trench section; 212-Lower trench section; 213-First region; 214-Second region; 215-Depth micro-load; 22-Active region; 221-End; 222-Middle;
[0037] 110 - Process chamber; 120 - Support base; 130 - Upper RF power supply; 140 - Upper matching unit; 150 - RF coil; 160 - Dielectric window; 170 - Lower matching unit; 180 - Lower RF power supply. Detailed Implementation
[0038] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0039] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0040] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0041] Figure 1 This is a topographic image of the target etching pattern for an active array in a DRAM. (Example:) Figure 1 As shown, multiple active regions 22 (AA) in the active array are arranged collinearly or parallelly. The isolation groove 21 is located in the region between two adjacent AAs along the direction parallel to the AA, which is the first region 213. The region between two adjacent AAs along the direction perpendicular to the AA is the second region 214. The critical dimensions (CD) of the first region 213 are larger than the dimensions of the second region 214. Ideally, the two ends 221 of the AA in the length direction are arc-shaped, and the depths of the first region 213 and the second region 214 of the isolation groove 21 are the same.
[0042] Figure 2a This is an etching topography of the isolation trench 21 obtained according to the first deep silicon etching method provided by the relevant technology, along the direction perpendicular to AA. Figure 2b This is an etching topography of the isolation trench 21 along the direction parallel to AA, obtained according to the first deep silicon etching method provided by the relevant technology. Figure 3The image shows the etching topography of an active array obtained by a second deep silicon etching method provided by related technologies, wherein the end 221 of AA is subjected to a clipping phenomenon.
[0043] In the related technology of etching silicon substrate 20 to form isolation trench 21, since the CD of the first region 213 of isolation trench 21 is greater than that of the second region 214, there is a pattern density difference between different regions of isolation trench 21. During the etching process of forming isolation trench 21 according to the first deep silicon etching method, the etching rate of the first region 213 is greater than that of the second region 214, resulting in the formation of depth micro-loads 215 in different regions of isolation trench 21, such as... Figure 2a and Figure 2b As shown, the depth of the first region 213 of the isolation trench 21 is greater than the depth of the second region 214, thus affecting the morphological accuracy of the isolation trench 21 and AA, and consequently affecting the electrical properties and yield of the product. To reduce the depth microload 215 of the isolation trench 21, the duty cycle of the lower electrode power in the etching step of the second deep silicon etching method is increased compared to the first deep silicon etching method. However, while increasing the plasma etching intensity of the etching step to reduce the depth microload 215, the etching intensity on the mask layer 10 also increases, leading to increased mask layer 10 loss and reduced effective height. In particular, as... Figure 3 As shown, under the micro-load caused by the difference in pattern density of the opening 11, the etching loss of the end 221 of the mask layer 10 corresponding to AA is greater than that of the middle part 222. This can easily cause the end 221 of AA to suffer from the phenomenon of tip clipping, and even lead to wire breakage defects. The electrical properties and yield of the product still cannot be guaranteed.
[0044] This embodiment provides a deep silicon etching method that divides the etching process into two cyclic steps. The deposition step (Dep) of the second cyclic step (Loop 2) uses oxygen-containing gas as a protective gas, and its lower electrode power is greater than that of the deposition step in the first cyclic step (Loop 1). This balances the etching rate of different regions of the isolation trench 21, optimizes the depth micro-load effect, and improves the depth consistency of the isolation trench 21. Simultaneously, the use of oxygen-containing gas as a protective gas in the deposition step prevents the consumption of the mask layer 10 during deposition. This reduces the depth micro-load 215, improves the depth consistency of the isolation trench 21, reduces the consumption of the mask layer 10, and ensures the effective height of the mask layer 10, thereby improving the morphological accuracy of the formed isolation trench 21 and AA, and enhancing the electrical properties and yield of the product. The deep silicon etching method provided by this embodiment will be described in detail below with reference to the accompanying drawings.
[0045] This embodiment provides a deep silicon etching method, including a first cycle step and a second cycle step. Both the first cycle step and the second cycle step include an etching step (Main etch, ME) for etching to form trenches on a silicon substrate 20, a removal step (Breakthrough, BT) for removing by-products, and a deposition step for forming a protective layer on the sidewalls of the trenches. The protective gas used in the deposition step of the second cycle step includes an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than the lower electrode power of the deposition step of the first cycle step.
[0046] Initially, a mask layer 10, such as a SiO2 mask layer 10, is provided on the top of the silicon substrate 20, and the mask layer 10 has an opening 11 that defines the region of the isolation trench 21. During the process, the first cycle step is used to etch and form the upper trench section 211 of the isolation trench 21. The upper trench section 211 is close to the opening 11 of the mask layer 10, and no lower electrode power is required or only a small lower electrode power is applied. The protective gas in the deposition step can enter the upper trench section 211 in greater quantities and deposit a protective layer on its sidewalls and bottom wall. The CD of the first region 213 of 211 is greater than that of the second region 214. Under the micro-load caused by the difference in pattern density, the thickness of the protective layer deposited in the first region 213 of the upper trench section 211 is greater, thereby slowing down the etching rate of the first region 213 in the first cycle step. In the first region 213 and the second region 214 of the upper trench section 211, the deposition rate of the deposition step and the etching rate of the etching step correspond to each other, thereby balancing the overall etching rate of the upper trench section 211 and optimizing the depth micro-load effect of the first cycle step.
[0047] The subsequent second cycle step is used to etch and form the lower trench section 212 of the isolation trench 21. The lower trench section 212 is relatively deep, and the opening 11CD of the mask layer 10 is relatively small, making it difficult for the protective gas to enter the lower trench section 212. The deposition step of the second cycle step uses oxygen-containing gas as the protective gas, and the lower electrode power applied in the deposition step of the second cycle step is greater than the lower electrode power in the deposition step of the first cycle step. When the deposition step of the second cycle step is executed, its lower electrode power can attract more oxygen-containing gas into the lower trench section 212. The enhanced micro-loading effect of oxygen-containing gas on the silicon sidewalls and bottom walls of the lower trench section 212 results in a thicker protective layer being deposited on the trench sidewalls and bottom walls of the first region 213 with a larger CD. This correspondingly slows down the etching rate of the first region 213 in the second cycle step. In the first region 213 and the second region 214 of the lower trench section 212, the deposition rate of the deposition step corresponds to the etching rate of the etching step, thereby balancing the overall etching rate of the lower trench section 212, optimizing the depth micro-loading effect, and improving the depth consistency of the isolation trench 21.
[0048] Meanwhile, the deposition step in the second cycle uses oxygen-containing gas as a protective gas. The oxygen-containing gas forms a protective layer through the silicon oxide sidewall and silicon bottom wall. The application of the lower electrode power will not increase the consumption of the mask layer 10 in the deposition step. Thus, while reducing the micro-load 215 of the isolation trench 21 and improving the consistency of the isolation trench 21 depth, it also reduces the consumption of the mask layer 10 and ensures the effective height of the mask layer 10. This improves the morphological accuracy of the isolation trench 21 and AA, reduces defects such as AA tipping or even wire breakage, and improves the electrical properties and yield of the product.
[0049] Specifically, the oxygen-containing gas in the second cycle can be O2; the deposition step in the first cycle can also use an oxygen-containing gas, such as O2, as a protective gas to reduce the consumption of the mask layer 10 during the process and further ensure the effective height of the mask layer 10.
[0050] In this embodiment of the invention, the lower electrode power of the deposition step in the first cycle is 0, and the lower electrode power of the deposition step in the second cycle is 10-80W. The upper trench section 211 is close to the opening 11 of the mask layer 10. Since no lower electrode power is applied during the deposition step of the first cycle, a relatively large amount of protective gas can enter the upper trench section 211. This effectively alleviates the depth micro-load effect of the first cycle, improves the operational convenience of the deposition step, and reduces its energy consumption. The lower trench section 212 has a large depth-to-width ratio, making it difficult for oxygen-containing gas to enter the lower trench section 212 during the deposition step of the second cycle. Applying a small lower electrode power of 10-80W can effectively guide the oxygen-containing gas into the lower trench section 212 without damaging the mask layer 10. This enhances the micro-loading effect of the oxygen-containing gas on the silicon sidewalls and bottom walls of the lower trench section 212, thereby balancing the overall etching rate of the lower trench section 212, optimizing the depth micro-loading effect, improving the depth consistency of the isolation trench 21, and further improving the morphological accuracy of the isolation trench 21 and AA, thus improving the electrical properties and yield of the product.
[0051] Specifically, in this embodiment of the invention, the lower electrode power of the deposition step in the second cycle is 30-60W. Applying a suitable range of lower electrode power to the deposition step in the second cycle ensures appropriate traction of the oxygen-containing gas by the lower electrode power and effective balance of the depth micro-load effect of the lower trench section 212; it reduces the situation where a lower electrode power that is too small results in a weak traction force for the oxygen-containing gas and a low degree of optimization of the depth micro-load effect, leading to a still large depth difference between the first region 213 and the second region 214, or an lower electrode power that is too large results in ineffective energy consumption.
[0052] In this embodiment of the invention, the flow rate of the oxygen-containing gas in the deposition step of the second cycle is 200–300 sccm. Specifically, the process formulation of the deposition step in the second cycle can be exemplified as follows: the protective gas includes O2, with a flow rate of 200–300 sccm, a chamber pressure of 10–15 mT, a chamber temperature of 45–60 °C, an upper electrode power of 1000–1500 W (13.56 MHz, continuous wave mode), and a lower electrode power of 30–60 W (13.56 MHz, continuous wave mode); the flow rate ratio of the process gas ejected from the nozzle in the chamber to the central, intermediate, and edge regions of the silicon substrate 20 is approximately 65:20:15, and the process time is 10–13 s.
[0053] Figure 4 This is a flowchart illustrating the first and second cycle steps in the deep silicon etching method provided in this embodiment of the invention.
[0054] like Figure 4 As shown in the embodiment of the present invention, in the first cycle step, an etching step, a deposition step, and a removal step are executed sequentially, wherein the process gas in the removal step includes a fluorocarbon gas; in the second cycle step, an etching step, a removal step, and a deposition step are executed sequentially. During the process, the etching step etches the silicon substrate 20 in the opening 11 region, transferring the opening 11 pattern of the mask layer 10 to the silicon substrate 20 to form a trench of a certain depth; the deposition step forms a protective layer with good resistance to ion bombardment through the silicon oxide sidewalls and silicon bottom wall to protect the silicon sidewalls and reduce the erosion of the silicon sidewalls by the etching step. At the same time, the etching step can bombard and remove the protective layer formed on the silicon bottom wall to perform effective vertical etching; the removal step can remove the by-products generated by the etching step to ensure the smooth and effective execution of the etching step.
[0055] The first cycle step is used to etch and form the upper trench segment 211 near the opening 11 of the mask layer 10. The fluorocarbon gas in the removal step of the first cycle step contains a certain amount of carbon. In the upper trench segment 211 with a smaller trench depth, a certain amount of carbon will remain on the bottom and sidewalls of the trench during the removal step reaction. The first cycle step is set to execute the ME step, Dep step and BT step in sequence. After the BT step in the previous cycle is completed, the ME step in the next cycle is immediately followed. The carbon remaining in the BT step in the previous cycle can form carbon polymer in the ME step and be deposited on the sidewalls and bottom wall of the trench, which protects the sidewalls of the trench.
[0056] As the first cycle proceeds, the trench depth increases, and the thickness of the carbon polymer formed on the trench sidewalls gradually increases, forming a conical trench with sidewalls sloping downwards towards the center. The carbon polymer provides etching allowance for the lateral erosion of the upper trench section 211 of the isolation trench 21 during the ME and BT steps in the second cycle, resisting the lateral erosion of the silicon sidewalls of the upper trench section 211 of the isolation trench 21 during the second cycle. After the first cycle is completed, the second cycle continues: the ME, BT, and Dep steps are executed sequentially to ensure smooth etching and maintain the verticality of the silicon sidewalls of the lower trench section 212. Simultaneously, the carbon polymer formed on the upper trench section 211 of the isolation trench 21 protects the silicon sidewalls in this area, resisting the lateral erosion of the silicon sidewalls in this area during the second cycle, further reducing the lateral erosion of the upper trench section 211 of the isolation trench 21, thereby further improving the morphological accuracy of the isolation trench 21 and AA, and further improving product yield.
[0057] After the second cycle step reaches the required number of cycles, an etching step is performed to remove the protective layer formed in the deposition step of the last cycle, thereby obtaining the isolation trench 21 at the target depth.
[0058] Specifically, in the first cycle, the etching step can use Cl2 as the main etching gas, combined with one or more inert auxiliary gases such as Ar, He, and N2, which is beneficial for the uniformity of etching across the entire wafer. A small amount of O2 is introduced to protect the sidewalls. The deposition step uses a higher upper electrode power and turns off the lower electrode power, with O2 used to form a protective layer on the silicon sidewalls to resist subsequent lateral etching. The removal step uses a fluorine-containing gas to promptly remove the Si-Cl byproducts formed after the etching step to prevent them from accumulating at the bottom and obstructing etching. In the second cycle, the etching step uses higher upper and lower electrode powers than the etching step in the first cycle, and NF3 is added to make the etching deeper and straighter. The deposition step turns on the lower electrode power, and the other process formulations are basically the same as the deposition step in the first cycle. The process formulation for the removal step is basically the same as the removal step in the first cycle.
[0059] In this embodiment of the invention, the number of cycles in the first cycle step is 2 to 4. Setting the number of cycles in the first cycle step to be greater than or equal to 2 ensures the amount of carbon polymer formed in the upper trench section 211, guaranteeing effective protection of the upper trench section 211 by the carbon polymer in the first and second cycle steps, reducing the lateral erosion of the silicon sidewalls of the upper trench section 211 by the first and second cycle steps, thereby ensuring the morphological accuracy of the upper trench section 211 and the isolation trench 21. Furthermore, setting the number of cycles in the first cycle step to be less than or equal to 4, a smaller number of cycles, reduces the risk of the etching step directly bombarding the mask layer 10 during the etching process after the removal step of the previous cycle removes byproducts from the top and sidewalls of the mask layer 10, which would cause significant damage to the mask layer 10. By reducing the number of cycles in the first cycle step, the physical bombardment capability of the etching step on the mask layer 10 is weakened, thereby ensuring the effective height of the mask layer 10, correspondingly ensuring the morphological accuracy of the subsequently formed isolation trench 21 and AA, and ensuring the electrical properties and yield of the product.
[0060] Specifically, taking two cycles as an example, the first cycle step aims to minimize the consumption of the mask layer 10 by ensuring that the carbon polymer formed in the upper trench section 211 effectively protects it.
[0061] In this embodiment of the invention, the number of cycles in the second cycle step is 11 to 15. After the number of cycles in the first cycle step is reduced, the number of cycles in the second cycle step is increased accordingly to ensure the depth of the isolation trench 21. In this embodiment of the invention, the cycle sequence of the second cycle step adopts ME step, BT step, and Dep step to ensure the verticality of the lower trench section 212 and the isolation trench 21. The removal step of the second cycle step increases the lower RF power and uses oxygen-containing gas as a protective gas, which can effectively optimize the depth micro-load effect and improve the depth consistency of the lower trench section 212. This effectively ensures the morphological accuracy of the isolation trench 21 and AA, and ensures the electrical properties and yield of the product.
[0062] In this embodiment of the invention, before performing the first cycle step, a pre-removal step (BT0) is first performed to remove the oxide layer on the surface of the silicon substrate 20. The surface of the silicon substrate 20 is exposed in the opening 11 region of the mask layer 10. The exposed region of the silicon substrate 20 can contact the ambient gas to oxidize and form a natural oxide layer. Before performing the cycle step, the pre-removal step is first performed to remove the natural oxide layer to ensure that the etching in the subsequent cycle step proceeds smoothly.
[0063] The following section, in conjunction with etching morphology diagrams and specific process formulations, details the effects of optimizing the number of cycles in the first cycle step and optimizing the deposition step in the second cycle step in the deep silicon etching method provided by the embodiments of the present invention on increasing the effective height of the mask layer 10 and reducing the depth micro-load effect of the isolation trench 21.
[0064] Figure 5a For deep silicon etching methods in Figure 4 The electron microscope image of the etching morphology of the isolation trench 21 along the direction perpendicular to AA is obtained under the cyclic process shown, without optimizing the number of cycles in the first cycle step and the deposition step in the second cycle step. Figure 5b For deep silicon etching methods in Figure 4 The electron microscope image of the etching morphology of the isolation trench 21 along the AA direction is obtained under the cyclic process shown, without optimizing the number of cycles in the first cycle step and the deposition step in the second cycle step.
[0065] Figure 5a and Figure 5b The image was obtained from the unoptimized deep silicon etching method, which specifically included a first cycle step and a second cycle step. The first cycle step sequentially cyclically repeated the etching, deposition, and removal steps, with more than 4 cycles. The second cycle step sequentially repeated the etching, removal, and deposition steps, with the lower electrode power of the deposition step being 0, and the number of cycles being 10–14. Initially, the height of the mask layer 10 was approximately [missing information]. like Figure 5a and Figure 5b As shown, after the first and second loop steps, the remaining height of the mask layer 10 is approximately... The depth of the first region 213 of the isolation trench 21 is approximately: The depth of the second region 214 of the isolation trench 21 is approximately smaller than the depth of the first region 213. That is, the depth of the isolation groove 21 and the micro-load 215 are approximately equal to
[0066] Figure 6a Electron micrograph of the etching morphology of the isolation trench 21 along the direction perpendicular to AA, obtained by the first deep silicon etching method provided in the embodiment of the present invention. Figure 6b An electron microscope image of the etching morphology of the isolation trench 21 along the direction parallel to AA, obtained by the first deep silicon etching method provided in an embodiment of the present invention.
[0067] The difference between the first deep silicon etching method provided in this embodiment and the previous deep silicon etching method is that the number of cycles in the first cycle step of the first deep silicon etching method provided in this embodiment is greater than 2 and less than 4, which is less than the number of cycles in the first cycle step of the previous deep silicon etching method; correspondingly, the number of cycles in the second cycle step of the first deep silicon etching method provided in this embodiment is 11 to 15, which is greater than the number of cycles in the second cycle step of the previous deep silicon etching method. For example... Figure 6a and 6b As shown, after reducing the number of iterations in the first loop step, the remaining height of the mask layer 10 is approximately... The depth has increased compared to before optimization; the depth of the first region 213 of the isolation trench 21 is approximately... The depth of the second region 214 of the isolation trench 21 is approximately smaller than the depth of the first region 213. The depth of the isolation groove 21 and the microload 215 are approximately equal to... As the number of cycles in the second cycle increases, the depth of the micro-load 215 formed increases.
[0068] In the deep silicon etching method of this embodiment of the invention, after reducing the number of cycles in the first cycle step compared to the previous method, the wear on the mask layer 10 can be effectively reduced, the effective height of the mask layer 10 can be increased, the mask layer 10 can be used to restrict and protect the topography of the AA and the isolation trench 21, and the defects of AA tipping or even wire breakage can be reduced.
[0069] Figure 7a Electron micrograph of the etching morphology of the isolation trench 21 along the direction perpendicular to AA, obtained by the second deep silicon etching method provided in the embodiment of the present invention. Figure 7b Electron micrograph of the etching morphology of the isolation trench 21 along the direction parallel to AA, obtained by the second deep silicon etching method provided in the embodiment of the present invention.
[0070] The second deep silicon etching method provided in this embodiment of the invention optimizes the removal step in the second cycle step based on the first deep silicon etching method provided in this embodiment of the invention. The difference is that the lower electrode power in the removal step of the second cycle step in the second deep silicon etching method provided in this embodiment of the invention is 30-60W, which is an improvement in the lower electrode power. Figure 7a and 7b As shown, after applying the lower electrode power to the removal step of the second cycle, the remaining height of the mask layer 10 is approximately... The effective height of the mask layer 10 remains approximately constant; the depth of the first region 213 of the isolation trench 21 is approximately... The depth of the second region 214 of the isolation trench 21 is approximately smaller than the depth of the first region 213. The depth of the isolation groove 21 and the microload 215 are approximately equal to... It has been reduced by nearly half compared to before optimization.
[0071] In the deep silicon etching method of this embodiment of the invention, the depth micro-load effect of the isolation trench 21 can be reduced by nearly half compared with the previous method, thereby effectively reducing the depth micro-load 215 of the isolation trench 21, improving the depth consistency of the isolation trench 21, improving the morphological accuracy of AA and the isolation trench 21, and improving the electrical properties and yield of the product.
[0072] like Figure 8As shown, this embodiment also provides a semiconductor process apparatus, including: a process chamber 110, a support base 120, an upper radio frequency power supply 130, a lower radio frequency power supply 180, and a controller. The support base 120 is used to support a silicon substrate 20; the upper radio frequency power supply 130 is used to apply upper electrode power to the process chamber 110; the lower radio frequency power supply 180 is used to apply lower electrode power to the support base 120; the controller includes a memory and a processor. The memory stores computer instructions, and the processor executes the computer instructions to perform the aforementioned deep silicon etching method. This semiconductor process apparatus is capable of performing the aforementioned deep silicon etching method and possesses all the beneficial effects of the etching method, which will not be elaborated further here.
[0073] Specifically, in this semiconductor process equipment, a dielectric window 160 is provided above the carrier base 120 within the process chamber 110. An RF coil 150 is positioned above the dielectric window 160. An upper matching unit 140 is provided between the RF coil 150 and the upper RF power supply 130. The upper RF power supply 130 provides RF power to the RF coil 150 through the upper matching unit 140, thereby exciting the process gas inside the process chamber 110 to generate plasma. A lower matching unit 170 is provided between the carrier base 120 and the lower RF power supply 180. The lower RF power supply 180 provides RF power to the carrier base 120 through the lower matching unit 170 to provide RF bias. The carrier base 120 can be, for example, an electrostatic chuck, a mechanical chuck, or a vacuum adsorption chuck.
[0074] The semiconductor process equipment in this application embodiment can be either an inductively coupled plasma (ICP) device or a capacitively coupled plasma (CCP) device. This application embodiment does not limit the type of semiconductor process equipment.
[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A deep silicon etching method, characterized in that, The process includes a first cycle step and a second cycle step. Both the first cycle step and the second cycle step include an etching step for etching to form a trench on a silicon substrate (20), a removal step for removing byproducts, and a deposition step for forming a protective layer on the sidewalls of the trench. The trench includes a first region (213) and a second region (214). The size of the first region (213) is larger than the size of the second region (214). The protective gas used in the deposition step of the second cycle step includes an oxygen-containing gas. The lower electrode power of the deposition step of the first cycle step is 0, and the lower electrode power of the deposition step of the second cycle step is greater than the lower electrode power of the deposition step of the first cycle step, so that more oxygen-containing gas can be drawn into the lower trench section (212) in the deposition step of the second cycle step, and a thicker protective layer is deposited on the trench sidewalls and bottom walls of the larger first region (213), thereby slowing down the etching rate of the larger first region (213) in the trench by the etching step in the second cycle step. In the second cycle step, the lower electrode power of the deposition step is 10~80W.
2. The deep silicon etching method according to claim 1, characterized in that, The lower electrode power of the deposition step in the second cycle step is 30~60W.
3. The deep silicon etching method according to claim 1, characterized in that, The flow rate of the oxygen-containing gas in the deposition step of the second cycle step is 200~300 sccm.
4. The deep silicon etching method according to claim 1, characterized in that, In the second cycle step, the etching step, the removal step, and the deposition step are executed sequentially.
5. The deep silicon etching method according to any one of claims 1-4, characterized in that, In the first cycle step, the etching step, the deposition step, and the removal step are executed sequentially, wherein the process gas in the removal step includes a fluorocarbon gas.
6. The deep silicon etching method according to claim 5, characterized in that, The first loop step is repeated 2 to 4 times.
7. The deep silicon etching method according to claim 5, characterized in that, The second loop step is repeated 11 to 15 times.
8. The deep silicon etching method according to any one of claims 1-4, characterized in that, Before performing the first cycle step, a pre-removal step is first performed to remove the oxide layer on the surface of the silicon substrate (20).
9. A semiconductor process apparatus, characterized in that, include: The process chamber (110), the support base (120), the upper RF power supply (130), the lower RF power supply (180), and the controller, wherein, The support base (120) is used to support the silicon substrate (20); The upper radio frequency power supply (130) is used to apply upper electrode power to the process chamber (110); The lower radio frequency power supply (180) is used to apply lower electrode power to the support base (120); The controller includes a memory and a processor, the memory storing computer instructions, and the processor executing the computer instructions to perform the deep silicon etching method according to any one of claims 1-8.