Driving circuit and driving device of high-side NMOS (N-channel metal oxide semiconductor) tube

Abstract

The invention discloses a driving circuit and a driving device for a high-side NMOS (N-channel Metal Oxide Semiconductor) tube, and the voltage at a switch end in the driving circuit changes along with the change of the output voltage of a high-side power tube, so that external VDD (Voltage Drain Drain) power supply or internal charge pump power supply can be automatically selected according to the output voltage of the high-side power tube; therefore, the whole driving power supply is realized by the external power supply and the charge pump together, the design requirement on the charge pump is reduced, the chip area required by the charge pump is reduced, the cost is reduced, meanwhile, the generation of the whole driving voltage does not need to use an external CBOOT capacitor, and the bootstrap capacitor in the whole driving circuit is not used for generating high voltage, so that the driving power supply is more stable. The driving module is not directly connected, and only the switching end of the switching unit needs to be connected, so that DC current consumption does not exist, and the problem of switching frequency limitation is solved; therefore, the defects in the traditional technology are overcome, and the method is suitable for large-scale application and popularization.

Description

Technical Field

[0001] The present invention relates to the technical field of NMOS transistor driving, and in particular to a driving circuit and a driving device for a high-side NMOS transistor. Background Art

[0002] High-side NMOS drivers are usually used in areas where high-voltage side loads need to be controlled, such as power management, motor control, and other fields. In practical applications, taking half-bridge drivers as an example, the drivers of high-side NOMS tubes are usually designed with two structures: (1) NMOS is used as the lower tube and PMOS is used as the upper tube; (2) NMOS tubes are used for both the lower tube and the upper tube; Among them, the driving circuit structure of PMOS as the upper tube is simple, but since the layout area required to achieve the same on-resistance using PMOS tubes is larger than that of NMOS tubes, as the current capability requirements of the driving circuit increase, more and more driving circuits use NMOS power tubes as high-side driving switches in order to reduce the chip area.

[0003] However, the use of NMOS power transistors as high-side drive switches increases the complexity of the drive circuit design. Existing high-side NMOS power transistor drive circuits are mainly implemented in the following two ways: See also Figure 1 As shown, Figure 1 It is a common high-side NMOS power tube drive circuit. Its implementation mainly relies on CBOOT capacitor, anti-reverse circuit, drive buf and LDO circuit. Among them, CBOOT capacitor and anti-reverse circuit together constitute a high-voltage generating circuit. The high voltage VHP generated by it is VOUT+5V (assuming the LDO output voltage is 5V). In practical applications, the VHP voltage value can be changed by setting the LDO voltage. The high-voltage VHP is used to provide power to the driver buf, and in conjunction with the high-side control signal, it can realize the normal opening or closing function of the high-side power transistor HSN. However, the aforementioned drive circuit has the following disadvantages: the anti-reverse circuit and CBOOT device generally need to be external (i.e., they are placed outside the chip), which will increase the cost of chip use. At the same time, this structure has certain restrictions on the minimum switching frequency of the power transistor. If the power transistor switching frequency is low, the VHP voltage will be lower than the HSN turn-on voltage, which will cause the HSN conduction function to fail (i.e., because the CBOOT device is part of the high-voltage generation circuit and needs to be connected to the buf, there is DC current consumption, that is, it will discharge. Based on this, based on this, it needs to be charged at intervals. If the switching frequency of the power transistor is lower than this interval, the CBOOT device voltage will be insufficient, which will cause the VHP voltage to be lower than the HSN turn-on voltage).

[0004] Figure 2It is another existing high-side NMOS power tube drive circuit, which solves the Figure 1 The driving circuit shown in the figure limits the switching frequency. Specifically, a charge pump circuit is designed inside or outside the chip to generate a high voltage of VDD+5V. Then, an LDO circuit is designed under this high voltage to output VHP=VOUT+5V, thereby providing power to the HSN driving buf. In this way, the aforementioned structure no longer limits the minimum switching frequency of the driving circuit. However, since the power supply for the entire driving process is provided by the high voltage generated by the charge pump, the second driving circuit has higher requirements for the design of the charge pump. If the charge pump is designed on-chip, a larger chip area will be required.

[0005] Therefore, the aforementioned prior art has the problems of requiring external devices to cooperate in order to realize the driving function, limiting the minimum switching frequency of the driving circuit, and causing area consumption and increased chip cost due to on-chip design. Therefore, based on the aforementioned deficiencies, how to provide a driving circuit for a high-side NMOS transistor that can reduce costs, does not require an external CBOOT capacitor, and does not have a minimum switching frequency limit has become an urgent problem to be solved. Summary of the Invention

[0006] The technical problem to be solved by the present invention is the problem of driving the high-side NOMS tube. The purpose is to provide a driving circuit and a driving device for a high-side NMOS tube, which solves the problems in traditional technology that external devices are required to cooperate to realize the driving function, the minimum switching frequency of the driving circuit is limited, and the on-chip design causes area consumption and increases chip costs.

[0007] The present invention is achieved through the following technical solutions: In a first aspect, a driving circuit for a high-side NMOS transistor is provided, comprising: An adaptive power switching module, the adaptive power switching module comprising a first switch unit and a second switch unit, wherein the output ends of the first switch unit and the second switch unit are both electrically connected to the power supply end of the driving module, the output end of the driving module is electrically connected to the gate of the high-side NMOS transistor, and the drain of the high-side NMOS transistor is electrically connected to the VDD power supply; The power supply end of the first switch unit is electrically connected to the VDD power supply, and the power supply end of the second switch unit is electrically connected to the charge pump, wherein the switch end of the first switch unit is electrically connected to the source of the high-side NMOS transistor and the VDD power supply, and the switch end of the second switch unit is electrically connected to the source of the high-side NMOS transistor through a bootstrap capacitor; Among them, the voltage at the switch end of the first switch unit and the second switch unit rises or falls with the output voltage of the high-side NMOS tube, and is used to be turned on or off according to the voltage at the corresponding switch end to turn on the VDD power supply or the charge pump to power the driving module.

[0008] Based on the above disclosure, the present invention provides a high-side NMOS transistor drive circuit, which is provided with an adaptive power switching module, wherein the adaptive power switching module includes a first switch unit and a second switch unit, wherein the power supply ends of the first switch unit and the second switch unit are respectively connected to different power supplies (i.e., connected to the VDD power supply and the charge pump, respectively), the switch ends of the two switch units are both electrically connected to the source of the high-side NMOS transistor, and the voltages at the switch ends of the two switch units rise or fall with the output voltage of the high-side NMOS transistor, so as to be turned on or off according to the voltages at the corresponding switch ends; based on this, the above design causes the voltages at the switch ends of the two switch units to change synchronously with the output voltage of the high-side NMOS transistor, so that the switch units can automatically switch on or off according to the output voltage of the high-side power transistor, thereby connecting the VDD power supply or the charge pump to the drive module to complete the power supply switching.

[0009] Through the above-described design, the voltage at the switch terminal of the high-side NMOS transistor drive circuit provided by the present invention varies with the output voltage of the high-side power transistor. Therefore, the external VDD power supply or the internal charge pump power supply can be automatically selected according to the output voltage of the high-side power transistor. In this way, the entire drive power supply is jointly provided by the external power supply and the charge pump, which reduces the design requirements for the charge pump and thus reduces the chip area required for the charge pump (i.e., a smaller chip area can be used to design an internal charge pump that meets the driving capability), thereby reducing costs. At the same time, the entire drive voltage generation does not require the use of an external CBOOT capacitor, and the bootstrap capacitor in the entire drive circuit is not directly connected to the drive module, but only to the switch terminal of the switch unit. Therefore, there is no DC current consumption, thereby solving the problem of switching frequency limitation. Therefore, compared with traditional technologies, the present invention does not require an external CBOOT capacitor, reduces the driving requirements of the charge pump, and eliminates the switching frequency limitation, making it very suitable for large-scale application and promotion.

[0010] In one possible design, the first switching unit includes: a first MOS transistor, wherein the gate of the first MOS transistor serves as the switching end of the first switching unit, and is electrically connected to the source of the high-side NMOS transistor and the VDD power supply, respectively; the drain of the first MOS transistor serves as the power supply end of the first switching unit, and is electrically connected to the VDD power supply; and the source of the first MOS transistor serves as the output end of the first switching unit, and is electrically connected to the power supply end of the driving module.

[0011] In one possible design, the first switching unit also includes: a first diode, wherein the gate of the first MOS tube is electrically connected to the cathode of the first diode, the anode of the first diode is electrically connected to the source of the high-side NMOS tube, and the first diode is a Zener diode.

[0012] In one possible design, the first switching unit further includes: a current source, wherein an input end of the current source is electrically connected to the VDD power supply, an output end of the current source is electrically connected to the source of the high-side NMOS tube through the first diode, and a common end of the current source and the first diode is electrically connected to the gate of the first MOS tube.

[0013] In one possible design, the CPLD unit further includes: an anti-reverse circuit, wherein the drain of the first MOS tube is electrically connected to the VDD power supply through the anti-reverse circuit.

[0014] In one possible design, the anti-reverse circuit includes: an anti-reverse diode, wherein the positive electrode of the anti-reverse diode is electrically connected to the VDD power supply, and the negative electrode of the anti-reverse diode is electrically connected to the drain of the first MOS tube.

[0015] In one possible design, the second switch unit includes: a second MOS transistor, wherein a gate of the second MOS transistor serves as a switch end of the second switch unit and is electrically connected to a low-voltage power supply and a positive electrode of the bootstrap capacitor, respectively, and a negative electrode of the bootstrap capacitor is electrically connected to a source of the high-side NMOS transistor; The drain of the second MOS transistor serves as the power supply end of the second switch unit and is electrically connected to the output end of the charge pump, wherein the source of the second MOS transistor serves as the output end of the second switch unit and is electrically connected to the power supply end of the driving module, and the input end of the charge pump is electrically connected to the VDD power supply.

[0016] In one possible design, the second switching unit further includes: a second diode, wherein the gate of the second MOS tube is electrically connected to the cathode of the second diode, and the anode of the second diode is electrically connected to the low-voltage power supply.

[0017] In one possible design, the driving module includes: a first driver and a second driver, wherein the input end of the first driver is used to receive an external driving signal, the output end of the first driver is electrically connected to the input end of the second driver, the output end of the second driver is electrically connected to the gate of the high-side NMOS tube, and the power supply ends of the first driver and the second driver are both electrically connected to the output ends of the first switch unit and the second switch unit.

[0018] In a second aspect, a driving device is provided, comprising: a load module and a driving circuit of the high-side NMOS tube in the first aspect or any possible design of the first aspect, wherein the source of the high-side NMOS tube in the driving circuit of the high-side NMOS tube is electrically connected to the controlled end of the load module, and the ground end of the load module is grounded.

[0019] Compared with the prior art, the present invention has the following advantages and beneficial effects: (1) The voltage at the switch end of the driving circuit of the high-side NMOS tube provided by the present invention changes with the output voltage of the high-side power tube. Therefore, the external VDD power supply or the internal charge pump power supply can be automatically selected according to the output voltage of the high-side power tube. In this way, the entire driving power supply is realized by the external power supply and the charge pump, which reduces the design requirements for the charge pump, thereby reducing the chip area required for the charge pump (that is, a smaller chip area can be consumed to design an internal charge pump that meets the driving capability), reducing the cost. At the same time, the generation of the entire driving voltage does not require the use of an external CBOOT capacitor, and the bootstrap capacitor in the entire driving circuit is not used to generate high voltage and is not directly connected to the driving module, but only needs to be connected to the switch end of the switching unit. Therefore, there is no DC current consumption, thereby solving the problem of switching frequency limitation. Therefore, compared with the traditional technology, the present invention does not require an external CBOOT capacitor, reduces the driving requirements of the charge pump, and removes the switching frequency limitation, making it very suitable for large-scale application and promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the examples. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be considered as limiting the scope. A person of ordinary skill in the art can also derive other relevant drawings based on these drawings without inventive effort. In the drawings: Figure 1 A schematic diagram of a commonly used high-side NMOS power transistor drive circuit provided by the present invention; Figure 2 A schematic diagram of another commonly used high-side NMOS power transistor driving circuit provided by the present invention; Figure 3 A schematic diagram of a driving circuit for a high-side NMOS transistor provided in an embodiment of the present invention; Figure 4 This is a diagram showing the operating timing and node voltage waveforms of the driving circuit of the high-side NMOS transistor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the following examples and accompanying drawings. The exemplary embodiments of the present invention and their descriptions are intended only to explain the present invention and are not intended to limit the present invention. It should be understood that although the terms "first," "second," and so on may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the exemplary embodiments of the present invention.

[0022] Example: See also Figure 3 As shown, the driving circuit of the high-side NMOS transistor provided in this embodiment can automatically select external VDD power supply or internal charge pump power supply according to the output voltage of the high-side power transistor during operation. In this way, on the one hand, no external CBOOT capacitor is required, and on the other hand, the driving capability requirements of the internal charge pump are greatly reduced, which can effectively reduce the area of ​​the on-chip charge pump and thus reduce the chip cost. At the same time, there is no DC current consumption at the GBT node in the circuit, that is, there is no discharge problem of the capacitor, and the voltage at the node can be maintained for a relatively long time. Based on this, the problem of switching frequency limitation existing in traditional technology can be solved. Therefore, compared with traditional technology, this driving circuit does not require an external CBOOT capacitor, reduces the driving requirements of the charge pump, and removes the limitation of switching frequency, making it very suitable for large-scale application and promotion.

[0023] Furthermore, for example, the driving circuit of the aforementioned high-side NMOS transistor may include, but is not limited to: an adaptive power switching module, a VDD power supply, a charge pump, a driving module, and a high-side NMOS transistor HSN (which serves as a switching device and is configured on the high-potential side of the circuit), wherein the VDD power supply and the charge pump serve as the power supply for the entire driving module, and in conjunction with the external driving signal received by the driving module, they can realize on and off control of the high-side NMOS transistor HSN, and the adaptive power switching module is used to use the output voltage of the high-side NMOS transistor HSN to switch the power supply during operation, so as to jointly realize drive control of the high-side NMOS transistor HSN based on the external power supply and the charge pump.

[0024] Optionally, the following provides a specific structure of the aforementioned adaptive power switching module: In this embodiment, the adaptive power switching module may include, but is not limited to: a first switch unit and a second switch unit, wherein the output ends of the first switch unit and the second switch unit are both electrically connected to the power supply end of the driving module, the output end of the driving module is electrically connected to the gate of the high-side NMOS tube HSN, and the drain of the high-side NMOS tube HSN is electrically connected to the VDD power supply; at the same time, the power supply end of the first switch unit is electrically connected to the VDD power supply, the power supply end of the second switch unit is electrically connected to the charge pump, the switch end of the first switch unit is electrically connected to the source of the high-side NMOS tube HSN and the VDD power supply, and the switch end of the second switch unit is electrically connected to the source of the high-side NMOS tube HSN through a bootstrap capacitor C1.

[0025] Furthermore, the voltage at the switch end of the first switch unit and the second switch unit rises or falls with the output voltage of the high-side NMOS tube HSN, and is used to be turned on or off according to the voltage at the corresponding switch end to turn on the VDD power supply or the charge pump to power the driving module.

[0026] In a specific implementation, the aforementioned first and second switch units can be understood as MOS transistor switches, whose on and off states are determined by an applied voltage. In this embodiment, the switch terminals of the two switch units are connected to the output voltage of the high-side NMOS transistor HSN (i.e., the voltage output by its source), so that the voltage at the switch terminals changes synchronously with the output voltage (i.e., increases with an increase in the output voltage and decreases with a decrease in the output voltage). Therefore, during the entire driving process, the voltage at the two switch terminals changes dynamically with the output voltage of the high-side NMOS transistor HSN. Based on this, when the voltage at the switch terminal is greater than the corresponding threshold voltage, the switch unit can be automatically turned on. Similarly, when it is less than the corresponding threshold voltage, it can be automatically turned off. In this way, the two switch units can select an external power supply or a charge pump to power the driving module.

[0027] Through the aforementioned design, this embodiment can automatically select external VDD power supply or internal charge pump power supply according to the output voltage of the high-side power tube, that is, the entire drive power supply does not need to be entirely borne by the charge pump, thereby reducing the design requirements for the charge pump, so that a built-in charge pump that meets the drive capability can be designed by consuming a smaller portion of chip area, thereby reducing the chip area required for the charge pump. At the same time, the generation of the entire drive voltage does not require the use of an external CBOOT capacitor, thereby reducing costs. Moreover, C1 in the drive circuit is not used to generate high voltage and is not directly connected to the drive module, but only needs to be connected to the switch end of the switching unit. Therefore, there is no DC current consumption, thereby solving the problem of switching frequency limitation. Therefore, this embodiment solves the three disadvantages of traditional technologies and is very suitable for large-scale application and promotion.

[0028] Furthermore, the following provides a detailed circuit structure of the aforementioned adaptive power switching module and driving module: First, a specific circuit of the first switch unit in the adaptive power switching module is provided: In a specific implementation, the first switch unit may include, but is not limited to, a first MOS transistor SN2.

[0029] See also Figure 3 As shown, the gate of the first MOS transistor SN2 serves as the switch end of the first switch unit, and is electrically connected to the source of the high-side NMOS transistor HSN and the VDD power supply, respectively. The drain of the first MOS transistor SN2 serves as the power supply end of the first switch unit, and is electrically connected to the VDD power supply. The source of the first MOS transistor SN2 serves as the output end of the first switch unit, and is electrically connected to the power supply end of the driving module. In this way, it is equivalent to that the gate voltage of the first MOS transistor SN2 changes with the output voltage of the high-side NMOS transistor HSN. Therefore, when the voltage between its gate and source (i.e., the VGS voltage) is higher than the corresponding threshold voltage, the first MOS transistor SN2 will be turned on, thereby adopting the VDD power supply for power supply.

[0030] In a specific application, for example, the first switch unit further includes: a first diode D1 and a current source, see Figure 3 As shown, the gate of the first MOS transistor SN2 is electrically connected to the cathode of the first diode D1, and the anode of the first diode D1 is electrically connected to the source of the high-side NMOS transistor HSN (that is, the source of HSN is connected through the first diode D1). At the same time, the input end of the current source is electrically connected to the VDD power supply, and the output end of the current source is electrically connected to the source of the high-side NMOS transistor HSN through the first diode D1. The common connection end of the current source and the first diode D1 is electrically connected to the gate of the first MOS transistor SN2.

[0031] In this way, the aforementioned first switching unit generates a reference voltage, namely VREF=VOUT+VZNR, by using the current source in the VDD domain and the first diode D1 in the VOUT domain (VOUT refers to the output voltage of HSN, and VZNR represents the voltage drop of the first diode D1). Then, a high-voltage NMOS device (i.e., the first MOS transistor SN2) connected to VDD is used to generate a VHP voltage to power the driver module.

[0032] Similarly, the main structure of the second switch unit also uses MOS tubes, see Figure 3 shown.

[0033] In a specific application, the second switch unit may include, but is not limited to: a second MOS transistor SN1 and a second diode D2, wherein the gate of the second MOS transistor SN1 serves as a switch end of the second switch unit, and is electrically connected to a low-voltage power supply (i.e. Figure 3 VLDO in the figure, which is the output voltage of the LDO circuit, that is, the output voltage of the very low dropout (VLDP) regulator) and the positive electrode of the bootstrap capacitor C1, and the negative electrode of the bootstrap capacitor C1 is electrically connected to the source of the high-side NMOS transistor HSN; at the same time, the drain of the second MOS transistor SN1 serves as the power supply end of the second switch unit and is electrically connected to the output end of the charge pump, the source of the second MOS transistor SN1 serves as the output end of the second switch unit and is electrically connected to the power supply end of the drive module, and the input end of the charge pump is electrically connected to the VDD power supply; in addition, in this embodiment, see Figure 3 As shown, the gate of the second MOS transistor SN1 is electrically connected to the cathode of the second diode D2, and the anode of the second diode D2 is electrically connected to the low-voltage power supply.

[0034] In this way, the gate voltage of the second MOS transistor SN1 also changes with the output voltage of HSN. Therefore, when the output voltage of HSN changes, the VGS voltage of the second MOS transistor SN1 will also change accordingly. When it rises to the threshold voltage, it will also be turned on, thereby connecting the charge pump to the power supply to the driver module; similarly, when it drops below the threshold voltage, it will also be cut off, thereby disconnecting the charge pump from supplying power to the driver module.

[0035] Specifically: The second switch unit is composed of an on-chip high-voltage capacitor ( Figure 3 The output of the second MOS tube SN1 power tube is connected to the power supply end of the drive circuit to realize the power supply of the charge pump to the drive module.

[0036] Based on the above description, when the output voltage is 0 and the driving module outputs a high level, the first MOS transistor SN2 is turned on and the second MOS transistor SN1 is turned off. The first MOS transistor SN2 is connected to the VDD power supply to power the driving module and turns on the high-side NMOS transistor HSN. During the driving process, the gate voltages of the first MOS transistor SN2 and the second MOS transistor SN1 rise with the output voltage. When the gate voltage of the first MOS transistor SN2 rises to the VDD voltage and the gate voltage of the second MOS transistor SN1 rises above the threshold voltage, the first MOS transistor SN2 is turned off and the second MOS transistor SN2 is turned on. At this time, the charge pump is used to power the driving module, thereby maintaining the on state of the high-side NMOS transistor HSN. Of course, when the high-side NMOS transistor HSN needs to be turned off, the principle is the same, which will be described in detail in the following overall working process.

[0037] In a specific implementation, for example, the first diode D1 is a Zener diode, and the first MOS transistor SN2 and the second MOS transistor SN1 are both NMOS transistors. In order to improve the reliability of the driving circuit, this embodiment further provides an anti-reverse circuit.

[0038] See also Figure 3 As shown, the drain of the first MOS transistor SN2 is electrically connected to the VDD power supply through the anti-reverse circuit. In this embodiment, the anti-reverse circuit may include, but is not limited to, an anti-reverse diode. Therefore, the connection structure of the entire anti-reverse circuit is as follows: the positive electrode of the anti-reverse diode is electrically connected to the VDD power supply, and the negative electrode of the anti-reverse diode is electrically connected to the drain of the first MOS transistor SN2. In this way, backflow to VDD when the gate voltage is higher than VDD can be prevented, thereby improving the stability of the circuit during operation.

[0039] After completing the detailed description of the circuit structure of the adaptive power switching module, the following provides a circuit structure of the aforementioned driving module. Figure 3 As shown: In a specific implementation, the driving module may include, but is not limited to: a first driver buf1 and a second driver buf2, wherein the input end of the first driver buf1 is used to receive an external driving signal, the output end of the first driver buf1 is electrically connected to the input end of the second driver buf2, the output end of the second driver buf2 is electrically connected to the gate of the high-side NMOS transistor HSN, and the power supply ends of the first driver buf1 and the second driver buf2 are both electrically connected to the output ends of the first switch unit and the second switch unit (that is, both are electrically connected to the source of the first MOS transistor SN2 and the source of the second MOS transistor SN1); in this way, by supplying power to the two drivers and combining them with the external driving signal (that is, a high-level or low-level signal), the high-side NMOS transistor HSN can be turned on or off.

[0040] Therefore, through the above detailed circuit description of the driving circuit, its overall working principle is as follows: The HSN startup process is described as follows: The first switch generates a reference voltage, VREF = VOUT + VZNR, using a current source in the VDD domain and a first diode D1 in the VOUT domain (VOUT refers to the output voltage of HSN, and VZNR represents the voltage drop across the first diode D1). A high-voltage NMOS device (i.e., first MOS transistor SN2) connected to VDD then generates a VHP voltage. By designing the VREF voltage value, VHP ≈ VOUT + 5V can be ensured (5V refers to the gate-source drive voltage range of the device in a typical integrated circuit process. Of course, the gate-source drive voltage range is not limited to 5V, as the gate-source drive voltage range of devices with different process technologies may also be 3.3V or 15V, etc.; this embodiment uses 5V as an example). The second switch unit comprises an on-chip high-voltage capacitor, a high-voltage NMOS device (second MOS transistor SN1), and an on-chip charge pump. The output of the second MOS transistor SN1 is connected to the power supply terminal of the driver circuit, thereby enabling the charge pump to supply power to the driver module. The initial potential of VOUT is 0V, the initial voltage of the GBT node is VLDO-VDIO (VDIO is the diode forward voltage, i.e., the forward voltage of the second diode D2). The first MOS transistor SN2 is initially in the on state, and the initial potential of VHP is VREF-VGS (the gate-source voltage of the first MOS transistor SN2). By designing the VREF voltage value, the initial state of VHP can be guaranteed to be 5V. At the same time, the initial VGS voltage of the second MOS transistor SN1 (the gate-source voltage of SN1) is approximately equal to VLDO-VDIO-5V. Therefore, as long as the VLDO voltage is kept less than VDIO+5V+VGSN, SN1 can be guaranteed to be initially in the off state. At this time: when the external drive signal controls the gate signal HG of HSN to be high, the power supply of the gate drive buffer is VHP. VHP is powered by the left circuit, and the entire power supply is provided by VDD.

[0041] At this time, the VGS voltage of HSN is 5V, VOUT starts to rise, and at the same time, the voltage of the GBT node also rises with VOUT, and its voltage value is VOUT+VLDO-VDIO. The VGS of SN1 remains unchanged at VLDO-VDIO-5V, SN1 remains off, and the VREF voltage rises with VOUT (that is, the gate voltage of the first MOS tube SN2 rises with the output voltage). The S-terminal voltage of SN2 remains at VREF-VGS, that is, VHP remains at VREF-VGSN, and SN2 remains on. Until VREF=VOUT+5V≈VDD, the VREF voltage The voltage remains at VDD and no longer follows the rise of VOUT. At this time, the circuit on the left cannot complete power supply (that is, the first MOS tube SN2 is cut off), and the gate voltage of SN1 on the right continues to rise with VOUT. The VGS voltage of SN1 gradually increases. When the VOUT voltage rises above VDD+VGSN+VDIO-VLDO (threshold voltage), SN1 starts to turn on, and the power supply of VHP is completed by VCP. The voltage of VHP continues to rise from VDD until VHP=VCP. When the VOUT potential rises to VDD, the VGS of HSN is ≈ 5V, and it remains on with low impedance.

[0042] The HSN shutdown process works as follows: The initial potential of VOUT is VDD, the initial potential of the GBT node is approximately equal to VCP, the initial state of SN2 is closed, the initial potential of VHP is VCP, and the initial state of SN1 is open. At this time: when the external drive signal controls the gate signal HG of HSN to be low, the power supply of the gate drive buf is VHP. The power supply of VHP is completed by the circuit on the right, and all current is supplied by the charge pump. At the same time, the VGS voltage of HSN is 0V, VOUT begins to decrease, and the voltage of the GBT node also decreases with VOUT. When the VOUT voltage drops below VDD-5V, VREF begins to decrease with VOUT. The VHP potential is VDD, and the potential of the GBT node is: VCP-VDD+VOUT≈5V+VOUT. The VGS voltage of SN1 is: 5V+VOUT-VDD≈0. Therefore, the VGS potential of SN1 is ≈0V at this time, and SN1 remains closed until the next time HSN is turned on. When VOUT continues to drop to VDD-5V-VGSN, the VHP potential = VREF-VGSN. SN2 starts to conduct, and the VHP potential is provided by VDD until VOUT reaches 0. VHP is fixed at VZNR-VGSN, and the power tube HSN maintains the VGS=0 state unchanged.

[0043] As can be seen from the operating process above, when the high-side power transistor is turned on or off, the driver circuit is powered by VDD for a long period of time. The built-in charge pump only provides power when VOUT rises or falls to a certain value (such as rising to VDD). Therefore, this embodiment greatly reduces the driving capability requirements of the charge pump and does not require an external CBOOT capacitor to generate high voltage. This reduces the area of ​​the on-chip charge pump and thus reduces chip cost.

[0044] At the same time, since C1 in the driver circuit is not used to generate high voltage and is not directly connected to the driver, it only needs to be connected to the gate of the second MOS transistor SN1. In this way, there is no DC current consumption at the node GBT. Therefore, the voltage of the GBT can be maintained for a relatively long time. Based on this, this circuit architecture can support very low switching frequencies. Even if the GBT cannot maintain voltage for a long time, only a small current source in the VCP domain is needed to replenish the GBT's charge; thus, the problem of traditional switching frequency limitation is solved.

[0045] In addition, this embodiment also provides a working timing diagram of the circuit provided in this embodiment and a voltage waveform diagram of each node, see Figure 4 As shown, from Figure 4 It can be seen that the VHP and VCP voltages switch as the output voltage changes during the driving process. Based on this, it is explained that the drive circuit realizes the function of automatically selecting external VDD power supply or internal charge pump power supply according to the output state of the high-side power tube.

[0046] In one possible design, the second aspect of this embodiment provides a driving device, which includes a load module and the driving circuit of the high-side NMOS tube described in the first aspect of the embodiment, wherein the source of the high-side NMOS tube HSN in the driving circuit of the high-side NMOS tube is electrically connected to the controlled end of the load module, and the ground end of the load module is grounded.

[0047] Among them, for example, the aforementioned load module can be but is not limited to using a motor, that is, the high-side NMOS driver is used to build a half-bridge or full-bridge circuit, and the switching state of the high-side and low-side NMOS is controlled by the PWM signal to adjust the speed and direction of the motor.

[0048] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A driving circuit for a high-side NMOS transistor, characterized in that: include: An adaptive power switching module, the adaptive power switching module comprising a first switch unit and a second switch unit, wherein the output ends of the first switch unit and the second switch unit are both electrically connected to the power supply end of the driving module, the output end of the driving module is electrically connected to the gate of a high-side NMOS transistor (HSN), and the drain of the high-side NMOS transistor (HSN) is electrically connected to a VDD power supply; The power supply end of the first switch unit is electrically connected to a VDD power supply, and the power supply end of the second switch unit is electrically connected to a charge pump, wherein the switch end of the first switch unit is electrically connected to the source of the high-side NMOS transistor (HSN) and the VDD power supply, and the switch end of the second switch unit is electrically connected to the source of the high-side NMOS transistor (HSN) via a bootstrap capacitor (C1); The voltage at the switch end of the first switch unit and the second switch unit rises or falls with the output voltage of the high-side NMOS transistor (HSN), and is used to be turned on or off according to the voltage at the corresponding switch end to turn on the VDD power supply or the charge pump to power the driving module.

2. The driving circuit of a high-side NMOS transistor according to claim 1, characterized in that: The first switch unit includes: a first MOS tube (SN2), wherein the gate of the first MOS tube (SN2) serves as a switch end of the first switch unit and is electrically connected to the source of the high-side NMOS tube (HSN) and the VDD power supply, respectively; the drain of the first MOS tube (SN2) serves as a power supply end of the first switch unit and is electrically connected to the VDD power supply; and the source of the first MOS tube (SN2) serves as an output end of the first switch unit and is electrically connected to the power supply end of the driving module.

3. The driving circuit of a high-side NMOS transistor according to claim 2, characterized in that: The first switch unit further includes: a first diode (D1), wherein the gate of the first MOS tube (SN2) is electrically connected to the cathode of the first diode (D1), the anode of the first diode (D1) is electrically connected to the source of the high-side NMOS tube (HSN), and the first diode (D1) is a Zener diode.

4. The driving circuit of a high-side NMOS transistor according to claim 3, characterized in that: The first switch unit further includes: a current source, wherein an input end of the current source is electrically connected to the VDD power supply, an output end of the current source is electrically connected to the source of the high-side NMOS transistor (HSN) through the first diode (D1), and a common connection end of the current source and the first diode (D1) is electrically connected to the gate of the first MOS transistor (SN2).

5. The driving circuit of a high-side NMOS transistor according to claim 2, characterized in that: It is characterized in that it further comprises: an anti-reverse circuit, wherein the drain of the first MOS tube (SN2) is electrically connected to the VDD power supply through the anti-reverse circuit.

6. The driving circuit of a high-side NMOS transistor according to claim 5, characterized in that: The anti-reverse circuit comprises an anti-reverse diode, wherein the positive electrode of the anti-reverse diode is electrically connected to the VDD power supply, and the negative electrode of the anti-reverse diode is electrically connected to the drain of the first MOS transistor (SN2).

7. The driving circuit of a high-side NMOS transistor according to claim 1, characterized in that: The second switch unit comprises: a second MOS transistor (SN1), wherein the gate of the second MOS transistor (SN1) serves as a switch end of the second switch unit and is electrically connected to a low-voltage power supply and a positive electrode of the bootstrap capacitor (C1), respectively, and the negative electrode of the bootstrap capacitor (C1) is electrically connected to the source of the high-side NMOS transistor (HSN); The drain of the second MOS transistor (SN1) serves as the power supply end of the second switch unit and is electrically connected to the output end of the charge pump, wherein the source of the second MOS transistor (SN1) serves as the output end of the second switch unit and is electrically connected to the power supply end of the drive module, and the input end of the charge pump is electrically connected to the VDD power supply.

8. The driving circuit of a high-side NMOS transistor according to claim 7, characterized in that: The second switch unit further includes: a second diode (D2), wherein the gate of the second MOS tube (SN1) is electrically connected to the cathode of the second diode (D2), and the anode of the second diode (D2) is electrically connected to the low-voltage power supply.

9. The driving circuit of a high-side NMOS transistor according to claim 1, characterized in that: The driving module includes: a first driver and a second driver, wherein the input end of the first driver is used to receive an external driving signal, the output end of the first driver is electrically connected to the input end of the second driver, the output end of the second driver is electrically connected to the gate of the high-side NMOS transistor (HSN), and the power supply ends of the first driver and the second driver are both electrically connected to the output ends of the first switch unit and the second switch unit.

10. A driving device, characterized in that: include: A load module and a driving circuit for a high-side NMOS transistor according to any one of claims 1 to 9, wherein the source of the high-side NMOS transistor (HSN) in the driving circuit for the high-side NMOS transistor is electrically connected to the controlled end of the load module, and the ground end of the load module is grounded.

Images