Parallel buffer compensation circuit for rectifier and parameter design method thereof

Abstract

The invention provides a parallel buffer compensation circuit for a rectifier and a parameter design method thereof, the parallel buffer compensation circuit comprises a series branch, the series branch comprises a buffer capacitor and a buffer resistor which are connected in parallel with a diode, and the diode, the buffer capacitor and the buffer resistor which are connected in parallel with the diode form a series unit which is connected in series with the rectifier. The number of the series connection units is n, the buffer parameter selection design method has the advantages that distributed capacitance of nodes between series units to a high-voltage end and a ground end, leakage inductance of an external circuit and a reverse square wave power supply with a high dv / dt step are mainly considered, and the buffer parameter selection design method not only meets the requirement for preventing diode triggering mistaken conduction, but also meets the requirement for high-voltage power supply and high-dv / dt step reverse square wave power supply. The method also comprises limitation for suppressing voltage unbalance of the diode; according to the invention, extra switching loss of the diode is reduced, overvoltage damage of the diode caused by uneven voltage is avoided, the service life of the diode is prolonged, and power consumption and device cost are reduced for safe and stable operation of a rectifier system.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a parallel buffer compensation circuit for a rectifier and a parameter design method thereof. Background Art

[0002] High-voltage uncontrolled rectifiers are a key component of high-voltage DC power supplies. Due to the limited high-voltage rating of the power supply, rectifiers typically require multiple low-voltage diodes connected in series to create a near-equivalent high-voltage diode to achieve the desired rectification. In practice, discrete diodes connected in series have found widespread application in lightweight, miniaturized converters with output voltages in the tens of kilovolts, such as electrostatic precipitators and portable X-ray machines.

[0003] However, the series connection of diodes also has its limitations. The series system is discrete and never a whole, which means that there are always differences between individual diodes. During switching, the leakage inductance in the system line and the distributed capacitance of the diode series node to the high voltage end and the ground end will produce extremely high voltage peaks and oscillations on the diode voltage, resulting in uneven voltage distribution and additional switching losses during the on-off state, and even damage to the diode. Especially in the scenario of high dv / dt square wave or step wave excitation, the charging and discharging of the distributed capacitance causes the diode node voltage to change dramatically, which in turn leads to diode voltage imbalance and triggering misconduction. These problems affect the energy utilization and reliability of the entire system.

[0004] To ensure safe and stable rectifier operation, compensation technology must address two issues: diode voltage imbalance and misdirected diode conduction during square-wave step events. A typical approach to achieving this is to connect a resistor-capacitor circuit in parallel across the diode. However, the distributed capacitance at the node where the diode connects can cause voltage oscillations and even generate adverse coupling with improperly designed resistor-capacitor snubber circuits, especially during high dv / dt square-wave step events, leading to these two issues.

[0005] Currently, there are two common methods for designing parallel RC snubber circuits. The first method uses parallel RC circuits with non-equal parameters. However, for applications with a large number of diodes in series, the step of calculating the parameters of each RC group individually significantly increases the workload and makes system design more cumbersome. The second method uses parallel RC circuits with equal parameters. This method is simple, convenient, and cost-effective, but the derivation of RC parameters under the influence of distributed capacitance is oversimplified, especially ignoring the square wave step application scenario. The resulting relationship and design parameters have limitations and loopholes in practical applications. Both methods lack practicality in engineering applications. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a parallel buffer compensation circuit for a rectifier and a parameter design method thereof, which are used to solve the problems of voltage imbalance and reverse step misconduction existing in the series connection of multiple discrete diodes in the field of high-voltage power supply.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides the following technical solutions: A parallel buffer compensation circuit for a rectifier includes a series branch connected in parallel at both ends of a diode, the series branch including a buffer capacitor and a buffer resistor connected in parallel with the diode, the cathode of the diode connected to the anode of the buffer capacitor, the cathode of the buffer capacitor connected to one end of the buffer resistor, and the other end of the buffer resistor connected to the anode of the diode, the diode, the buffer capacitor connected in parallel with the diode, and the buffer resistor forming a series unit connected in series with the rectifier, wherein the series unit is n groups, wherein: .

[0008] In one embodiment of the present invention, the rectifier includes a DC power supply and an inductor connected in series with the DC power supply, the positive electrode of the DC power supply is connected to one end of the inductor, and the negative electrode of the DC power supply and the other end of the inductor are connected in series with n groups of series units.

[0009] In one embodiment of the present invention, The diodes in the series units are connected in series in sequence, and the cathode of the diode at the head end is also connected to the other end of the inductor, and the anode of the diode at the tail end is also connected to the negative electrode of the DC power supply.

[0010] In one embodiment of the present invention, the rectifier further includes n-1 distributed capacitors connected in series with the diode node to the high-voltage end, the positive electrodes of the n-1 distributed capacitors to the high-voltage end are all connected to the other end of the inductor, and the negative electrodes of the n-1 distributed capacitors to the high-voltage end are all connected to the wire between two adjacent diodes.

[0011] In one embodiment of the present invention, the rectifier further includes n-1 distributed capacitors connected in series with the diode nodes to the ground end, the positive electrodes of the n-1 distributed capacitors to the ground end are all connected to the wire between two adjacent diodes, and the negative electrodes of the n-1 distributed capacitors to the ground end are all connected to the negative electrode of the DC power supply and grounded.

[0012] A parameter design method for a parallel buffer compensation circuit for a rectifier, based on the parallel buffer compensation circuit for a rectifier, comprises the following steps: S1, determining the number of groups of series units , circuit parameter inductance, distributed capacitance and power supply characteristics; S2, assigning an initial value to the buffer resistor; S3, assigning an initial value to the buffer capacitor; S4, calculating constraint condition 1, and determining whether the initial value of the buffer capacitor satisfies constraint condition 1. If not, jump to S3 and adjust the assignment of the buffer capacitor until constraint condition 1 is satisfied; S5. Calculate constraint 2 and continue to determine whether the value assigned to the buffer capacitor at this time satisfies constraint 2. If not, jump to S3 and continue adjusting the value assigned to the buffer capacitor until constraint 2 is satisfied. S6. Calculate the voltage imbalance and determine whether the voltage imbalance is less than a minimum value. If not, jump to S2 and adjust the value assigned to the buffer resistor until the voltage imbalance is less than the minimum value. S7. Output the value range of the buffer resistor and the buffer capacitor that achieves a smaller voltage imbalance.

[0013] In one embodiment of the present invention, the formula of the constraint condition 1 is: ;in, represents the diode voltage, which can also be equivalent to the maximum diode voltage for the constraint condition 1.

[0014] In one embodiment of the present invention, the diode voltage is obtained according to the following formula: : ; ; Wherein, the buffer resistor is R, the buffer capacitor is C, 、 、 and Represents a combination of parameters, 、 、 and Both represent coefficient matrices, L represents system leakage inductance, represents the power supply excitation, and Represent the distributed capacitance to the high voltage end and to the ground end respectively.

[0015] In one embodiment of the present invention, the formula for the constraint condition 2 is: ;in, Indicates the first diode voltage at the high voltage end, It is the minimum value used to measure the voltage balance.

[0016] In one embodiment of the present invention, the voltage imbalance is calculated according to the following formula: ;in, is the voltage imbalance.

[0017] As described above, the parallel buffer compensation circuit for a rectifier and the parameter design method thereof of the present invention have the following beneficial effects: 1. Compared with related technologies in the field, the present invention simultaneously considers distributed capacitance, line leakage inductance, and square wave power supply excitation, can accurately select and design the parameters of the buffer compensation circuit, improve the switching efficiency of the diode device, and is not limited to the type of diode, making the application scenarios of the present invention more extensive; 2. The RC buffer compensation circuit method proposed in this invention includes the overall relationship between the components and parameters of the entire system. The selected values ​​effectively solve the problems of misconduction and voltage imbalance caused by square wave power step on the diode, reduce diode loss, and extend the service life of the diode; 3. The present invention solves the cost problem of related technologies that use non-equal resistance and capacitance parameters and ignore the large-scale series connection of diodes, thereby improving the work efficiency of engineering technology applications. It has a simple principle, convenient operation, low cost, and meets user requirements. In summary, the present invention focuses on the distributed capacitance of the nodes between the series units to the high-voltage end and the ground end, the leakage inductance of the external circuit, and the reverse square wave power supply with high dv / dt steps. The proposed buffer parameter selection design method not only includes the requirement of preventing the diode from being triggered and mis-conducted, but also includes the restriction of suppressing the voltage imbalance of the diode; it reduces the additional switching loss of the diode, avoids the overvoltage damage of the diode caused by voltage unevenness, and at the same time increases the working life of the diode, reduces the power consumption and device cost for the safe and stable operation of the rectifier system, and improves the overall reliability of the power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A circuit diagram of a rectifier in a parallel buffer compensation circuit with series diodes disclosed in an embodiment of the present invention; Figure 2 Schematic diagram of an equivalent circuit of a rectifier in a parallel buffer compensation circuit with series diodes disclosed in an embodiment of the present invention; Figure 3 Schematic diagram of the overall flow of a parameter design method for a parallel buffer compensation circuit for a rectifier disclosed in an embodiment of the present invention; Figure 4 Schematic diagram of a step voltage waveform obtained without adopting the parameter design method of the parallel buffer compensation circuit for a rectifier disclosed in an embodiment of the present invention; Figure 5 Schematic diagram of a step voltage waveform obtained by adopting the parameter design method of the parallel buffer compensation circuit for a rectifier disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless there is a conflict.

[0020] The first embodiment of the present invention relates to a parallel buffer compensation circuit for a rectifier, such as Figure 1 As shown, it includes a series branch connected in parallel at both ends of the diode, the series branch includes a snubber capacitor C and a snubber resistor R connected in parallel with the diode D, the cathode of the diode D is connected to the anode of the snubber capacitor C, the negative electrode of the snubber capacitor C is connected to one end of the snubber resistor R, and the other end of the snubber resistor R is connected to the anode of the diode D. The diode D, the snubber capacitor C connected in parallel with the diode D, and the snubber resistor R constitute a series unit connected in series with the rectifier. There are n series units, wherein, .

[0021] Rectifier includes DC power supply and DC power supply Series inductor L, DC power supply The positive electrode is connected to one end of the inductor L, and the DC power supply n groups of series units are connected in series between the negative electrode of and the other end of the inductor L; The diodes D in the series units are connected in series in sequence, and the cathode of the diode D at the head end is also connected to the other end of the inductor L, and the anode of the diode D at the tail end is also connected to the DC power supply. negative connection.

[0022] The rectifier also includes n-1 diodes D connected in series with the distributed capacitance of the high voltage terminal. , n-1 distributed capacitances on the high voltage side The positive poles are connected to the other end of the inductor L, and n-1 distributed capacitors on the high voltage end The negative electrodes of the diodes are connected to the wires between two adjacent diodes D; the rectifier also includes n-1 diodes D in series with the distributed capacitance of the node to the ground. , n-1 distributed capacitances to ground The positive electrodes are connected to the wires between two adjacent diodes D, and the n-1 distributed capacitances to the ground are The negative poles of the DC power supply Connect the negative terminal of the power cord to ground.

[0023] Specifically, if Figure 1 As shown, the power supply part includes a DC power supply capable of providing a step wave and series inductance L, to achieve high dv / dt step excitation for the series system; distributed capacitance includes the distributed capacitance of the diode series node to the high voltage end and the distributed capacitance to ground , which is the key factor causing misconduction and voltage imbalance in diode D, is therefore used as an important parameter to derive the design method of a diode parallel snubber compensation circuit. The snubber compensation circuit includes a series branch consisting of a snubber capacitor C and a snubber resistor R, which are connected in parallel across diode D to suppress misconduction and voltage imbalance, ensuring safe and stable operation of the system with low power consumption. Among them, the n diodes of the series discrete diode devices from the high voltage end to the ground end are numbered D1, D2, ... D n The diode D in the embodiment described is a common high-voltage silicon diode but is not limited to a common high-voltage silicon diode, so it has a wider range of practicality; and the distributed capacitance of each node of the diode D in series to the high-voltage end Assuming that they are approximately equal, the distributed capacitance to the ground It is considered to be approximately equal, which has no effect on the derived design method of the parallel snubber compensation circuit parameters; and the parallel snubber compensation circuit adopts a design method of equal parameter resistance and capacitance, which avoids the tedious process of separately calculating the parameters of each group of parallel snubber compensation circuits with a large number of diodes on a large scale.

[0024] The second embodiment of the present invention relates to a parameter design method for a parallel buffer compensation circuit of a rectifier, the process is as follows: Figure 3 As shown, the details are as follows: S1. Determine the number of series units , Circuit parameters inductance L, distributed capacitance and and power supply characteristics.

[0025] S2. Assign an initial value to the buffer resistor R.

[0026] S3. Assign an initial value to the buffer capacitor C.

[0027] S4. Calculate constraint 1, and based on constraint 1: If the constraint condition 1 is not met, jump to S3 and increase the value of the buffer capacitor C.

[0028] Specifically, Represents the diode voltage. For constraint condition 1, it can also be equivalent to the maximum diode voltage. The diode voltage It can be obtained by the following formula: ; ;in, 、 、 and Represents a combination of parameters, 、 、 and Both represent coefficient matrices, L represents system leakage inductance, represents the power supply excitation, and Represents the distributed capacitance to the high voltage end and to the ground end respectively; and also describes the diode voltage The formula belongs to the s-domain. To obtain the (maximum) voltage, an inverse transformation to the time domain is required, which can be solved with the help of software.

[0029] S5. Calculate constraint 2, and based on constraint 2: If the constraint condition 2 is not met, jump to S3 and increase the value of the buffer capacitor C.

[0030] Specifically, Represents the voltage of the first diode D at the high voltage end, It is the minimum value used to measure the voltage balance. A preset constant with a relatively small value.

[0031] S6. Calculation , and compare Value and The size of the value, if If it is larger, jump to S2 and increase the value of the buffer resistor R.

[0032] S7, output realization Smaller value range of snubber resistor R and snubber capacitor C.

[0033] Further, according to Figure 2 , use the node current method to calculate the node i Write the KCL equation; (1); Then there are boundary conditions for the high-voltage node ac and node n: (2); Furthermore, we can write the KCL equations for other nodes and construct the node equation group in matrix form: (3); among them, is a 1*(n-1) all-one vector, A and B are both (n-1)*(n) order matrices, representing coefficient matrices; Furthermore, the matrix equation is Laplace transformed and simplified to obtain the s-domain node voltage expression: (4); among them, , D(s), E(s), d 0 (s) and f 0 (s)is the parameter matrix of the solution, d 0 (s) and f 0 (s) The initial condition matrix representing the Laplace transform process of the equation is defined as follows: (5); among them, Represents a combination of parameters, 、 、 and Both represent coefficient matrices; Furthermore, to address the issues of misconduction and voltage imbalance, the following restrictions are imposed: (7); where the definition Indicates voltage imbalance, definition It is the minimum value used to measure the voltage balance; With reference to the above derivation, the parameter design process of the parallel snubber compensation circuit with series diodes under restricted conditions can be realized, such as Figure 3 As shown: Clearly define the number of diodes in series, circuit parameters inductance L, distributed capacitance and As well as the power supply characteristics, assign initial values ​​to the snubber resistor R and the snubber capacitor C, calculate the (maximum) voltage of the diode according to formula (6), and determine whether Otherwise, increase the value of the buffer capacitor C and determine whether Otherwise, increase the value of the buffer capacitor C and calculate the voltage imbalance of the resistance and capacitance parameters that meet the constraint conditions. , select the smaller Otherwise, increase the value of the buffer resistor R and repeat the above process to obtain the range of resistance and capacitance parameters.

[0034] Figure 4 FIG. 1 is a schematic diagram of a diode voltage waveform during a step-down period of an external reverse square wave power supply obtained without adopting the parameter design method for a parallel buffer compensation circuit for a rectifier of the present invention. Figure 4 It can be seen that the maximum peak voltage difference reaches 325V, and the voltage imbalance is It reaches 0.86, and at the same time, the first diode at the high-voltage end is turned on; Figure 5 Schematic diagram of the diode voltage waveform during the step-down period of an external reverse square wave power supply obtained by using the parameter design method of the parallel buffer compensation circuit for a rectifier of the present invention. Figure 5 It can be seen that the maximum peak voltage difference is only 7V, and the voltage imbalance is A value of 0.04 can be achieved without any diode conduction. The simulation and experimental results of this embodiment fully demonstrate the effectiveness of the proposed parameter design method for the parallel snubber compensation circuit. The selected values ​​effectively address the issues of misconduction and voltage imbalance caused by square-wave power supply steps, reducing diode losses and extending diode service life. This method can be used in system design for large-scale series diodes.

[0035] It should be noted that when designing the parameters of the parallel snubber compensation circuit, its operating principle is as follows: Under ideal conditions, the series diode device will maintain a voltage-equalizing blocking state despite an external reverse power supply excitation step. However, due to the presence of distributed capacitance, when a power supply step occurs, a portion of the charge in the series circuit flows through the distributed capacitance. At the same time, the voltage across the capacitor cannot change suddenly, resulting in a difference in the potential changes between the positive and negative poles of the diode, which can cause diode oscillation, misconduction, and voltage imbalance. The parallel RC snubber compensation circuit will increase the charge flow path during the power supply step, offsetting the influence of the charge flowing through the distributed capacitance, thereby ensuring the normal operation of the series diode.

[0036] In summary, the present invention aims to improve and solve the technical problems of voltage imbalance and reverse step misconduction existing in the series connection of multiple discrete diodes in the field of high-voltage power supply. Therefore, the distributed capacitance of the nodes between the series units to the high-voltage end and the ground end, the leakage inductance of the external circuit, and the reverse square wave power supply with high dv / dt step are mainly considered. A buffer compensation circuit and its parameter design method are proposed to ensure the safe and stable operation of the diode series rectifier with low cost and low power consumption. The circuit not only includes the requirement of preventing the diode from being triggered and misconducted, but also includes the restriction of suppressing the voltage imbalance of the diode; the additional switching loss of the diode is reduced, the overvoltage damage of the diode caused by voltage unevenness is avoided, and the working life of the diode is increased. The safe and stable operation of the rectifier system is reduced in power consumption and device cost, and the overall reliability of the power supply is improved.

[0037] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any equivalent modifications or variations made by persons skilled in the art without departing from the spirit and technical concepts disclosed herein shall be encompassed by the claims of the present invention.

Claims

1. A parallel buffer compensation circuit for a rectifier, characterized in that: The invention comprises a series branch connected in parallel at both ends of a diode, wherein the series branch comprises a buffer capacitor and a buffer resistor connected in parallel with the diode, the cathode of the diode is connected to the anode of the buffer capacitor, the cathode of the buffer capacitor is connected to one end of the buffer resistor, and the other end of the buffer resistor is connected to the anode of the diode, and the diode, the buffer capacitor and the buffer resistor connected in parallel with the diode constitute a series unit connected in series with a rectifier, and the series unit is n groups, wherein: .

2. The parallel buffer compensation circuit for a rectifier according to claim 1, characterized in that: The rectifier includes a DC power supply and an inductor connected in series with the DC power supply. The positive electrode of the DC power supply is connected to one end of the inductor, and n groups of series units are connected in series between the negative electrode of the DC power supply and the other end of the inductor.

3. The parallel buffer compensation circuit for a rectifier according to claim 2, characterized in that: The diodes in the series units are connected in series in sequence, and the cathode of the diode at the head end is also connected to the other end of the inductor, and the anode of the diode at the tail end is also connected to the negative electrode of the DC power supply.

4. The parallel buffer compensation circuit for a rectifier according to claim 2, wherein: The rectifier also includes n-1 diodes connected in series at the distributed capacitors of the high-voltage end, the positive electrodes of the n-1 distributed capacitors of the high-voltage end are all connected to the other end of the inductor, and the negative electrodes of the n-1 distributed capacitors of the high-voltage end are all connected to the wire between two adjacent diodes.

5. The parallel buffer compensation circuit for a rectifier according to claim 2, characterized in that: The rectifier also includes n-1 distributed capacitors connected in series with the diode nodes to the ground end, the positive electrodes of the n-1 distributed capacitors to the ground end are all connected to the wire between two adjacent diodes, and the negative electrodes of the n-1 distributed capacitors to the ground end are all connected to the negative electrode of the DC power supply and grounded.

6. A parameter design method for a parallel buffer compensation circuit for a rectifier, characterized by: The parallel buffer compensation circuit for a rectifier according to any one of claims 1 to 5 comprises the following steps: S1. Determine the number of series units , circuit parameters inductance, distributed capacitance and power supply characteristics; S2, assign initial value to buffer resistor; S3, assign initial value to buffer capacitor; S4, calculating constraint condition 1, and determining whether the initial value of the buffer capacitor satisfies constraint condition 1. If not, jump to S3 and adjust the value of the buffer capacitor until constraint condition 1 is satisfied. S5, calculate constraint condition 2, and continue to determine whether the value assigned to the buffer capacitor at this time satisfies constraint condition 2. If not, jump to S3 and continue to adjust the value assigned to the buffer capacitor until constraint condition 2 is satisfied. S6. Calculate the voltage imbalance and determine whether the voltage imbalance is less than a minimum value. If not, jump to S2 and adjust the value of the buffer resistor until the voltage imbalance is adjusted to be less than the minimum value. S7. The value range of the buffer resistor and the buffer capacitor to achieve a smaller voltage imbalance at the output.

7. The parameter design method for a parallel buffer compensation circuit for a rectifier according to claim 6, characterized in that: The formula of the restriction condition 1 is: ;in, represents the diode voltage, which can also be equivalent to the maximum diode voltage for the constraint condition 1.

8. The parameter design method for a parallel buffer compensation circuit for a rectifier according to claim 7, characterized in that: The diode voltage is obtained according to the following formula : ； ； Among them, the buffer resistor is R, the buffer capacitor is C, 、 、 and Represents a combination of parameters, 、 、 and Both represent coefficient matrices, L represents system leakage inductance, represents the power supply excitation, and Represent the distributed capacitance to the high voltage end and to the ground end respectively.

9. The parameter design method for a parallel buffer compensation circuit for a rectifier according to claim 6, characterized in that: The formula of the constraint condition 2 is: ;in, Indicates the first diode voltage at the high voltage end, It is the minimum value used to measure the voltage balance.

10. The parameter design method for a parallel buffer compensation circuit for a rectifier according to claim 6, characterized in that: Calculate the voltage unbalance according to the following formula: ;in, is the voltage imbalance.

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