Parallel buffer compensation circuit for rectifier and parameter design method thereof

Abstract

The application provides a parallel buffer compensation circuit for a rectifier and a parameter design method thereof, comprising a series branch, the series branch comprising a buffer capacitor and a buffer resistor in parallel with a diode, the diode, the buffer capacitor and the buffer resistor in parallel with the diode constituting a series unit in series with the rectifier, and the series unit being n groups, wherein, the application has the following beneficial effects: the application focuses on the node-to-high-voltage-end and node-to-ground-end distributed capacitance between the series units, external circuit leakage inductance and a reverse square wave power supply with high dv / dt steps, the buffer parameter selection design method proposed not only contains the requirement of preventing the diode from triggering misdirecting, but also contains the limitation of inhibiting the voltage imbalance of the diode; the additional switching loss of the diode is reduced, the overvoltage damage of the diode caused by the voltage imbalance is avoided, the working life of the diode is increased, the power consumption and the device cost of the safe and stable operation of the rectifier system are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit technology, in particular to a parallel buffer compensation circuit for rectifiers and a parameter design method thereof. BACKGROUND

[0002] High-voltage uncontrolled rectifiers are key components of high-voltage DC power supplies. Due to the limitation of the high-voltage level of the power supply, the rectifier generally needs to be connected in series with multiple low-voltage diodes to approximate a high-voltage diode to complete the rectification work. In fact, series discrete diodes have been widely used, such as electrostatic precipitators and portable X-ray machines, and other lightweight and small-sized converters with output voltages of tens of kilovolts.

[0003] However, diode series also has its limitations, because the series system is discrete and will never be a whole, which means that there is always a difference between individual diodes. During the switching conversion, the leakage inductance existing in the system line and the distributed capacitance of the diode series node to the high-voltage end and to the ground end will have a very high voltage peak and oscillation effect on the diode voltage, resulting in uneven voltage distribution and additional switching loss during the on-off change state, and even damaging the diode. Especially for high dv / dt square wave or step wave excitation scenarios, the charging and discharging of the distributed capacitance will cause the diode node voltage to change dramatically, which in turn leads to diode voltage imbalance and trigger mis-conduction. These problems affect the energy utilization and reliability of the entire system.

[0004] In order to ensure the safe and stable operation of the rectifier, the compensation technology needs to solve two problems, one is the diode voltage imbalance problem, and the other is the diode mis-conduction problem under square wave step. The parallel blocking-capacitor circuit connected across the diode is a typical method to achieve buffering. However, the distributed capacitance existing at the node connected to the diode will cause voltage oscillation, and even will produce vicious coupling with the blocking-capacitor buffer circuit with improper parameter design, especially at the moment of high dv / dt square wave step, resulting in the above two problems.

[0005] There are two common methods for parallel blocking-capacitor buffer circuits at present, one is to derive the method of using parallel non-equal parameter blocking-capacitor circuits, but for a large number of diode series applications, the step of calculating each set of blocking-capacitor parameters separately greatly increases the work intensity, making the system design more cumbersome. The second is to use the method of parallel equal parameter blocking-capacitor circuits, which is simple, convenient and cost-saving, but the derivation process of the blocking-capacitor parameters under the influence of the distributed capacitance is too simplified, especially the square wave step application scenario is ignored, and the derived relationship and design parameters have limitations and loopholes in actual application. Both methods lack practicality in engineering application. SUMMARY

[0006] In view of the above-mentioned defects of the prior art, the purpose of the present application is to provide a parallel buffer compensation circuit for a rectifier and a parameter design method thereof, which are used to solve the problems of voltage imbalance and reverse step misdirecting on of a plurality of discrete diodes in series in the field of high-voltage power supply.

[0007] To achieve the above object and other related objects, the present application provides the following technical solutions.

[0008] A parallel buffer compensation circuit for a rectifier comprises a series branch connected in parallel with a diode, the series branch comprising a buffer capacitor and a buffer resistor connected in parallel with the diode, the negative electrode of the diode being connected with the positive electrode of the buffer capacitor, the negative electrode of the buffer capacitor being connected with one end of the buffer resistor, the other end of the buffer resistor being connected with the positive electrode of the diode, the diode, the buffer capacitor and the buffer resistor connected in parallel with the diode constituting a series unit connected in series with the rectifier, the series unit being n groups, wherein, .

[0009] In an embodiment of the present application, the rectifier comprises a direct-current power supply and an inductor connected in series with the direct-current power supply, the positive electrode of the direct-current power supply being connected with one end of the inductor, and the negative electrode of the direct-current power supply being connected with the other end of the inductor in series with the n groups of series units.

[0010] In an embodiment of the present application, The diodes in the series units are connected in series in turn, the negative electrode of the diode at the head end being further connected with the other end of the inductor, and the positive electrode of the diode at the tail end being further connected with the negative electrode of the direct-current power supply.

[0011] In an embodiment of the present application, the rectifier further comprises n-1 distribution capacitors connected with the high-voltage end, the positive electrodes of the n-1 distribution capacitors being all connected with the other end of the inductor, and the negative electrodes of the n-1 distribution capacitors being all connected on the conductor between two adjacent diodes.

[0012] In an embodiment of the present application, the rectifier further comprises n-1 distribution capacitors connected with the ground end, the positive electrodes of the n-1 distribution capacitors being all connected on the conductor between two adjacent diodes, and the negative electrodes of the n-1 distribution capacitors being all connected with the negative electrode of the direct-current power supply and grounded.

[0013] A parameter design method of a parallel buffer compensation circuit for a rectifier, based on the parallel buffer compensation circuit for a rectifier, comprises the following steps: S1, determining the number of groups of series units , circuit parameters inductance, distributed capacitance and power supply characteristics; S2, assigning initial value to the buffer resistance; S3, assigning initial value to the buffer capacitance; S4, calculating the restriction condition 1, and judging whether the initial value of the buffer capacitance satisfies the restriction condition 1, if not, jumping to S3 and adjusting the assignment of the buffer capacitance until the restriction condition 1 is satisfied;

[0014] S5, calculating the restriction condition 2, and continuously judging whether the assignment of the buffer capacitance satisfies the restriction condition 2, if not, jumping to S3 and continuously adjusting the assignment of the buffer capacitance until the restriction condition 2 is satisfied; S6, calculating the voltage unbalance degree, and judging whether the voltage unbalance degree is less than the minimum value, if not, jumping to S2 and adjusting the assignment of the buffer resistance until the voltage unbalance degree is less than the minimum value; S7, outputting the value range of the buffer resistance and the buffer capacitance which realize smaller voltage unbalance degree.

[0015] In an embodiment of the present application, the formula of the restriction condition 1 is: ; wherein, represents the diode voltage, and for the restriction condition 1, it can be equivalent to the maximum voltage of the diode.

[0016] In an embodiment of the present application, the diode voltage is obtained according to the following formula: ; ; wherein, the buffer resistance is R, the buffer capacitance is C, 、 、 and represent parameter combinations, 、 、 and all represent coefficient matrices, L represents system leakage inductance, represents power supply excitation, and respectively represent the distributed capacitance of the high-voltage end and the ground end.

[0017] In an embodiment of the present application, the formula of the restriction condition 2 is: ; wherein, represents the first diode voltage of the high-voltage end, is the minimum value for measuring the voltage balance degree.

[0018] In an embodiment of the present application, the voltage unbalance degree is calculated according to the following formula: ; wherein, is the voltage unbalance degree.​

[0019] As described above, the parallel buffer compensation circuit for the rectifier and the parameter design method thereof have the following beneficial effects:

[0020] 1. Compared with the related art, the present application considers the distributed capacitance, line leakage inductance and square wave power excitation, and can accurately select and design the buffer compensation circuit parameters, improve the switching efficiency of the diode device, is not limited to the diode type, and makes the application scenarios of the present application more extensive.

[0021] 2. The resistance-capacitance buffer compensation circuit method includes the overall relationship of the entire system device and parameters, and the selected value actually solves the mis-conduction and voltage imbalance problem of the diode caused by the square wave power step, reduces the diode loss, and prolongs the service life of the diode.

[0022] 3. The present application solves the cost problem of the related art that adopts non-equal resistance-capacitance parameters and ignores the large-scale diode series connection, improves the work efficiency of engineering technology application, has simple principle, convenient operation and low cost, and meets the user requirements.

[0023] In summary, the present application focuses on the node between the series units, the distributed capacitance of the high-voltage end and the ground end, the external circuit leakage inductance and the reverse square wave power of the high dv / dt step, the proposed buffer parameter selection and design method not only includes the requirement of preventing the diode from triggering mis-conduction, but also includes the limitation of suppressing the voltage imbalance of the diode; reduces the additional switching loss of the diode, avoids the overvoltage damage of the diode caused by the voltage imbalance, prolongs the service life of the diode, reduces the power consumption and device cost for the safe and stable operation of the rectifier system, and improves the reliability of the power supply as a whole. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a circuit schematic diagram of the rectifier of the series diode parallel buffer compensation circuit disclosed in the embodiment of the present application.

[0025] Figure 2 It is an equivalent circuit schematic diagram of the rectifier of the series diode parallel buffer compensation circuit disclosed in the embodiment of the present application.

[0026] Figure 3 It is a whole flowchart of the parameter design method of the parallel buffer compensation circuit for the rectifier disclosed in the embodiment of the present application.

[0027] Figure 4 It is a step voltage waveform schematic diagram obtained without using the parameter design method of the parallel buffer compensation circuit for the rectifier disclosed in the embodiment of the present application.

[0028] Figure 5A schematic diagram of a step voltage waveform obtained by using the parameter design method of the parallel buffer compensation circuit for the rectifier of the present application is shown in the embodiments of the present application. DETAILED DESCRIPTION

[0029] The advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of the present specification. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0030] The first embodiment of the present application relates to a parallel buffer compensation circuit for a rectifier, as shown in Figure 1 including a series branch connected in parallel with a diode, the series branch including a buffer capacitor C and a buffer resistor R connected in parallel with the diode D, the negative electrode of the diode D being connected to the positive electrode of the buffer capacitor C, the negative electrode of the buffer capacitor C being connected to one end of the buffer resistor R, the other end of the buffer resistor R being connected to the positive electrode of the diode D, the diode D, the buffer capacitor C and the buffer resistor R connected in parallel with the diode D forming a series unit connected in series with the rectifier, the series unit being n groups, wherein, .

[0031] The rectifier includes a direct current power supply and an inductor L connected in series with the direct current power supply , the positive electrode of the direct current power supply being connected to one end of the inductor L, the negative electrode of the direct current power supply being connected to the other end of the inductor L, and the n groups of series units being connected in series therebetween. The diodes D in the n groups of series units are connected in series in turn, and the negative electrode of the diode D at the head end is also connected to the other end of the inductor L, and the positive electrode of the diode D at the tail end is also connected to the negative electrode of the direct current power supply .

[0032] The rectifier further includes n-1 distribution capacitors connected in parallel with the high voltage end of the diode D series node, the positive electrodes of the n-1 distribution capacitors connected in parallel with the high voltage end are all connected to the other end of the inductor L, and the negative electrodes of the n-1 distribution capacitors connected in parallel with the high voltage end are all connected to the conductive wire between two adjacent diodes D; the rectifier further includes n-1 distribution capacitors connected in parallel with the ground end of the diode D series node, the positive electrodes of the n-1 distribution capacitors connected in parallel with the ground end are all connected to the conductive wire between two adjacent diodes D, and the negative electrodes of the n-1 distribution capacitors connected in parallel with the ground end are all connected to the negative electrode of the direct current power supply and grounded.

[0033] Specifically, as shown inFigure 1 As shown in the figure, the power supply part includes a direct current power supply capable of providing a staircase wave and a series inductance L to realize a high dv / dt step excitation for the series system; the distributed capacitance includes a distributed capacitance of the diode series node pair high voltage end and a distributed capacitance of the ground end , which is a key factor causing the mis-conduction of the diode D and the voltage imbalance, and thus is used as an important parameter for deriving the design method of the parallel buffer compensation circuit of the diode; the buffer compensation circuit includes a series branch composed of a buffer capacitance C and a buffer resistance R, which is connected in parallel across the diode D to suppress the mis-conduction and voltage imbalance problem, ensure the safe and stable operation of the system, and realize low-power operation;

[0034] wherein the series discrete diode devices are numbered D1, D2, … Dn from the high voltage end to the ground end n The diode D in the described embodiment is a general high-voltage silicon diode but is not limited to a general high-voltage silicon diode, and thus has more extensive practicability; the diode D is also connected in series with the distributed capacitance of each node pair high voltage end which is considered to be approximately equal, and the distributed capacitance of the ground end which is considered to be approximately equal, and has no effect on the parameter design method of the derived parallel buffer compensation circuit; in addition, the parallel buffer compensation circuit adopts the design method of equal parameter resistance and capacitance, which avoids the cumbersome process of separately calculating and taking values of the parameters of each group of parallel buffer compensation circuits of a large number of diodes.

[0035] The second embodiment of the present application relates to a parameter design method of a parallel buffer compensation circuit for a rectifier, and the flow is as shown in the figure Figure 3 , and the details are as follows:

[0036] S1, determine the number of series units , circuit parameters inductance L, distributed capacitance and , and power supply characteristics.

[0037] S2, assign an initial value to the buffer resistance R.

[0038] S3, assign an initial value to the buffer capacitance C.

[0039] S4, calculate the limit condition 1, and according to the limit condition 1: , if the limit condition 1 is not met, jump to S3 and increase the assigned value of the buffer capacitance C.

[0040] Specifically, wherein, represents the diode voltage, and for the limit condition 1, the diode voltage can also be equivalent to the maximum voltage of the diode, and the diode voltage can be obtained by the following formula: ; ; wherein, 、 、 and denote parameter combinations, 、 、 and denote coefficient matrices, L denotes the system leakage inductance, denotes the power excitation, and denote the distributed capacitances to the high-voltage terminal and to ground, respectively; and the formula describing the diode voltage is in the s domain, and obtaining the (maximum) voltage requires an inverse transformation into the time domain, which can be solved with the aid of software.

[0041] S5, calculate the limit condition 2, and according to the limit condition 2: , if the limit condition 2 is not met, jump to S3 and increase the assignment of the buffer capacitor C.

[0042] Specifically, wherein, denotes the first diode D voltage of the high-voltage terminal, is a minimum value used to measure the voltage balance degree, is a small constant value set in advance.

[0043] S6, calculate , and compare the value of with the value of , if is larger, jump to S2 and increase the assignment of the buffer resistor R.

[0044] S7, output the value range of the buffer resistor R and the buffer capacitor C that realize smaller.

[0045] Further, according to Figure 2 , the node current method is used to write KCL equations for the nodes i ; (1); then there are boundary conditions for the high-voltage node ac and the node n: (2);

[0046] Further, KCL equations are also written for other nodes, and a node equation group is constructed to be expressed in matrix form: (3); wherein, is a 1*(n-1) all-1 vector, A and B are both (n-1)*(n) matrices, and denote coefficient matrices;

[0047] Further, Laplace transform is made to the matrix equation and the expression of node voltage in s domain is obtained: (4); wherein, , D(s), E(s), d 0 (s) and f 0 (s) is the parameter matrix of the solution, d 0 (s) and f 0 (s) represents the initial condition matrix in the process of Laplace transform of the equation, and is specifically defined as follows: (5); wherein, represents the parameter combination, 、 、 and all represent the coefficient matrix;

[0048] Further, for the two problems of misdirecting and voltage imbalance, the following restriction conditions are made: (7); wherein, the definition represents the voltage imbalance degree, and the definition is the minimum value for measuring the voltage balance degree;

[0049] According to the above derivation, the parameter design process of the parallel buffer compensation circuit of the series diode can be realized under the restriction condition, as shown in Figure 3 : the number of series diodes is determined, the circuit parameters inductance L, distributed capacitance and and the power supply characteristics are assigned initial values, the (maximum) voltage of the diode is calculated according to formula (6), whether is judged according to the restriction condition 1, otherwise the assigned value of the buffer capacitance C is increased, whether is judged according to the restriction condition 2, otherwise the assigned value of the buffer capacitance C is increased, the voltage imbalance degree of the resistance-capacitance parameters satisfying the restriction condition is calculated and compared , the resistance-capacitance parameters realizing smaller value are selected, otherwise the assigned value of the buffer resistance R is increased, and the above process is repeated to obtain the value range of the resistance-capacitance parameters.

[0050] Figure 4 is a diode voltage waveform diagram in the step-down period of an external reverse square wave power supply obtained by using the parallel buffer compensation circuit of the rectifier without adopting the parameter design method of the present application, Figure 4 It can be seen from the figure that the maximum peak voltage difference reaches 325V, and the voltage imbalance degree reach 0.86, while the first diode on the high-voltage end also appears to be conducting; Figure 5 The diode voltage waveform diagram in the external reverse square wave power step-down period obtained by the parameter design method of the parallel buffer compensation circuit for the rectifier of the application is shown in the figure, Figure 5 It can be seen from the figure that the maximum peak voltage difference is only 7V, and the voltage imbalance 0.04 can be achieved, and none of the diodes appears to be conducting; The simulation and experimental results of the embodiment fully verify the effectiveness of the parameter design method of the parallel buffer compensation circuit proposed in the application, and the selected values effectively solve the mis-conduction and voltage imbalance problems caused by the square wave power step on the diode, reduce the diode loss, and prolong the service life of the diode. It can be used for system design in the field of large-scale series diodes.

[0051] It should be noted that when designing the parameters of the parallel buffer compensation circuit, the working principle is as follows: in the ideal case of series diode devices, although the external reverse power excitation step is excited, the diode will still maintain the blocking state of voltage sharing; However, due to the existence of distributed capacitance, when the power supply occurs step, part of the charge of the series circuit flows through the distributed capacitance, and the voltage across the capacitor cannot change suddenly, which causes the difference between the cathode and anode potential of the diode, resulting in mis-conduction and voltage imbalance of the diode oscillation; The parallel resistance-capacitance buffer compensation circuit increases the charge flow path when the power supply steps, offsets the influence of the charge flowing through the distributed capacitance, and thus ensures the normal working state of the series diode.

[0052] In summary, the application aims to improve and solve the technical problems of voltage imbalance and reverse step mis-conduction of multiple discrete diodes in series in the high-voltage power supply field, so the node between the series units is considered, the distributed capacitance of the high-voltage end and the ground end, the external circuit leakage inductance, and the reverse square wave power of high dv / dt step are considered, and a buffer compensation circuit and its parameter design method are proposed to ensure the safe and stable operation of the diode series rectifier with low cost and low power consumption. Not only does it contain the requirement of preventing diode trigger mis-conduction, but also contains the limitation of suppressing diode voltage imbalance; It reduces the additional switching loss of the diode, avoids the overvoltage damage of the diode caused by voltage imbalance, and prolongs the service life of the diode. It reduces the power consumption and device cost of the safe and stable operation of the rectifier system, and improves the reliability of the power supply as a whole.

[0053] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. All equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.

Claims

1. A parameter design method for a parallel buffer compensation circuit for a rectifier, characterized in that: Includes the following steps: S1. Determine the number of series units. Circuit parameters, including inductance, distributed capacitance, and power supply characteristics; S2, assign an initial value to the buffer resistor; S3. Assign an initial value to the buffer capacitor; S4. Calculate constraint 1 and determine whether the initial value of the buffer capacitor meets constraint 1. If it does not meet the constraint, jump to S3 and adjust the value of the buffer capacitor until constraint 1 is met. S5. Calculate constraint 2 and continue to determine whether the value of the buffer capacitor meets constraint 2. If constraint 2 is not met, jump to S3 and continue to adjust the value of the buffer capacitor until constraint 2 is met. S6. Calculate the voltage imbalance and determine whether the voltage imbalance is less than the minimum value. If not, jump to S2 and adjust the value of the buffer resistor until the voltage imbalance is less than the minimum value. S7. Outputs a range of values ​​for buffer resistors and buffer capacitors to achieve a smaller voltage imbalance. The formula for constraint 1 is as follows: ;in, This represents the diode voltage, which, for constraint 1, can also be equivalent to the maximum diode voltage; the diode voltage is obtained according to the following formula. : ； ； The buffer resistor is R, and the buffer capacitor is C. , , and Indicates parameter combination, , , and All represent the coefficient matrix, and L represents the system leakage inductance. Indicates power supply excitation. and These represent the distributed capacitance to the high-voltage terminal and the capacitance to ground, respectively. The formula for constraint 2 is: ;in, This indicates the voltage of the first diode at the high-voltage end. The minimum value is used to measure voltage balance; voltage imbalance is calculated using the following formula: ;in, This refers to the voltage imbalance.

2. The parameter design method for a parallel buffer compensation circuit for a rectifier according to claim 1, characterized in that: The parameter design method for the parallel buffer compensation circuit for the rectifier is based on the parallel buffer compensation circuit for the rectifier. The parallel buffer compensation circuit includes a series branch connected in parallel across a diode. This series branch includes a buffer capacitor and a buffer resistor connected in parallel with the diode. The negative terminal of the diode is connected to the positive terminal of the buffer capacitor. The negative terminal of the buffer capacitor is connected to one end of the buffer resistor, and the other end of the buffer resistor is connected to the positive terminal of the diode. The diode, the buffer capacitor connected in parallel with the diode, and the buffer resistor constitute a series unit connected in series with the rectifier. There are n groups of these series units. .

3. The parameter design method for a parallel buffer compensation circuit for a rectifier according to claim 2, characterized in that: The rectifier includes a DC power supply and an inductor connected in series with the DC power supply. The positive terminal of the DC power supply is connected to one end of the inductor, and the negative terminal of the DC power supply is connected in series with n sets of series units between the other end of the inductor and the other end of the DC power supply.

4. The parameter design method for a parallel buffer compensation circuit for a rectifier according to claim 3, characterized in that: The diodes in the series unit are connected in series. The negative terminal of the diode at the first end of the series connection is also connected to the other end of the inductor, and the positive terminal of the diode at the last end of the series connection is also connected to the negative terminal of the DC power supply.

5. The parameter design method for a parallel buffer compensation circuit for a rectifier according to claim 3, characterized in that: The rectifier also includes n-1 distributed capacitances of diodes connected in series to the high-voltage end. The positive terminals of the n-1 distributed capacitances to the high-voltage end are all connected to the other end of the inductor, and the negative terminals of the n-1 distributed capacitances to the high-voltage end are all connected to the wire between two adjacent diodes.

6. The parameter design method for a parallel buffer compensation circuit for a rectifier according to claim 3, characterized in that: The rectifier also includes n-1 distributed capacitances to ground at the series-connected nodes of diodes. The positive terminals of the n-1 distributed capacitances to ground are all connected to the wire between two adjacent diodes, and the negative terminals of the n-1 distributed capacitances to ground are all connected to the negative terminal of the DC power supply and grounded.

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