Current mode PWM controller

Abstract

The invention belongs to the technical field of PWM controller circuits, and particularly relates to a current mode PWM controller. Comprising an oscillator module, an FB detection module, an overload protection module, a hiccup control module and a PWM comparator CMP1, the FB detection module inputs a feedback voltage signal FB through an FB port so as to control the conduction and cut-off of a triode Q1, and outputs three paths of voltage signals to the overload protection module, the hiccup control module and the PWM comparator CMP1; the CS detection module is used for inputting an inductive current signal of an off-chip loop through a CS port, converting the inductive current signal into a voltage signal CS through an off-chip sampling resistor Rd, sending the voltage signal CS into the chip, processing the voltage signal CS through a leading edge blanking circuit, and outputting a signal P876G; the peak current detection module is used for superposing the voltage signal CS and a triangular wave signal N4G output by the oscillator module, then carrying out leading edge blanking switching and then inputting the voltage signal CS and the triangular wave signal N4G to a PWM comparator CMP1; according to the invention, rapid load response can be realized through peak current detection and voltage / current double feedback.

Description

Technical Field

[0001] The present invention belongs to the technical field of PWM controller circuits, and in particular relates to a current mode PWM controller. Background Art

[0002] Current mode PWM controller is the core control technology in switching power supply, which is mainly divided into three types: Peak Current Mode (PCM), Valley Current Mode (VCM) and Hysteretic Current Mode (HCM), each with different advantages and disadvantages: (1) Peak current mode control mode, advantages: fast dynamic response, suitable for high-frequency switching; with built-in cycle-by-cycle current limiting protection, high reliability, insensitive to input voltage changes, suitable for wide input range, easy to implement multi-phase parallel connection, suitable for high current applications; disadvantages: slope compensation is required, otherwise subharmonic oscillation may occur when the duty cycle is >50%, sensitive to noise, current detection accuracy affects stability, and light load efficiency is low; (2) Average current mode (VCM) control mode, advantages: suitable for low-side switching topologies such as synchronous Buck, simpler to detect the lower tube current Single; no slope compensation is required, good stability; high efficiency at light load, suitable for battery-powered devices; Disadvantages: dynamic response is slightly slower than PCM, high accuracy is required for valley detection of inductor current, and duty cycle adjustment range is limited; (3) Hysteresis current mode (HCM) control mode, Advantages: no fixed frequency clock is required, adaptive switching frequency (variable frequency control), extremely fast transient response, suitable for high dynamic loads (such as FPGA, ASIC power supply) without compensation network requirements, simplified design; Disadvantages: switching frequency is not fixed, EMI is difficult to optimize, frequency may be too low at light load, affecting output ripple, current detection accuracy and noise immunity are weak.

[0003] The PWM controller in the existing technology has the main defect of the contradiction between dynamic response and stability. When the peak current mode (PCM) control mode is adopted, slope compensation is required to prevent subharmonic oscillation, but excessive compensation will reduce the dynamic response speed. Although the hysteresis control (HCM) has a fast response, its variable frequency characteristics lead to complex EMI design, making it difficult to meet the needs of high-precision power supply. Summary of the Invention

[0004] The present invention aims to provide a current-mode PWM controller that achieves fast load response through peak current detection and dual voltage / current feedback. The current loop directly participates in PWM comparison, resulting in a response speed 5-10 times faster than pure voltage feedback, making it suitable for transient load scenarios (such as CPU dynamic frequency modulation).

[0005] To solve the above technical problems, the present invention provides a current mode PWM controller, comprising: The FB detection module inputs the feedback voltage signal FB through the FB port to control the conduction and cutoff of the transistor Q1, and outputs three voltage signals to the overload protection module, the hiccup control module and the PWM comparator CMP1; The CS detection module inputs the inductor current signal of the off-chip loop through the CS port, converts the inductor current signal into a voltage signal CS through the off-chip sampling resistor Rd and sends it into the chip. After being processed by the leading edge blanking circuit, the output signal P876_G; The peak current detection module outputs a signal X835_YN by superimposing the voltage signal CS with the triangular wave signal N4_G output by the oscillator module, performing leading edge blanking switching, and then inputting the signal to the PWM comparator CMP1. The signal is compared with the voltage signal P879_G output by the FB detection module. A hiccup control module compares the voltage signal P872_G output by the FB detection module with a comparison threshold and then outputs a signal X840_SNN to control whether the oscillator module enters the hiccup mode; An overload protection module compares the voltage signal R932_PLUS output by the FB detection module with the overload threshold and then outputs a signal X821_Y; An overcurrent protection module, which compares the signal P876_G input to the overcurrent protection module with an overcurrent threshold and outputs a signal X815_YN; The PWM logic control module is used to process the input signals X835_YN, X821_Y and X815_YN and output the signal X823_Y as the input control signal of the soft drive module to determine the duty cycle of the chip output drive signal.

[0006] Preferably, the FB detection module includes: a transistor Q1, resistors R0~R6 and a current source I1; one end of the current source I1 is connected to the power supply X2_D, and the other end is connected to one end of the resistor R6, the other end of the resistor R6 is connected to one end of the resistor R1, one end of the resistor R2, and the base and collector of the transistor Q1, the other end of the resistor R1 is connected to the FB port, the FB port is connected to an off-chip optocoupler U0 connected to the chip output voltage, and a current signal is output to the resistor R1 at the FB end through the optocoupler U0 to form a voltage signal FB, the other end of the resistor R2 is connected to the power supply X2_D, the emitter of the transistor Q1 is connected to the resistor R3 and one end of the resistor R4, the other end of the resistor R4 outputs the voltage signal P872_G, the other end of the resistor R3 is connected to one end of the resistor R0 and outputs the voltage signal R932_PLUS, and the other end of the resistor R0 is connected to the grounded resistor R5 and outputs the voltage signal P879_G.

[0007] Preferably, the peak current detection module includes: an operational amplifier OP1, resistors R7~R8 and an NMOS transistor N1; the positive input end of the operational amplifier OP1 is connected to the triangular wave signal N4_G, the negative input end is connected to the output end and is connected to one end of the resistor R7, the other end of the resistor R7 is connected to one end of the resistor R8 and the drain of the NMOS transistor N1 and outputs a blanked superimposed signal, the other end of the resistor R8 is connected to the voltage signal CS, the gate of the NMOS transistor N1 is connected to the rectangular wave blanking control signal X824_Y, and the source of the NMOS transistor N1 is grounded.

[0008] Preferably, the overload protection module includes: a comparator CMP2, a NOT gate X1, a NOT gate X5, an AND gate X2~X4, an AND gate X6, a T flip-flop TFF and a D flip-flop DFF; the positive input terminal of the comparator CMP2 is connected to the voltage signal R932_PLUS, the negative input terminal is connected to the overload threshold voltage P364_D, the output terminal is connected to the input terminal 1 of the AND gate X2 through the NOT gate X1, the input terminal 2 of the AND gate X2 is connected to the logic signal "1", the output terminal of the AND gate X2 is connected to the input terminal 1 of the AND gate X3~X4, the input terminal 2 of the AND gate X3 is connected to the logic signal "1", and the AND gate X2 is connected to the input terminal 1 of the AND gate X3~X4. The second input terminal of the gate X4 is connected to the rectangular wave signal X1255_Q, the output terminal of the AND gate X3 is connected to the Reset terminals of the T flip-flop TFF and the D flip-flop DFF, the output terminal of the AND gate X4 is connected to the CLK terminal of the T flip-flop TFF, the Q terminal of the T flip-flop TFF is connected to the CLK terminal of the D flip-flop DFF, the D terminal of the D flip-flop DFF is connected to the logic signal "1", the Q terminal of the D flip-flop DFF is connected to the input terminal 1 of the AND gate X6 through the NOT gate X5, the input terminal 2 of the AND gate X6 is connected to the logic signal "1", and the output terminal of the AND gate X6 outputs the signal X821_Y.

[0009] Preferably, the hiccup control module includes: an operational amplifier OP2, a NOT gate X7 and a selector MUX; the positive input terminal of the operational amplifier OP2 is connected to the comparison threshold voltage X840_Y and the signal X840_SNN, the negative input terminal is connected to the voltage signal P872_G, the output terminal is connected to the S terminal of the selector MUX through the NOT gate X7, the A terminal of the selector MUX is connected to the voltage signal P191_G, the B terminal of the selector MUX is connected to the voltage signal R736_MINUS, and the Y terminal of the selector MUX outputs the signal X840_SNN.

[0010] Preferably, the CS detection module includes: a sampling resistor Rd, a resistor R12 and an NMOS transistor N3; the inductor current signal of the input off-chip loop is converted into a voltage signal CS through the grounded sampling resistor Rd and input to one end of the resistor R12, the other end of the resistor R12 is connected to the drain of the NMOS transistor N3 and outputs a signal P876_G, the gate of the NMOS transistor N3 is connected to the rectangular wave blanking control signal X824_Y, and the source of the NMOS transistor N3 is grounded.

[0011] Preferably, the overcurrent protection module includes: a comparator CMP3 and NOT gates X8~X9; the positive input terminal of the comparator CMP3 inputs a signal P876_G, the negative input terminal inputs an overcurrent threshold voltage R399_PLUS, and the output terminal is sequentially connected to the NOT gates X8~X9 to output a signal X815_YN.

[0012] Preferably, an overcurrent threshold voltage generating module is further included, and the overcurrent threshold voltage generating module includes: an operational amplifier OP3, an NMOS tube N2, a resistor R9 and a self-biased low-voltage cascode current mirror; the positive input terminal of the operational amplifier OP3 is connected to the reference voltage R736_MINUS, the negative input terminal is connected to the grounded resistor R9 and the source of the NMOS tube N2, the output terminal is connected to the gate of the NMOS tube N2, and the drain of the NMOS tube N2 is connected to the input terminal of the self-biased low-voltage cascode current mirror.

[0013] Preferably, the self-biased low-voltage cascode current mirror includes: PMOS transistors P1 to P15 and resistors R10 to R11; the sources of the PMOS transistors P1, PMOS transistors P4, PMOS transistors P7, PMOS transistors P10 and PMOS transistors P13 are connected to the power supply VCC1, the gates of the PMOS transistors P1 and PMOS transistors P13 are grounded, the drain of the PMOS transistor P1 is connected to the source of the PMOS transistor P2, the drain of the PMOS transistor P2 is connected to the source of the PMOS transistor P3, the drain of the PMOS transistor P3 is connected to the gates of the PMOS transistors P2, PMOS transistors P5, PMOS transistors P8, PMOS transistors P11 and PMOS transistors P14, and one end of the resistor R11, the other end of the resistor R11 is connected to the gates of the PMOS transistors P3, PMOS transistors P6, PMOS transistors P9, PMOS transistors P12 and PMOS transistors P15 and serves as an input end, the PMOS transistors P4, PMOS transistors P7 and PMOS transistors P13 are grounded, the drain of the PMOS transistor P1 is connected to the source of the PMOS transistor P2, the drain of the PMOS transistor P2 is connected to the source of the PMOS transistor P3, the drain of the PMOS transistor P3 is connected to the gates of the PMOS transistors P2, PMOS transistors P5, PMOS transistors P8, PMOS transistors P11 and PMOS transistors P14, and one end of the resistor R11, the other end of the resistor R11 is connected to the gates of the PMOS transistors P3, PMOS transistors P6, PMOS transistors P9, PMOS transistors P12 and PMOS transistors P15 and serves as an input end, The gate of the OS transistor P10 is connected to the control signals D1 to D3 in sequence, the drain of the PMOS transistor P4 is connected to the source of the PMOS transistor P5, the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6, the drain of the PMOS transistor P7 is connected to the source of the PMOS transistor P8, the drain of the PMOS transistor P8 is connected to the source of the PMOS transistor P9, the drain of the PMOS transistor P10 is connected to the source of the PMOS transistor P11, and the drain of the PMOS transistor P11 is connected to the source of the PMOS transistor P12. The electrode of the PMOS transistor P12 is connected to the source of the PMOS transistor P12, the drain of the PMOS transistor P13 is connected to the source of the PMOS transistor P14, the drain of the PMOS transistor P14 is connected to the source of the PMOS transistor P15, the drain of the PMOS transistor P7 is connected to the source of the PMOS transistor P8, and the drains of the PMOS transistors P6, PMOS transistors P9, PMOS transistors P12 and PMOS transistors P15 are connected to the grounded resistor R10 and output the overcurrent threshold voltage R399_PLUS.

[0014] Preferably, the resistance ratio of the resistor R9 and the resistor R10 is 2:1; the current ratio of the left self-biased current mirror and the current ratio of the four replica current mirrors on the right in the self-biased low-voltage common-source common-gate current mirror is 4:4:2:1:1.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention offers both dynamic response and stability. It achieves rapid load response through peak current detection and dual voltage / current feedback. The current loop directly participates in PWM comparison, resulting in a response 5-10 times faster than pure voltage feedback, making it suitable for transient load scenarios (such as CPU dynamic frequency modulation).

[0016] The present invention has low ripple and low noise characteristics; by setting a current detection circuit with leading edge blanking, it eliminates the current detection spike interference when the switch tube is turned on, improves the accuracy and stability of current detection, and ensures the normal operation of the power supply.

[0017] The present invention has high reliability and protection capabilities; through multi-cycle overcurrent protection (OCP), the current is detected in each switching cycle to avoid inductor saturation and machine explosion. Through overload protection (OLP), when the feedback voltage exceeds the threshold, the frequency is forced to be reduced or shut down to protect the back-end circuit. Through adaptive current limiting, the current limiting threshold is set by external resistors, and different power levels can be flexibly adapted. Through the built-in slope compensation function, the stability problem of current mode control when the duty cycle is greater than 50% is improved, further improving the stability and reliability of the power supply system. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a principle block diagram of a current mode PWM controller provided by the present invention.

[0019] Figure 2 It is a circuit diagram of the FB detection module provided by the present invention.

[0020] Figure 3 This is a circuit diagram of the overload protection module provided by the present invention.

[0021] Figure 4 This is a circuit diagram of the peak current detection module provided by the present invention.

[0022] Figure 5 This is a circuit diagram of the hiccup control module provided by the present invention.

[0023] Figure 6 It is a circuit diagram of the CS detection module provided by the present invention.

[0024] Figure 7 This is a circuit diagram of the overcurrent protection module provided by the present invention.

[0025] Figure 8 This is a circuit diagram of the overcurrent threshold voltage generating module provided by the present invention.

[0026] Figure 9 This is a relationship diagram of the FB voltage corresponding to the chip operating mode provided by the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0028] like Figures 1 to 9As shown, an embodiment of the present invention specifically provides a current mode PWM controller, including: The FB detection module inputs the feedback voltage signal FB through the FB port to control the conduction and cutoff of the transistor Q1, and outputs three voltage signals to the overload protection module, the hiccup control module and the PWM comparator CMP1; The CS detection module inputs the inductor current signal of the off-chip loop through the CS port, converts the inductor current signal into a voltage signal CS through the off-chip sampling resistor Rd and sends it into the chip. After being processed by the leading edge blanking circuit, the output signal P876_G; The peak current detection module outputs a signal X835_YN by superimposing the voltage signal CS with the triangular wave signal N4_G output by the oscillator module, performing leading edge blanking switching, and then inputting the signal to the PWM comparator CMP1. The signal is compared with the voltage signal P879_G output by the FB detection module. A hiccup control module compares the voltage signal P872_G output by the FB detection module with a comparison threshold and then outputs a signal X840_SNN to control whether the oscillator module enters the hiccup mode; An overload protection module compares the voltage signal R932_PLUS output by the FB detection module with the overload threshold and then outputs a signal X821_Y; An overcurrent protection module, which compares the signal P876_G input to the overcurrent protection module with an overcurrent threshold and outputs a signal X815_YN; The PWM logic control module is used to process the input signals X835_YN, X821_Y and X815_YN and output the signal X823_Y as the input control signal of the soft drive module to determine the duty cycle of the chip output drive signal.

[0029] The FB detection module includes: a transistor Q1, resistors R0~R6 and a current source I1; one end of the current source I1 is connected to the power supply X2_D, and the other end is connected to one end of the resistor R6. The other end of the resistor R6 is connected to one end of the resistor R1, one end of the resistor R2, and the base and collector of the transistor Q1. The other end of the resistor R1 is connected to the FB port, and the FB port is connected to the off-chip optocoupler U0 connected to the chip output voltage. The optocoupler U0 outputs a current signal to the resistor R1 at the FB end to form a voltage signal FB. The other end of the resistor R2 is connected to the power supply X2_D. The emitter of the transistor Q1 is connected to one end of the resistor R3 and the resistor R4. The other end of the resistor R4 outputs the voltage signal P872_G. The other end of the resistor R3 is connected to one end of the resistor R0 and outputs the voltage signal R932_PLUS. The other end of the resistor R0 is connected to the grounded resistor R5 and outputs the voltage signal P879_G.

[0030] The FB terminal voltage reflects the off-chip output load. The larger the FB terminal voltage, the greater the load. The optical signal is converted into a current signal by the off-chip optocoupler, and a voltage is formed at the FB terminal through the internal resistor. The FB terminal is responsible for detecting the output voltage, which reflects the off-chip load and can affect the working state of the chip. Figure 9 As shown, when the FB voltage is less than 1.5V (including FB short-circuited to ground), it is considered to be in a zero-load state, the oscillator frequency is reduced to the minimum, and the chip output OUT is low. When the FB voltage gradually increases from 1.5V, it indicates that the load is gradually increasing and the oscillator frequency is gradually increasing. When the FB voltage reaches around 2.1V, the load is moderate and the oscillator frequency is stable. As the load gradually increases, the FB voltage rises to 4.6V, the load is too heavy, triggering the overload protection, and OUT outputs a low level. In particular, when the optocoupler is open, the FB open-circuit voltage is 5.3V, OUT outputs a low level, and enters the optocoupler open-circuit protection.

[0031] The peak current detection module includes: an operational amplifier OP1, resistors R7-R8, and an NMOS transistor N1; the positive input terminal of the operational amplifier OP1 is connected to the triangular wave signal N4_G, the negative input terminal is connected to the output terminal and is connected to one end of the resistor R7, the other end of the resistor R7 is connected to one end of the resistor R8 and the drain of the NMOS transistor N1, and outputs a blanked superimposed signal, the other end of the resistor R8 is connected to the voltage signal CS, the gate of the NMOS transistor N1 is connected to the rectangular wave blanking control signal X824_Y, and the source of the NMOS transistor N1 is grounded.

[0032] The chip adopts the peak current detection mode. The FB detection module completes the sampling of the FB terminal voltage and sends it to the PWM comparator for comparison with the inductor current signal and the triangular wave signal N4_G superimposed mixed signal to adjust the OUT output.

[0033] When the OUT terminal remains at a low level, a high level is generated at the blanking control signal X824_Y, turning on transistor N1 and pulling the output signal P876_G to ground. At this point, the off-chip switch is off, the resistance across sampling resistor Rd is 0, and the input from the CS terminal is also 0. When the OUT terminal changes from a low level of 0 to a high level of 1, the blanking control signal X824_Y becomes low, turning off transistor N1. At this point, transistor N1 normally feeds the CS terminal voltage signal into the slope compensation circuit (composed of operational amplifier OP1 and resistor R7) in the peak current detection module. That is, during the period when the off-chip switch is on, the input CS terminal signal remains low. This period is known as the leading edge blanking time.

[0034] The overload protection module includes: a comparator CMP2, a NOT gate X1, a NOT gate X5, an AND gate X2~X4, an AND gate X6, a T flip-flop TFF and a D flip-flop DFF; the positive input terminal of the comparator CMP2 is connected to the voltage signal R932_PLUS, the negative input terminal is connected to the overload threshold voltage P364_D output by the bandgap circuit BGR, the output terminal is connected to the input terminal 1 of the AND gate X2 through the NOT gate X1, the input terminal 2 of the AND gate X2 is connected to the logic signal "1", the output terminal of the AND gate X2 is connected to the input terminal 1 of the AND gates X3~X4, the input terminal 2 of the AND gate X3 is connected to the logic signal "1", and the AND gate X2 is connected to the input terminal 1 of the AND gates X3~X4. The second input terminal of the gate X4 is connected to the rectangular wave signal X1255_Q output by the frequency divider, the output terminal of the AND gate X3 is connected to the Reset terminals of the T flip-flop TFF and the D flip-flop DFF, the output terminal of the AND gate X4 is connected to the CLK terminal of the T flip-flop TFF, the Q terminal of the T flip-flop TFF is connected to the CLK terminal of the D flip-flop DFF, the D terminal of the D flip-flop DFF is connected to the logic signal "1", the Q terminal of the D flip-flop DFF is connected to the input terminal 1 of the AND gate X6 through the NOT gate X5, the input terminal 2 of the AND gate X6 is connected to the logic signal "1", and the output terminal of the AND gate X6 outputs the signal X821_Y.

[0035] The principle of delay and protection is: when the voltage signal R932_PLUS exceeds the fixed threshold value P364_D of the comparator, the output signal P532_S of the comparator CMP2 is set to a high level. At this time, the output of the AND gate X3 is 1, and the reset terminals of the T flip-flop TFF and the D flip-flop DFF are invalid, and the AND gate X4 will continue to output a rectangular wave with a period of 31.51ms. This signal serves as the clock signal of the T flip-flop TFF. The characteristic of the T flip-flop TFF is that as long as the falling edge of the clock arrives, the previous state will be flipped. Therefore, depending on the time of the overload trigger, the time it needs to wait for the falling edge to arrive will also be different. This results in the total delay time not being exactly 30ms, but the delay caused by the trigger structure is considered to be 30ms. The result is actually to divide the signal X1255_Q provided by the divider again. The output of the T flip-flop TFF serves as the clock signal of the D flip-flop DFF. When the clock falling edge arrives, the D flip-flop DFF outputs a high-level signal, which then passes through the NOT gate X5 and the AND gate X6 to output a low-level overload protection signal that enters the PWM logic control module, causing the output OUT to be pulled low. The actual total delay time should be between 30ms and 60ms.

[0036] The higher the FB voltage, the closer the system is to an overload condition. Overload is an abnormal operating state. The overload protection module detects the voltage signal provided by the FB detection module. When the FB voltage exceeds 4.6V, it pulls down the OUT output to prevent overload.

[0037] The hiccup control module includes: an operational amplifier OP2, a NOT gate X7 and a selector MUX; the positive input terminal of the operational amplifier OP2 is connected to the comparison threshold voltage X840_Y and the signal X840_SNN, the negative input terminal is connected to the voltage signal P872_G, the output terminal is connected to the S terminal of the selector MUX through the NOT gate X7, the A terminal of the selector MUX is connected to the voltage signal P191_G, the B terminal of the selector MUX is connected to the voltage signal R736_MINUS, the voltage of the voltage signal P191_G is slightly higher than the voltage of the voltage signal R736_MINUS, and the Y terminal of the selector MUX outputs the signal X840_SNN.

[0038] The hiccup control module primarily utilizes an op amp and a selector to form a hysteresis comparator, corresponding to two FB voltages. Signal P872_G is linked to the FB voltage. When the FB voltage increases from 0, the comparator output goes high, locking the selector to the high threshold. At this point, S = 0, and SNN = 0, placing the oscillator in hiccup mode at a fixed frequency of 21kHz. OUT is pulled low, shutting down the output. When the FB voltage rises to approximately 1.5V, the comparator flips, locking the low threshold, indicating a light load condition. Within a certain voltage range of approximately 1.5V to 2.1V, the oscillator frequency increases with increasing load.

[0039] The hiccup control module determines whether the chip enters green or hiccup mode based on the voltage signal provided by the FB detection module. It then sends a signal to the oscillator module to determine the chip's operating mode. In hiccup mode, the power tube switching frequency is greatly reduced, thereby reducing system power consumption.

[0040] The CS detection module includes: a sampling resistor Rd, a resistor R12, and an NMOS transistor N3. The grounded sampling resistor Rd converts the inductor current signal input to the off-chip loop into a voltage signal CS, which is input to one end of the resistor R12. The other end of the resistor R12 is connected to the drain of the NMOS transistor N3 and outputs a signal P876_G. The gate of the NMOS transistor N3 is connected to the rectangular wave blanking control signal X824_Y, and the source of the NMOS transistor N3 is grounded.

[0041] The overcurrent protection module includes: a comparator CMP3 and NOT gates X8~X9; the positive input terminal of the comparator CMP3 inputs a signal P876_G, the negative input terminal inputs an overcurrent threshold voltage R399_PLUS, and the output terminal is sequentially connected to the NOT gates X8~X9 to output a signal X815_YN.

[0042] When the OUT terminal remains low, the blanking control signal X824_Y generates a high level, turning on transistor N3 and pulling the output signal P876_G to ground. At this point, the off-chip switch is off, the resistance across sampling resistor Rd is zero, and the input from the CS terminal is also zero. When the OUT terminal transitions from a low level of 0 to a high level of 1, the blanking control signal X824_Y becomes low, turning off transistor N3. At this point, transistor N3 normally feeds the CS terminal voltage signal to the overcurrent protection module. That is, during the period when the off-chip switch is on, the input CS terminal signal remains low. This period is known as the leading edge blanking time.

[0043] After the CS input voltage is processed by the leading-edge blanking circuit, the overcurrent protection module compares the CS detection module's output signal P876_G with the overcurrent threshold voltage R399_PLUS. When the voltage of signal P876_G exceeds the overcurrent threshold voltage R399_PLUS, the external switch current is considered excessive and overcurrent protection is required. Comparator CMP3 outputs signal X815_YN as a high level 1, which eventually pulls the OUT output low after a period of time (Td_OCP), thus protecting the circuit. When the CS detection module's output voltage falls below the overcurrent threshold voltage, the X815_YN output is a low level 0, indicating that the current flowing through the external switch is appropriate, and the chip maintains normal operation.

[0044] It also includes an overcurrent threshold voltage generating module, which includes: an operational amplifier OP3, an NMOS tube N2, a resistor R9 and a self-biased low-voltage cascode current mirror; the positive input terminal of the operational amplifier OP3 is connected to the reference voltage R736_MINUS, the negative input terminal is connected to the grounded resistor R9 and the source of the NMOS tube N2, the output terminal is connected to the gate of the NMOS tube N2, and the drain of the NMOS tube N2 is connected to the input terminal of the self-biased low-voltage cascode current mirror.

[0045] A self-biased low-voltage cascode current mirror includes: PMOS transistors P1 to P15 and resistors R10 to R11; the sources of the PMOS transistors P1, PMOS transistors P4, PMOS transistors P7, PMOS transistors P10 and PMOS transistors P13 are connected to the power supply VCC1, the gates of the PMOS transistors P1 and P13 are grounded, the drain of the PMOS transistor P1 is connected to the source of the PMOS transistor P2, the drain of the PMOS transistor P2 is connected to the source of the PMOS transistor P3, the drain of the PMOS transistor P3 is connected to the gates of the PMOS transistors P2, PMOS transistors P5, PMOS transistors P8, PMOS transistors P11 and PMOS transistors P14, and one end of the resistor R11, the other end of the resistor R11 is connected to the gates of the PMOS transistors P3, PMOS transistors P6, PMOS transistors P9, PMOS transistors P12 and PMOS transistors P15 and serves as an input end, the PMOS transistors P4, PMOS transistors P7 and PMOS transistors P10 are connected to the gates of the PMOS transistors P3, PMOS transistors P6, PMOS transistors P9, PMOS transistors P12 and PMOS transistors P15 and serve as an input end, The gates of the PMOS transistors are connected to the control signals D1 to D3 provided by the frequency divider output in sequence, the drain of the PMOS transistor P4 is connected to the source of the PMOS transistor P5, the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6, the drain of the PMOS transistor P7 is connected to the source of the PMOS transistor P8, the drain of the PMOS transistor P8 is connected to the source of the PMOS transistor P9, the drain of the PMOS transistor P10 is connected to the source of the PMOS transistor P11, and the drain of the PMOS transistor P11 is connected to the source of the PMOS transistor P12. The drain of the PMOS transistor P12 is connected to the source of the PMOS transistor P12, the drain of the PMOS transistor P13 is connected to the source of the PMOS transistor P14, the drain of the PMOS transistor P14 is connected to the source of the PMOS transistor P15, the drain of the PMOS transistor P7 is connected to the source of the PMOS transistor P8, and the drains of the PMOS transistors P6, PMOS transistors P9, PMOS transistors P12, and PMOS transistors P15 are connected to the grounded resistor R10 and output the overcurrent threshold voltage R399_PLUS.

[0046] In the overcurrent threshold voltage generation module, operational amplifier OP3 uses a negative feedback structure to create a virtual short circuit in the input signal, causing the voltage at the inverting input of operational amplifier OP3 to equal the voltage of R736_MINUS, where R736_MINUS is the voltage generated by the linear power supply circuit. Once the virtual short circuit is complete, the potential of signal R403_PLUS (i.e., the voltage across resistor R9 in the equivalent circuit) is fixed, and the current flowing through resistor R9 also remains constant. The generated current acts as a current source for the self-biased low-voltage cascode structure, which is replicated by the current mirror structure on the right half. Ultimately, the current passes through resistor R10 to generate the overcurrent threshold voltage R399_PLUS.

[0047] The current ratios of the self-biased current mirror and the four replica current mirror circuits on the right are 4:4:2:1:1, respectively, and R9:R10 = 2:1. During normal chip operation, all three PMOS transistors (P4, P7, and P10) remain on. At this point, the current ratio across R9 and R10 is 1:2. Given their resistance ratios, the voltages across R9 and R10 should be consistent.

[0048] In summary, the present invention integrates voltage / current dual feedback, and uses real-time comparison logic between the voltage signal output by the FB detection module and the current sampling signal output by the peak current detection module in the PWM comparator CMP1. Furthermore, an adaptive slope compensation circuit is used to prevent subharmonic oscillations by dynamically adjusting the compensation amount (e.g., the compensation slope changes with the duty cycle). Furthermore, a current detection circuit with leading-edge blanking (LEB) is used: LEB time setting technology (e.g., a 200ns blanking window) and anti-interference filtering design (e.g., RC low-pass filter parameters). Furthermore, a cycle-by-cycle current limiting method is used: a real-time comparison circuit between the current sampling signal and the dynamic threshold, i.e., the overcurrent threshold voltage R399_PLUS (set by an external resistor), to flexibly adapt to different power levels. Furthermore, a feedback mechanism for overload protection is used: overload threshold detection and forced frequency reduction / shutdown execution logic (e.g., by lowering the PWM drive signal) to protect the back-end circuit. Furthermore, peak current mode optimization is used: while reducing the switching frequency, the current loop quickly responds to load transients (e.g., dynamic adjustment of the current sampling gain).

[0049] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A current mode PWM controller, characterized in that: include: The FB detection module inputs the feedback voltage signal FB through the FB port to control the conduction and cutoff of the transistor Q1, and outputs three voltage signals to the overload protection module, the hiccup control module and the PWM comparator CMP1; The CS detection module inputs the inductor current signal of the off-chip loop through the CS port, converts the inductor current signal into a voltage signal CS through the off-chip sampling resistor Rd and sends it into the chip. After being processed by the leading edge blanking circuit, the output signal P876_G; The peak current detection module outputs a signal X835_YN by superimposing the voltage signal CS with the triangular wave signal N4_G output by the oscillator module, performing leading edge blanking switching, and then inputting the signal to the PWM comparator CMP1. The signal is compared with the voltage signal P879_G output by the FB detection module. A hiccup control module compares the voltage signal P872_G output by the FB detection module with a comparison threshold and then outputs a signal X840_SNN to control whether the oscillator module enters the hiccup mode; An overload protection module compares the voltage signal R932_PLUS output by the FB detection module with the overload threshold and then outputs a signal X821_Y; An overcurrent protection module, which compares the signal P876_G input to the overcurrent protection module with an overcurrent threshold and outputs a signal X815_YN; The PWM logic control module is used to process the input signals X835_YN, X821_Y and X815_YN and output the signal X823_Y as the input control signal of the soft drive module to determine the duty cycle of the chip output drive signal.

2. A current mode PWM controller according to claim 1, characterized in that: The FB detection module includes: a transistor Q1, resistors R0~R6 and a current source I1; one end of the current source I1 is connected to the power supply X2_D, and the other end is connected to one end of the resistor R6. The other end of the resistor R6 is connected to one end of the resistor R1, one end of the resistor R2, and the base and collector of the transistor Q1. The other end of the resistor R1 is connected to the FB port, and the FB port is connected to the off-chip optocoupler U0 connected to the chip output voltage. The optocoupler U0 outputs a current signal to the resistor R1 at the FB end to form a voltage signal FB. The other end of the resistor R2 is connected to the power supply X2_D. The emitter of the transistor Q1 is connected to one end of the resistor R3 and the resistor R4. The other end of the resistor R4 outputs the voltage signal P872_G. The other end of the resistor R3 is connected to one end of the resistor R0 and outputs the voltage signal R932_PLUS. The other end of the resistor R0 is connected to the grounded resistor R5 and outputs the voltage signal P879_G.

3. A current mode PWM controller according to claim 1, characterized in that: The peak current detection module includes: an operational amplifier OP1, resistors R7-R8, and an NMOS transistor N1; the positive input terminal of the operational amplifier OP1 is connected to the triangular wave signal N4_G, the negative input terminal is connected to the output terminal and is connected to one end of the resistor R7, the other end of the resistor R7 is connected to one end of the resistor R8 and the drain of the NMOS transistor N1, and outputs a blanked superimposed signal, the other end of the resistor R8 is connected to the voltage signal CS, the gate of the NMOS transistor N1 is connected to the rectangular wave blanking control signal X824_Y, and the source of the NMOS transistor N1 is grounded.

4. A current mode PWM controller according to claim 1, characterized in that: The overload protection module includes: a comparator CMP2, a NOT gate X1, a NOT gate X5, AND gates X2 to X4, an AND gate X6, a T flip-flop TFF, and a D flip-flop DFF; the positive input terminal of the comparator CMP2 is connected to the voltage signal R932_PLUS, the negative input terminal is connected to the overload threshold voltage P364_D, the output terminal is connected to the input terminal 1 of the AND gate X2 through the NOT gate X1, the input terminal 2 of the AND gate X2 is connected to the logic signal "1", the output terminal of the AND gate X2 is connected to the input terminal 1 of the AND gates X3 to X4, the input terminal 2 of the AND gate X3 is connected to the logic signal "1", and the AND gates X The second input terminal of the AND gate X4 is connected to the rectangular wave signal X1255_Q, the output terminal of the AND gate X3 is connected to the Reset terminals of the T flip-flop TFF and the D flip-flop DFF, the output terminal of the AND gate X4 is connected to the CLK terminal of the T flip-flop TFF, the Q terminal of the T flip-flop TFF is connected to the CLK terminal of the D flip-flop DFF, the D terminal of the D flip-flop DFF is connected to the logic signal "1", the Q terminal of the D flip-flop DFF is connected to the input terminal 1 of the AND gate X6 through the NOT gate X5, the input terminal 2 of the AND gate X6 is connected to the logic signal "1", and the output terminal of the AND gate X6 outputs the signal X821_Y.

5. A current mode PWM controller according to claim 1, characterized in that: The hiccup control module includes: an operational amplifier OP2, a NOT gate X7 and a selector MUX; the positive input terminal of the operational amplifier OP2 is connected to the comparison threshold voltage X840_Y and the signal X840_SNN, the negative input terminal is connected to the voltage signal P872_G, the output terminal is connected to the S terminal of the selector MUX through the NOT gate X7, the A terminal of the selector MUX is connected to the voltage signal P191_G, the B terminal of the selector MUX is connected to the voltage signal R736_MINUS, and the Y terminal of the selector MUX outputs the signal X840_SNN.

6. A current mode PWM controller according to claim 1, characterized in that: The CS detection module includes: a sampling resistor Rd, a resistor R12, and an NMOS transistor N3. The grounded sampling resistor Rd converts the inductor current signal input to the off-chip loop into a voltage signal CS, which is input to one end of the resistor R12. The other end of the resistor R12 is connected to the drain of the NMOS transistor N3 and outputs a signal P876_G. The gate of the NMOS transistor N3 is connected to the rectangular wave blanking control signal X824_Y, and the source of the NMOS transistor N3 is grounded.

7. A current mode PWM controller according to claim 6, characterized in that: The overcurrent protection module includes: a comparator CMP3 and NOT gates X8~X9; the positive input terminal of the comparator CMP3 inputs a signal P876_G, the negative input terminal inputs an overcurrent threshold voltage R399_PLUS, and the output terminal is sequentially connected to the NOT gates X8~X9 to output a signal X815_YN.

8. A current mode PWM controller according to claim 7, characterized in that: It also includes an overcurrent threshold voltage generating module, which includes: an operational amplifier OP3, an NMOS tube N2, a resistor R9 and a self-biased low-voltage cascode current mirror; the positive input terminal of the operational amplifier OP3 is connected to the reference voltage R736_MINUS, the negative input terminal is connected to the grounded resistor R9 and the source of the NMOS tube N2, the output terminal is connected to the gate of the NMOS tube N2, and the drain of the NMOS tube N2 is connected to the input terminal of the self-biased low-voltage cascode current mirror.

9. A current mode PWM controller according to claim 8, characterized in that: A self-biased low-voltage cascode current mirror includes: PMOS transistors P1 to P15 and resistors R10 to R11; the sources of the PMOS transistors P1, PMOS transistors P4, PMOS transistors P7, PMOS transistors P10 and PMOS transistors P13 are connected to the power supply VCC1, the gates of the PMOS transistors P1 and P13 are grounded, the drain of the PMOS transistor P1 is connected to the source of the PMOS transistor P2, the drain of the PMOS transistor P2 is connected to the source of the PMOS transistor P3, the drain of the PMOS transistor P3 is connected to the gates of the PMOS transistors P2, PMOS transistors P5, PMOS transistors P8, PMOS transistors P11 and PMOS transistors P14, and one end of the resistor R11, the other end of the resistor R11 is connected to the gates of the PMOS transistors P3, PMOS transistors P6, PMOS transistors P9, PMOS transistors P12 and PMOS transistors P15 and serves as an input end, the PMOS transistors P4, PMOS transistors P7 and PMOS transistors The gate of the transistor P10 is connected to the control signals D1 to D3 in sequence, the drain of the PMOS transistor P4 is connected to the source of the PMOS transistor P5, the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6, the drain of the PMOS transistor P7 is connected to the source of the PMOS transistor P8, the drain of the PMOS transistor P8 is connected to the source of the PMOS transistor P9, the drain of the PMOS transistor P10 is connected to the source of the PMOS transistor P11, and the drain of the PMOS transistor P11 is connected to the source of the PMOS transistor P11. The source of the PMOS transistor P12 is connected, the drain of the PMOS transistor P13 is connected to the source of the PMOS transistor P14, the drain of the PMOS transistor P14 is connected to the source of the PMOS transistor P15, the drain of the PMOS transistor P7 is connected to the source of the PMOS transistor P8, and the drains of the PMOS transistors P6, PMOS transistors P9, PMOS transistors P12, and PMOS transistors P15 are connected to the grounded resistor R10 and output the overcurrent threshold voltage R399_PLUS.

10. A current mode PWM controller according to claim 9, characterized in that: The resistance ratio of the resistor R9 and the resistor R10 is 2:1; the current ratio of the left self-biased current mirror and the current ratio of the four right replica current mirrors in the self-biased low-voltage cascode current mirror is 4:4:2:1:1.

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