Signal recognition circuit, system on chip

Abstract

The application discloses a signal recognition circuit and a system on chip, and relates to the technical field of signal recognition.The circuit comprises N band-pass filter units, N second logic gate units, N-1 first logic gate units and a recognition unit, N is a positive integer greater than 2, the N band-pass filter units are connected with the N second logic gate units in one-to-one correspondence, the i-th first logic gate unit is connected with the i-th band-pass filter unit, the i+1-th band-pass filter unit, the i-th second logic gate unit and the i+1-th second logic gate unit, i is a positive integer greater than 0 and smaller than N, and the recognition unit is connected with the N second logic gate units.The to-be-recognized signal is input into the band-pass filter unit, the first logic gate unit performs logical operation on the filtering result, the second logic gate unit performs logical operation on the output of the first logic gate unit and the filtering result, and the recognition unit obtains the identity recognition result of the to-be-recognized signal according to the output of the second logic gate unit.Therefore, resource waste can be avoided.

Description

Technical Field

[0001] This invention relates to the field of signal recognition technology, and in particular to a signal recognition circuit and a system-on-a-chip. Background Technology

[0002] In small package on-chip systems, due to the limited number of pins, multiple unrelated or even mutually exclusive input signals often share the same input pin as the input source. Therefore, it is necessary to identify the identity information of the input signals.

[0003] In related technologies, on-chip systems input the signal to be identified into multiple bandpass filters with different effective frequency ranges, and determine the identity information of the signal to be identified based on the bandpass filters through which the signal passes.

[0004] However, in order to ensure recognition accuracy, the methods for determining the identity information of the signal to be identified in related technologies require that the effective frequency ranges of different bandpass filters not overlap, resulting in a small number of available windows within a certain frequency range and causing a waste of resources. Summary of the Invention

[0005] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, a first objective of this invention is to provide a signal recognition circuit to avoid resource waste.

[0006] The second objective of this invention is to provide a system-on-a-chip.

[0007] To achieve the above objectives, a first aspect of the present invention provides a signal recognition circuit. The circuit includes an recognition unit, N bandpass filter units, N-1 first logic gate units, and N second logic gate units, where N is a positive integer greater than or equal to 3. The N bandpass filter units are connected one-to-one with the N second logic gate units. The i-th first logic gate unit is connected to the i-th bandpass filter unit, the (i+1)-th bandpass filter unit, the i-th second logic gate unit, and the (i+1)-th second logic gate unit, where i is a positive integer greater than 0 and less than N. The recognition unit is connected to the N second logic gate units. The bandpass filter units perform bandpass filtering on the received signal to be recognized and send the filtering result to the first and second logic gate units. The first logic gate units perform a first logical operation on the received signal. The second logic gate units perform a second logical operation on the output signal of the first logic gate unit and the filtering result. The recognition unit obtains the identity recognition result of the signal to be recognized based on the output signals of the N second logic gate units.

[0008] In addition, the signal recognition circuit according to embodiments of the present invention may also have the following additional technical features:

[0009] According to one embodiment of the present invention, when the signal to be identified is a positive pulse width signal, the first logical operation is an XOR operation and the second logical operation is an AND operation; when the signal to be identified is a negative pulse width signal, the first logical operation is an XNOR operation and the second logical operation is an OR operation.

[0010] According to one embodiment of the present invention, the upper limit of the effective frequency range of the (i-1)th bandpass filter unit is the minimum frequency value of the center frequency window of the i-th bandpass filter unit, and the lower limit of the effective frequency range of the (i+1)th bandpass filter unit is the maximum frequency value of the center frequency window of the i-th bandpass filter unit. The center frequency window of the i-th bandpass filter unit is a preset frequency window within the effective frequency range of the i-th bandpass filter unit, and the effective frequency range of the i-th bandpass filter unit is the frequency range within which the output signal strength of the i-th bandpass filter unit is greater than a preset threshold.

[0011] According to one embodiment of the present invention, the identification unit is specifically configured to: when a preset signal exists among the output signals of the N second logic gate units, obtain the identification result of the signal to be identified based on the target second logic gate unit that outputs the preset signal; when the preset signal does not exist among the output signals of the N second logic gate units, identify the signal to be identified as an invalid signal.

[0012] According to an embodiment of the present invention, the identification unit is further configured to: when a preset signal exists among the output signals of the N second logic gate units, determine a target bandpass filter unit based on the target second logic gate unit, query a preset bandpass filter unit-signal identity correspondence table based on the target bandpass filter unit, and obtain the identity recognition result of the signal to be identified, wherein the target bandpass filter unit is a bandpass filter unit connected to the target second logic gate unit.

[0013] According to one embodiment of the present invention, the lower limit of the effective frequency range of the (i-1)th bandpass filter unit is the maximum frequency value of the center frequency window of the ith bandpass filter unit, and the upper limit of the effective frequency range of the (i+1)th bandpass filter unit is the minimum frequency value of the center frequency window of the ith bandpass filter unit. The center frequency window of the ith bandpass filter unit is a preset frequency window within the effective frequency range of the ith bandpass filter unit, and the effective frequency range of the ith bandpass filter unit is the frequency range within which the output signal strength of the ith bandpass filter unit is greater than a preset threshold.

[0014] According to one embodiment of the present invention, the circuit further includes: N Schmitt trigger units, wherein the N Schmitt trigger units are connected one-to-one with the N bandpass filter units and one-to-one with the N second logic gate units, the first Schmitt trigger unit is connected to the first first logic gate unit, the Nth Schmitt trigger unit is connected to the (N-1)th first logic gate unit, and the jth Schmitt trigger unit is connected to the (j-1)th and the jth first logic gate unit, where j is a positive integer greater than 1 and less than N; the Schmitt trigger units are used to perform shaping operations on the output signals of the bandpass filter units and send the shaping results to the first logic gate units and the second logic gate units.

[0015] According to one embodiment of the present invention, the circuit further includes: N registers, each of the N registers being connected to one of the N second logic gate units in a one-to-one correspondence, and each of the N registers being connected to the identification unit. The registers are used to receive the output signal of the second logic gate unit when a trigger signal is received at the trigger terminal of the register, and to output the output signal of the second logic gate unit to the identification unit.

[0016] According to one embodiment of the present invention, when the signal to be identified is a positive pulse width signal, the trigger terminal is the negative edge trigger terminal of the clock of the register, and the trigger signal is the falling edge of the signal to be identified; when the signal to be identified is a negative pulse width signal, the trigger terminal is the positive edge trigger terminal of the clock of the register, and the trigger signal is the rising edge of the signal to be identified. The circuit further includes: a buffer, the buffer being connected to the trigger terminals of N registers and the input pin of the signal identification circuit, the buffer being used to delay sending the signal to be identified to the trigger terminal of the register when the signal to be identified is received, so that the trigger signal in the signal to be identified triggers the register to receive the output signal of the second logic gate unit and outputs the output signal to the identification unit.

[0017] To achieve the above objectives, a second aspect of the present invention provides a system-on-a-chip including the signal recognition circuit described above.

[0018] According to embodiments of the present invention, a signal recognition circuit and a system-on-a-chip include N bandpass filter units, N-1 first logic gate units, N second logic gate units, and a recognition unit, where N is a positive integer greater than or equal to 3. The N bandpass filter units are connected one-to-one with the N second logic gate units. The i-th first logic gate unit is connected to the i-th bandpass filter unit, the (i+1)-th bandpass filter unit, the i-th second logic gate unit, and the (i+1)-th second logic gate unit, where i is a positive integer greater than 0 and less than N. The recognition unit is connected to the N second logic gate units. The bandpass filter units perform bandpass filtering on the received signal to be recognized and send the filtering result to the second logic gate units and the first logic gate units. The first logic gate units perform a first logic operation on the received signal. The second logic gate units perform a second logic operation on the output signal of the first logic gate unit and the filtering result. The recognition unit obtains the identity recognition result of the signal to be recognized based on the output signals of the N second logic gate units. Therefore, by setting the aforementioned first logic gate unit and connecting the i-th first logic gate unit to the i-th bandpass filter unit and the (i+1)-th bandpass filter unit, it is possible to distinguish between two cases: the signal to be identified is within the effective frequency range of one bandpass filter, and the signal to be identified is within the effective frequency range of two bandpass filters. This allows for partial overlap of the effective frequency ranges of different bandpass filters, improving bandwidth utilization and avoiding resource waste. Furthermore, by setting the aforementioned second logic gate unit and connecting the i-th first logic gate unit to the i-th second logic gate unit and the (i+1)-th second logic gate unit, since the second logic gate unit is connected one-to-one with the bandpass filter unit, the output signal of the first logic gate unit is converted into an output signal corresponding one-to-one with the bandpass filter unit. This allows the identification unit to easily and directly determine which bandpass filter unit the signal to be identified passed through based on the output of the second logic gate unit, thereby obtaining the identification result of the signal to be identified.

[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a signal recognition circuit according to an embodiment of the present invention;

[0021] Figure 2 This is a circuit diagram of a signal recognition circuit according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the operation of a signal recognition circuit according to an embodiment of the present invention;

[0023] Figure 4 This is a structural block diagram of a system-on-a-chip according to an embodiment of the present invention. Detailed Implementation

[0024] The signal recognition circuit and system-on-a-chip of embodiments of the present invention are described below with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described with reference to the accompanying drawings are exemplary and should not be construed as limiting the present invention.

[0025] Figure 1 This is a schematic diagram of the signal recognition circuit according to an embodiment of the present invention.

[0026] like Figure 1 As shown, the signal recognition circuit 100 includes: N bandpass filter units 101, N second logic gate units 102, N-1 first logic gate units 103, and a recognition unit 108, where N is a positive integer greater than or equal to 3. The N bandpass filter units 101 are connected one-to-one with the N second logic gate units 102. The i-th first logic gate unit 103 is connected to the second output terminals of the i-th bandpass filter unit 101, the (i+1)-th bandpass filter unit 101, the i-th second logic gate unit 102, and the (i+1)-th second logic gate unit 102, where i is a positive integer greater than 0 and less than N. The identification unit 108 is connected to N second logic gate units 102; wherein, the bandpass filter unit 101 is used to perform bandpass filtering on the received signal to be identified, and send the filtering result to the second logic gate unit 102 and the first logic gate unit 103. The first logic gate unit 103 is used to perform a first logic operation on the received signal, and the second logic gate unit 102 is used to perform a second logic operation on the output signal of the first logic gate unit 103 and the filtering result. The identification unit 108 is used to obtain the identification result of the signal to be identified based on the output signals of the N second logic gate units 102.

[0027] It should be noted that, Figure 1 The signal recognition circuit 100 also includes an input pin 104. The signal to be recognized is input to N bandpass filter units 101 through the input pin 104. In practical applications, it is not limited to the input pin 104. It is sufficient to enable the signal to be recognized to be input to N bandpass filter units 101 at the same time.

[0028] Specifically, in order to identify the signal to be identified, N bandpass filter units 101 are set in the signal identification circuit 100. Different bandpass filter units 101 have different effective frequency ranges. Therefore, when the same signal to be identified is input into N bandpass filter units 101, the different bandpass filter units 101 will have different filtering capabilities for the signal to be identified because of their different effective frequency ranges.

[0029] The aforementioned effective frequency range refers to the frequency range where the output signal strength of the bandpass filter unit 101 is greater than a preset threshold. The preset threshold refers to the signal strength threshold at which the signal can be recognized by the subsequent circuitry of the bandpass filter unit 101. In other words, for the i-th bandpass filter unit 101, if the frequency of the signal to be recognized is within the effective frequency range of the i-th bandpass filter unit 101, then the signal to be recognized can be recognized by the subsequent circuitry after passing through the i-th bandpass filter unit 101; if the frequency of the signal to be recognized is not within the effective frequency range of the i-th bandpass filter unit 101, then the signal to be recognized cannot effectively pass through the i-th bandpass filter unit 101, that is, after passing through the i-th bandpass filter unit 101, the signal strength will be attenuated to the point where it cannot be recognized by the subsequent circuitry.

[0030] However, if only the bandpass filter unit 101 is used, in order to ensure accurate identification, the effective frequency ranges of the two bandpass filters must not overlap, resulting in low utilization of frequency band resources.

[0031] Therefore, in order to avoid wasting resources, the signal recognition circuit 100 is designed to include N second logic gate units 102 and N-1 first logic gate units 103. Moreover, the N bandpass filter units 101 are connected one-to-one with the N second logic gate units 102, and the i-th first logic gate unit 103 is connected to the i-th bandpass filter unit 101, the (i+1)-th bandpass filter unit 101, the i-th second logic gate unit 102 and the (i+1)-th second logic gate unit 102.

[0032] Let's take N=3 as an example for illustration.

[0033] At this time, the first logic gate unit 103 is connected to the first bandpass filter unit 101, the second bandpass filter unit 101, the first second logic gate unit 102, and the second second logic gate unit 102. The second logic gate unit 103 is connected to the second bandpass filter unit 101, the third bandpass filter unit 101, the second second logic gate unit 102, and the third second logic gate unit 102. Since the N bandpass filter units 101 are connected one-to-one with the N second logic gate units 102, the first bandpass filter unit 101 is connected to the first second logic gate unit 102, the second bandpass filter unit 101 is connected to the second second logic gate unit 102, and the third bandpass filter unit 101 is connected to the third second logic gate unit 102.

[0034] When the signal to be identified is input, the signal to be identified will be simultaneously input to the first bandpass filter unit 101, the second bandpass filter unit 101, and the third bandpass filter unit 101.

[0035] At this time, when the frequency of the signal to be identified is only within the effective frequency range of the second bandpass filter unit 101, the signal to be identified passes through the second bandpass filter unit 101 but does not pass through the first and third bandpass filter units 101, making the input signal states of the first logic gate unit 103 and the second logic gate unit 103 consistent, thereby making the output signal states of the first logic gate unit 103 and the second logic gate unit 103 consistent.

[0036] When the frequency of the signal to be identified is within the effective frequency range of the first bandpass filter unit 101 and the second bandpass filter unit 101, the signal to be identified will pass through the first bandpass filter unit 101 and the second bandpass filter unit 101, but will not pass through the third bandpass filter unit 101. This causes the output signal states of the first logic gate unit 103 and the second logic gate unit 103 to be inconsistent, thereby making the output signal states of the first logic gate unit 103 and the second logic gate unit 103 consistent.

[0037] When the frequency of the signal to be identified is not within the range of the first bandpass filter unit 101, the second bandpass filter unit 101 and the third bandpass filter unit 101, since no signal passes through the bandpass filter unit 101, the output signal state of the first logic gate unit 103 is the state when no signal passes through.

[0038] In other words, by setting the first logic gate unit 103 and connecting the i-th first logic gate unit 103 to the i-th bandpass filter unit 101 and the (i+1)-th bandpass filter unit 101, it is possible to distinguish between two cases: the signal to be identified is within the effective frequency range of one bandpass filter and the signal to be identified is within the effective frequency range of two bandpass filters. This enables support for partial overlap of the effective frequency ranges of different bandpass filter units 101, thereby improving bandwidth utilization and avoiding resource waste.

[0039] However, since the first logic gate unit 103 does not correspond to the bandpass filter unit 101, if only the first logic gate unit 103 is used, it will be difficult to determine which bandpass filter units 101 the signal to be identified has passed through, even if it is known whether a signal has passed through the bandpass filter unit 101 and how many bandpass filter units 101 the signal has passed through, making it difficult to determine the identity of the signal to be identified.

[0040] Therefore, the aforementioned second logic gate unit 102 is configured, and the i-th first logic gate unit 103 is configured to connect the i-th second logic gate unit 102 and the (i+1)-th second logic gate unit 102. Since the second logic gate unit 102 is connected one-to-one with the bandpass filter unit 101, and the signal state output by the second logic gate unit 102 will also differ when the first logic gate unit 103 outputs signals of different states, the second logic gate unit 102 is configured to convert the output signal of the first logic gate unit 103 into an output signal that corresponds one-to-one with the bandpass filter unit 101 while retaining the output signal state of the first logic gate unit 103. This allows the identification unit 108 to easily and directly determine which bandpass filter unit 101 the signal to be identified passed through based on the output of the second logic gate unit 102, thereby obtaining the identification result of the signal to be identified.

[0041] As a specific embodiment, the settings of the second logic gate unit 102 and the first logic gate unit 103 can be configured according to the type of the signal to be identified. When the signal to be identified is a positive pulse width signal, the first logic operation is an XOR operation and the second logic operation is an AND operation; when the signal to be identified is a negative pulse width signal, the first logic operation is an XNOR operation and the second logic operation is an OR operation.

[0042] For example, when the signal to be identified is a positive pulse width signal, the second logic gate unit 102 includes an AND gate and the first logic gate unit 103 includes an XOR gate; when the signal to be identified is a negative pulse width signal, the second logic gate unit 102 includes an OR gate and the first logic gate unit 103 includes an XNOR gate.

[0043] The following description uses a specific example.

[0044] In this specific embodiment, when the first logic gate unit 103 performs an XOR operation on the signal input to the first logic gate unit 103, the second logic gate unit 102 performs an AND operation on the signal input to the second logic gate unit 102. For example, the first logic gate unit 103 is an XOR gate, the second logic gate unit 102 is an AND gate, the bandpass filter unit 101 is a bandpass filter, the signal to be identified is a positive pulse width signal, and N=3.

[0045] Specifically, if the signal to be identified is only within the effective frequency range of the second bandpass filter unit 101, then the signal to be identified will only pass through the second bandpass filter unit 101. Since the signal to be identified is a positive pulse width signal, when the signal to be identified is at a high level, the output signal of the second bandpass filter unit 101 is at a high level, and the output signals of the first bandpass filter unit 101 and the second bandpass filter unit 101 are both at a low level. At this time, the first logic gate unit 103 and the second logic gate unit 103 will both output a high level due to different inputs, the first logic gate unit 102 will output 0, the second logic gate unit 102 will output 1, and the second logic gate unit 102 will output 0.

[0046] If the signal to be identified is within the effective frequency range of the first bandpass filter unit 101 and the second bandpass filter unit 101, then the signal to be identified passes through the first bandpass filter unit 101 and the second bandpass filter unit 101, but does not pass through the third bandpass filter unit 101. When the signal to be identified is at a high level, the output signals of the first bandpass filter unit 101 and the second bandpass filter unit 101 are high, and the output signal of the third bandpass filter unit 101 is low. At this time, the first logic gate unit 103 will output a low level because the inputs are the same, the second logic gate unit 103 will output a high level because the inputs are different, the first logic gate unit 102 will output 0, the second logic gate unit 102 will output 0, and the third logic gate unit 102 will output 0.

[0047] If the signal to be identified is not within the effective frequency range of any of the three bandpass filter units 101, the outputs of the three bandpass filter units 101 are all 0. The first logic gate unit 103 and the second logic gate unit 103 are both XOR gates. Therefore, when the outputs of the three bandpass filter units 101 are all 0, both input terminals of the first logic gate unit 103 will input 0, and both input terminals of the second logic gate unit 103 will also input 0. In this case, the first logic gate unit 103 and the second logic gate unit 103 will both output a low level because the inputs are the same, and thus all three second logic gate units 102 will output 0.

[0048] It can be seen that the second logic gate unit 102 will output 1 only when the signal to be identified is within the effective frequency range of the second bandpass filter unit 101. In other cases, all three second logic gate units 102 will output 0. This means that when the second logic gate unit 102 outputs 1, it is determined that the signal to be identified only passes through the second bandpass filter, thereby enabling the identification of the signal to be identified.

[0049] Therefore, by setting the aforementioned first logic gate unit 103 and connecting the i-th first logic gate unit 103 to the i-th bandpass filter unit 101 and the (i+1)-th bandpass filter unit 101, it is possible to distinguish between two cases: the signal to be identified is within the effective frequency range of one bandpass filter and the signal to be identified is within the effective frequency range of two bandpass filters. This allows for partial overlap of the effective frequency ranges of different bandpass filters, improving bandwidth utilization and avoiding resource waste. Furthermore, by setting the aforementioned second logic gate unit 102 and connecting the i-th first logic gate unit 103 to the i-th second logic gate unit 102 and the (i+1)-th second logic gate unit 102, since the second logic gate unit 102 is connected one-to-one with the bandpass filter unit 101, the output signal of the first logic gate unit 103 is converted into an output signal corresponding one-to-one with the bandpass filter unit 101. This allows the identification unit 108 to easily and directly determine which bandpass filter unit 101 the signal to be identified passed through based on the output of the second logic gate unit 102, thereby obtaining the identification result of the signal to be identified.

[0050] In some embodiments of the present invention, the upper limit of the effective frequency range of the (i-1)th bandpass filter unit 101 is the minimum frequency value of the center frequency window of the ith bandpass filter unit 101, and the lower limit of the effective frequency range of the (i+1)th bandpass filter unit 101 is the maximum frequency value of the center frequency window of the ith bandpass filter unit 101. The center frequency window of the ith bandpass filter unit 101 is a preset frequency window within the effective frequency range of the ith bandpass filter unit 101, and the effective frequency range of the ith bandpass filter unit is the frequency range in which the output signal strength of the ith bandpass filter unit is greater than a preset threshold.

[0051] The upper limit of the effective frequency range is the maximum value of the effective frequency range of the bandpass filter unit 101. That is, if the frequency of the signal to be identified is higher than the upper limit of the effective frequency range of the i-th bandpass filter unit 101, the signal to be identified will not pass through the i-th bandpass filter unit 101 effectively. The lower limit of the effective frequency range is the minimum value of the effective frequency range of the bandpass filter unit 101. That is, if the frequency of the signal to be identified is lower than the lower limit of the effective frequency range of the i-th bandpass filter unit 101, the signal to be identified will not pass through the i-th bandpass filter unit 101 effectively. After passing through the i-th bandpass filter unit 101, the signal to be identified will attenuate to the point that it cannot be identified by subsequent circuits.

[0052] Specifically, for each bandpass filter unit 101, a center frequency window is set. This center frequency window is within the effective frequency range of the bandpass filter unit 101. Moreover, for the i-th bandpass filter unit 101, the upper limit of the effective frequency range of the (i-1)-th bandpass filter unit 101 is the minimum frequency value of the center frequency window of the i-th bandpass filter unit 101, and the lower limit of the effective frequency range of the (i+1)-th bandpass filter unit 101 is the maximum frequency value of the center frequency window of the i-th bandpass filter unit 101.

[0053] At this time, referring to the first logic gate unit 103 used to perform an XOR operation on the signal input to the first logic gate unit 103, the second logic gate unit 102 used to perform an AND operation on the signal input to the second logic gate unit 102. For example, the first logic gate unit 103 is an XOR gate, the second logic gate unit 102 is an AND gate, the above-mentioned bandpass filter unit 101 is a bandpass filter, and the above-mentioned signal to be identified is a positive pulse width signal. In a specific embodiment where N=3, when the signal to be identified is within the center frequency window range of the second bandpass filter unit 101, the second second logic gate unit 102 outputs 1. When the signal to be identified is within the effective frequency range of the second bandpass filter unit 101 but not within the center frequency range of the second bandpass filter unit 101, all three second logic gate units 102 will output 0.

[0054] As can be seen, the above-mentioned center frequency range is the effective signal frequency range of the signal to be identified. That is, when the frequency of the signal to be identified falls within the center frequency range of any bandpass filter unit 101, the signal to be identified is an effective signal.

[0055] In some embodiments of the present invention, the lower limit of the effective frequency range of the (i-1)th bandpass filter unit 101 is the maximum frequency value of the center frequency window of the i-th bandpass filter unit 101, and the upper limit of the effective frequency range of the (i+1)th bandpass filter unit 101 is the minimum frequency value of the center frequency window of the i-th bandpass filter unit 101. The center frequency window of the i-th bandpass filter unit 101 is a preset frequency window within the effective frequency range of the i-th bandpass filter unit 101, and the effective frequency range of the i-th bandpass filter unit is the frequency range in which the output signal strength of the i-th bandpass filter unit is greater than a preset threshold.

[0056] In some embodiments of the present invention, the identification unit 108 is specifically used to: when a preset signal exists in the output signals of the N second logic gate units 102, obtain the identification result of the signal to be identified according to the target second logic gate unit 102 that outputs the preset signal; when the preset signal does not exist in the output signals of the N second logic gate units 102, identify the signal to be identified as an invalid signal.

[0057] Continuing with the example where the first logic gate unit 103 is used to perform an XOR operation on the signal input to the first logic gate unit 103, and the second logic gate unit 102 is used to perform an AND operation on the signal input to the second logic gate unit 102, for example, the first logic gate unit 103 is an XOR gate, the second logic gate unit 102 is an AND gate, the bandpass filter unit 101 is a bandpass filter, the signal to be identified is a positive pulse width signal, and N=3, a specific embodiment will be described.

[0058] As shown above, when the signal to be identified is only within the effective frequency range of the second bandpass filter unit 101, the second second logic gate unit 102 will output 1. In other cases, all three second logic gate units 102 will output 0. In this case, the aforementioned preset signal is 1. Therefore, when the signal to be identified is only within the effective frequency range of the second bandpass filter unit 101, the preset signal 1 is present in the output signals of the three second logic gate units 102. The second second logic gate unit 102 that outputs the preset signal 1 is identified as the target second logic gate unit 102, and the identification result is obtained based on the target second logic gate unit 102. In other cases, all three second logic gate units 102 will output 0. When the preset signal is not present in the output signals of the three second logic gate units 102, the signal to be identified is identified as an invalid signal.

[0059] In some embodiments of the present invention, the identification unit 108 is further configured to: when a preset signal exists in the output signals of the N second logic gate units 102, determine the target bandpass filter unit 101 according to the target second logic gate unit 102, query the preset bandpass filter unit 101-signal identity correspondence table according to the target bandpass filter unit 101, and obtain the identity recognition result of the signal to be identified, wherein the target bandpass filter unit 101 is a bandpass filter unit 101 connected to the target second logic gate unit 102.

[0060] Specifically, as described above, the upper limit of the effective frequency range of the (i-1)th bandpass filter unit 101 is set to the minimum frequency value of the center frequency window of the ith bandpass filter unit 101, and the lower limit of the effective frequency range of the (i+1)th bandpass filter unit 101 is set to the maximum frequency value of the center frequency window of the ith bandpass filter unit 101. Alternatively, the lower limit of the effective frequency range of the (i-1)th bandpass filter unit 101 is set to the maximum frequency value of the center frequency window of the ith bandpass filter unit 101, and the upper limit of the effective frequency range of the (i+1)th bandpass filter unit 101 is set to the minimum frequency value of the center frequency window of the ith bandpass filter unit 101.

[0061] However, in practical applications, when configuring the bandpass filter unit 101, it cannot be guaranteed that the cutoff frequency of one bandpass filter unit 101 will fall exactly on the boundary of the center frequency window of its adjacent bandpass filter unit 101. This can lead to a difference between the actual center frequency window of the bandpass filter unit 101 and its theoretical center frequency window. For example, assuming that theoretically the upper limit of the effective frequency range of the (i-1)th bandpass filter unit 101 is the minimum frequency of the center frequency window of the ith bandpass filter unit 101, but in reality the effective frequency range of the (i-1)th bandpass filter unit 101... If the upper limit of the effective frequency range of the (i-1)th bandpass filter unit 101 is slightly smaller than the minimum frequency value of the center frequency window of the i-th bandpass filter unit 101, then if the signal to be identified falls within the frequency range between the upper limit of the effective frequency range of the (i-1)th bandpass filter unit 101 and the minimum frequency value of the center frequency window of the i-th bandpass filter unit 101, the signal to be identified can only pass through the i-th bandpass filter unit 101. That is, the frequency range between the upper limit of the effective frequency range of the (i-1)th bandpass filter unit 101 and the minimum frequency value of the center frequency window of the i-th bandpass filter unit 101 will actually become the center frequency window of the i-th bandpass filter unit 101.

[0062] At this time, in order to avoid the identification error of the signal to be identified caused by the inconsistency between the actual center frequency window and the theoretical center frequency window, a bandpass filter unit 101-signal identity correspondence table is set in advance. That is, the identity of the signal to be identified is identified by the bandpass filter unit 101 through which the signal to be identified passes, thereby avoiding the identification error of the signal to be identified caused by the inconsistency between the actual center frequency window and the theoretical center frequency window.

[0063] Continuing with the example where the first logic gate unit 103 is used to perform an XOR operation on the signal input to the first logic gate unit 103, and the second logic gate unit 102 is used to perform an AND operation on the signal input to the second logic gate unit 102, for example, the first logic gate unit 103 is an XOR gate, the second logic gate unit 102 is an AND gate, the bandpass filter unit 101 is a bandpass filter, the signal to be identified is a positive pulse width signal, and N=3, a specific embodiment will be described.

[0064] Specifically, a pre-set bandpass filter unit 101-signal identity correspondence table is configured. For example, the first bandpass filter unit 101 corresponds to the first signal identity, the second bandpass filter unit 101 corresponds to the second signal identity, and the third bandpass filter unit 101 corresponds to the third signal identity. In this case, when the signal to be identified is only within the effective frequency range of the second bandpass filter unit 101, the second second logic gate unit 102 will output 1, and the second second logic gate unit 102 that outputs the preset signal 1 is determined to be the target second logic gate unit 102. Then, the identity recognition result of the signal to be identified is obtained by looking up the table as the second signal identity.

[0065] In some embodiments of the present invention, the signal recognition circuit 100 further includes: N Schmitt trigger units, which are connected one-to-one with N bandpass filter units 101 and one-to-one with N second logic gate units 102; the first Schmitt trigger unit is connected to the first first logic gate unit 103; the Nth Schmitt trigger unit is connected to the (N-1)th first logic gate unit 103; and the jth Schmitt trigger unit is connected to the (j-1)th and jth first logic gate units 103, where j is a positive integer greater than 1 and less than N; the Schmitt trigger units are used to perform shaping operations on the output signal of the bandpass filter unit 101 and send the shaping result to the second logic gate unit 102 and the first logic gate unit 103.

[0066] Specifically, because a bandpass filter unit 101 is used, the signal recognition circuit 100 can be applied to both analog and digital signals. In order to improve the signal recognition accuracy when the signal to be recognized is an analog signal, a Schmitt trigger is configured for each bandpass filter unit 101. The Schmitt trigger is used to shape the output signal of the bandpass filter unit 101, converting the analog signal output by the bandpass filter unit 101 into a digital signal, thereby further improving the accuracy of the identification of the signal to be recognized.

[0067] In some embodiments of the present invention, the signal recognition circuit 100 further includes: N registers, each of which is connected to one of the N second logic gate units 102. All N registers are connected to the recognition unit 108. The registers are used to receive the output signal of the second logic gate unit 102 when a trigger signal is received at the trigger terminal of the register, and to output the output signal of the second logic gate unit 102 to the recognition unit 108.

[0068] In some embodiments of the present invention, when the signal to be identified is a positive pulse width signal, the trigger terminal is the negative edge trigger terminal of the register's clock, and the trigger signal is the falling edge of the signal to be identified. When the signal to be identified is a negative pulse width signal, the trigger terminal is the positive edge trigger terminal of the register's clock, and the trigger signal is the rising edge of the signal to be identified. The signal identification circuit 100 further includes a buffer, which connects the trigger terminals of N registers and the input pin 104 of the signal identification circuit 100. The buffer is used to delay sending the signal to be identified to the trigger terminal of the register when the signal to be identified is received, so that the trigger signal in the signal to be identified triggers the register to receive the output signal of the second logic gate unit 102 and outputs the output signal to the identification unit 108.

[0069] Specifically, the input terminal of the signal recognition circuit 100 is set to an input pin 104. The signal to be recognized is not only input to N bandpass filter units 101 through the input pin 104, but also input to the buffer through the input pin 104, and then input to the trigger terminal of the register after being buffered by the buffer.

[0070] The above-mentioned signal to be identified also includes a trigger signal. When the signal to be identified is input to the register after being delayed by the buffer, the trigger signal in the signal to be identified will trigger the register to receive the output signal of the second logic gate unit 102 and output the output signal to the identification unit 108.

[0071] In some embodiments of the present invention, when the signal to be identified is a positive pulse width signal, the second logic gate unit 102 is used to perform an AND operation on the signal input to the second logic gate unit 102. For example, the second logic gate unit 102 can be set as an AND gate, and the first logic gate unit 103 is used to perform an XOR operation on the signal input to the first logic gate unit 103. For example, the first logic gate unit 103 can be set as an XOR gate, the trigger terminal is the negative edge trigger terminal of the register clock, and the trigger signal is the falling edge of the signal to be identified. When the signal to be identified is a negative pulse width signal, the second logic gate unit 102 is used to perform an OR operation on the signal input to the second logic gate unit 102. For example, the second logic gate unit 102 can be set as an OR gate, and the first logic gate unit 103 is used to perform an XNOR operation on the signal input to the first logic gate unit 103. For example, the first logic gate unit 103 can be set as an XNOR gate, the trigger terminal is the positive edge trigger terminal of the register clock, and the trigger signal is the rising edge of the signal to be identified.

[0072] The following description uses a specific example.

[0073] In this specific embodiment, the input signal can be either a positive pulse width signal or a negative pulse width signal. The signal recognition circuit 100 is a circuit within the system-on-a-chip (SoC), therefore, the input terminal of the signal recognition circuit 100 is the SoC input pin 104. The bandpass filter unit 101 is a bandpass filter. N is a positive integer greater than 7.

[0074] When the signal to be identified is a positive pulse width signal, the second logic gate unit 102 is an AND gate, the first logic gate unit 103 is an XOR gate, the trigger terminal is the negative edge trigger terminal of the register clock, and the trigger signal is the falling edge of the signal to be identified.

[0075] At this time, see Figure 2 Using N bandpass filters and Schmitt trigger units for shaping, N preprocessed signals are obtained. Figure 2 In the diagram, 107 represents the aforementioned buffer. Following the top-to-bottom order, the first row's bandpass filter unit 101, Schmitt unit 105, and register 106 are bandpass filter 1, Schmitt unit 1, and register 1, respectively. The second row's bandpass filter unit 101, Schmitt unit 105, and register 106 are bandpass filter 2, Schmitt unit 2, and register 2, respectively. The third row's bandpass filter unit 101, Schmitt unit 105, and register 106 are bandpass filter 3, Schmitt unit 3, and register 2, respectively. Register 3, and so on, the bandpass filter unit 101, Schmitt unit 105, and register 106 in the i-th row are bandpass filter i, Schmitt unit i, and register i, respectively; the bandpass filter unit 101, Schmitt unit 105, and register 106 in the second-to-last row are bandpass filter N-1, Schmitt unit N-1, and register N-1, respectively; and the bandpass filter unit 101, Schmitt unit 105, and register 106 in the last row are bandpass filter N, Schmitt unit N, and register N, respectively.

[0076] The relationship between the above bandpass filter and the target digital signal can be found in [reference needed]. Figure 3 ,exist Figure 3 In this context, boundary gain refers to the condition where, if the gain of a bandpass filter at a certain frequency is less than the boundary gain, then the signal at that frequency cannot effectively pass through the bandpass filter.

[0077] Bandpass filters with adjacent passband frequencies can have small frequency spacing and a large frequency overlap range, allowing the frequency at the boundary gain of each filter to be close to the center frequency window of the adjacent filter. This increases the number of target digital signals allowed within a certain frequency range.

[0078] To avoid simultaneous triggering or identification of target digital signals corresponding to two adjacent bandpass filters within the effective frequency range, a digital processing method is employed. The preprocessed signal i is XORed with its adjacent preprocessed signals i-1 and i+1. If both XOR results are 1, it indicates that the signal to be identified is within the center frequency window and pulse width window corresponding to the target digital signal i, indicating a valid input signal. This enables the relevant preprocessed signals to be sent to the data input of the register, and the data input of the i-th register receives a valid value of 1. If any XOR result is 0, it indicates that the input signal to be identified is not within the center frequency window or pulse width window corresponding to any of the target digital signals, but rather lies between the center frequency windows and pulse width windows corresponding to two adjacent bandpass filters. This determines the signal to be identified to be invalid, and an invalid value of 0 is sent to the data input of the corresponding register. The pulse width window mentioned above is obtained based on the center frequency window.

[0079] After the input signal to be identified is connected to a first-level buffer 107, the output of buffer 107 is connected to the negative edge trigger of the clock of each register, so that the processing of the signal to be identified is completed before the falling edge of the signal to be identified reaches the register, and the register setup time is satisfied. In this way, after the input pulse width ends, after the delay of buffer 107, N target digital signals can be obtained by sampling from N registers. The sampling result is a level signal, which is friendly to low-frequency applications and low-power clockless mode applications.

[0080] When it is necessary to clear the valid target digital signal from the previous moment, a pulse width outside the specified frequency band can be sent.

[0081] When the signal to be identified is a negative pulse width signal, the second logic gate unit 102 is an OR gate, the first logic gate unit 103 is an XNOR gate, the trigger terminal is the positive edge trigger terminal of the register clock, and the trigger signal is the rising edge of the signal to be identified. At this time, the aforementioned preset signal is 0.

[0082] In summary, the signal recognition circuit of this embodiment includes N bandpass filter units, N-1 first logic gate units, N second logic gate units, and a recognition unit, where N is a positive integer greater than or equal to 3. The N bandpass filter units are connected one-to-one with the N second logic gate units. The i-th first logic gate unit is connected to the i-th bandpass filter unit, the (i+1)-th bandpass filter unit, the i-th second logic gate unit, and the (i+1)-th second logic gate unit, where i is a positive integer greater than 0 and less than N. The recognition unit is connected to the N second logic gate units. The bandpass filter units are used to perform bandpass filtering on the received signal to be recognized and send the filtering result to the second logic gate units and the first logic gate units. The first logic gate units are used to perform a first logic operation on the received signal. The second logic gate units are used to perform a second logic operation on the output signal of the first logic gate unit and the filtering result. The recognition unit is used to obtain the identity recognition result of the signal to be recognized based on the output signals of the N second logic gate units. Therefore, by setting the aforementioned first logic gate unit and connecting the i-th first logic gate unit to the i-th bandpass filter unit and the (i+1)-th bandpass filter unit, it is possible to distinguish between two cases: the signal to be identified is within the effective frequency range of one bandpass filter, and the signal to be identified is within the effective frequency range of two bandpass filters. This allows for partial overlap of the effective frequency ranges of different bandpass filters, improving bandwidth utilization and avoiding resource waste. Furthermore, by setting the aforementioned second logic gate unit and connecting the i-th first logic gate unit to the i-th second logic gate unit and the (i+1)-th second logic gate unit, since the second logic gate unit is connected one-to-one with the bandpass filter unit, the output signal of the first logic gate unit is converted into an output signal corresponding one-to-one with the bandpass filter unit. This allows the identification unit to easily and directly determine which bandpass filter unit the signal to be identified passed through based on the output of the second logic gate unit, thereby obtaining the identification result of the signal to be identified.

[0083] Furthermore, this invention proposes a system-on-a-chip.

[0084] Figure 4 This is a structural block diagram of a system-on-a-chip according to an embodiment of the present invention.

[0085] like Figure 4 As shown, the system-on-chip 10 includes the signal recognition circuit 100 described above.

[0086] The on-chip system of this invention, through the signal recognition circuit of the above embodiment, by setting the aforementioned first logic gate unit and connecting the i-th first logic gate unit to the i-th bandpass filter unit and the (i+1)-th bandpass filter unit, can distinguish between two cases: the signal to be identified is within the effective frequency range of one bandpass filter and the signal to be identified is within the effective frequency range of two bandpass filters. This achieves partial overlap of the effective frequency ranges of different bandpass filters, improving bandwidth utilization and avoiding resource waste. Furthermore, by setting the aforementioned second logic gate unit and connecting the i-th first logic gate unit to the i-th second logic gate unit and the (i+1)-th second logic gate unit, since the second logic gate unit is connected one-to-one with the bandpass filter unit, the output signal of the first logic gate unit is converted into an output signal corresponding one-to-one with the bandpass filter unit. This allows the recognition unit to easily and directly determine which bandpass filter unit the signal to be identified passed through based on the output of the second logic gate unit, thereby obtaining the identification result of the signal to be identified.

[0087] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein can be considered as a ordered list of executable instructions for implementing logical functions, which can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0088] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0089] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0090] In the description of this specification, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as limiting the present invention.

[0091] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0092] In this specification, unless otherwise stated, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly defined. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0093] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0094] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A signal recognition circuit, characterized in that, The circuit includes an identification unit, N bandpass filter units, N-1 first logic gate units, and N second logic gate units, where N is a positive integer greater than or equal to 3. The N bandpass filter units are connected one-to-one with the N second logic gate units. The i-th first logic gate unit is connected to the i-th bandpass filter unit, the (i+1)-th bandpass filter unit, the i-th second logic gate unit, and the (i+1)-th second logic gate unit, where i is a positive integer greater than 0 and less than N. The identification unit is connected to the N second logic gate units. The bandpass filtering unit is used to perform bandpass filtering on the received signal to be identified, and send the filtering result to the first logic gate unit and the second logic gate unit. The first logic gate unit is used to perform a first logic operation on the received signal, and the second logic gate unit is used to perform a second logic operation on the output signal of the first logic gate unit and the filtering result. The identification unit is used to obtain the identification result of the signal to be identified based on the output signals of N second logic gate units. When the signal to be identified is a positive pulse width signal, the first logical operation is an XOR operation, and the second logical operation is an AND operation; When the signal to be identified is a negative pulse width signal, the first logical operation is an XNOR operation, and the second logical operation is an OR operation; The upper limit of the effective frequency range of the (i-1)th bandpass filter unit is the minimum frequency value of the center frequency window of the ith bandpass filter unit, and the lower limit of the effective frequency range of the (i+1)th bandpass filter unit is the maximum frequency value of the center frequency window of the ith bandpass filter unit. The center frequency window of the ith bandpass filter unit is a preset frequency window within the effective frequency range of the ith bandpass filter unit, and the effective frequency range of the ith bandpass filter unit is the frequency range within which the output signal strength of the ith bandpass filter unit is greater than a preset threshold.

2. The signal recognition circuit according to claim 1, characterized in that, The identification unit is specifically used for: When a preset signal exists among the output signals of the N second logic gate units, the identity recognition result of the signal to be identified is obtained according to the target second logic gate unit that outputs the preset signal. When the preset signal is not present in the output signals of the N second logic gate units, the signal to be identified is identified as an invalid signal.

3. The signal recognition circuit according to claim 2, characterized in that, The identification unit is further configured to: When a preset signal exists among the output signals of the N second logic gate units, a target bandpass filter unit is determined according to the target second logic gate unit. The preset bandpass filter unit-signal identity correspondence table is queried according to the target bandpass filter unit to obtain the identity recognition result of the signal to be identified. The target bandpass filter unit is the bandpass filter unit connected to the target second logic gate unit.

4. The signal recognition circuit according to claim 1, characterized in that, The lower limit of the effective frequency range of the (i-1)th bandpass filter unit is the maximum frequency value of the center frequency window of the ith bandpass filter unit, and the upper limit of the effective frequency range of the (i+1)th bandpass filter unit is the minimum frequency value of the center frequency window of the ith bandpass filter unit. The center frequency window of the ith bandpass filter unit is a preset frequency window within the effective frequency range of the ith bandpass filter unit, and the effective frequency range of the ith bandpass filter unit is the frequency range in which the output signal strength of the ith bandpass filter unit is greater than a preset threshold.

5. The signal recognition circuit according to claim 1, characterized in that, The circuit also includes: There are N Schmitt trigger units, each of which is connected to one of the N bandpass filter units and to one of the N second logic gate units. The first Schmitt trigger unit is connected to the first first logic gate unit, the Nth Schmitt trigger unit is connected to the (N-1)th first logic gate unit, and the jth Schmitt trigger unit is connected to the (j-1)th and jth first logic gate units, where j is a positive integer greater than 1 and less than N. The Schmitt trigger unit is used to shape the output signal of the bandpass filter unit and send the shaping result to the first logic gate unit and the second logic gate unit.

6. The signal recognition circuit according to claim 1, characterized in that, The circuit also includes: There are N registers, each of which is connected to one of the N second logic gate units. All N registers are connected to the identification unit. When a trigger signal is received at the trigger terminal of the register, the register receives the output signal of the second logic gate unit and outputs the output signal of the second logic gate unit to the identification unit.

7. The signal recognition circuit according to claim 6, characterized in that, When the signal to be identified is a positive pulse width signal, the trigger terminal is the negative edge trigger terminal of the register's clock, and the trigger signal is the falling edge of the signal to be identified. When the signal to be identified is a negative pulse width signal, the trigger terminal is the positive edge trigger terminal of the register's clock, and the trigger signal is the rising edge of the signal to be identified. The circuit further includes: A buffer is provided, which connects the trigger terminals of N registers to the input pin of the signal recognition circuit. When the signal to be recognized is received, the buffer delays the transmission of the signal to be recognized to the trigger terminal of the register, so that the trigger signal in the signal to be recognized triggers the register to receive the output signal of the second logic gate unit and outputs the output signal to the recognition unit.

8. A system-on-a-chip, characterized in that, Includes the signal recognition circuit according to any one of claims 1-7.

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