UCIe-based data transmission methods, storage media, and artificial intelligence chips

Abstract

This disclosure provides a UCIe-based data transmission method, storage medium, and artificial intelligence chip. The data transmission method includes the following steps: communicating with a second chip via a first chip; pre-sampling multiple previously valid frame signals via the second chip; transmitting the current valid frame signal and a data signal to the second chip via the first chip; determining the error bit positions of the multiple previously valid frame signals via the second chip; generating a detection signal based on the error bit positions via the second chip; and deciding whether to write the data signal into the receive buffer module of the second chip based on the detection signal. The UCIe-based data transmission method, storage medium, and artificial intelligence chip disclosed herein provide excellent data transmission quality.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a UCIe-based data transmission method, storage medium, and artificial intelligence chip. Background Technology

[0002] According to the Universal Chiplet Interconnect Express (UCIe) protocol, when a valid framing error occurs, the physical layer can no longer send data to the upper adaptation layer, and data sent from the other end will no longer be received until the retraining process is completed and the system returns to active status. Therefore, a valid framing error will result in data interruption.

[0003] A common cause of this is that when the valid frame signal channel maintains a low or high level for an extended period and then suddenly transitions to a high or low level, the receiving circuit may be unable to perform the level transition in time, resulting in a gradual edge change and thus causing false detection of the valid frame signal. Alternatively, in extreme temperature environments, circuit performance may be affected by temperature and power supply noise, potentially causing random glitches in the valid frame signal channel, leading to false detection of the valid frame signal.

[0004] The above situation will cause the sampling of the valid frame signal on the valid frame signal channel to be incorrect, but the sampling of the data signal channel (data lane) will be correct. In other words, when the received data is correct, the valid frame error caused by the above situation will frequently trigger the system to retrain and cause data interruption, thereby affecting the system's data transmission efficiency and chip performance. Summary of the Invention

[0005] This disclosure relates to a UCIe-based data transmission method, storage medium, and artificial intelligence chip that can achieve good data transmission quality.

[0006] According to embodiments of this disclosure, the UCIe-based data transmission method includes the following steps: communicating with a second core through a first core; pre-sampling multiple previously valid frame signals through the second core; transmitting a current valid frame signal and a data signal to the second core through the first core; determining the error bit positions of the multiple previously valid frame signals through the second core; generating a detection signal through the second core based on the error bit positions; and determining whether to write the data signal into the receive buffer module of the second core based on the detection signal.

[0007] In the data transmission method according to an embodiment of the present disclosure, the data transmission method further includes: receiving a first raw data signal through a first mapping module of the first chip, and converting the first raw data signal into a mapped data signal through the first mapping module; and scrambling the mapped data signal through a scrambling module of the first chip to generate the data signal.

[0008] In the data transmission method according to an embodiment of the present disclosure, the data transmission method further includes: outputting the data signal to the transmission module of the first chip through the scrambling module; outputting the current valid frame signal to the transmission module through the valid frame signal generation module of the first chip; and synchronously transmitting the data signal and the valid frame signal to the second chip through the transmission module.

[0009] In the data transmission method according to an embodiment of the present disclosure, the data transmission method further includes: receiving the data signal and the current valid frame signal through the receiving module of the second chip; outputting the current valid frame signal to the valid frame signal detection module of the second chip through the receiving module; and generating the detection signal through the valid frame signal detection module according to the error occurrence frequency of the plurality of previous valid frame signals.

[0010] In the data transmission method according to an embodiment of the present disclosure, the step of generating the detection signal further includes: determining, by the valid frame signal detection module, whether the number of times the error bit position occurs at the data edge is greater than a threshold; when the number of times the error bit position occurs at the data edge is greater than the threshold, setting a valid frame signal mask by the valid frame signal detection module; and generating the detection signal by the valid frame signal detection module according to the valid frame signal mask.

[0011] In the data transmission method according to an embodiment of the present disclosure, the step of generating the detection signal further includes: performing an XOR operation on the current valid frame signal and the standard valid frame signal through the valid frame signal detection module to generate a first operand sequence; performing a bitwise inversion operation on the first operand sequence through the valid frame signal detection module to generate a second operand sequence; performing a bitwise OR operation on the second operand sequence and the valid frame signal mask through the valid frame signal detection module to generate a third operand sequence; and performing a bitwise AND operation on the third operand sequence through the valid frame signal detection module to generate the detection signal.

[0012] In the data transmission method according to an embodiment of the present disclosure, the step of generating the detection signal further includes: when the number of times the error bit position occurs at the data edge is not greater than the threshold, counting the first number and the second number of bits with a value of 1 in the current valid frame signal in the first high-level interval and the second high-level interval respectively by the valid frame signal detection module; and determining whether the first number and the second number are both greater than or equal to 2 by the valid frame signal detection module, and generating the detection signal.

[0013] In the data transmission method according to an embodiment of the present disclosure, the step of deciding whether to write the data signal into the receiving buffer module includes: outputting the detection signal to the receiving buffer module through the valid frame signal detection module; and the receiving buffer module deciding whether to store the data signal based on the detection signal.

[0014] In the data transmission method according to an embodiment of the present disclosure, the data transmission method further includes: inverting the detection signal by the valid frame signal detection module to generate a valid frame error signal.

[0015] In the data transmission method according to an embodiment of the present disclosure, the data transmission method further includes: after the second chip writes the data signal into the receiving buffer module according to the detection signal, the receiving buffer module outputs the data signal to the descrambling module of the second chip; the descrambling module generates a descrambling signal according to the data signal and outputs the descrambling signal to the demapping module of the second chip; and the demapping module converts the descrambling signal into a second original data signal.

[0016] In the data transmission method according to an embodiment of the present disclosure, the data transmission method further includes: when the demapping module outputs the second original data signal, the second chip outputs the next valid signal.

[0017] According to embodiments of this disclosure, the computer-readable storage medium of this disclosure is used to store a computer program that is executed by a processor to implement the steps of the UCIe-based data transmission method described above.

[0018] According to embodiments of this disclosure, the artificial intelligence chip includes a first chip and a second chip. The second chip is coupled to the first chip and is used to communicate with the first chip. The second chip pre-samples a plurality of previously valid frame signals, and the first chip transmits a current valid frame signal and a data signal to the second chip. The second chip determines the error bit positions of the plurality of previously valid frame signals, and the second chip generates a detection signal based on the error bit positions. The second chip determines whether to write the data signal into the receive buffer module of the second chip based on the detection signal.

[0019] Based on the above, the UCIe-based data transmission method, storage medium, and artificial intelligence chip disclosed herein can improve the detection efficiency of valid frame signals, thereby effectively reducing the probability of misjudgment caused by sampling errors of valid frame signals when the data signals are correct, which would frequently trigger the chip to enter the retraining process and data interruption, thus enhancing the stability of UCIe data reception between chips.

[0020] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a data transmission system according to an embodiment of the present disclosure;

[0022] Figure 2 This is a schematic diagram of the data transmission path of the physical layer of UCIe according to an embodiment of this disclosure;

[0023] Figure 3 This is a flowchart of a data transmission method according to an embodiment of the present disclosure;

[0024] Figure 4 These are scheduling flowcharts for two different methods according to embodiments of this disclosure;

[0025] Figure 5 This is a data timing diagram of multiple signals according to an embodiment of the present disclosure;

[0026] Figure 6 This is a data timing diagram of multiple signals according to another embodiment of the present disclosure;

[0027] Figure 7 This is a schematic diagram of the effective frame signal data in an embodiment of this disclosure;

[0028] Figure 8 This is a data timing diagram of multiple signals according to another embodiment of the present disclosure;

[0029] Figure 9 This is a schematic diagram of the effective frame signal data in an embodiment of this disclosure;

[0030] Figure 10 This is a schematic diagram of an artificial intelligence chip according to an embodiment of this disclosure.

[0031] Explanation of icon numbers:

[0032] 100: Data transmission system;

[0033] 110: First chip;

[0034] 111: First physical layer architecture;

[0035] 121: Second physical layer architecture;

[0036] 112: Mapping module;

[0037] 113: Scrambling module;

[0038] 114: Valid frame signal generation module;

[0039] 115: Sending module;

[0040] 120: Second core;

[0041] 122: Receiver module;

[0042] 123: Receive buffer module;

[0043] 124: Valid frame signal detection module;

[0044] 125: Descrambling module;

[0045] 126: Demapping module;

[0046] 601: First edge gradually changes;

[0047] 602: The second edge gradually changes direction;

[0048] 603: The third edge gradually changes direction;

[0049] 604: The fourth edge gradually changes color;

[0050] 801: First random burr;

[0051] 802: Second random burr;

[0052] 901: First high-level range;

[0053] 902: Second high-level range;

[0054] 1000: Artificial intelligence chip;

[0055] t1: First time;

[0056] t2: Second time;

[0057] t3: The third time;

[0058] ODS: First raw data signal;

[0059] ODS': Second raw data signal;

[0060] MDS: Mapped Data Signal;

[0061] DS: Data signal;

[0062] VS: First valid signal;

[0063] VS': Second valid signal;

[0064] VFS: Current valid frame signal;

[0065] TS: Detection signal;

[0066] DDS: Descrambling signal;

[0067] VFES: Valid Frame Error Signal;

[0068] CLK: First clock signal;

[0069] RX_CLK: Second clock signal;

[0070] VD: Valid frame data;

[0071] DD: Data;

[0072] MS: Effective frame signal mask;

[0073] D1: The first operational sequence;

[0074] D2: Second operational sequence;

[0075] D3: Third operational sequence. Detailed Implementation

[0076] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0077] Figure 1 This is a schematic diagram of a data transmission system according to an embodiment of this disclosure. (See reference...) Figure 1 The data transmission system 100 includes a first chiplet 110 and a second chiplet 120. The first chiplet 110 and the second chiplet 120 are used to implement die-to-die communication based on UCIe. The first chiplet 110 may be coupled to the second chiplet 120, for example, through multiple bump lanes.

[0078] In this embodiment, the Link Training State Machine (LTSM) of the UCIe in the data transmission system 100 can, for example, sequentially complete the bypass initialization state (SBINIT), main path initialization state (MBINIT), main path training state (MBTRAIN), and link initialization state (LINKINIT) to establish a link between the first core 110 and the second core 120, and then enter a normal operating state. During normal operation, data can be sent and received between the first core 110 and the second core 120.

[0079] In normal operation, when either the first core 110 or the second core 120, acting as a receiver, detects a sampling error in the valid frame signal (i.e., a valid frame error), the Link Training State Machine (LTSM) of the data transmission system 100 will be triggered, entering the Physical Layer Retraining (PHYRETRAIN) process. During the PHYRETRAIN process, the link between the first core 110 and the second core 120 will be disconnected, and data transmission and reception operations will cease. Therefore, the data transmission system 100 of this embodiment can improve the efficiency of detecting valid frame signals, thereby reducing the probability of misjudgment due to sampling errors in the valid frame signal when the data signal is correct, thus preventing frequent triggering of the first core 110 and the second core 120 to enter the PHYRETRAIN process and data interruption.

[0080] In one embodiment of this disclosure, the data transmission system 100 may be implemented in an electronic device, and the electronic device includes a storage unit and a processor. The storage unit is used to store data. The processor is coupled to the storage unit and is used to execute the UCIe-based data transmission method as described in the embodiments of this disclosure to transmit data.

[0081] Processors may include, for example, a central processing unit (CPU) or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), other similar processing devices, or combinations thereof.

[0082] Storage units may include, for example, random access memory (RAM), non-volatile memory, hard disk drive (HDD), or solid state drive (SSD). Random access memory may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). Non-volatile memory may include, for example, flash memory or read-only memory (ROM).

[0083] Figure 2 This is a schematic diagram of the data transmission path of the physical layer of UCIe according to an embodiment of this disclosure. (See reference) Figure 2 , Figure 1 The first core 110 may have the following characteristics: Figure 2 The first physical layer architecture 111 is shown, and the second core 120 may have the following characteristics: Figure 2 The second physical layer architecture 121 is shown. In this embodiment, the first physical layer architecture 111 of the first chip 110 includes a mapping module 112, a scrambling module 113, a valid frame signal generation module 114, and a transmitting module 115. The second physical layer architecture 121 of the second chip 120 includes a receiving module 122, a receiving buffer module 123, a valid frame signal detection module 124, a descrambling module 125, and a demapping module 126. In this embodiment, the scrambling module 113 is coupled to the mapping module 112, the valid frame signal generation module 114, and the transmitting module 115. The valid frame signal generation module 114 is coupled to the transmitting module 115. The receiving buffer module 123 is coupled to the receiving module 122, the valid frame signal detection module 124, and the descrambling module 125.

[0084] In this embodiment, the mapping module 112 of the first chip 110 is used to receive the first raw data signal ODS. The mapping module 112 can obtain the first raw data signal ODS from the previous stage chip or other circuits. The mapping module 112 is used to convert the first raw data signal ODS into a mapped data signal MDS, and output the mapped data signal MDS to the scrambling module 113. The scrambling module 113 is used to scramble the mapped data signal MDS to generate a data signal DS.

[0085] In this embodiment, the valid frame signal generation module 114 is used to receive the first valid signal VS. The valid frame signal generation module 114 may obtain the first valid signal VS from the previous stage chip or other circuitry. The valid frame signal generation module 114 is used to generate the current valid frame signal VFS based on the first valid signal VS.

[0086] In this embodiment, the scrambling module 113 outputs the data signal DS to the transmitting module 115, and the valid frame signal generation module 114 outputs the current valid frame signal VFS to the transmitting module 115. In this embodiment, the transmitting module 115 is used to synchronously transmit the data signal DS and the current valid frame signal VFS to the receiving module 122 of the second chip 120.

[0087] In this embodiment, the receiving module 122 of the second chip 120 is used to receive the data signal DS and the current valid frame signal VFS. The receiving module 122 outputs the current valid frame signal VFS to the valid frame signal detection module 124. In this embodiment, the valid frame signal detection module 124 is used to generate a detection signal TS and a valid frame error signal VFES based on the error occurrence frequency of multiple previous valid frame signals. The valid frame signal detection module 124 can output the detection signal TS to the receive buffer module 123 and output the valid frame error signal VFES to the next stage chip or other subsequent circuits. In this embodiment, the second chip 120 can determine whether to write the data signal DS into the receive buffer module 123 based on the detection signal TS.

[0088] Figure 3 This is a flowchart of a data transmission method according to an embodiment of this disclosure. (See also...) Figure 2 as well as Figure 3 The first core 110 and the second core 120 may perform the following steps S310 to S360. In step S310, the first core 110 and the second core 120 communicate. In step S320, the second core 120 may presample multiple previously valid frame signals. In this embodiment, the mapping module 112 may receive the first raw data signal ODS and convert the first raw data signal ODS into a mapped data signal MDS. The mapping module 112 may output the mapped data signal MDS to the scrambling module 113. The scrambling module 113 may scramble the mapped data signal MDS to generate a data signal DS. The valid frame signal generation module 114 may generate a current valid frame signal VFS based on the first valid signal VS.

[0089] In step S330, the first chip 110 can transmit the current valid frame signal VFS and the data signal DS to the second chip 120. In this embodiment, the transmitting module 115 of the first chip 110 can synchronously transmit the data signal DS and the current valid frame signal VFS to the receiving module 122 of the second chip 120. In step S340, the second chip 120 can determine the position of the error bits of multiple valid frame signals. In step S350, the second chip 120 can generate a detection signal TS according to the position of the error bits. In step S360, the second chip 120 can decide whether to write the data signal DS into the receiving buffer module 123 of the second chip 120 according to the detection signal TS.

[0090] In this embodiment, the second chip 120 can determine the data location where the main error bit occurs based on the error bit positions of multiple previously recorded valid frame signals, and generate a corresponding detection signal TS accordingly. Therefore, the second chip 120 can effectively decide whether to write the data signal DS into its receive buffer module 123 based on the detection signal TS. Furthermore, the method for generating the detection signal TS will be determined by the following... Figure 5 Detailed description of the embodiments.

[0091] Figure 4 This is a scheduling flowchart illustrating two methods of embodiments of this disclosure. (See reference...) Figure 2 as well as Figure 4 In this embodiment, the first core 110 and the second core 120 may perform the following steps S410 to S480. In step S410, the valid frame signal detection module 124 may initialize the valid frame signal mask and selection signal.

[0092] In step S420, the valid frame signal detection module 124 can determine whether the system frequently triggers the retraining process due to valid frame errors. If not, the valid frame signal detection module 124 can directly detect whether the current valid frame signal VFS has a data error and generate a corresponding detection signal TS and a valid frame error signal VFES. In one embodiment, the valid frame signal detection module 124 of the second chip 120 can, for example, determine whether the system frequently triggers the retraining process due to valid frame errors based on whether the number of erroneous valid frame signals among the previous multiple valid frame signals within a preset period is greater than a preset number threshold, but this disclosure is not limited thereto.

[0093] In this embodiment, if the current valid frame signal VFS does not have a data error, the detection signal TS can be, for example, data with a bit value of "1", and the valid frame error signal VFES can be, for example, data with a bit value of "0". Conversely, if the current valid frame signal VFS has a data error, the detection signal TS can be, for example, data with a bit value of "0", and the valid frame error signal VFES can be, for example, data with a bit value of "1".

[0094] In this embodiment, if the valid frame signal detection module 124 determines that the system frequently triggers the retraining process due to valid frame errors, then step S430 is executed. In step S430, the valid frame signal detection module 124 can check the error bit positions of multiple previous valid frame signals, wherein the data of the multiple previous valid frame signals can be pre-sampled and pre-stored in a register. In step S440, the valid frame signal detection module 124 can determine whether the number of times the error bit position occurs at the data edge is greater than a threshold. If yes, the valid frame signal detection module 124 can generate a detection signal TS according to a first method. If no, the valid frame signal detection module 124 can generate a detection signal TS according to a second method.

[0095] In the first method, in step S450, the valid frame signal detection module 124 can set a valid frame signal mask. In step S460, the valid frame signal detection module 124 can generate a detection signal TS based on the valid frame signal mask.

[0096] In the second method, in step S470, the valid frame signal detection module 124 counts a first number and a second number of bits with a value of 1 in the first high-level interval and the second high-level interval, respectively. That is, the valid frame signal detection module 124 counts the first number of bits with a value of 1 in the first high-level interval and the second number of bits with a value of 1 in the second high-level interval. In step S480, the valid frame signal detection module 124 generates a detection signal TS based on the first and second counts.

[0097] In this embodiment, the valid frame signal detection module 124 can output the detection signal TS to the receive buffer module 123. The receive buffer module 123 can decide whether to store the data signal DS based on the detection signal TS.

[0098] For example, pairing reference Figure 5 , Figure 5This is a data timing diagram of multiple signals according to an embodiment of the present disclosure. A clock cycle in the Logical Physical Layer (LPL) can be, for example, 16 Unit Intervals (UI). Within a clock cycle in the LPL, the high-level state of the first clock signal CLK from time 1 to time 2 can be 8 UI, and the low-level state of the first clock signal CLK from time 2 to time 3 can be 8 UI. Within a clock cycle in the LPL, the effective frame signal channel of the second chip 120 can receive effective frame data VD. The effective frame data VD can consist of two 8-bit data sequences, which can be represented in binary as, for example, "0000 1111" and "0000 1111", with the lower-order "1" being sent first. Furthermore, within one clock cycle of the logic physical layer, the data signal channel of the second chip 120 can synchronously receive data DD, where data DD can be 16 bits of data, and is received by the second chip 120 synchronously with the valid frame data VD.

[0099] In the Physical Media Attachment (PMA) layer, the second clock signal RX_CLK is sampled on both edges, and one clock cycle of the second clock signal RX_CLK can be 2 UI in length. Within one clock cycle of the physical layer, the high-level state of the second clock signal RX_CLK can be 1 UI in length, and the low-level state of the second clock signal RX_CLK can be 1 UI in length. Therefore, the receiving module 122 of the second chip 120 can obtain the current valid frame signal VFS and the data signal DS. It should be noted that the current valid frame signal VFS is used to ensure that the data transmitted by the transmitting module 115 of the first chip 110 is transmitted in frames, and each 8 bits can be considered a packet. Therefore, when the current valid frame signal VFS is normal, the receiving module 122 samples the current valid frame signal VFS and obtains data with the binary sequence "1111 0000 1111 0000". Therefore, in one clock cycle of the logic physical layer, the receiving module 122 of the second chip 120 can sample the binary sequence of valid frame data as "1111 0000 1111 0000". The valid frame signal detection module 124 can determine that the current valid frame signal VFS is normal, and therefore can output a detection signal TS with a bit value of "1" to the receiving buffer module 123, and can output a valid frame error signal VFES with a bit value of "0" to the next stage chip or subsequent circuit. Furthermore, the receiving module 122 can write the data signal DS into the receiving buffer module 123 according to the detection signal TS. The receiving buffer module 123 can output the data signal DS to the descrambling module 125. The descrambling module generates a descrambling signal DDS according to the data signal DS, and outputs the descrambling signal DDS to the demapping module 126. The demapping module 126 can convert the descrambled signal DDS into the second original data signal ODS' and output the second original data signal ODS' to the next stage chip or subsequent circuit. The second chip 120 can output the next second valid signal VS' to the next stage chip or subsequent circuit.

[0100] For example, pairing reference Figure 6 and Figure 7 , Figure 6 This is a data timing diagram of multiple signals according to another embodiment of the present disclosure. Figure 7 This is a schematic diagram of the valid frame signal data in an embodiment of this disclosure. When the system frequently triggers a retraining process due to valid frame errors, as determined in step S440 above, if the number of times the erroneous bit positions of the previous multiple valid frame signals occur at data edges exceeds a threshold, it indicates that the receiving module 122 has encountered an error during the reception of the data signal DS. Figure 6The examples shown are the first edge gradual change 601, the second edge gradual change 602, the third edge gradual change 603, and the fourth edge gradual change 604. In response, the valid frame signal detection module 124 can, for example, set the bit value of the selection signal to "0" to perform the first method of generating the detection signal TS. Furthermore, the valid frame signal detection module 124 can set the binary sequence of the valid frame signal mask MS to "1001 1001 1001 1001" (its hexadecimal representation is "9999"). Additionally, the binary sequence of the standard (normal) valid frame signal is set to "1111 0000 1111 0000" (the left side of the sequence is the low-order bits, and the right side is the high-order bits).

[0101] In response, the effective frame signal detection module 124 can sample... Figure 6 The current valid frame signal VFS shown is used to obtain the following: Figure 7 The binary sequence shown is "0110 0000 0110 0000". The valid frame signal detection module 124 can perform an XOR operation between the data of the current valid frame signal VFS and the data of the reference valid frame signal (whose hexadecimal representation is "0f0f") to generate a first operand sequence D1. The first operand sequence D1 has the following characteristics: Figure 7 The binary sequence shown is "10010000 1001 0000". Next, the valid frame signal detection module 124 can perform a bitwise inversion operation on the first operand sequence D1 to generate the second operand sequence D2. The second operand sequence D2 has the following characteristics: Figure 7 The binary sequence shown is “0110 1111 01101111”. Next, the valid frame signal detection module 124 performs a bitwise OR operation on the second operand D2 and the valid frame signal mask MS (whose hexadecimal representation is “9999”) to generate the third operand D3. The third operand D3 has the following characteristics: Figure 7 The binary sequence shown is "1111 1111 1111 1111". Next, the valid frame signal detection module 124 performs a bitwise AND operation on all the bits of the third operand D3 to generate a detection signal TS with a bit value of "1". Furthermore, the valid frame signal detection module 124 inverts the detection signal TS to generate a valid frame error signal VFES with a bit value of "0".

[0102] In this way, the receiving module 122 can write the data signal DS into the receiving buffer module 123 according to the detection signal TS with a bit value of "1". The receiving buffer module 123 can output the data signal DS to the descrambling module 125. The descrambling module can generate a descrambling signal DDS according to the data signal DS and output the descrambling signal DDS to the demapping module 126. The demapping module 126 can convert the descrambling signal DDS into a second original data signal ODS' and output the second original data signal ODS' to the next stage chip or subsequent circuit, and the second chip 120 can output the next second valid signal VS' to the next stage chip or subsequent circuit.

[0103] Therefore, the first method described above can effectively reduce detection errors caused by gradual edge changes in the effective frame signal (VFS) under certain extreme operating conditions due to level transitions in the effective frame signal channel after a long idle period (e.g., a bit value suddenly changing from 0 to 1 or from 1 to 0). In other words, it can help avoid frequent retraining processes in the data transmission system 100 due to frequent detection errors of the effective frame signal, thus preventing data interruptions.

[0104] For example, pairing reference Figure 8 and Figure 9 , Figure 8 This is a data timing diagram of multiple signals according to another embodiment of the present disclosure, and Figure 9 This is a schematic diagram of the valid frame signal data in an embodiment of this disclosure. When the system frequently triggers a retraining process due to valid frame errors, as determined in step S440 above, if the number of times the erroneous bit positions of the previous multiple valid frame signals occur at data edges does not exceed a threshold, it indicates that the receiving module 122 has encountered an error during the reception of the data signal DS. Figure 8 The examples shown are the first random spike 801 and the second random spike 802.

[0105] To address this, the valid frame signal detection module 124 can, for example, set the bit value of the selection signal to "1" to perform the second method of generating the detection signal TS. The valid frame signal detection module 124 can sample... Figure 8 The current valid frame signal VFS shown is used to obtain the following: Figure 7 The binary sequence shown is "1101 0000 1111 0100". The valid frame signal detection module 124 can count the first number and the second number of bits with a value of 1 in the current valid frame signal VFS in the first high-level interval 901 and the second high-level interval 902, respectively. Then, the valid frame signal detection module 124 can determine whether the first number and the second number are both greater than or equal to 2, and generate a detection signal TS.

[0106] like Figure 9 As shown, the number of bits with a value of 1 in the current valid frame signal VFS in the first high-level interval 901 can be 3, and the number of bits with a value of 1 in the current valid frame signal VFS in the second high-level interval 902 can be 4. The valid frame signal detection module 124 can determine that both the first and second numbers are greater than or equal to 2. Therefore, the valid frame signal detection module 124 can generate a detection signal TS with a bit value of "1". Furthermore, the valid frame signal detection module 124 can invert the detection signal TS to generate a valid frame error signal VFES with a bit value of "0".

[0107] In this way, the receiving module 122 can write the data signal DS into the receiving buffer module 123 according to the detection signal TS with a bit value of "1". The receiving buffer module 123 can output the data signal DS to the descrambling module 125. The descrambling module can generate a descrambling signal DDS according to the data signal DS and output the descrambling signal DDS to the demapping module 126. The demapping module 126 can convert the descrambling signal DDS into a second original data signal ODS' and output the second original data signal ODS' to the next stage chip or subsequent circuit, and the second chip 120 can output the next second valid signal VS' to the next stage chip or subsequent circuit.

[0108] Therefore, the second method described above can effectively reduce detection errors caused by random spikes in the valid frame signal channel due to the influence of power supply noise, crosstalk, and temperature drift. In other words, it can help avoid frequent retraining processes caused by frequent detection errors in the valid frame signal, thus preventing data transmission system 100 from frequently entering the retraining process and resulting in data interruption.

[0109] Figure 10 This is a schematic diagram of an artificial intelligence chip according to an embodiment of this disclosure. (See reference) Figure 10 In one embodiment, the artificial intelligence chip 1000 may include a first chip 110 and a second chip 120. The first chip 110 and the second chip 120 are used to realize inter-chip communication based on a common chip interconnect technology (e.g., based on UCIe). The first chip 110 and the second chip 120 may form a data transmission system. For related implementation methods and technical details regarding the first chip 110 and the second chip 120, please refer to the descriptions of the above embodiments. Furthermore, the data transmission method between the first chip 110 and the second chip 120 can also refer to the processes of the above embodiments, thus providing sufficient teaching, suggestions, and implementation instructions. In addition, in another embodiment, the number of chips in the artificial intelligence chip 1000 is not limited to... Figure 10 The first core 110 and the second core 120 are shown.

[0110] In one embodiment, the artificial intelligence chip 1000 can be any one of a central processing unit, a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU).

[0111] In summary, the UCIe-based data transmission method, storage medium, and artificial intelligence chip disclosed herein can help avoid frequent retraining processes in the data transmission system due to frequent detection errors in the valid frame signal, which could lead to data interruptions. The UCIe-based data transmission method, storage medium, and artificial intelligence chip disclosed herein can improve detection errors in the valid frame signal (e.g., under certain extreme operating conditions, detection errors caused by gradual edge changes in the valid frame signal due to level transitions in the valid frame signal channel after a long idle period (e.g., a sudden change in bit value from 0 to 1, or from 1 to 0), or detection errors caused by random spikes in the valid frame signal channel due to power supply noise, crosstalk, and temperature drift).

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A data transmission method based on UCIe, characterized in that, include: Communication is achieved between the first and second cores; The second chip presamples multiple previously valid frame signals; The first chip transmits the current valid frame signal and data signal to the second chip. The second chip is used to determine the position of the erroneous bits in the plurality of previously valid frame signals; The second chip generates a detection signal based on the position of the error bit; and... The second chip determines whether to write the data signal into the receiving buffer module of the second chip based on the detection signal.

2. The data transmission method based on UCIe according to claim 1, characterized in that, Also includes: The first raw data signal is received by the first mapping module of the first core, and the first raw data signal is converted into a mapped data signal by the first mapping module. The scrambling module of the first core is used to scramble the mapped data signal to generate the data signal.

3. The data transmission method based on UCIe according to claim 2, characterized in that, Also includes: The scrambling module outputs the data signal to the transmitting module of the first chip; as well as, The current valid frame signal is output to the transmitting module through the valid frame signal generation module of the first chip; and... The data signal and the current valid frame signal are synchronously transmitted to the second chip via the transmission module.

4. The UCIe-based data transmission method according to claim 3, characterized in that, Also includes: The data signal and the current valid frame signal are received by the receiving module of the second chip; The receiving module outputs the current valid frame signal to the valid frame signal detection module of the second chip. as well as, The detection signal is generated by the valid frame signal detection module based on the error occurrence frequency of the plurality of previous valid frame signals.

5. The UCIe-based data transmission method according to claim 4, characterized in that, The step of generating the detection signal further includes: The effective frame signal detection module determines whether the number of times the error bit position occurs at the data edge is greater than a threshold. When the number of times the error bit position occurs at the data edge exceeds the threshold, the valid frame signal mask is set by the valid frame signal detection module; and, The detection signal is generated by the effective frame signal detection module based on the effective frame signal mask.

6. The UCIe-based data transmission method according to claim 5, characterized in that, The step of generating the detection signal further includes: The effective frame signal detection module performs an XOR operation on the current effective frame signal and the reference effective frame signal to generate a first operand sequence. The effective frame signal detection module performs a bitwise inversion operation on the first operand sequence to generate the second operand sequence; The effective frame signal detection module performs a bitwise OR operation on the second operand sequence and the effective frame signal mask to generate a third operand sequence; and, The detection signal is generated by performing a bitwise AND operation on the third operand sequence through the effective frame signal detection module.

7. The UCIe-based data transmission method according to claim 5, characterized in that, The step of generating the detection signal further includes: When the number of times the error bit position occurs at the data edge is not greater than the threshold, the valid frame signal detection module counts the first and second numbers of bits with a value of 1 in the current valid frame signal in the first high-level interval and the second high-level interval, respectively; and, The effective frame signal detection module determines whether both the first quantity and the second quantity are greater than or equal to 2, and generates the detection signal.

8. The UCIe-based data transmission method according to claim 4, characterized in that, The step of deciding whether to write the data signal into the receive buffer module includes: The effective frame signal detection module outputs the detection signal to the receiving buffer module; and... The receiving buffer module determines whether to store the data signal based on the detected signal.

9. The UCIe-based data transmission method according to claim 4, characterized in that, Also includes: The valid frame signal detection module inverts the detected signal to generate a valid frame error signal.

10. The UCIe-based data transmission method according to claim 1, characterized in that, Also includes: After the second chip writes the data signal into the receiving buffer module according to the detection signal, the receiving buffer module outputs the data signal to the descrambling module of the second chip. The descrambling module generates a descrambling signal based on the data signal and outputs the descrambling signal to the demapping module of the second chip; and, The descrambling module converts the descrambling signal into a second raw data signal.

11. The UCIe-based data transmission method according to claim 10, characterized in that, Also includes: When the demapping module outputs the second raw data signal, the second core outputs the next valid signal.

12. A computer-readable storage medium for storing a computer program, characterized in that, The computer program is executed by a processor to implement the steps of the UCIe-based data transmission method as described in any one of claims 1 to 11.

13. An artificial intelligence chip, characterized in that, include: First core; as well as The second core is coupled to the first core and is used to communicate with the first core. The second core presamples multiple previously valid frame signals, and the first core transmits the current valid frame signal and data signal to the second core. The second chip determines the position of the erroneous bits in the plurality of previous valid frame signals, and the second chip generates a detection signal based on the position of the erroneous bits. The second chip determines whether to write the data signal into the receiving buffer module of the second chip based on the detection signal.

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