Method and apparatus for aligning multi-channel data based on delay compensation

Abstract

The application provides a multi-channel data alignment method and device based on delay compensation, which comprises the following steps: a target data in a data channel is detected by using an alignment mark detection module; a corresponding data reconstruction module is arranged on the multi-channel data, and the data reconstruction module is used for reconstructing the target data, so that the alignment marks of the data of each data channel are in the same position in one beat data; a data calibration module receives data output by a plurality of buffer modules, detects delay deviation between the data of the multi-channel data, and outputs the delay deviation to a delay matrix module, and detects delay deviation between the target data of the multi-channel data, and the delay matrix module controls the time when each buffer module transmits data to the data calibration module. The application also provides a device for realizing the above method. The application can flexibly realize multi-channel data alignment with low complexity.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data synchronization processing, in particular to a multi-channel data alignment method based on delay compensation and a device for implementing the method. BACKGROUND

[0002] The physical layer channel of data transmission includes a physical coding sublayer (PCS) and a physical medium attachment (PMA), the physical coding sublayer is used to complete parallel transmission of data, generally, the data transmission rate of a data channel of the physical coding sublayer is 25G, therefore, when the data transmission rate requirement is 50G, two data channels need to be used for data transmission, and if the data transmission rate requirement is 100G, four data channels need to be used.

[0003] Since data is transmitted in multiple different data channels, when data of multiple different data channels reaches the receiving end, the time at which data of multiple data channels reaches the receiving end is often inconsistent due to clock signal jitter, lines, links, etc. Therefore, the problem of simultaneous arrival of data of multiple data channels at the receiving end needs to be solved, and the technology for achieving simultaneous arrival of data of multiple data channels at the receiving end is called multi-channel data alignment technology.

[0004] The existing multi-channel data alignment technology inserts alignment markers in multiple data channels at the same time when sending data at the sending end, the receiving end detects the alignment markers after receiving data of each data channel, writes data to the buffer corresponding to the data channel when detecting the alignment marker in the data channel, but the data in the buffer is not read immediately, but is read at the same time after the alignment markers in all data channels are detected, so that the first read data of all data channels is the alignment marker. Since the alignment markers are written into each data channel at the same time, when the alignment markers in each channel are read at the same time, the purpose of aligning data of multiple data channels can be achieved.

[0005] Another existing multi-channel data alignment method inserts a certain time delay in the data channel that detects the alignment marker first, so that the data in the data channel that detects the alignment marker first is output with a delay, thereby achieving the purpose of multi-channel data alignment.

[0006] However, the prior art needs to set up a separate control unit to uniformly manage all data channels, and when the data of the data channels increases, the complexity of control will increase. In addition, since the number of data channels used by the chip needs to be fixed in advance when the chip is made, that is, it is determined whether the data channels are 2, 4 or 8, once the chip is fixed and completed, the number of data channels cannot be changed, therefore, the existing multi-channel data alignment technology has the problems of complex control and difficulty in changing.

[0007] In addition, since the prior art needs to use a management unit to uniformly manage all data channels, the control information on the read side needs to be informed to all data channels at the same time, but since some data channels are far away from the management unit, the transmission time of the control information is long, which cannot meet the requirements of the control timing, which puts higher requirements on the design, back-end layout and production process of the chip, increases the design cost of the chip, and even cannot achieve the design goal of the chip. SUMMARY

[0008] The first object of the present application is to provide a multi-channel data alignment method based on delay compensation with low control complexity and flexible control of the number of data channels.

[0009] The second object of the present application is to provide a multi-channel data alignment device based on delay compensation for accurately implementing data alignment of multiple data channels.

[0010] To achieve the first object of the present application, the multi-channel data alignment method based on delay compensation provided by the present application comprises: transmitting target data of a plurality of data channels to a plurality of corresponding alignment mark detection modules respectively, and the alignment mark detection modules detect the alignment marks in the target data; setting corresponding data reconstruction modules on the plurality of data channels, the data reconstruction modules are used for reconstructing the target data, so that the alignment marks of the data of the plurality of data channels are in the same position in one beat data after reconstruction, and outputting the reconstructed data of the plurality of data reconstruction modules to corresponding cache modules; a data calibration module receives the data output by the plurality of cache modules, detects the delay deviation between the target data of the plurality of data channels, and a delay matrix module controls the time when each cache module transmits data to the data calibration module based on the delay deviation information.

[0011] As can be seen from the above scheme, after the alignment mark detection module detects the alignment mark, the data of each data channel is first reconstructed by the data reconstruction module, and the alignment mark of the data of each reconstructed data channel is in the same position in one beat data. Subsequently, the delay deviation information of each data channel is calculated by the data calibration module, and the time when each cache module outputs data is controlled, so as to realize the delay processing of each data channel, so that each data channel can output the alignment mark at the same time, and thus the alignment of the multi-channel data is realized.

[0012] Since the application does not need to set a complex manager to manage data of each channel, and the alignment control process is simple, the complexity of alignment control is reduced. In addition, when the number of data channels increases, only the number of alignment mark detection modules and cache modules needs to be increased, which can adapt to different numbers of data channels.

[0013] A preferred scheme is that the alignment mark detection module outputs a detection signal to the data read enable generation module after detecting the alignment mark, and the data read enable generation module outputs a read start signal to the delay matrix module after receiving the detection signals output by the plurality of alignment mark detection modules.

[0014] Therefore, the data read enable generation module outputs the read start signal to the delay matrix module only after obtaining the detection signals output by the plurality of alignment mark detection modules, thereby ensuring that each data channel has been detected the alignment mark when each cache module outputs the reconstructed data.

[0015] A preferred scheme is that the delay matrix module determines the time of outputting the read enable signal to each cache module based on the delay deviation information, and outputs the read enable signal to the corresponding cache module at the corresponding time, and the cache module outputs data to the data calibration module after receiving the read enable signal.

[0016] Therefore, the delay matrix module outputs the read enable signal to each cache module, so that the time of outputting data to the data calibration module by each cache module is not the same, so that each cache module can output the alignment mark at the same time, thereby realizing data alignment.

[0017] A further scheme is that the delay matrix module is provided with a plurality of delay channels, one delay channel corresponding to one cache module, and each delay channel receives the read start signal; after the delay matrix module determines the time of outputting the read enable signal to each cache module based on the delay deviation information, the read start signal is delayed by the delay channel corresponding to the cache module before the time of outputting the read enable signal to the cache module.

[0018] Therefore, by individually controlling the delay channel corresponding to each data channel, the delay time of each data channel can be flexibly set, without using complex algorithms to control data delay, thereby reducing the difficulty of delay control.

[0019] A still further scheme is that when the data reconstruction module reconstructs the target data of one data channel, the target data in the data channel is shifted so that the starting bit of the alignment mark is moved to a preset alignment position in one beat data.

[0020] Therefore, the alignment of the multiple data channels in the beat data can be realized by simply shifting the data, avoiding complex calculation, and the data reconstruction is relatively simple.

[0021] Further, after the alignment mark detection module detects the alignment mark in the data of the corresponding data channel, the detection mark is written to the corresponding buffer module; after the data calibration module receives the data output by the multiple buffer modules, the time of obtaining the detection mark is used to determine the delay deviation between the multiple data channels.

[0022] Therefore, the data calibration module determines the delay deviation between the multiple data channels by detecting the time of obtaining the detection mark in the data output by each buffer module, and can accurately calculate the time deviation between each data channel.

[0023] Further, after the data calibration module receives the data output by the multiple buffer modules, the data channel that first obtains the detection mark is used as the reference data channel, and the time of obtaining the detection mark by the subsequent data channels is used to determine the delay deviation between the subsequent data channels and the reference data channel.

[0024] Therefore, the delay deviation between the subsequent data channels is calculated based on a reference data channel, which can unify the calculation basis and ensure the accuracy of the calculation of the delay deviation between the data channels.

[0025] Further, the data calibration module sets the reference delay time of the reference data channel as the maximum delay time, and calculates the delay time of each subsequent data channel based on the maximum delay time; after the data calibration module determines the delay deviation between the multiple data channels, the minimum target data channel of the delay time in the subsequent data channels is obtained, and the delay time of each data channel is updated based on the target time of the target data channel.

[0026] Therefore, by the above operation, the delay time of each data channel can be represented by the minimum value, so that the actual delay time of each delay channel of the delay matrix module is reduced.

[0027] To achieve the above-mentioned second object, the multi-channel data alignment device based on delay compensation provided by the application comprises a plurality of alignment mark detection modules, which are used for detecting the alignment marks in the data of one data channel; a plurality of data reconstruction modules, one data reconstruction module being used for reconstructing the data of one data channel, so that the alignment marks of the data of the plurality of data channels are in the same position in one beat data after reconstruction; a plurality of cache modules, one cache module storing the reconstructed data output from one data reconstruction module; a data calibration module, which receives the data output from the plurality of cache modules and detects the delay deviation between the target data of the plurality of data channels; and a delay matrix module, which controls the time when each cache module transmits data to the data calibration module based on the delay deviation information.

[0028] As can be seen from the above scheme, the multi-channel data alignment device only needs to be provided with a plurality of modules such as the alignment mark detection modules, the cache modules, the delay matrix module and the data calibration module, without the need to be provided with a complex control circuit, and each module does not need to perform complex calculation, thereby being capable of reducing the control complexity of data alignment. In addition, the multi-channel data alignment device can flexibly expand the number of data channels, and can adapt to different application scenarios with different numbers of data channels.

[0029] A preferred scheme is that the delay matrix module comprises a delay channel corresponding to one data channel, and the delay channel has a plurality of series-connected delay units.

[0030] As can be seen from this, by separately controlling the operation of each delay unit, the delay time of each delay channel can be flexibly adjusted, so that the delay time adjustment of each data channel is very flexible.

[0031] A further scheme is that the delay unit has a multiplexer and a delay timer, the delay timer receives an input signal, and the multiplexer receives the input signal and the signal output by the delay timer and can selectively output one of the input signal and the signal output by the delay timer.

[0032] As can be seen from this, the structure of the delay unit is very simple, and the delay time control of the delay unit can be flexibly realized through the multiplexer, thereby reducing the production cost of the data alignment device and improving the flexibility of delay time adjustment. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural block diagram of an embodiment of the multi-channel data alignment device based on delay compensation of the application.

[0034] Figure 2 is the first case of the alignment mark in the embodiment of the multi-channel data alignment device based on delay compensation of the application.

[0035] Figure 3 is the second case of alignment mark in the embodiment of the application of the multi-channel data alignment device based on delay compensation.

[0036] Figure 4 is the first case before data reconstruction in the embodiment of the application of the multi-channel data alignment device based on delay compensation.

[0037] Figure 5 is the first case after data reconstruction in the embodiment of the application of the multi-channel data alignment device based on delay compensation.

[0038] Figure 6 is the second case before data reconstruction in the embodiment of the application of the multi-channel data alignment device based on delay compensation.

[0039] Figure 7 is the structural block diagram of the delay matrix module in the embodiment of the application of the multi-channel data alignment device based on delay compensation.

[0040] Figure 8 is the structural block diagram of a delay unit in the embodiment of the application of the multi-channel data alignment device based on delay compensation.

[0041] The application will be further described below in combination with the drawings and embodiments. DETAILED DESCRIPTION

[0042] The multi-channel data alignment device based on delay compensation of the application is used for alignment operation of data of data channels of multiple parallel transmission data, so that multiple data channels can output data received at the same time at the same time.

[0043] Referring to Figure 1 The multi-channel data alignment device based on delay compensation of the embodiment needs to receive target data of multiple data channels, for example, receives target data of four data channels, which are target data sent by the first data channel 11, the second data channel 12, the third data channel 13 and the fourth data channel 14 respectively, and needs to align target data sent by the four data channels.

[0044] The embodiment is provided with multiple alignment mark detection modules, data reconstruction modules and cache modules, and is provided with a data read enable generation module 51, a delay matrix module 52 and a data calibration module 53. Among them, the number of alignment mark detection modules, data reconstruction modules and cache modules is equal to the number of data channels, and the data channels, alignment mark detection modules, data reconstruction modules and cache modules correspond one by one.

[0045] Since the target data of each data channel is added with an alignment mark, the embodiment needs to detect the alignment mark in the target data sent by each data channel through an alignment mark detection module. Specifically, the first alignment mark detection module 21 detects the target data sent by the first data channel 11 to detect whether the sent target data contains an alignment mark. Referring to Figure 2 The alignment mark is a four-bit binary number, which is represented by am0, am1, am2, and am3. The first alignment mark detection module 21 detects whether the target data sent by the first data channel 11 contains am0 to am3. If am0 to am3 are detected, the target data sent by the first data channel 11 needs to be reconstructed. Therefore, the first alignment mark detection module 21 needs to send the data containing the detected alignment mark to the first data reconstruction module 31 for data reconstruction processing.

[0046] Similarly, the second alignment mark detection module 22 detects the target data sent by the second data channel 12, the third alignment mark detection module 23 detects the target data sent by the third data channel 13, and the fourth alignment mark detection module 24 detects the target data sent by the fourth data channel 14. Each alignment mark detection module detects the target data of the corresponding data channel in the same way.

[0047] When the alignment mark detection module detects the alignment mark of the target data, the size of a container needs to be determined according to the length of the alignment mark length and the write data bit width width of the cache module. The determination rule of the container size is as follows: first, calculate the ratio of the length of the alignment mark length to the write data bit width width of the cache module, and take the integer part of the ratio, for example, if the ratio is 2.6, the integer part is 2. Then, it is judged whether the integer part is less than or equal to 1. If it is less than or equal to 1, the size of the container is twice the length of the alignment mark length. If the integer part is greater than 1, the size of the container is twice the write data bit width width of the cache module. Usually, the ratio of the length of the alignment mark length to the write data bit width width of the cache module is less than or equal to 1 after taking the integer part, so the size of the container is usually twice the length of the alignment mark length.

[0048] Since the data transmission of the data channel is affected by various factors, the position of the alignment mark in the target data of each data channel is not the same, for example Figure 2 In the first data channel 11, the alignment mark is located at D1 to D4 of the second byte, for example Figure 3As shown, the alignment mark of the second data channel 12 is located at D3 to D6 of the first byte. Therefore, in this embodiment, the alignment mark is used as a reference to achieve target data alignment for each data channel. In the example above, the length of the alignment mark is 4 bits, so the container size is 8 bits. The alignment mark detection module detects the alignment mark in units of 8 bits.

[0049] After the first alignment mark detection module 21 detects the alignment mark of the first data channel 11, it transmits the data to the first data reconstruction module 31 for reconstruction. Similarly, after the second alignment mark detection module 22 detects the alignment mark of the second data channel 12, it transmits the data to the second data reconstruction module 32 for reconstruction. Therefore, in this embodiment, multiple data reconstruction modules reconstruct the target data of their respective data channels, so that the alignment marks of each data channel in the reconstructed data are located at the same position in one data cycle. Assuming... Figure 2 and Figure 3 As shown, the alignment markers of the first data channel 11 are located at D1 to D4 of the second byte, while the alignment markers of the second data channel 12 are located at D3 to D6 of the first byte. During data reconstruction, the target data of each data channel is shifted so that the starting bit am0 of the alignment marker is located at the same position in one data cycle. In this embodiment, the same position is the first bit of one data cycle, i.e., D0 of the first byte. Therefore, the first data reconstruction module 31 shifts the target data of the first data channel 11 so that the starting bit am0 of the alignment marker moves from the D1 bit of the second byte to the D0 bit of the first byte, which is 9 bits lower. For example, for the data of the first byte, before shifting, as shown... Figure 4 As shown, after the shift, the starting position am0 of the alignment mark becomes the starting position of one data cycle, as follows. Figure 5 As shown, the reconstructed data is written to the first cache module 41.

[0050] Similarly, the second data reconstruction module 32 shifts the target data of the second data channel 12, causing the start bit am0 of the alignment mark to move from bit D3 of the first byte to bit D0 of the first byte, that is, to move it 3 bits lower. Furthermore, since the alignment mark is a four-bit binary number, it may appear in cases where it spans multiple bytes, such as... Figure 6 As shown, assuming that in a certain data channel, the start bit am0 of the alignment mark is in the D5 bit of the first byte, then the end bit am3 of the alignment mark appears at the first bit of the second byte, i.e., the D8 bit. When reconstructing the data, the data of the second byte needs to be moved to the first byte one by one so that the start bit am0 of the alignment mark is at the first bit of the data in one clock cycle.

[0051] Of course, in other embodiments, the start bit of the alignment marker after data reconstruction does not necessarily have to be located at the first bit of the beat data, but can be located at a specific position of a specific byte, as long as the start bit of the alignment marker of each data channel is located at the same position. In addition, when data is shifted, the removed data can be directly deleted, for example, the data of D0 to D2 of the first byte of Figure 3 is directly deleted. Alternatively, the removed data is stored in a specific memory, and when the data is needed later, the removed data is read from the memory.

[0052] It should be noted that, due to the data transmission delay between data channels, the alignment markers of different data channels are located in different beat data, for example, the alignment markers of the first data channel 11 and the second data channel 12 are both located in the first beat data, while the alignment markers of the third data channel 13 and the fourth data channel 14 are located in the second beat data, or the alignment markers of the four data channels are located in different beat data. Each data reconstruction module can only move the alignment marker to the same position of the beat data, but cannot realize cross-beat alignment. For example, after reconstruction by the first data reconstruction module 31 and the second data reconstruction module 32, the start bit of the alignment marker of the first data channel 11 and the start bit of the alignment marker of the second data channel 12 are both located at the first bit of the first beat data, while after reconstruction by the third data reconstruction module 33 and the fourth data reconstruction module 34, the start bit of the alignment marker of the third data channel 13 and the start bit of the alignment marker of the fourth data channel 14 are both located at the first bit of the second beat data. Of course, in actual situations, the alignment markers of the four data channels can be located in four beat data.

[0053] In addition, each alignment marker detection module sends a detection signal to the data read enable generation module 51 after detecting the alignment marker of the data channel, to inform the data read enable generation module 51 that the alignment marker of the corresponding data channel has been found. The data read enable generation module 51 needs to receive all the detection signals output by the alignment marker detection modules before outputting a read start signal to the delay matrix module 52.

[0054] On the other hand, each data reconstruction module outputs the reconstructed data to the corresponding cache module, for example, the first data reconstruction module 31 reconstructs the data of the first data channel 11 and then outputs the data to the first cache module 41. In addition, the first data reconstruction module 31 also writes the position of the start bit of the alignment marker to the first cache module 41, for example, marks that the start bit of the alignment marker is located at the first bit of a beat data. In addition, after the first alignment marker detection module 21 detects the alignment marker in the data of the first data channel 11, it also writes a detection marker flag to the first cache module 41, for example, when writing data to the first cache module 41, a bit is added as a detection marker. When the detection marker is set, it indicates that the first data channel 11 has been detected the alignment marker.

[0055] Similarly, the second data reconstruction module 32 also writes the reconstructed data to the second cache module 42, and also writes a detection marker after detecting the alignment marker. The third data reconstruction module 33 also writes the reconstructed data to the third cache module 43, and the fourth data reconstruction module 34 also writes the reconstructed data to the fourth cache module 44.

[0056] In this embodiment, each cache module is a first-in-first-out buffer (FIFO). Since the alignment markers of each data channel are not located in the same beat data, in order to realize that the alignment markers of each data channel can be output at the same time, it is necessary to make the reconstructed data of each cache module not output at the same time, that is, to make at least part of the data of the cache module be delayed output. Therefore, in this embodiment, the read enable signal of at least part of the cache module is delayed to output, so that each cache module outputs data with a certain time difference.

[0057] In this embodiment, the read enable signal of each cache module is output by the delay matrix module 52. The delay matrix module 52 needs to output the read enable signal of each cache module respectively, for example, output the first read enable signal rd_0 to the first cache module 41, the second read enable signal rd_1 to the second cache module 42, the third read enable signal rd_2 to the third cache module 43, and the fourth read enable signal rd_4 to the fourth cache module 44. The time of outputting the read enable signal of each cache module of the delay matrix module 52 is not the same, but is determined according to the data beat where the alignment marker of each data channel is located. Therefore, after receiving the read start signal output by the data read enable generation module 51, the delay matrix module 52 needs to output the read start signal with delay. In addition, since the delay time of each data channel is not the same, for this reason, the delay matrix module 52 is provided with a plurality of delay channels, and each delay channel corresponds to a data channel.

[0058] Referring to Figure 7Each delay channel includes a plurality of delay units connected in series, for example, the first delay channel includes N delay units, which are delay units D00 to D0N respectively, the second delay channel also includes N delay units, which are delay units D10 to D1N respectively, the Mth delay channel includes N delay units, which are delay units DM0 to DMN respectively, and so on. Each delay unit has the same structure, which is described below with reference to Figure 8 A delay unit 70 is provided with a multiplexer 71 and a delay unit 72, wherein the delay unit 72 can receive an externally input signal, for example, a read enable signal output by the data read enable generation module 51 or a signal output by the previous delay unit 70, and delay the received signal by one time unit, which can be 1 nanosecond. The multiplexer 71 has two input ends and an output end, the first input end receives the signal output by the delay unit 72, and the second input end directly receives an external signal, for example, a read enable signal output by the data read enable generation module 51 or a signal output by the previous delay unit 70. The control end of the multiplexer 71 receives a control signal, and according to the control signal, the multiplexer 71 switches the output to be the signal received by the first input end or the signal received by the second input end. For example, when the control signal is high, the multiplexer 71 outputs the signal received by the first input end, i.e. the signal output by the delay unit 72, and when the control signal is low, the multiplexer 71 outputs the signal received by the second input end. Therefore, the external signal is either delayed and then output by the delay unit 72 or directly output by the multiplexer 71, and by changing the level of the control signal of the multiplexer 71, the input signal can be delayed or not delayed.

[0059] Since each delay channel includes a plurality of delay units 70 connected in series, by controlling the operation of the plurality of delay units 70 in a delay channel, the delay time of each delay channel can be flexibly set, and the delay can be adjusted from 0 to several milliseconds.

[0060] Since each delay channel can receive the read enable signal output by the data read enable generation module 51, the read enable signal is delayed for different times in different delay channels to form read enable signals corresponding to different cache modules, and the read enable signals of each cache module are sent to the corresponding cache module.

[0061] After each cache module receives the read enable signal, it outputs the cached data to the data alignment module 53 in a first-in, first-out manner, and after the data alignment module 53 receives the data output by each cache module, it performs the following steps to align the data.

[0062] The first step is to check the time when each data lane is detected to have the alignment mark, that is, to check the time when each cache module outputs the detection mark flag. Since the alignment marks of different data lanes can be in different shots of data, the times when the cache modules output the detection mark are often not the same.

[0063] For example, the data calibration module 53 detects that the data lane that obtains the detection mark earliest is set as the reference data lane, such as the first data lane 11 that is found to have the detection mark earliest, and the first data lane is set as the reference data lane. The detection marks of other data lanes will be found subsequently, and therefore the other data lanes are set as subsequent data lanes.

[0064] After detecting the detection mark of the reference data lane, the time is counted from 0 for other data lanes and the delay skew between the reference data lane and the subsequent data lanes is calculated based on the counted time. At the same time, the delay time of the reference data lane is set as the maximum delay time max_skew. When the detection mark on the second data lane is detected, the counting time of the second data lane ends, for example, the counting time of the second data lane is T1, that is, the second data lane is delayed by T1 compared with the reference data lane, and the delay skew between the second data lane and the reference data lane is T1, and the delay time of the second data lane is max_skew-T1. Similarly, when the detection mark on the third data lane is detected, the counting time of the third data lane ends, for example, the counting time of the third data lane is T2, that is, the third data lane is delayed by T2 compared with the reference data lane, and the delay skew between the third data lane and the reference data lane is T2, and the delay time of the third data lane is max_skew-T2. In this way, the delay of the transmission data between all subsequent data lanes and the reference data lane can be calculated, and the delay time of each data lane can be calculated.

[0065] After obtaining the delay times of all data lanes, the delay times of all data lanes form delay skew information, and the delay skew information is sent to the delay matrix module 52. The delay skew information includes the delay time of each data lane. After receiving the delay skew information, the delay matrix module 52 controls the operation of the corresponding delay lane according to the delay time of each data lane, that is, controls the control signal of the multiplexer in each delay unit in each delay lane, and then determines the actual delay time of each delay lane. In this way, the delay matrix module 52 delays the read enable signal output to each cache module, so that each cache module needs to pass through the corresponding delay time before it can continue to output data to the data calibration module 53.

[0066] Since the detection marks of each cache module are read to the data correction module 53 first with the alignment marks, when the detection marks are read by the data correction module 53, the alignment marks of each data channel are not read, and thus the alignment marks of each data channel are not output at this time.

[0067] In the second step, after a period of time, the alignment marks of each cache module should be output at the same time. Thus, the data correction module 53 needs to determine whether the alignment marks of each data channel are read at the same time. If it is found that the alignment mark of a data channel is read at a time different from the alignment marks of other data channels, majority decision needs to be performed, that is, the time of reading the alignment marks of the majority of data channels is taken as the reference, and the data channel whose reading of the alignment mark is abnormal is adjusted according to the reference, that is, the delay time of each data channel is recalculated by the method of the first step.

[0068] If all data channels can read the alignment marks at the same time, the operation of the third step is performed: the delay times of each data channel are obtained, and the minimum value of the delay times of each data channel is calculated, for example, the delay time of a data channel is the minimum, and the minimum value of the delay time is t_min, the data channel is set as a target data channel, and then the delay times of all data channels are updated based on the minimum value of the delay time t_min. For example, the maximum delay time max_skew is set as 20, and the delay times of the second data channel and the third data channel are 18 and 15 respectively, and if the delay of the target data channel is 12, that is, the minimum value of the delay time t_min is 12, the delay times of all data channels need to be recalculated based on the minimum value of the delay time to minimize the delay times of all data channels. The specific operation is that the delay time of the target data channel is reduced to 1 as a reference, and the delay times of all data channels are recalculated according to the reference. Since the minimum value of the delay time t_min needs to be reduced from 12 to 1, the delay times corresponding to each data channel are also reduced by 11, that is, the delay time of the reference data channel is reduced from 20 to 9, the delay time of the second data channel is reduced from 18 to 7, and the delay time of the third data channel is reduced from 15 to 4, and so on. After obtaining the updated delay times of each data channel, the updated delay times of each channel are output to the delay matrix module 52, and the delay matrix module 52 controls the operation of each delay channel based on the updated delay times.

[0069] Fourth step: after a period of time, the data calibration module 53 should read the alignment marks of each data channel at the same time again, if the reading time of the alignment mark of a data channel is different from the reading time of the alignment marks of other data channels, it indicates that the delay of the data channel deviates, return to execute the second step again, and execute majority decision again, until all data channels can output the alignment mark at the same time.

[0070] It can be seen that the target data of each data channel is reconstructed by the data reconstruction module, so that the alignment marks of each data channel can be located at the same position of one beat data, thereby realizing the alignment of the alignment marks in one beat data. Then, the data calibration module 51 and the delay matrix module 52 realize the data beat alignment between multiple data channels, so that each data channel can output one beat data containing the alignment mark at the same time.

[0071] Since the application does not need to set a complex control module to control each data channel, only a plurality of data reconstruction modules, delay matrix modules 52 and data calibration modules 53 can complete the data alignment operation of multiple data channels, the data alignment operation is not complex, and can be realized by hardware, thereby reducing the cost of data alignment. In addition, the data read enable generation module 51, the delay matrix module 52 and the data calibration module 53 can process the data of multiple data channels at the same time, and can flexibly adapt to any number of data channels, so the number of data channels is not sensitive to the scheme of the application, and the number of data channels can be easily expanded.

[0072] In addition, since the delay matrix module 52 is provided with a plurality of delay channels, and the delay time of each delay channel can be flexibly set, the use requirements of different delay conditions can be met. In addition, when the chip is laid out, the distance between the delay matrix unit 52 and each cache module can be set to be relatively small, so that the read enable signal of each cache module can be reached in a very short time, thereby avoiding the problem that the alignment marks of each data channel are not output at the same time due to the transmission delay of the read enable signal.

[0073] Finally, it should be emphasized that the above is only the preferred embodiment of the application, and is not used to limit the application. For those skilled in the art, the application can have various changes and modifications, any modification, equivalent replacement, improvement, etc. within the spirit and principles of the application, should be included in the protection scope of the application.

Claims

1. A multi-channel data alignment method based on delay compensation, characterized in that, include: The target data from multiple data channels is transmitted to multiple corresponding alignment mark detection modules, and the alignment mark detection modules detect the alignment marks in the target data. A corresponding data reconstruction module is set on multiple data channels. The data reconstruction module is used to reconstruct the target data so that the alignment mark is in the same position in a single data frame after the target data of multiple data channels is reconstructed. The reconstructed data after reconstruction by multiple data reconstruction modules is output to the corresponding cache module. The data calibration module receives data output from multiple cache modules and detects the delay deviation between target data from multiple data channels. The delay matrix module controls the time for each cache module to transmit data to the data calibration module based on the delay deviation information. By delaying the output of read enable signals to at least a portion of the cache modules, each cache module outputs data with a certain time difference.

2. The multi-channel data alignment method based on delay compensation according to claim 1, characterized in that: After detecting the alignment mark, the alignment mark detection module outputs a detection signal to the data read enable generation module. After receiving the detection signals output by multiple alignment mark detection modules, the data read enable generation module outputs a read start signal to the delay matrix module.

3. The multi-channel data alignment method based on delay compensation according to claim 2, characterized in that: The delay matrix module determines the time to output the read enable signal to each of the cache modules based on the delay deviation information, and outputs the read enable signal to the corresponding cache module at the corresponding time. After receiving the read enable signal, the cache module outputs data to the data calibration module.

4. The multi-channel data alignment method based on delay compensation according to claim 3, characterized in that: The delay matrix module is configured with multiple delay channels, each delay channel corresponds to one cache module, and each delay channel receives the read start signal; After determining the time to output the read enable signal to each of the cache modules based on the delay deviation information, the delay matrix module applies the delay channel corresponding to the cache module to delay the read start signal before the time to output the read enable signal to the cache module is reached.

5. The multi-channel data alignment method based on delay compensation according to any one of claims 1 to 4, characterized in that: When the data reconstruction module reconstructs the target data of a data channel, it shifts the target data within the data channel so that the starting position of the alignment mark is moved to a preset alignment position in a data frame.

6. The multi-channel data alignment method based on delay compensation according to any one of claims 1 to 4, characterized in that: After the alignment mark detection module detects the alignment mark in the data of the corresponding data channel, it writes the detection mark to the corresponding cache module. After receiving data output from multiple cache modules, the data calibration module determines the delay deviation between multiple data channels based on the acquisition time of the detection marker.

7. The multi-channel data alignment method based on delay compensation according to claim 6, characterized in that: After receiving data output from multiple cache modules, the data calibration module uses the data channel that first acquires the detection mark as the reference data channel, and determines the delay deviation between the subsequent data channels and the reference data channel based on the time when the subsequent data channels acquire the detection mark.

8. The multi-channel data alignment method based on delay compensation according to claim 7, characterized in that: The data calibration module sets the reference delay time of the reference data channel to the maximum delay time, and calculates the delay time of each of the subsequent data channels based on the maximum delay time. After determining the delay deviation between multiple data channels, the data calibration module obtains the target data channel with the smallest delay time among the subsequent data channels, and updates the delay time of each data channel based on the delay time of the target data channel.

9. A multi-channel data alignment device based on delay compensation, characterized in that, include: Multiple alignment mark detection modules, one of which is used to detect alignment marks in the data of a data channel; Its features are: Multiple data reconstruction modules, one of which is used to reconstruct the data of a data channel, so that the alignment mark is in the same position in a single data frame after the target data of multiple data channels are reconstructed; Multiple caching modules, one of which stores reconstructed data output from one of the data reconstruction modules; The data calibration module receives data output from multiple cache modules and detects the delay deviation between target data from multiple data channels; The delay matrix module controls the time for each cache module to transmit data to the data calibration module based on delay deviation information. By delaying the output of read enable signals to at least a portion of the cache modules, each cache module outputs data with a certain time difference.

10. The multi-channel data alignment device based on delay compensation according to claim 9, characterized in that: The delay matrix module includes a delay channel corresponding to the data channel, and the delay channel has multiple delay units connected in series; The delay unit has a multiplexer and a delay unit. The delay unit receives an input signal, and the multiplexer receives the input signal and the signal output by the delay unit, and can selectively output either the input signal or the signal output by the delay unit.

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