Method for signaling maximum transform size and residual coding

Abstract

SUMMARY The present invention provides systems and methods for signaling a maximum transform size and residual coding methods. According to certain disclosed embodiments, the method comprises: receiving a bitstream comprising a set of pictures; determining, from the received bitstream, a value of a coding tree block size; and based on the value of the coding tree block size, determining whether to signal a flag indicating a maximum transform size of luma samples.

Description

[0001] Cross-reference to related applications

[0002] This disclosure claims priority to U.S. Provisional Application No. 62 / 980,117, filed on February 21, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to video processing, and more specifically, to methods and apparatus for signaling maximum transform size and residual coding methods. Background Technology

[0004] Video is a set of still images (or "frames") that capture visual information. To reduce storage memory and transmission bandwidth, video can be compressed before storage or transmission and then decompressed before display. The compression process is usually called encoding, and the decompression process is usually called decoding. There are various video coding formats that use standardized video coding techniques, the most common being prediction, transform, quantization, entropy coding, and in-loop filtering. Standardization organizations have developed video coding standards, such as the High Efficiency Video Coding (HEVC / H.265) standard, the Universal Video Coding (VVC / H.266) standard, and the AVS standard, specifying particular video coding formats. As more and more advanced video coding techniques are adopted in video standards, the coding efficiency of new video coding standards is becoming increasingly higher. Summary of the Invention

[0005] Embodiments of this disclosure provide a method and apparatus for signaling a maximum transform size. In some exemplary embodiments, the method includes: receiving a bitstream comprising a set of images; determining a value of a coding tree block size based on the received bitstream; and determining, based on the value of the coding tree block size, whether to signal a flag indicating the maximum transform size of a luminance sample.

[0006] The apparatus may include a memory storing an instruction set; and one or more processors configured to execute the instruction set to cause the apparatus to: receive a bitstream comprising a set of images; determine a value for a coded tree block size based on the received bitstream; and determine, based on the value of the coded tree block size, whether to signal a flag for a maximum transform size for luminance samples.

[0007] Embodiments of this disclosure also provide a non-transitory computer-readable medium storing an instruction set executable by at least one processor of a computer to cause the computer to perform a method for signaling a maximum transform size, the method comprising: receiving a bitstream comprising a set of images; determining a value of a coded tree block size based on the received bitstream; and determining, based on the value of the coded tree block size, whether to signal a flag indicating a maximum transform size for a luminance sample.

[0008] This disclosure also provides a method and apparatus for signaling a residual coding method. In some exemplary embodiments, the method includes: receiving a bitstream comprising a set of images; determining, based on the received bitstream, the value of the first flag indicating whether a transform skip mode is enabled; and determining, based on the value of the first flag, whether to signal a second flag indicating the residual coding method.

[0009] The apparatus may include a memory storing an instruction set; and one or more processors configured to execute the set of instructions to cause the apparatus to: receive a bitstream comprising a set of images; determine, based on the received bitstream, the value of the first flag indicating whether a transform skip mode is enabled; and, based on the value of the first flag, determine whether to signal a second flag indicating a residual coding method.

[0010] Embodiments of this disclosure also provide a non-transitory computer-readable medium storing an instruction set executable by at least one processor of a computer to cause the computer to perform a method for signaling a residual coding method, the method comprising: receiving a bitstream comprising a set of images; determining, based on the received bitstream, the value of the first flag indicating whether a transform skip mode is enabled; and determining, based on the value of the first flag, whether to signal an indication of a second flag indicating the residual coding method. Attached Figure Description

[0011] Embodiments and aspects of this disclosure are illustrated in the following detailed description and accompanying drawings. The various features shown in the figures are not drawn to scale.

[0012] Figure 1 This is a schematic diagram of the structure of an exemplary video sequence consistent with some embodiments of this disclosure.

[0013] Figure 2A This is a schematic diagram illustrating an exemplary encoding process of a hybrid video encoding system consistent with some embodiments of this disclosure.

[0014] Figure 2BThis is a schematic diagram illustrating another exemplary encoding process of a hybrid video encoding system consistent with some embodiments of this disclosure.

[0015] Figure 3A This is a schematic diagram illustrating an exemplary decoding process of a hybrid video coding system consistent with some embodiments of this disclosure.

[0016] Figure 3B This is a schematic diagram illustrating another exemplary decoding process of a hybrid video coding system consistent with some embodiments of this disclosure.

[0017] Figure 4 This is a block diagram of an exemplary apparatus for encoding or decoding video, consistent with some embodiments of this disclosure.

[0018] Figure 5A This is an exemplary method for signaling the maximum transformation size, consistent with some embodiments of this disclosure.

[0019] Figure 5B This is an exemplary method for signaling the maximum transformation size, consistent with some embodiments of this disclosure.

[0020] Figure 6A This is an exemplary method for signaling a residual coding method, consistent with some embodiments of this disclosure.

[0021] Figure 6B This is an exemplary method for signaling a residual coding method, consistent with some embodiments of this disclosure. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein, unless otherwise stated, the same numerals in different drawings denote the same or similar elements. The embodiments set forth in the following description of the exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with aspects of this disclosure as described in the appended claims. Specific aspects of this disclosure are described below in more detail. In the event of any conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall prevail.

[0023] The Joint Video Experts Group (JVET) of the ITU-T Video Coding Experts Group (ITU-T VCEG) and the ISO / IEC Moving Picture Experts Group (ISO / IEC MPEG) is currently developing the Universal Video Coding (VVC / H.266) standard. The VVC standard aims to double the compression efficiency of its predecessor, the High Efficiency Video Coding (HEVC / H.265) standard. In other words, VVC aims to achieve the same subjective quality as HEVC / H.265 using half the bandwidth.

[0024] To achieve the same subjective quality as HEVC / H.265 using half the bandwidth, JVET has been developing techniques other than HEVC using the Joint Exploratory Model (JEM) reference software. With the incorporation of coding techniques into JEM, JEM achieves higher coding performance than HEVC.

[0025] The VVC standard is a recent development and continues to include more coding techniques that provide better compression performance. VVC is based on a hybrid video coding system that has been used in modern video compression standards such as HEVC, H.264 / AVC, MPEG2, and H.263.

[0026] Video is a set of still images (or “frames”) arranged in chronological order to store visual information. These images can be captured and stored in chronological order using video capture devices (e.g., cameras), and displayed in a time-series using video playback devices (e.g., televisions, computers, smartphones, tablets, video players, or any end-user terminal with a display capability). Furthermore, in some applications, video capture devices can transmit captured video in real time to video playback devices (e.g., computers with monitors), such as for surveillance, conferencing, or live broadcasting.

[0027] To reduce the storage space and transmission bandwidth required for such applications, video can be compressed before storage and transmission, and decompressed before display. Compression and decompression can be implemented by software executed by a processor (e.g., a processor in a general-purpose computer) or dedicated hardware. The module used for compression is typically called an "encoder," and the module used for decompression is typically called a "decoder." Encoders and decoders can be collectively referred to as a "codec." Encoders and decoders can be implemented as any of a variety of suitable hardware, software, or combinations thereof. For example, hardware implementations of encoders and decoders can include circuits such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combination thereof. Software implementations of encoders and decoders can include program code embedded in a computer-readable medium, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process. Video compression and decompression can be implemented using various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, the H.26x series, etc. In some applications, a codec can decompress video from a first encoding standard and recompress the decompressed video using a second encoding standard; in this case, the codec can be referred to as a "transcoder."

[0028] Video encoding processes identify and retain useful information that can be used to reconstruct the image, while ignoring unimportant reconstruction information. If ignoring unimportant information prevents complete reconstruction, such an encoding process can be called "lossy." Otherwise, it can be called "lossless." Most encoding processes are lossy, a trade-off to reduce required storage space and transmission bandwidth.

[0029] Useful information about an encoded image (referred to as the "current image") includes changes relative to a reference image (e.g., a previously encoded and reconstructed image). Such changes can include variations in pixel position, brightness, or color, with positional changes being the most important. The positional changes of a set of pixels representing an object can reflect the object's movement between the reference and current images.

[0030] An image encoded without referencing another image (i.e., it is its own reference image) is called an "I-image". An image encoded using a previous image as a reference image is called a "P-image", and an image encoded using both a previous image and a future image as reference images is called a "B-image" (the reference is "bidirectional").

[0031] Figure 1 The structure of an example video sequence 100 according to some embodiments of the present disclosure is shown. The video sequence 100 may be live video or video that has been captured and archived. The video 100 may be real-life video, computer-generated video (e.g., computer game video), or a combination of both (e.g., real video with augmented reality effects). The video sequence 100 may be input from a video capture device (e.g., a camera), a video archive containing previously captured video (e.g., a video file stored on a storage device), or a video feed interface (e.g., a video broadcast transceiver) receiving video from a video content provider.

[0032] like Figure 1 As shown, video sequence 100 may include a series of images arranged temporally along a timeline, including images 102, 104, 106, and 108. Images 102-106 are consecutive, with more images between images 106 and 108. Figure 1 In this diagram, image 102 is an I-image, and its reference image is image 102 itself. Image 104 is a P-image, and its reference image is image 102, as indicated by the arrow. Image 106 is a B-image, and its reference images are images 104 and 108, as indicated by the arrow. In some embodiments, the reference image of an image (e.g., image 104) may not immediately precede or follow the image. For example, the reference image of image 104 may be an image preceding image 102. It should be noted that the reference images of images 102-106 are merely examples, and this disclosure does not limit the scope to such cases. Figure 1 An example of the reference image shown.

[0033] Typically, due to the computational complexity of encoding and decoding tasks, video codecs do not encode or decode the entire image at once. Instead, they can segment the image into basic segments and encode or decode each segment sequentially. In this disclosure, such basic segments are referred to as basic processing units (“BPUs”). For example, Figure 1 Structure 110 illustrates an example structure of an image (e.g., any of images 102-108) from video sequence 100. In structure 110, the image is divided into 4×4 basic processing units, whose boundaries are shown as dashed lines. In some embodiments, the basic processing unit may be referred to as a “macroblock” in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC), or as a “coding tree unit” (“CTU”) in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing unit may have a variable size in the image, such as 128×128, 64×64, 32×32, 16×16, 4×8, 16×32, or pixels of any shape and size. The size and shape of the basic processing units for the image can be chosen based on a balance between coding efficiency and the level of detail to be maintained within the basic processing units. The CTU is the largest block unit and can contain up to 128×128 luma samples (plus corresponding chroma samples depending on the chroma format). The CTU can be further divided into coding units (CUs) using quadtrees, binary trees, ternary trees, or combinations thereof.

[0034] A basic processing unit can be a logical unit that may include a set of different types of video data stored in computer memory (e.g., in a video frame buffer). For example, a basic processing unit for a color image may include a luminance component (Y) representing achromatic luminance information, one or more chrominance components (e.g., Cb and Cr) representing color information, and associated syntax elements, where the luminance and chrominance components may have the same size as the basic processing unit. In some video coding standards (e.g., H.265 / HEVC or H.266 / VVC), the luminance and chrominance components may be referred to as “code tree blocks” (“CTBs”). Any operation performed on a basic processing unit may be performed repeatedly on each of its luminance and chrominance components.

[0035] Video encoding involves multiple operational stages, examples of which are as follows: Figure 2A-2B and Figures 3A-3BAs shown. For each stage, the size of the basic processing unit may still be too large for the processing, and therefore can be further divided into segments referred to herein as "basic processing subunits". In some embodiments, the basic processing subunit may be referred to as a "block" in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC), or as a "coding unit" ("CU") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing subunit may have the same size as the basic processing unit or a smaller size. Similar to the basic processing unit, the basic processing subunit is also a logical unit that may include a set of different types of video data (e.g., Y, Cb, Cr, and associated syntax elements) stored in computer memory (e.g., in a video frame buffer). Any operation performed on the basic processing subunit may be repeated for each of its luminance and chrominance components. It should be noted that this division can be performed to further levels as needed for processing. It should also be noted that different schemes can be used to divide the basic processing units for different stages.

[0036] For example, in the pattern decision-making stage (examples of which are in...) Figure 2B As shown, the encoder can decide which prediction mode (e.g., intra-frame prediction or inter-frame prediction) to use for a basic processing unit, which may be too large to make such a decision. The encoder can divide the basic processing unit into multiple basic processing subunits (e.g., CUs in H.265 / HEVC or H.266 / VVC) and determine the prediction type for each individual basic processing subunit.

[0037] For another example, in the prediction phase (the example is in...) Figure 2A-2B As shown in the diagram, the encoder can perform prediction operations at the level of a basic processing subunit (e.g., a CU). However, in some cases, the basic processing subunit may still be too large to handle. The encoder can further divide the basic processing subunit into smaller segments (e.g., referred to as "prediction blocks" or "PBs" in H.265 / HEVC or H.266 / VVC) at which prediction operations can be performed.

[0038] For another example, in the transformation phase (the example of which is in...) Figure 2A-2BAs shown in the diagram, the encoder can perform transformation operations on residual basic processing subunits (e.g., CUs). However, in some cases, the basic processing subunits may still be too large to process. The encoder can further divide the basic processing subunits into smaller segments (e.g., referred to as "transform blocks" or "TBs" in H.265 / HEVC or H.266 / VVC), at which level transformation operations can be performed. It is important to note that the partitioning scheme of the same basic processing subunit can differ between the prediction and transformation phases. For example, in H.265 / HEVC or H.266 / VVC, the prediction blocks and transform blocks of the same CU can have different sizes and numbers.

[0039] exist Figure 1 In structure 110, the basic processing unit 112 is further divided into 3×3 basic processing sub-units, the boundaries of which are shown by dashed lines. Different basic processing units of the same image can be divided into basic processing sub-units in different schemes.

[0040] In some implementations, to provide parallel processing capabilities and fault tolerance for video encoding and decoding, an image can be divided into regions for processing, such that the encoding or decoding process for a given region of the image can be independent of information from any other region of the image. In other words, each region of the image can be processed independently. By doing so, the codec can process different regions of the image in parallel, thereby improving encoding efficiency. Furthermore, when data in one region is corrupted during processing or lost during network transmission, the codec can correctly encode or decode other regions of the same image without relying on the corrupted or lost data, thus providing fault tolerance. In some video coding standards, images can be divided into different types of regions. For example, H.265 / HEVC and H.266 / VVC provide two types of regions: “slices” and “tiles.” It should also be noted that different images in the video sequence 100 can have different partitioning schemes for dividing the image into regions.

[0041] For example, in Figure 1 In the diagram, structure 110 is divided into three regions 114, 116, and 118, whose boundaries are shown as solid lines within structure 110. Region 114 comprises four basic processing units. Regions 116 and 118 each comprise six basic processing units. It should be noted that... Figure 1 The basic processing unit, basic processing subunit, and structural region of 110 are merely examples, and this disclosure does not limit its embodiments.

[0042] Figure 2A A schematic diagram of an exemplary encoding process 200A according to an embodiment of the present disclosure is shown. For example, the encoding process 200A may be performed by an encoder. Figure 2AAs shown, the encoder can encode the video sequence 202 into a video bitstream 228 according to process 200A. Similar to... Figure 1 Video sequence 100 and video sequence 202 may include a set of images arranged in chronological order (referred to as "original images"). Similar to... Figure 1 In structure 110, each raw image of video sequence 202 can be divided into basic processing units, basic processing subunits, or regions by an encoder for processing. In some embodiments, the encoder can perform process 200A at the level of basic processing units for each raw image of video sequence 202. For example, the encoder can perform process 200A iteratively, wherein the encoder can encode basic processing units in one iteration of process 200A. In some embodiments, the encoder can perform process 200A in parallel for regions (e.g., regions 114-118) of each raw image of video sequence 202.

[0043] refer to Figure 2A The encoder feeds the basic processing unit (referred to as the "raw BPU") of the original image of video sequence 202 to prediction stage 204 to generate prediction data 206 and prediction BPU 208. The encoder subtracts the predicted BPU 208 from the raw BPU to generate residual BPU 210. The encoder feeds residual BPU 210 to transform stage 212 and quantization stage 214 to generate quantization transform coefficients 216. The encoder feeds prediction data 206 and quantization transform coefficients 216 to binary encoding stage 226 to generate video bitstream 228. Components 202, 204, 206, 208, 210, 212, 214, 216, 226, and 228 may be referred to as the "forward path". During process 200A, after quantization stage 214, the encoder feeds quantization transform coefficients 216 to inverse quantization stage 218 and inverse transform stage 220 to generate reconstructed residual BPU 222. The encoder can add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a prediction reference 224, which is used in the prediction stage 204 of the next iteration of process 200A. Components 218, 220, 222, and 224 of process 200A can be referred to as the "reconstruction path". The reconstruction path can be used to ensure that both the encoder and decoder use the same reference data for prediction.

[0044] The encoder can iteratively execute process 200A to encode each raw BPU (in the forward path) of the original image and generate a prediction reference 224 for encoding the next raw BPU (in the reconstruction path) of the original image. After encoding all raw BPUs of the original image, the encoder can continue to encode the next image in the video sequence 202.

[0045] Referring to process 200A, the encoder may receive a video sequence 202 generated by a video acquisition device (e.g., a camera). As used herein, the term "receive" can refer to any action that receives, inputs, acquires, retrieves, obtains, reads, accesses, or is used for inputting data in any manner.

[0046] In prediction phase 204, during the current iteration, the encoder can receive the original BPU and prediction reference 224, and perform prediction operations to generate prediction data 206 and prediction BPU 208. Prediction reference 224 can be generated from the reconstruction path of previous iterations of process 200A. The purpose of prediction phase 204 is to reduce information redundancy by extracting prediction data 206 from prediction data 206 and prediction reference 224 that can be used to reconstruct the original BPU into prediction BPU 208.

[0047] Ideally, the predicted BPU 208 should be identical to the original BPU. However, due to non-ideal prediction and reconstruction operations, the predicted BPU 208 is typically slightly different from the original BPU. To record these differences, the encoder can subtract the predicted BPU 208 from the original BPU to generate a residual BPU 210. For example, the encoder can subtract the value of the corresponding pixel in the predicted BPU 208 (e.g., grayscale or RGB value) from the pixel value of the original BPU. Each pixel in the residual BPU 210 can have a residual value as the result of this subtraction between the corresponding pixel in the original BPU and the predicted BPU 208. Compared to the original BPU, the predicted data 206 and the residual BPU 210 can have fewer bits, but they can be used to reconstruct the original BPU without a significant quality degradation. Thus, the original BPU is compressed.

[0048] To further compress the residual BPU 210, in the transform stage 212, the encoder can reduce its spatial redundancy by decomposing the residual BPU 210 into a set of two-dimensional “base patterns”. Each base pattern is associated with “transform coefficients”. The base patterns can have the same size (e.g., the size of the residual BPU 210), and each base pattern can represent the frequency (e.g., the frequency of brightness variation) component of the residual BPU 210. None of the base patterns can be reproduced from any combination (e.g., a linear combination) of any other base patterns. In other words, the decomposition decomposes the variation of the residual BPU 210 into the frequency domain. This decomposition is analogous to the discrete Fourier transform of a function, where the base patterns are analogous to the base functions of the discrete Fourier transform (e.g., trigonometric functions), and the transform coefficients are analogous to the coefficients associated with the base functions.

[0049] Different transform algorithms can use different base patterns. Various transform algorithms, such as discrete cosine transform, discrete sine transform, etc., can be used in transform stage 212. The transform at transform stage 212 is reversible. That is, the encoder can recover the residual BPU 210 through the inverse operation of the transform (called the "inverse transform"). For example, to recover the pixels of the residual BPU 210, the inverse transform can be to multiply the values ​​of the corresponding pixels of the base pattern by the corresponding correlation coefficients and sum the products to produce a weighted sum. For video coding standards, both the encoder and decoder can use the same transform algorithm (and therefore have the same base pattern). Therefore, the encoder can only record the transform coefficients, from which the decoder can reconstruct the residual BPU 210 without receiving the base pattern from the encoder. Compared to the residual BPU 210, the transform coefficients can have fewer bits, but they can be used to reconstruct the residual BPU 210 without significant quality degradation. Therefore, the residual BPU 210 is further compressed.

[0050] The encoder can further compress the transform coefficients during the quantization stage 214. During the transform process, different fundamental patterns can represent different frequencies of change (e.g., brightness change frequencies). Because the human eye is generally better at recognizing low-frequency changes, the encoder can ignore information about high-frequency changes without causing significant quality degradation in decoding. For example, in the quantization stage 214, the encoder can generate quantized transform coefficients 216 by dividing each transform coefficient by an integer value (called the “quantization parameter”) and rounding the quotient to its nearest integer. After such an operation, some transform coefficients of the high-frequency fundamental patterns can be converted to zero, and the transform coefficients of the low-frequency fundamental patterns can be converted to smaller integers. The encoder can ignore the zero-valued quantized transform coefficients 216, thus further compressing the transform coefficients. This quantization process is also reversible, where the quantized transform coefficients 216 can be reconstructed into transform coefficients in the inverse operation of quantization (called “inverse quantization”).

[0051] Because the encoder ignores the remainder of the division during rounding, quantization stage 214 can be lossy. Typically, quantization stage 214 contributes the most to information loss in process 200A. The greater the information loss, the fewer bits are required for the quantization transform coefficients 216. To obtain different levels of information loss, the encoder can use different quantization parameter values ​​or any other parameter of the quantization process.

[0052] In the binary encoding stage 226, the encoder can encode the prediction data 206 and the quantization transform coefficients 216 using binary encoding techniques, such as entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless or lossy compression algorithm. In some embodiments, in addition to the prediction data 206 and the quantization transform coefficients 216, the encoder can encode other information in the binary encoding stage 226, such as the prediction mode used in the prediction stage 204, the parameters of the prediction operation, the transform type at the transform stage 212, the parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bit rate control parameters), etc. The encoder can use the output data of the binary encoding stage 226 to generate a video bitstream 228. In some embodiments, the video bitstream 228 can be further packaged for network transmission.

[0053] Following the reconstruction path of process 200A, in the inverse quantization stage 218, the encoder can perform inverse quantization on the quantized transform coefficients 216 to generate reconstructed transform coefficients. In the inverse transform stage 220, the encoder can generate a reconstruction residual BPU 222 based on the reconstructed transform coefficients. The encoder can add the reconstruction residual BPU 222 to the prediction BPU 208 to generate a prediction reference 224 that will be used in the next iteration of process 200A.

[0054] It should be noted that other variations of process 200A can be used to encode video sequence 202. In some embodiments, the stages of process 200A may be performed by the encoder in different orders. In some embodiments, one or more stages of process 200A may be combined into a single stage. In some embodiments, a single stage of process 200A may be divided into multiple stages. For example, transform stage 212 and quantization stage 214 may be combined into a single stage. In some embodiments, process 200A may include additional stages. In some embodiments, process 200A may be omitted. Figure 2A One or more stages in the process.

[0055] Figure 2B A schematic diagram of another example encoding process 200B according to an embodiment of the present disclosure is shown. Process 200B can be modified from process 200A. For example, process 200B can be used by an encoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared to process 200A, the forward path of process 200B further includes a mode decision stage 230, and divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044. The reconstruction path of process 200B also additionally includes a loop filtering stage 232 and a buffer 234.

[0056] Generally, prediction techniques can be categorized into two types: spatial prediction and temporal prediction. Spatial prediction (e.g., intra-frame image prediction or "intra-prediction") uses pixels from one or more already encoded neighboring BPUs in the same image to predict the current BPU. That is, the prediction reference 224 in spatial prediction can include neighboring BPUs. Spatial prediction can reduce the inherent spatial redundancy of images. Temporal prediction (e.g., inter-image prediction or "inter-frame prediction") uses regions from one or more already encoded images to predict the current BPU. That is, the prediction reference 224 in temporal prediction can include encoded images. Temporal prediction can reduce the inherent temporal redundancy of images.

[0057] In reference process 200B, during the forward path, the encoder performs prediction operations in spatial prediction phase 2042 and temporal prediction phase 2044. For example, in spatial prediction phase 2042, the encoder may perform intra-frame prediction. For the original BPU of the encoded image, prediction reference 224 may include one or more adjacent BPUs that have been encoded (in the forward path) and reconstructed (in the reconstruction path) in the same image. The encoder can generate the predicted BPU 208 by interpolating adjacent BPUs. Interpolation techniques may include, for example, linear interpolation or interpolation, polynomial interpolation or interpolation, etc. In some embodiments, the encoder may perform interpolation at the pixel level, for example, by interpolating to predict the value of the corresponding pixel for each pixel of BPU 208. The adjacent BPUs used for interpolation may be located in various directions relative to the original BPU, such as in the vertical direction (e.g., at the top of the original BPU), the horizontal direction (e.g., to the left of the original BPU), the diagonal direction (e.g., at the lower left, lower right, upper left, or upper right of the original BPU), or any direction defined in the video coding standard used. For intra-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the neighboring BPUs used, the size of the neighboring BPUs used, the interpolation parameters, the orientation of the neighboring BPUs used relative to the original BPU, etc.

[0058] In another example, during the temporal prediction phase 2044, the encoder can perform inter-frame prediction. For the original BPU of the current image, the prediction reference 224 can include one or more images (referred to as "reference images") that have been encoded (in the forward path) and reconstructed (in the reconstruction path). In some embodiments, the reference images can be encoded and reconstructed on a BPU-by-BPU basis. For example, the encoder can add the reconstructed residual BPU 222 to the prediction BPU 208 to generate a reconstructed BPU. When all reconstructed BPUs for the same image have been generated, the encoder can generate a reconstructed image as the reference image. The encoder can perform a "motion estimation" operation to search for matching regions within the range of the reference image (referred to as a "search window"). The position of the search window in the reference image can be determined based on the position of the original BPU in the current image. For example, the search window can be centered at a location in the reference image that has the same coordinates as the original BPU in the current image and can extend outward by a predetermined distance. When the encoder identifies a region in the search window that resembles the original BPU (e.g., by using a PEL recursive algorithm, a block matching algorithm, etc.), the encoder can determine such a region as a matching region. The matching region can have a different size than the original BPU (e.g., less than, equal to, greater than, or with a different shape). This is because the reference image and the current image are temporally separated on the timeline (e.g., as...). Figure 1 As shown in the image, the matching region can be considered to have "moved" to the original BPU's location over time. The encoder can record the direction and distance of this movement as a "motion vector." When using multiple reference images (e.g., such as...), Figure 1 In image 106, the encoder can search for matching regions and determine the associated motion vector for each reference image. In some embodiments, the encoder can assign weights to the pixel values ​​of the matching regions of each matching reference image.

[0059] Motion estimation can be used to identify various types of motion, such as translation, rotation, scaling, etc. For inter-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the matching region, the motion vector associated with the matching region, the number of reference images, the weights associated with the reference images, etc.

[0060] To generate the predicted BPU 208, the encoder can perform a "motion compensation" operation. Motion compensation can be used to reconstruct the predicted BPU 208 based on the predicted data 206 (e.g., motion vectors) and the predicted reference 224. For example, the encoder can move a matching region of the reference image according to the motion vectors, where the encoder can predict the original BPU of the current image. When using multiple reference images (e.g., such as...), Figure 1In image 106), the encoder can move the matching region of the reference image based on the individual motion vectors and average pixel values ​​of the matching region. In some embodiments, if the encoder has already assigned weights to the pixel values ​​of the matching regions of the respective matching reference images, the encoder can add the weighted sums of the pixel values ​​of the moved matching regions.

[0061] In some embodiments, inter-frame prediction can be unidirectional or bidirectional. Unidirectional inter-frame prediction can use one or more reference images in the same temporal direction relative to the current image. For example, Figure 1 Image 104 in the diagram is a one-way inter-frame prediction image, where the reference image (i.e., image 102) precedes image 104. Two-way inter-frame prediction can use one or more reference images in two temporal directions relative to the current image. For example, Figure 1 Image 106 in the image is a bidirectional inter-frame prediction image, in which the reference image (i.e., images 104 and 08) is relative to image 104 in two temporal directions.

[0062] Referring again to the forward path of process 200B, after spatial prediction 2042 and temporal prediction stages 2044, in the mode decision stage 230, the encoder can select a prediction mode (e.g., one of intra-frame prediction or inter-frame prediction) for the current iteration of process 200B. For example, the encoder can perform a rate distortion optimization technique, whereby the encoder selects a prediction mode based on the bit rate of the candidate prediction modes and the distortion of the reconstructed reference image under the candidate prediction modes to minimize the value of the cost function. Based on the selected prediction mode, the encoder can generate the corresponding prediction BPU 208 and prediction data 206.

[0063] In the reconstruction path of process 200B, if intra-frame prediction mode has been selected in the forward path, the encoder can directly feed prediction reference 224 (e.g., the current BPU that has been encoded and reconstructed in the current image) to spatial prediction stage 2042 for later use (e.g., for interpolating the next BPU of the current image) after generating prediction reference 224. If inter-frame prediction mode has been selected in the forward path, the encoder can feed prediction reference 224 (e.g., the current image where all BPUs have been encoded and reconstructed) to loop filter stage 232 after generating prediction reference 224. In this stage, the encoder can apply loop filters to prediction reference 224 to reduce or eliminate distortions introduced by inter-frame prediction (e.g., block artifacts). The encoder can apply various loop filter techniques at loop filter stage 232, such as deblocking, adaptive sampling compensation, adaptive loop filtering, etc. The loop-filtered reference image can be stored in buffer 234 (or "decoded image buffer") for later use (e.g., as an inter-frame prediction reference image for future images of video sequence 202). The encoder can store one or more reference images in buffer 234 for use at temporal prediction stage 2044. In some embodiments, the encoder can encode parameters of the loop filter (e.g., loop filter strength) as well as quantization transform coefficients 216, prediction data 206, and other information at binary encoding stage 226.

[0064] Figure 3A A schematic diagram of an exemplary decoding process 300A according to an embodiment of the present disclosure is shown. Process 300A may be corresponding to Figure 2A The compression process 200A in the video stream is followed by the decompression process. In some embodiments, process 300A can be similar to the reconstruction path of process 200A. The decoder can decode the video bitstream 228 into video stream 304 according to process 300A. Video stream 304 can be very similar to video sequence 202. However, due to information loss during compression and decompression (e.g., Figure 2A-2B In the quantization stage 214), the video stream 304 is typically different from the video sequence 202. Similar to... Figure 2A-2B In processes 200A and 200B, the decoder can perform process 300A at the basic processing unit (BPU) level for each image encoded in the video bitstream 228. For example, the decoder can perform process 300A iteratively, where the decoder can decode the basic processing unit in one iteration of process 300A. In some embodiments, the decoder can perform process 300A in parallel for a region (e.g., region 114-118) of each image encoded in the video bitstream 228.

[0065] like Figure 3AAs shown, the decoder can feed a portion of the video bitstream 228 associated with a basic processing unit (referred to as the "encoded BPU") of the encoded image to the binary decoding stage 302. In the binary decoding stage 302, the decoder can decode this portion into prediction data 206 and quantization transform coefficients 216. The decoder can feed the quantization transform coefficients 216 to the inverse quantization stage 218 and the inverse transform stage 220 to generate a reconstruction residual BPU 222. The decoder can feed the prediction data 206 to the prediction stage 204 to generate a prediction BPU 208. The decoder can add the reconstruction residual BPU 222 to the prediction BPU 208 to generate a prediction reference 224. In some embodiments, the prediction reference 224 can be stored in a buffer (e.g., a decoded image buffer in computer memory). The decoder can feed the prediction reference 224 to the prediction stage 204 for performing a prediction operation in the next iteration of process 300A.

[0066] The decoder can iteratively execute process 300A to decode each encoded BPU of the encoded image and generate a prediction reference 224 for the next encoded BPU of the encoded image. After decoding all encoded BPUs of the encoded image, the decoder can output the image to video stream 304 for display and continue decoding the next encoded image in video bit stream 228.

[0067] In the binary decoding stage 302, the decoder can perform the inverse operation of the binary encoding technique used by the encoder (e.g., entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless compression algorithm). In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the decoder can decode other information in the binary decoding stage 302, such as the prediction mode, parameters of the prediction operation, transform type, parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bit rate control parameters), etc. In some embodiments, if the video bitstream 228 is transmitted over a network in packets, the decoder can unpack it before feeding the video bitstream 228 to the binary decoding stage 302.

[0068] Figure 3B A schematic diagram of another example decoding process 300B according to an embodiment of the present disclosure is shown. Process 300B can be modified from process 300A. For example, process 300B can be used by a decoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared to process 300A, process 300B additionally divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044, and additionally includes a loop filtering stage 232 and a buffer 234.

[0069] In process 300B, for the encoding basic processing unit (referred to as the "current BPU") of the decoded encoded image (referred to as the "current image"), the prediction data 206 decoded by the decoder from the binary decoding stage 302 can include various types of data depending on the prediction mode used by the encoder to encode the current BPU. For example, if the encoder uses intra-frame prediction to encode the current BPU, the prediction data 206 can include prediction mode indicators (e.g., flag values) that indicate intra-frame prediction, parameters of the intra-frame prediction operation, etc. Parameters of the intra-frame prediction operation can include, for example, the positions (e.g., coordinates) of one or more neighboring BPUs used as references, the sizes of neighboring BPUs, interpolation parameters, the orientation of neighboring BPUs relative to the original BPU, etc. For another example, if the current BPU is encoded by inter-frame prediction used by the encoder, the prediction data 206 can include prediction mode indicators (e.g., flag values) that indicate inter-frame prediction, parameters of the inter-frame prediction operation, etc. The parameters of the inter-frame prediction operation may include, for example, the number of reference images associated with the current BPU, the weights associated with the reference images respectively, the positions (e.g., coordinates) of one or more matching regions in the corresponding reference images, and one or more motion vectors associated with the matching regions respectively.

[0070] Based on the prediction mode indicator, the decoder can decide whether to perform spatial prediction (e.g., intra-frame prediction) in the spatial prediction phase 2042 or temporal prediction (e.g., inter-frame prediction) in the temporal prediction phase 2044. The details of performing this spatial or temporal prediction are... Figure 2B As described herein, it will not be repeated below. After performing such spatial or temporal prediction, the decoder can generate a predicted BPU 208, which can be added to the predicted BPU 208 and the reconstructed residual BPU 222 to generate a prediction reference 224, as shown below. Figure 3A As described in [the text].

[0071] In process 300B, the decoder can feed prediction reference 224 to either spatial prediction stage 2042 or temporal prediction stage 2044 for performing prediction operations in the next iteration of process 300B. For example, if intra-frame prediction is used to decode the current BPU in spatial prediction stage 2042, the decoder can feed prediction reference 224 directly to spatial prediction stage 2042 for later use (e.g., for interpolating the next BPU of the current image) after generating prediction reference 224 (e.g., the decoded current BPU). If inter-frame prediction is used to decode the current BPU in temporal prediction stage 2044, the encoder can feed prediction reference 224 to loop filter stage 232 to reduce or eliminate distortion (e.g., block artifacts) after generating prediction reference 224 (e.g., a reference image where all BPUs are decoded). The decoder can, as follows: Figure 2BThe loop filter is applied to prediction reference 224 in the manner shown. The loop-filtered reference image can be stored in buffer 234 (e.g., a decoded image buffer in computer memory) for later use (e.g., as an inter-prediction reference image for future encoded images of video bitstream 228). The decoder can store one or more reference images in buffer 234 for use at temporal prediction stage 2044. In some embodiments, the prediction data can further include parameters of the loop filter (e.g., loop filter strength) when the prediction mode indicator of prediction data 206 indicates that inter-frame prediction is used to encode the current BPU.

[0072] Figure 4 This is a block diagram of an example apparatus 400 for encoding or decoding video according to embodiments of the present disclosure. Figure 4 As shown, device 400 may include processor 402. When processor 402 executes the instructions described herein, device 400 may become a dedicated machine for video encoding or decoding. Processor 402 may be any type of circuit capable of manipulating or processing information. For example, processor 402 may include any number of central processing units (or “CPU”), graphics processing units (or “GPU”), neural processing units (“NPU”), microcontroller units (“MCU”), optical processors, programmable logic controllers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), application-specific integrated circuits (ASICs), and any combination thereof. In some embodiments, processor 402 may also be a group of processors grouped into individual logic components. For example, such as Figure 4 As shown, processor 402 may include multiple processors, including processor 402a, processor 402b and processor 402n.

[0073] The device 400 may also include a memory 404 configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, such as Figure 4As shown, the stored data may include program instructions (e.g., for implementing stages in processes 200A, 200B, 300A, or 300B) and data for processing (e.g., video sequence 202, video bitstream 228, or video stream 304). Processor 402 can access the program instructions and data for processing (e.g., via bus 410) and execute the program instructions to perform operations or manipulations on the data for processing. Memory 404 may include a high-speed random access memory device or a non-volatile memory device. In some embodiments, memory 404 may include any combination of any number of random access memories (RAM), read-only memories (ROM), optical discs, magnetic disks, hard disks, solid-state drives, flash drives, secure digital cards (SD cards), memory sticks, compact flash memory (CF cards), etc. Memory 404 may also be a group of memories grouped into single logical components. Figure 4 (Not shown in the image).

[0074] Bus 410 may be a communication device for transmitting data between components within device 400, such as an internal bus (e.g., CPU-memory bus), an external bus (e.g., a Universal Serial Bus port, a Peripheral Component Interconnect Fast Port), or the like.

[0075] For ease of explanation and to avoid ambiguity, the processor 402 and other data processing circuitry are collectively referred to as "data processing circuitry" in this disclosure. The data processing circuitry may be implemented entirely in hardware, or as a combination of software, hardware, or firmware. Furthermore, the data processing circuitry may be a single, separate module, or may be wholly or partially integrated into any other component of the device 400.

[0076] The device 400 may also include a network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, intranet, local area network, mobile communication network, etc.). In some embodiments, the network interface 406 may include any combination of any number of network interface controllers (NICs), radio frequency (RF) modules, transceivers, transceivers, modems, routers, gateways, wired network adapters, wireless network adapters, Bluetooth adapters, infrared adapters, near field communication (“NFC”) adapters, cellular network chips, etc.

[0077] In some embodiments, optionally, the device 400 may further include a peripheral interface 408 to provide connectivity to one or more peripheral devices. Figure 4 As shown, peripheral devices may include, but are not limited to, cursor control devices (e.g., mouse, touchpad, or touchscreen), keyboards, displays (e.g., cathode ray tube displays, liquid crystal displays, or light-emitting diode displays), video input devices (e.g., cameras or input interfaces coupled to video files), etc.

[0078] It should be noted that the video codec (e.g., the codec for executing processes 200A, 200B, 300A, or 300B) can be implemented as any combination of any software or hardware modules in device 400. For example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more software modules of device 400, such as program instances that can be loaded into memory 404. As another example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more hardware modules of device 400, such as dedicated data processing circuitry (e.g., FPGA, ASIC, NPU, etc.).

[0079] In the first reference embodiment, the sequence parameter set (SPS) syntax element sps_max_luma_transform_size_64flag is signaled to specify the maximum transform size.

[0080] `sps_max_luma_transform_size_64flag` equal to 1 indicates that the maximum transform size in the luminance sample is 64. `sps_max_luma_transform_size_64flag` equal to 0 indicates that the maximum transform size in the luminance sample is 32. In the first reference embodiment, `sps_max_luma_transform_size_64flag` is always signaled regardless of the value of the coding tree block size (CtbSizeY). However, if CtbSizeY is less than 64, there is no need to signal `sps_max_luma_transform_size_64_flag`, and it can be inferred that it is 0.

[0081] Furthermore, in the second reference embodiment, a stripe-level residual coding selection method can be used. The following is an example of the semantics of slice_ts_residual_coding_disabled_flag:

[0082]

[0083] In the second reference embodiment, slice_ts_residual_coding_disabled_flag is always notified by a signal. However, since slice_ts_residual_coding_disabled_flag specifies the residual coding method for transform skip mode, if transform skip mode is disabled at the SPS level, it is not necessary to notify slice_ts_residual_coding_disabled_flag by a signal in the slice header, and it can be inferred that it is 0.

[0084] This disclosure provides methods and apparatus for reducing the aforementioned coding redundancy.

[0085] Figure 5A This is an exemplary method for signaling the maximum transformation size, consistent with some embodiments of this disclosure. In some embodiments, method 500A may be comprised of an encoder, a decoder, and devices (e.g., Figure 4 The device 400) is executed by one or more software or hardware components. For example, a processor (e.g., Figure 4 The processor 402) can execute method 500A. In some embodiments, method 500A may be implemented by a computer program product contained in a computer-readable medium, the computer program product comprising a processor 402 (e.g., a computer program product containing a processor 402) that executes method 500A. Figure 4 The device 400 executes computer-executable instructions, such as program code. The method may include the following steps.

[0086] In step 501, a bitstream comprising a set of images is received. As described, a basic processing unit for a color image may include a luminance component (Y) representing achromatic luminance information, one or more chrominance components (e.g., Cb and Cr) representing color information, and associated syntax elements, wherein the luminance and chrominance components may have the same size as the basic processing unit. In some video coding standards (e.g., H.265 / HEVC or H.266 / VVC), the luminance and chrominance components may be referred to as “code tree blocks” (“CTBs”). Any operation performed on a basic processing unit may be repeated on each of its luminance and chrominance components.

[0087] In step 503, the value of the coded tree block size is determined based on the received bit stream. The value of the coded tree block size is signaled in the received bit stream. For example, the value of CtbSizeY in the exemplary semantics is determined.

[0088] In step 505, a flag indicating the maximum transform size of the luminance samples is determined based on the value of the coding tree block size. For example, the Sequence Parameter Set (SPS) syntax element `sps_max_luma_transform_size_64flag` can be used to specify the maximum transform size. `sps_max_luma_transform_size_64flag` equal to 1 indicates that the maximum transform size in the luminance samples is 64. `sps_max_luma_transform_size_64flag` equal to 0 indicates that the maximum transform size in the luminance samples is 32.

[0089] In some embodiments, step 505 may include, for example: Figure 5B Steps 505-1, 505-3, and 505-5 are shown.

[0090] In step 505-1, the value of the coded tree block size is determined based on the received bit stream to determine whether it satisfies the first condition or the second condition.

[0091] In some embodiments, the first condition may be a value greater than 32, and the second condition may be a value less than or equal to 32. Meeting the first condition will cause a flag indicating the maximum change size to be signaled. Otherwise, meeting the second condition will cause it to be determined that the flag has not been signaled.

[0092] In step 505-3, in response to a value greater than 32 for the coded tree block size, the flag is signaled.

[0093] Exemplary SPS syntax is described below in Table 1. In some exemplary embodiments for signaling the maximum transform size, the sps_max_luma_transform_size_64 flag is signaled only if CtbSizeY is greater than 32. Table 1 shows a portion of an exemplary SPS syntax table for signaling the maximum transform size according to some disclosed embodiments. In Table 1, rows with "if(CtbSizeY>32)" indicate changes to the syntax used in the first reference embodiment. As described, in the first reference embodiment, sps_max_luma_transform_size_64_flag is always signaled regardless of the value of the encoding tree block size (CtbSizeY). Conversely, according to some embodiments of this disclosure, sps_max_luma_transform_size_64_flag is not always signaled. As shown in Table 1, signaling of sps_max_luma_transform_size_64_flag is conditional on CtbSizeY.

[0094] Table 1: Exemplary SPS syntax table for the disclosed method for signal notification of maximum transformation size

[0095]

[0096] In step 505-5, in response to the value of the encoded tree block size being less than or equal to 32, it is determined that the flag was not signaled.

[0097] In the signaling method consistent with Table 1, if CtbSizeY is not greater than 32, the value of sps_max_luma_transform_size_64_flag is inferred to be 0. The semantics of CtbSizeY are derived as follows.

[0098]

[0099] In some embodiments, the first and second conditions may differ from those described above. In the example below, the first condition may be a value not equal to 32, and the second condition may be a value equal to 32.

[0100] In the alternative step of step 505-3, a flag is signaled in response to the value of the coded tree block size not being equal to 32.

[0101] In an alternative step 505-5, in response to the value of the encoded tree block size being equal to 32, it is determined that the flag has not been signaled.

[0102] An exemplary syntax is described below. The suggested syntax change shown in Table 1 can also be implemented using the condition "CtbSizeY != 32" instead of "CtbSizeY > 32". In this case: if CtbSizeY is not equal to 32, then sps_max_luma_transform_size_64flag is signaled; if CtbSizeY is equal to 32, then sps_max_luma_transform_size_64flag is inferred to be 0.

[0103] An exemplary syntax description is as follows. The suggested syntax change shown in Table 1 can also be implemented using the condition "CtbSizeY>=64" instead of "CtbSizeY>32". In this case: if CtbSizeY is greater than or equal to 64, then sps_max_luma_transform_size_64flag is signaled; if CtbSizeY is less than 64, then sps_max_luma_transform_size_64flag is inferred to be 0. In other words, sps_max_luma_transform_size_64flag only needs to be signaled when CtbSizeY is greater than 32. If CtbSizeY is not greater than 32, then sps_max_luma_transform_size_64flag is not signaled and is inferred to be equal to 0. Alternatively, sps_max_luma_transform_size_64flag is only signaled when CtbSizeY is greater than or equal to 64. If CtbSizeY is less than 64, then sps_max_luma_transform_size_64_flag will not be signaled and its value will not be inferred to be 0.

[0104] In some exemplary embodiments for signaling the maximum transform size, the notification of `sps_max_luma_transform_size_64_flag` is conditional on `sps_log2_ctu_size_minus5` instead of using `CtbSizeY`. As described above, `sps_log2_ctu_size_minus5` plus 5 specifies the luma code tree block size for each code tree unit (CTU). A CTU can be 128×128 luma samples (plus corresponding chroma samples depending on the chroma format). Table 2 below shows a portion of an exemplary SPS syntax table for signaling the maximum transform size according to some disclosed embodiments. In Table 2, rows with "if(sps_log2_ctu_size_minus5>0)" show changes to the syntax used in the first reference embodiment. As described, in the first reference embodiment, `sps_max_luma_transform_size_64_flag` is always signaled regardless of the value of the code tree block size (e.g., `CtbSizeY`). Conversely, according to some embodiments of this disclosure, sps_max_luma_transform_size_64_flag is not always signaled. As shown in Table 2, in some embodiments, signaling of sps_max_luma_transform_size_64_flag is conditional on sps_log2_ctu_size_minus5. As shown in Table 2, if sps_log2_ctu_size_minus5 is greater than 0, sps_max_luma_transform_size_64_flag is signaled; if sps_log2_ctu_size_minus5 is 0, the value of sps_max_luma_transform_size_64_flag is inferred to be 0.

[0105] In some embodiments, the value of the coding tree block size in step 501 may also include a value associated with the luminance coding tree block size of each coding tree unit. This value (e.g., sps_log2_ctu_size_minus5) can be determined based on the received bitstream.

[0106] In some embodiments, in an alternative step 505-1, it may be determined whether the value associated with the luminance coding tree block size of each coding tree unit satisfies a first condition (e.g., greater than 0) or a second condition (e.g., equal to 0).

[0107] In some embodiments, in an alternative step of steps 505-3, the flag (e.g., sps_max_luma_transform_size_64_flag) is signaled in response to a value associated with the luminance coding tree block size of each coding tree unit satisfying a first condition (e.g., greater than 0).

[0108] In some embodiments, in an alternative step of steps 505-5, in response to a value associated with the luminance coding tree block size of each coding tree unit satisfying a second condition (e.g., equal to 0), it is determined that the flag (e.g., sps_max_luma_transform_size_64_flag) is not signaled.

[0109] Table 2: Exemplary SPS syntax table for the disclosed method of signaling the maximum transformation size

[0110]

[0111] The syntax changes shown in Table 2 can also be implemented using the condition "sps_log2_ctu_size_minus5 != 0". In this case: if sps_log2_ctu_size_minus5 is not equal to 0, then sps_max_luma_transform_size_64_flag is signaled; if sps_log2_ctu_size_minus5 is equal to 0, then sps_max_luma_transform_size_64_flag is inferred to be 0.

[0112] In some embodiments, the first condition may also be a non-zero value (e.g., sps_log2_ctu_size_minus5), as shown in the example above. In an alternative step of steps 505-3, in response to the value associated with the luma coding tree block size of each coding tree unit satisfying the first condition (e.g., sps_log2_ctu_size_minus5 != 0), a flag (e.g., sps_max_luma_transform_size_64_flag) is signaled.

[0113] Figure 6 illustrates an exemplary method for signaling a residual coding method, consistent with some embodiments of this disclosure. In some embodiments, method 600A may include an encoder, a decoder, and a device (e.g., Figure 4 The device 400) is executed by one or more software or hardware components. For example, a processor (e.g., Figure 4The processor 402) can execute method 600A. In some embodiments, method 600A may be implemented by a computer program product contained in a computer-readable medium, the computer program product comprising components implemented by a computer (e.g., a processor 402). Figure 4 The device 400 executes computer-executable instructions, such as program code. The method may include the following steps.

[0114] In step 601, a bitstream comprising a set of images is received. As described, a basic processing unit for a color image may include a luminance component (Y) representing achromatic luminance information, one or more chrominance components (e.g., Cb and Cr) representing color information, and associated syntax elements, wherein the luminance and chrominance components may have the same size as the basic processing unit. In some video coding standards (e.g., H.265 / HEVC or H.266 / VVC), the luminance and chrominance components may be referred to as “code tree blocks” (“CTBs”). Any operation performed on the basic processing unit may be repeated on each of its luminance and chrominance components.

[0115] In step 603, the value of a first flag indicating whether the transform skip mode is enabled is determined based on the received bit stream. The value of the first flag can be indicated by a signal in the received bit stream. For example, the value of `sps_transform_skip_enabled_flag` can be determined.

[0116] In step 605, the value of the first flag is used to determine whether a second flag indicating the residual coding method should be signaled. For example, the second flag could be a slice-level residual coding flag. The slice-level residual coding flag `slice_ts_residual_coding_disabled_flag` specifies the residual coding method for transform skip mode. If transform skip mode is disabled at the SPS level, no signal is needed in the slice header, and it can be inferred that it is 0.

[0117] In some embodiments, step 605 may include steps 605-1, 605-3, and 605-5, such as... Figure 6B As shown.

[0118] In step 605-1, the value of the first flag is determined based on the received bit stream to determine whether it satisfies the first condition or the second condition.

[0119] In some embodiments, the first condition may be a value of 1 for the first flag, and the second condition may be a value of 0 for the first flag. Meeting the first condition may result in a signal notifying the second flag. Otherwise, meeting the second condition may result in determining that the second flag has not been signaled.

[0120] In step 605-3, in response to the value of the first flag (e.g., sps_transform_skip_enabled_flag) being 1, the second flag (e.g., slice_ts_residual_coding_disabled_flag) is signaled.

[0121] In step 605-5, in response to the value of the first flag (e.g., sps_transform_skip_enabled_flag) being 0, it is determined that the second flag (e.g., slice_ts_residual_coding_disabled_flag) is not signaled.

[0122] Exemplary SPS syntax is described below in Table 3. In some exemplary embodiments used to signal the residual coding method, if `sps_transform_skip_enabled_flag` is equal to 1, the stripe-level residual coding flag is signaled. If `sps_transform_skip_enabled_flag` is equal to 0, the value of `slice_ts_residual_coding_disabled_flag` is inferred to be 0. The semantics of `sps_transform_skip_enabled_flag` are as follows.

[0123]

[0124] Table 3 shows a portion of an exemplary slice header syntax table for signaling a residual coding method according to some disclosed embodiments. In Table 3, rows with "if(sps_transform_skip_enabled_flag)" indicate changes to the syntax used in the second reference embodiment. As described above, in the second reference embodiment, slice_ts_residual_coding_disabled_flag is always signaled. In contrast, according to some embodiments of this disclosure, slice_ts_residual_coding_disabled_flag is not always signaled. Slice_ts_residual_coding_disabled_flag is signaled only when sps_transform_skip_enabled_flag equals 1. If sps_transform_skip_enabled_flag equals 0, slice_ts_residual_coding_disabled_flag is not signaled and is inferred to be equal to 0. The proposed changes can reduce signaling overhead at the slice header level.

[0125] Table 3: Exemplary slice header syntax table for the disclosed method of signaling residual coding method

[0126]

[0127] In some embodiments, a non-transitory computer-readable storage medium including instructions is also provided, and these instructions can be executed by a device (such as the disclosed encoder and decoder) to perform the methods described above. Common forms of non-transitory media include, for example, floppy disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, PROMs, and EPROMs, FLASH-EPROMs or any other flash memory, NVRAMs, caches, registers, any other memory chips or cassettes, and their networking versions. The device may include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memory.

[0128] The disclosed embodiments may be further described using the following terms:

[0129] 1. A method for signal notification of video data, characterized in that it includes:

[0130] Receive a bitstream containing a set of images;

[0131] Based on the received bit stream, determine the value of the coding tree block size; and

[0132] Based on the value of the coding tree block size, it is determined whether to signal a flag indicating the maximum change size of multiple luminance samples.

[0133] 2. The method according to Clause 1, wherein determining whether to notify the flag by signaling includes:

[0134] In response to a value greater than 32 for the size of the coded tree block, the flag is signaled; or

[0135] In response to the value of the coded tree block size being less than or equal to 32, it is determined that no signal is needed to notify the flag.

[0136] 3. The method according to Clause 1, wherein determining whether to notify the flag by signaling includes:

[0137] In response to the value of the coded tree block size not being equal to 32, the flag is notified by a signal; or

[0138] In response to the value of the coded tree block size being equal to 32, it is determined that the flag is not notified by a signal.

[0139] 4. The method according to Clause 1, wherein the value of the coding tree block size further includes a value associated with the luminance coding tree block size of the coding tree unit.

[0140] 5. The method according to Clause 4, wherein determining whether to notify the flag by signaling includes:

[0141] In response to a value greater than 0 associated with the size of the luminance coding tree block, the flag is signaled; or

[0142] In response to a value of 0 associated with the size of the luminance-coded tree block, it is determined that no signal should be used to notify the flag.

[0143] 6. The method according to Clause 4, wherein determining whether to signal the flag includes:

[0144] In response to a value not equal to 0 associated with the size of the luminance coding tree block, the flag is signaled; or

[0145] In response to a value of 0 associated with the size of the luminance-coded tree block, it is determined that no signal should be used to notify the flag.

[0146] 7. The method according to any one of clauses 1-6, wherein the mark indicates that the maximum transformation size is 64.

[0147] 8. A method for signal notification of video data, comprising:

[0148] Receive a bitstream containing a set of images;

[0149] Based on the received bit stream, the value of a first flag is determined. The value of the first flag indicates whether transition skip mode is enabled.

[0150] Based on the value of the first flag, it is determined whether to signal the second flag, which indicates the residual coding method.

[0151] 9. The method according to Clause 8, wherein determining whether to notify the second flag by signaling includes:

[0152] In response to the value of the first flag being 1, the second flag is signaled; or

[0153] In response to the value of the first flag being 0, it is determined that the second flag is not signaled.

[0154] 10. The method according to any one of Clauses 8 and 9, wherein:

[0155] The first flag is signaled in the sequence parameter set, and

[0156] The second mark is indicated by a signal in the strip header.

[0157] 11. A device for signal notification of video data, comprising:

[0158] Memory for storing instruction sets; and

[0159] One or more processors, the one or more processors being configured to execute the instruction set to cause the device to perform:

[0160] Receive a bitstream containing a set of images;

[0161] Based on the received bit stream, determine the value of the coding tree block size; and

[0162] Based on the value of the coding tree block size, it is determined whether to signal a flag indicating the maximum change size of the luminance sample.

[0163] 12. The apparatus according to clause 11, wherein, upon determining whether to signal the flag, the one or more processors are configured to execute the instruction set to cause the apparatus to further perform:

[0164] In response to a value greater than 32 for the size of the coded tree block, the flag is signaled; or

[0165] In response to a value of 32 or less for the size of the coded tree block, it is determined that no signal is needed to notify the flag.

[0166] 13. The apparatus according to clause 11, wherein, upon determining whether to signal the flag, the one or more processors are configured to execute the instruction set to cause the apparatus to further perform:

[0167] In response to the value of the coded tree block size not being equal to 32, the flag is notified by a signal; or

[0168] In response to the value of the coded tree block size being equal to 32, it is determined that no signal is needed to notify the flag.

[0169] 14. The apparatus as described in Clause 11, wherein the value of the coding tree block size further includes a value associated with the luminance coding tree block size of the coding tree unit.

[0170] 15. The apparatus according to Clause 14, wherein, upon determining whether to signal the flag, the one or more processors are configured to execute the instruction set to cause the apparatus to further perform:

[0171] In response to a value greater than 0 associated with the size of the luminance coding tree block, the flag is signaled; or

[0172] In response to a value of 0 associated with the size of the luminance-coded tree block, it is determined that no signal should be used to notify the flag.

[0173] 16. The apparatus according to Clause 14, wherein, upon determining whether to signal the flag, the one or more processors are configured to execute the instruction set to cause the apparatus to further perform:

[0174] In response to a value not equal to 0 associated with the size of the luminance coding tree block, the flag is signaled; or

[0175] In response to a value of 0 associated with the size of the luminance-coded tree block, it is determined that no signal is needed to notify the flag.

[0176] 17. The apparatus according to any one of clauses 11-16, wherein the mark indicates that the maximum transformation size is 64.

[0177] 18. A signal notification device for video data, comprising:

[0178] Memory for storing instruction sets; and

[0179] One or more processors, the one or more processors being configured to execute the instruction set to cause the device to perform:

[0180] Receive a bitstream containing a set of images;

[0181] Based on the received bit stream, the value of a first flag is determined. The value of the first flag indicates whether transition skip mode is enabled.

[0182] Based on the value of the first flag, it is determined whether to signal the second flag, which indicates the residual coding method.

[0183] 19. The apparatus according to Clause 18, wherein, upon determining whether to signal the second flag, the one or more processors are configured to execute the instruction set to cause the apparatus to further perform:

[0184] In response to the value of the first flag being 1, the second flag is signaled; or

[0185] In response to the value of the first flag being 0, it is determined that no signal should be sent to the second flag.

[0186] 20. The apparatus according to any one of clauses 18 and 19, wherein:

[0187] The first flag is signaled in the sequence parameter set, and

[0188] The second mark is indicated by a signal in the strip header.

[0189] 21. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a computer to cause the computer to perform a method for signaling video data, the method comprising:

[0190] Receive a bitstream containing a set of images;

[0191] Based on the received bit stream, determine the value of the coding tree block size; and

[0192] Based on the value of the coding tree block size, it is determined whether to signal a flag indicating the maximum change size of the luminance sample.

[0193] 22. The non-transitory computer-readable medium as described in Clause 21, wherein determining whether to signal the flag includes:

[0194] In response to a value greater than 32 for the size of the coded tree block, the flag is signaled; or

[0195] In response to a value of 32 or less for the size of the coded tree block, it is determined that no signal is needed to notify the flag.

[0196] 23. The non-transitory computer-readable medium as described in Clause 21, wherein determining whether to signal the flag includes:

[0197] In response to the value of the coded tree block size not being equal to 32, the flag is notified by a signal; or

[0198] In response to the value of the coded tree block size being equal to 32, it is determined that no signal is needed to notify the flag.

[0199] 24. In the non-transitory computer-readable medium as described in Clause 21, the value of the coding tree block size also includes a value associated with the luminance coding tree block size of the coding tree unit.

[0200] 25. The non-transitory computer-readable medium as described in Clause 24, wherein determining whether to signal the flag includes:

[0201] In response to a value greater than 0 associated with the size of the luminance coding tree block, the flag is signaled; or

[0202] In response to a value of 0 associated with the size of the luminance-coded tree block, it is determined that no signal should be used to notify the flag.

[0203] 26. The non-transitory computer-readable medium as described in Clause 24, wherein determining whether to signal the flag includes:

[0204] In response to a value not equal to 0 associated with the size of the luminance coding tree block, the flag is signaled; or

[0205] In response to a value of 0 associated with the size of the luminance-coded tree block, it is determined that no signal is needed to notify the flag.

[0206] 27. A non-transitory computer-readable medium according to any one of clauses 21-26, wherein the mark indicates that the maximum transformation size is 64.

[0207] 28. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a computer to cause the computer to perform a signal notification method for video data, the method comprising:

[0208] Receive a bitstream containing a set of images;

[0209] Based on the received bit stream, the value of a first flag is determined. The value of the first flag indicates whether transition skip mode is enabled.

[0210] Based on the value of the first flag, it is determined whether to signal the second flag, which indicates the residual coding method.

[0211] 29. The non-transitory computer-readable medium as described in Clause 28, wherein determining whether to signal the second flag includes:

[0212] In response to the value of the first flag being 1, the second flag is signaled; or

[0213] In response to the value of the first flag being 0, it is determined that no signal should be sent to the second flag.

[0214] 30. A non-transitory computer-readable medium according to any one of clauses 28 and 29, wherein:

[0215] The first flag is signaled in the sequence parameter set, and

[0216] The second mark is indicated by a signal in the strip header.

[0217] It should be noted that relational terms such as “first” and “second” in this document are used only to distinguish an entity or operation from another entity or operation, without requiring or implying any actual relationship or order between these entities or operations. Furthermore, the words “including,” “having,” “containing,” and “including,” and other similar forms, are semantically equivalent and open-ended, because one or more items following any of these words do not imply an exhaustive list of such one or more items, or that the list is limited to one or more items.

[0218] As used herein, unless otherwise specified, the term "or" includes all possible combinations unless impractical. For example, if a database is declared to include A or B, then unless otherwise expressly stated or impractical, the database may include A, or B, or A and B. As a second example, if a database is declared to include A, B, or C, then unless otherwise expressly stated or impractical, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0219] It should be understood that the above embodiments can be implemented by hardware, software (program code), or a combination of hardware and software. If implemented by software, it can be stored in the above-described computer-readable medium. The software, when executed by a processor, can perform the disclosed methods. The computing units and other functional units described in this disclosure can be implemented by hardware, software, or a combination of hardware and software. Those skilled in the art will also understand that the above-described multiple modules / units can be combined into one module / unit, and each of the above-described modules / units can be further divided into multiple sub-modules / sub-units.

[0220] In the foregoing description, numerous specific details have been described with reference to embodiments, which may vary depending on implementation. Certain modifications and variations can be made to the described embodiments. Other embodiments will be apparent to those skilled in the art upon consideration of the specification and practice disclosed herein. This specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended claims. The sequences of steps shown in the accompanying drawings are for illustrative purposes only and are not intended to limit the scope to any particular sequence of steps. Therefore, those skilled in the art will understand that these steps may be performed in a different order while implementing the same method.

[0221] Exemplary embodiments have been disclosed in the accompanying drawings and description. However, many variations and modifications can be made to these embodiments. Therefore, although specific terms are used, they are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A video decoding method for decoding a bitstream of a set of images, wherein the basic processing unit of the images includes a luminance component representing achromatic luminance information, comprising: Receive a bitstream associated with a coding tree block; determine the value of the coding tree block size associated with the SPS based on parameters signaled in the Sequence Parameter Set (SPS) in the bitstream; and; Based on the value of the coding tree block size, it is determined whether to decode a flag, which is associated with the maximum transform size of multiple luminance samples; In response to a value greater than 32 for the coded tree block size, the flag is decoded in the SPS. When the maximum transform size of the luminance sample is equal to 64, the value of the flag is set to 1, or when the maximum transform size of the luminance sample is equal to 32, the value of the flag is set to 0. If the value of the encoding tree block size is equal to or less than 32, the decoding of the flag is skipped.

2. The method according to claim 1, wherein the value of the coding tree block size is determined based on a parameter of the specific luminance coding tree block size of each coding tree unit.

3. The method of claim 1, wherein the flag includes sps_max_luma_transform_size_64_flag.

4. The method of claim 1, wherein the flag is included in the sequence parameter set.

5. The method according to claim 1, further comprising decoding the bitstream according to the Universal Video Coding Standard (VVC / H.266).

6. The method of claim 1, further comprising: In response to the value of the coded tree block size being equal to or less than 32, the value of the flag is equal to 0.

7. A video encoding method for encoding a set of images, wherein the basic processing unit of the images includes a luminance component representing achromatic luminance information, the method comprising: Based on parameters signaled in the Sequence Parameter Set (SPS), the value of the coding tree block size associated with the SPS is determined; and Based on the value of the coding tree block size, determine whether to signal a flag that indicates the maximum change size of multiple luminance samples; The determination of whether to signal the flag includes: in response to a value of the coding tree block size being greater than 32, sending the flag in the SPS; when the maximum change size of the luminance sample is equal to 64, the value of the flag is set to 1, or when the maximum change size of the luminance sample is equal to 32, the value of the flag is set to 0. If the value of the encoded block size is equal to or less than 32, the flag is not notified in the bit stream.

8. The method of claim 7, wherein the mark comprises: sps_max_luma_transform_size_64_flag.

9. The method of claim 7, further comprising: The image is encoded according to the Common Video Coding Standard (VVC / H.266) to generate the bitstream.

10. The method of claim 7, wherein if the value of the encoded tree block size is equal to or less than 32, the value of the flag is equal to 0.

11. The method of claim 7, wherein the value of the coding tree block size is determined based on a parameter of the specific luminance coding tree block size for each coding tree unit.

12. A non-transitory computer-readable storage medium storing an instruction set and a video bitstream, the instruction set being executable by one or more processors of a video coding method to generate the video bitstream, the video coding method being used to encode a set of images, the basic processing unit of the images including a luminance component representing achromatic luminance information, the method comprising: Based on the parameters signaled in the Sequence Parameter Set (SPS), the size of the coding tree block associated with the SPS is determined, and Based on the value of the coding tree block size, determine whether to signal a flag that indicates the maximum change size of multiple luminance samples; The determination of whether to signal the flag includes: in response to a value of the coding tree block size being greater than 32, sending the flag in the SPS; when the maximum change size of the luminance sample is equal to 64, the value of the flag is set to 1, or when the maximum change size of the luminance sample is equal to 32, the value of the flag is set to 0. If the value of the coding tree block size is equal to or less than 32, the flag is not notified by a signal in the bit stream.

13. The non-transitory computer-readable storage medium of claim 12, wherein the flag includes sps_max_luma_transform_size_64_flag.

14. The non-transitory computer-readable storage medium of claim 12, wherein the image is encoded according to the Universal Video Coding Standard (VVC / H.266) to generate the bitstream.

15. The non-transitory computer-readable storage medium of claim 12, wherein the parameter includes sps_log2_ctu_size_minus5.

Images