Counter array with noise reduction function, CIS image sensor and chip

Abstract

The invention discloses a CIS image sensor. The CIS image sensor comprises a pixel array, a comparator array, a counter array and a logic unit, the pixel array is used for generating pixel signals; the comparator array is used for comparing the pixel signal with the slope reference signal to obtain a comparator output signal; the counter array is used for processing the comparator output signal and the count value in the Gray code form, and outputting the processed data to the logic unit; and the logic unit is used for sorting and storing the data output by the counter array, and carrying out dark level compensation, channel difference compensation and noise reduction processing on the data to obtain output data. A counter array in the CIS image sensor adopts a Gray code counter, multiple CDS operation can be realized, and noise is greatly attenuated.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a counter array with a noise reduction function, a CIS image sensor and a chip. Background Art

[0002] Currently, the market has increasingly higher requirements for image sensors, mainly focusing on cost and performance. The performance requirement mainly focuses on low noise. The traditional approach is generally to suppress noise by reducing the noise bandwidth of the readout circuit. However, as the noise decreases, the suppression effect decreases exponentially. Summary of the Invention

[0003] The object of the present invention is to provide a counter array, a CIS image sensor and a chip with a noise reduction function, so as to reduce the noise of the image sensor by improving the structure of the counter array.

[0004] The present invention is achieved through the following technical solutions: In a first aspect, a first embodiment of the present invention provides a counter array with a noise reduction function, comprising: a Gray code buffer module and a logic operation array, The Gray code buffer module is used for buffering and storing count values ​​in Gray code form; The logic operation array is used for storing Gray code, performing CDS operation and signal output.

[0005] Further, the logic operation array includes a plurality of logic operation columns, and the logic operation columns include: a Latch_I subunit, a conversion subunit, a full adder and a Latch_O subunit; The Latch_I subunit is used to latch the count value of the corresponding channel in the counter array under the timing control signal; The conversion subunit is used to convert Gray code into 8421 code; The full adder is used to perform multiple CDS operations on the 8421 code under the control of the timing control signal; The Latch_O subunit is used to latch the count value of the corresponding channel output by the counter array under the timing control signal.

[0006] In a second aspect, another embodiment of the present invention provides a CIS image sensor, comprising a pixel array, a comparator array, a counter array, and a logic unit; The pixel array is used to generate pixel signals; The comparator array is used to compare the pixel signal and the ramp reference signal to obtain a comparator output signal; The counter array is used to process the comparator output signal and the count value in the form of Gray code, and output the processed data to the logic unit; The logic unit is used to sort and store the data output by the counter array, and perform dark level compensation, channel difference compensation and noise reduction on the data to obtain output data.

[0007] Furthermore, the counter array includes: a Gray code buffer module and a logic operation array; The Gray code buffer module is used for buffering and storing count values ​​in Gray code form; The logic operation array is used for latching the count value of the corresponding channel in the counter array in the form of Gray code under the timing control signal.

[0008] Furthermore, the logic operation array includes a plurality of logic operation columns, each of which includes a Latch_I sub-unit, and the Latch_I sub-unit is used to latch a count value in a Gray code format of a corresponding channel in the counter array under a timing control signal.

[0009] Furthermore, the logic operation column further includes: a conversion subunit, a full adder and a Latch_O subunit; The conversion subunit is used to convert the latched Gray code into 8421 code; The full adder is used to perform multiple CDS operations on the 8421 code under the control of the timing control signal; The Latch_O subunit is used to latch the count value of the corresponding channel output by the counter array under the timing control signal.

[0010] Furthermore, the logic unit includes: a sorting and storing subunit and a processing subunit, wherein the sorting and storing subunit is used to sort and store data and transmit the data to the processing subunit; The processing subunit is used to perform dark level compensation, channel difference compensation and noise reduction processing on the data.

[0011] Furthermore, it also includes a comparator type readout amplifier array, which is connected to the counter array and the logic unit respectively, and is used to detect and amplify the Gray code output by the logic operation array, and transmit the amplified Gray code signal to the logic unit.

[0012] Furthermore, the logic unit includes a conversion subunit, a full adder, a sorting storage subunit and a processing subunit; The conversion subunit is used to convert the amplified Gray code signal into 8421 code; The full adder is used to perform multiple CDS operations on the 8421 code under the control of the timing control signal; The sorting and storing subunit is used to sort and store the data processed by the full adder, and transmit the data to the processing subunit; The processing subunit is used to perform dark level compensation, channel difference compensation and noise reduction processing on the data transmitted from the sorting storage subunit.

[0013] In a third aspect, another embodiment of the present invention provides a chip, which includes the CIS image sensor described in the above embodiment.

[0014] Compared with the prior art, the present invention has the following advantages and beneficial effects: The present invention provides a counter array with noise reduction capabilities. Gray code counters are used within the counter array, resulting in excellent counting performance and robustness against power supply fluctuations. This allows for faster counting frequencies, multiple correlated double sampling (CCDS), and significant noise attenuation. Gray code counters eliminate multi-bit transition errors common in binary encoding, converting the Gray code to 8421 code and converting the voltage to digital code, reducing conversion errors and ensuring accurate image detail.

[0015] The present invention provides a CIS image sensor and chip, which adopts a Gray code counter in the counter array, so that it has excellent counting performance and resistance to power supply fluctuations, making the counting frequency faster, realizing multiple correlated double sampling operations, and significantly attenuating noise. The Gray code counter is used to eliminate the multi-bit jump error that is prone to binary coding, converting the Gray code into 8421 code, and converting the voltage into digital code, thereby reducing conversion errors and ensuring the restoration of image details. By sharing the data output stage, the vertical area is greatly reduced, saving costs. By setting up a comparator-type readout amplifier array, the differential input of the comparator can be used to complete the sensing amplification output before the input signal has completely dropped, so that the transmission can be completed in a very short time, thereby improving the data transmission speed and reducing the area of ​​the transmission channel to maintain the speed and frame rate unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the examples. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be considered as limiting the scope. A person of ordinary skill in the art can also derive other relevant drawings based on these drawings without inventive effort. In the drawings: Figure 1 A schematic structural diagram of a CIS image sensor provided by the first embodiment of the present invention; Figure 2 Schematic diagram of the structure of the counter array in the first embodiment of the present invention; Figure 3 Schematic diagram of the structure of the logical operation sequence in the first embodiment of the present invention; Figure 4A CIS image sensor NR1 control timing diagram provided by the first embodiment of the present invention; Figure 5 A CIS image sensor NR2 control timing diagram provided by the first embodiment of the present invention; Figure 6 A structural block diagram of a CIS image sensor provided by another embodiment of the present invention; Figure 7 A circuit diagram of a logic operation column of a CIS image sensor provided by another embodiment of the present invention; Figure 8 A CIS image sensor NR1 control timing diagram provided by another embodiment of the present invention; Figure 9 A CIS image sensor NR2 control timing diagram provided by another embodiment of the present invention; Figure 10 The output transmission circuit structure diagram of the comparator type sense amplifier array; Figure 11 This is a timing diagram of the data Data_IN being amplified by the comparator-type sense amplifier and transmitted to the logic unit. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0018] like Figure 1 As shown, a CIS image sensor provided by the first embodiment of the present invention includes a pixel array, a comparator array, a counter array and a logic unit; wherein the pixel array is used to generate pixel signals; the comparator array is used to compare the pixel signals with a ramp reference signal to obtain a comparator output signal; the counter array is used to process the comparator output signal and a count value in the form of a Gray code, and output the processed data to the logic unit; the logic unit is used to sort and store the data output by the counter array, and perform dark level compensation, channel difference compensation and noise reduction on the data to obtain output data.

[0019] like Figure 2As shown, the counter array includes: a Gray Code Counter (Gray Code Counter), a Gray Code Buffer module (Gray Code Buffer) and a logic operation array. The counter adopts a Gray Code Counter, which makes it have excellent counting performance and resistance to power supply fluctuations, making the counting frequency faster. Gray Code is a special binary encoding method. Its core feature is that there is only one binary bit different between two adjacent values ​​(such as the binary of 3→4 is 011→100, a 3-bit jump; while in Gray Code it is 010→110, only a 1-bit jump). The Gray Code Buffer module is used to buffer and store the count value in the form of Gray Code. Its function is to enhance the Slew (signal conversion time) capability of the Gray Code farthest from the Gray Code counter, reduce the rise and fall time, and facilitate accurate processing by the subsequent logic operation array. The logic operation array is used to latch the count value in the form of Gray Code of the corresponding channel in the counter array under the timing control signal. The logic operation array is composed of multiple identical logic operation columns. The function of the logic operation column is to obtain Gray Code, perform 8421 code conversion on Gray Code, add and subtract operations, store and output. As shown Figure 3 As shown, the logic operation column includes: a latch_I subunit, a conversion subunit, a full adder, and a latch_O subunit; the latch_I subunit is used to latch the count value of the corresponding channel in the counter array under the timing control signal; the conversion subunit is used to convert Gray code to 8421 code; the full adder is used to perform multiple CDS operations on the 8421 code under the control of the timing control signal; the latch_O subunit is used to latch the count value of the corresponding channel output by the counter array under the timing control signal. The outputs of multiple (usually 32) logic operation columns share a set of Bus buses Data_* and are output to the logic unit through the DataBuffer (data buffer module); the DataBuffer is used to improve the slew capacity of the output Bus bus Data_*, facilitating the logic unit to accurately obtain, process, and read. The size of the logic operation column is determined by the ADC readout accuracy (usually 10 bits) and whether multiple CDS operations are performed (in this embodiment, a single CDS operation is called NR1, and a double CDS operation is called NR2). The corresponding timing is as follows: Figure 4 、 5 shown.

[0020] The core of CDS technology is to perform two sampling operations: the first sampling is for the reference signal (such as the reset level), and the second sampling is for the target signal (such as the light-sensing signal). By subtracting these two signals, most background noise can be eliminated, including fixed noise (FPN), low-frequency noise (such as 1 / f noise), and reset noise (kTC noise). The mathematical principle is expressed as follows: 1. Reset signal sampling: R + N1 (R is fixed pattern noise and bias voltage, N1 is sampling noise); 2. Target signal sampling: S + R + N2 (S is the signal, N2 is the sampling noise); 3. Signal processing: (S + R + N2) - (R + N1) = S + (N2- N1).

[0021] Since the difference between N2 and N1 is very small, the fixed pattern noise and bias voltage can be effectively eliminated to obtain a relatively pure signal.

[0022] Multiple CDS operations apply this process multiple times to further reduce noise and improve signal quality. For example, by applying CDS technology in multiple stages or channels, noise can be more effectively eliminated, improving signal stability and accuracy. A single CDS operation can eliminate fixed noise (very low frequency), while multiple CDS operations can eliminate fixed noise and proportionally attenuate a portion of higher-frequency random thermal noise.

[0023] Figure 4 、 5 In the figure, GrayCode is the output of the Gray code counter, V_cmp is the pixel signal, the signal Ramp is the reference signal generated by the DAC, and V_cmp is the enable signal output by the comparator array after comparison of V_pix and Ramp; LAT1 and XLAT1 are obtained by the positive and negative outputs of V_cmp, and their function is to latch and store the GrayCode. The subsequent circuit converts the latched GrayCode into 8421 code; LAT1 and XLAT1 latch the converted 8421 code; WR<5:0>, WA<5:0>, WO<5:0>, and XWO<5:0> signals are full adder input and output read enable signals that cooperate with CLK_Ci for addition operation. Each signal in WR<5:0>, WA<5:0>, WO<5:0>, and XWO<5:0> has a total of 6 bits, and each bit is enabled in sequence. Each bit of input and output enable signal controls 2 bits 8421 code; MinusEN is the full adder addition and subtraction logic control signal, ADD_ZARO signal is the addend initial zero signal. Wout is the output enable signal of the counter array output Counter to the logic unit. Usually, the number of simultaneous actions is the shared number of output DataBus lines. Figure 4 、 5Table 1 shows the PrePhase (PP) and DataPhase (DD) outputs obtained from the MinusEN signal at different intervals, corresponding to NR1 and NR2, respectively. Compared to the control timing of NR1 and NR2, only the MinusEN signal is different; the other signals are repeatedly controlled in different intervals. This demonstrates that multiple CDS operations can be performed simply by changing the MinusEN signal. The counter array provided in this embodiment of the present invention can perform dual CDS operations, further reducing noise by 30% compared to sensors of equivalent specifications. Therefore, it achieves a noise reduction effect.

[0024]

[0025] according to Figure 3 It can be seen that the structure of the logic operation array is relatively complex, with many repeated call units. At the same time, the circuit layout usually needs to be manually drawn into a long strip layout with a width of 2-3um. In this way, the vertical dimension will reach more than 600um, which will greatly increase the area and cost of the entire sensor. To solve the above disadvantages, the structure of the CIS image sensor is improved, such as Figure 6 As shown. The CIS image sensor includes a pixel array, a comparator array, a counter array and a logic unit. The CIS image sensor also includes a comparator type readout amplifier array, which is connected to the counter array and the logic unit respectively, and is used to detect and amplify the Gray code output by the logic operation array, and transmit the amplified Gray code signal to the logic unit. Among them, the logic unit includes a conversion subunit, a full adder, a sorting storage subunit and a processing subunit; the conversion subunit is used to convert the amplified Gray code signal into 8421 code; the full adder is used to perform multiple CDS operations on the 8421 code under the control of the timing control signal; the sorting storage subunit is used to sort and store the data processed by the full adder, and transmit the data to the processing subunit; the processing subunit is used to perform dark level compensation, channel difference compensation and noise reduction on the data transmitted from the sorting storage subunit. As shown Figure 7 As shown, the logic operation column includes a Latch_I subunit, and the Latch_I subunit is used to latch the count value in the Gray code form of the corresponding channel in the counter array under the timing control signal.

[0026] use Figure 6In the counter array structure, since the Couter encoding conversion stage and the CDS operation stage circuits are shared, the overall counter array remains unchanged. The more shared circuits there are, the smaller the required area is, which can significantly reduce the area. The vertical dimension of the counter array can be reduced to less than 150μm, greatly reducing the vertical area and saving costs. Although the layout area of ​​the remaining circuits will increase the logic unit, since the output of the counter array is shared, it is usually considered that 32 logic operation columns share one bus line. Taking a logic operation column width of 2μm and a total number of 2000 logic operation columns as an example, the width of the occupied logic unit is 2000*2 / 32=125μm. At the same time, the logic unit can use automatic layout and routing EDA tools, so that the circuit layout can be a special-shaped structure, efficiently utilizing the layout area, and further reducing the width to less than 100μm. Figure 8 , 9 is the NR1 and NR2 control timing diagram of the circuit structure.

[0027] Due to the adoption Figure 1 In the CIS image sensor, only data needs to be transmitted within one clock cycle, while Figure 6 The CIS image sensor structure in the chip must complete transmission, Gray code conversion, and CDS operations within the same clock cycle while maintaining a constant frame rate and speed. To address this issue, a comparator-type readout amplifier array is added to the counter array output and logic unit input, significantly improving speed compared to traditional buffer structures. Taking the Hynix 90nm process as an example, a cascaded buffer structure drives data transmission on a 4000um long and 0.2um wide data line. Considering Avt and Pvt conditions, the delay is approximately 35ns. However, using a comparator-type readout amplifier array for sensing and amplification can complete data transmission in less than 10ns. This saved time is used for subsequent Gray code conversion and CDS operations, maintaining a constant frame rate and speed.

[0028] like Figure 10 Figure 1 shows the output transmission circuit structure of the comparator-type readout amplifier array. 32 counting logic units share a Data line at the output end. The Data_IN signal is obtained by attenuating the Data signal through a long-distance signal line. Vo is the final signal output to the logic unit, which is obtained by amplifying Data_IN through the comparator-type readout amplifier.

[0029] Figure 11 The figure shows the timing of data Data_IN being amplified by the comparator type readout amplifier and transmitted to the logic unit. Each transmission is divided into two stages: pre-charge stage and data transmission stage. In the pre-charge stage, Wout[*] is low and the CK signal is also low. Figure 10The middle MP transistor charges Data_IN to DVD, and the comparator is in the AutoZero stage, outputting a high voltage. During the transmission phase, both the CK and Wout[*] signals are high, and the comparator in the comparator-type sense amplifier array transmission circuit is in the comparison phase. If a "0" is transmitted, the Data_IN signal line has a path to ground, causing the corresponding potential to drop from the precharged AVD to GND, forming a ramp that is compared with the other end of the comparator, DVD, causing Vo to flip. The Vo flip speed is proportional to the comparator's operating current, i. By setting i, the transmission time can be reduced to less than 5ns. Combined with the precharge time, the single transmission time can be controlled to less than 10ns, significantly reducing the transmission time. If a "1" is transmitted, Data_IN maintains the precharged AVD voltage, the comparator does not flip, and the output is high, effectively reducing the bit error rate by half.

[0030] A CIS image sensor provided by an embodiment of the present invention utilizes a comparator-type readout amplifier array to complete sensing and amplification output using the comparator differential input before the input signal has completely dropped. Therefore, transmission can be completed in an extremely short time, thereby improving data transmission speed and reducing the transmission channel area to maintain speed and frame rate.

[0031] Another embodiment of the present invention provides a chip including the CIS image sensor described in the above embodiment.

[0032] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A counter array with noise reduction function, characterized in that: include: Gray code buffer module and logic operation array, The Gray code buffer module is used for buffering and storing count values ​​in Gray code form; The logic operation array is used for storing Gray code, performing CDS operation and signal output.

2. The counter array with noise reduction function according to claim 1, characterized in that: The logic operation array includes a plurality of logic operation columns, and the logic operation columns include: a Latch_I subunit, a conversion subunit, a full adder and a Latch_O subunit; The Latch_I subunit is used to latch the count value of the corresponding channel in the counter array under the timing control signal; The conversion subunit is used to convert Gray code into 8421 code; The full adder is used to perform multiple CDS operations on the 8421 code under the control of the timing control signal; The Latch_O subunit is used to latch the count value of the corresponding channel output by the counter array under the timing control signal.

3. A CIS image sensor, characterized in that: including a pixel array, a comparator array, a counter array, and a logic unit; The pixel array is used to generate pixel signals; The comparator array is used to compare the pixel signal and the ramp reference signal to obtain a comparator output signal; The counter array is used to process the comparator output signal and the count value in the form of Gray code, and output the processed data to the logic unit; The logic unit is used to sort and store the data output by the counter array, and perform dark level compensation, channel difference compensation and noise reduction on the data to obtain output data.

4. The CIS image sensor according to claim 3, wherein: The counter array includes: a Gray code buffer module and a logic operation array; The Gray code buffer module is used for buffering and storing count values ​​in Gray code form; The logic operation array is used for latching the count value of the corresponding channel in the counter array in the form of Gray code under the timing control signal.

5. The CIS image sensor according to claim 4, wherein: The logic operation array includes a plurality of logic operation columns, each of which includes a Latch_I subunit. The Latch_I subunit is used to latch a count value in a Gray code format of a corresponding channel in the counter array under a timing control signal.

6. The CIS image sensor according to claim 4, wherein: The logic operation column also includes: a conversion subunit, a full adder and a Latch_O subunit; The conversion subunit is used to convert the latched Gray code into 8421 code; The full adder is used to perform multiple CDS operations on the 8421 code under the control of the timing control signal; The Latch_O subunit is used to latch the count value of the corresponding channel output by the counter array under the timing control signal.

7. The CIS image sensor according to claim 6, wherein: The logic unit includes: a sorting and storing subunit and a processing subunit, wherein the sorting and storing subunit is used to sort and store data and transmit the data to the processing subunit; The processing subunit is used to perform dark level compensation, channel difference compensation and noise reduction processing on the data.

8. The CIS image sensor according to claim 4, wherein: It also includes a comparator type readout amplifier array, which is connected to the counter array and the logic unit respectively, and is used to detect and amplify the Gray code output by the logic operation array, and transmit the amplified Gray code signal to the logic unit.

9. The CIS image sensor according to claim 8, wherein: The logic unit includes a conversion subunit, a full adder, a sorting storage subunit and a processing subunit; The conversion subunit is used to convert the amplified Gray code signal into 8421 code; The full adder is used to perform multiple CDS operations on the 8421 code under the control of the timing control signal; The sorting and storage subunit is used to sort and store the data processed by the full adder, and transmit the data to the processing subunit; The processing subunit is used to perform dark level compensation, channel difference compensation and noise reduction processing on the data transmitted from the sorting storage subunit.

10. A chip, characterized in that: The chip includes the CIS image sensor according to any one of claims 3 to 9.

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