Test methods and electronic equipment for switches

Abstract

This application provides a testing method and electronic device for a switch, applicable to the field of switch technology. The method includes: when a first interface on the motherboard and a second interface on an interface board are connected, a first controller on the motherboard writes a preset value to a first register of a physical layer device on the interface board via a management data input / output interface to set the physical layer device to loopback mode, and reads a first flag signal from a second register of the physical layer device; in response to the first flag signal indicating successful loopback mode setting of the physical layer device, the first controller generates a preset diagnostic signal and sends the preset diagnostic signal to the physical layer device; in response to receiving the returned preset diagnostic signal, a test result is obtained based on the signal integrity of the returned preset diagnostic signal, the test result indicating the connection status between the motherboard and the interface board.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of switches, and more particularly to a test method of a switch and an electronic device. BACKGROUND

[0002] After the switch is assembled, the connection between the interface board and the main board is tested by observing the physical form of the exposed part of the connector, such as the insertion depth and the locking engagement state, to obtain a qualitative judgment result. However, the qualitative judgment result cannot guarantee the reliability of the test result. SUMMARY

[0003] In view of the above problems, the present application provides a test method of a switch and an electronic device for improving the reliability of the test result.

[0004] According to a first aspect of the present application, a test method of a switch is provided, comprising: in a case where a first interface of the main board and a second interface of the interface board are in a connected state, a first controller provided on the main board writes a preset value to a first register of a physical layer device provided on the interface board through a management data input and output interface, so as to set the physical layer device to a loopback mode, and reads a first flag bit signal from a second register of the physical layer device; in response to the first flag bit signal indicating that the loopback mode setting of the physical layer device is successful, the first controller generates a preset diagnosis signal and sends the preset diagnosis signal to the physical layer device; and in response to receiving a returned preset diagnosis signal, a test result is obtained according to the signal integrity of the returned preset diagnosis signal, and the test result indicates the connection state between the main board and the interface board.

[0005] A second aspect of the present application provides an electronic device comprising a main board and an interface board, wherein the main board is provided with a first controller, and the first controller is configured to execute the method described above.

[0006] According to the embodiments of the present application, the signal integrity of the preset diagnosis signal returned by the physical layer device is analyzed, and the analysis result is used to indicate the connection state between the main board and the interface board, thereby guaranteeing the reliability of the test result of the connection state between the main board and the interface board of the switch. Since the test of the connection state between the main board and the interface board of the switch is performed before the communication task of the switch, the normal communication task of the switch is not affected, and the reliability of the execution of the normal communication task of the switch is guaranteed. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above content and other purposes, features and advantages of the present application will be more clearly understood through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0008] Figure 1 The diagram illustrates a test method for a switch and an application scenario of an electronic device according to an embodiment of this application.

[0009] Figure 2 A flowchart of a test method for a switch according to an embodiment of this application is shown.

[0010] Figure 3 A schematic diagram of a high-speed connector PIN pin interface according to an embodiment of this application is shown.

[0011] Figure 4 A schematic diagram showing the structure of a motherboard’s first interface and an interface board’s second interface connected by a high-speed connector according to an embodiment of this application is provided.

[0012] Figure 5 A schematic diagram showing the direct connection between the first interface of the motherboard and the second interface of the interface board according to an embodiment of this application is shown.

[0013] Figure 6 A schematic diagram of the connection between the interface board and the motherboard according to an embodiment of this application is shown.

[0014] Figure 7 A flowchart of a test method for a switch according to another embodiment of this application is shown. Detailed Implementation

[0015] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0016] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0017] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0018] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0019] In today's rapidly developing information technology industry, the data center switch industry is undergoing profound changes driven by cloud computing, artificial intelligence, and the Internet of Things (IoT). With the explosive growth in data interaction demands, the market is placing higher requirements on the port flexibility of data center switches. To address this, major industry manufacturers have launched switch products with pluggable interface boards. These devices achieve flexible expansion of port configurations through modular design, and their core architecture involves high-speed signal interconnection between the interface board and the motherboard. In this architecture, high-speed signal transmission, such as SerDes (Serializer / Deserializer), between the interface board and the motherboard mainly relies on high-speed connectors for physical connection. However, due to structural design tolerances or assembly process deviations, high-speed connectors may not be installed correctly, leading to abnormal signal link contact. This abnormality will directly cause problems such as signal attenuation, increased bit error rate, and even link interruption, resulting in link errors and data transmission interruptions during equipment operation, seriously affecting system reliability. Since connectors are usually installed inside the equipment chassis, their assembly status cannot be directly judged by visual inspection, and traditional testing methods are insufficient to detect connection problems immediately after equipment assembly. In practical applications, such problems are often only initially identified during production line stress testing, or even after the equipment has been delivered to the customer and put into operation, triggering errors due to high-load data transmission, and only then can they be traced and located. This not only prolongs the troubleshooting cycle, increases production line rework costs and on-site maintenance difficulty, but may also cause continuous impact on user businesses due to service interruptions. Given the shortcomings of existing detection methods in terms of real-time performance and accuracy, there is an urgent need for a detection method that can quickly and reliably determine the connector connection status when the interface board is inserted into the device, in order to achieve early identification and accurate location of assembly problems and ensure the stable operation of data center switches.

[0020] Currently, in the field of data center switch pluggable interface board connector assembly inspection, manual visual inspection is commonly used for connectors exposed on the outside of the chassis and easily observable. Technicians, based on their accumulated assembly experience, subjectively judge the assembly quality by directly observing the physical position, mating depth, and appearance of the connectors. While this method is simple to operate and low in cost, its accuracy is highly dependent on the operator's skill level, resulting in significant human error and individual judgment differences, making it difficult to meet the requirements for high-precision assembly inspection.

[0021] For connectors installed inside the chassis in concealed locations, the enclosed space and poor visibility make it impossible to directly assess their assembly status visually with current technology. Even with the aid of auxiliary tools such as endoscopes, it is difficult to fully and clearly observe the actual mating of the connectors, making it difficult to detect potential assembly problems in a timely manner.

[0022] At the structural design level, existing technologies typically employ the addition of guide pins to assist assembly. These guide pins, through precise engagement with corresponding positioning holes, provide physical guidance and limitation during connector insertion, ensuring the connector is installed correctly as much as possible from a mechanical perspective. However, this passive structural protection method cannot actively detect the actual connection quality of the connector; it can only reduce the probability of assembly deviations and cannot fundamentally solve the problem of detecting connection abnormalities.

[0023] During the post-assembly testing phase, if system malfunctions such as signal errors or abnormal data transmission occur, technicians must manually disassemble the relevant components and check the connections between the port cards and the motherboard connectors one by one. This troubleshooting process is time-consuming and labor-intensive, and the fault location efficiency is low. This not only seriously affects production efficiency but may also lead to equipment delivery delays due to troubleshooting delays, increasing maintenance costs and customer service pressure.

[0024] Current testing methods lack a standardized judgment system based on electrical performance or mechanical parameters, relying solely on the physical morphology observation of the exposed parts of the connector (such as insertion depth and locking engagement status) for qualitative judgment. Furthermore, manual visual inspection heavily depends on the experience level of the operators and is significantly affected by external factors such as visual angle and lighting conditions. This judgment method leads to different conclusions being drawn by different inspectors for the same assembly state, making it difficult to guarantee the consistency and reliability of the test results. In addition, the testing technology for pluggable interface board connectors of data center switches suffers from defects such as strong subjectivity of manual visual inspection and lag in assembly state judgment.

[0025] Embodiments of this application provide a testing method for a switch, the switch including a motherboard and an interface board. The method includes: when a first interface of the motherboard and a second interface of the interface board are connected, a first controller located on the motherboard writes a preset value to a first register of a physical layer device located on the interface board through a Management Data Input / Output (MDIO) interface to set the physical layer device to loopback mode, and reads a first flag signal from a second register of the physical layer device; in response to the first flag signal indicating that the loopback mode of the physical layer device is successfully set, the first controller generates a preset diagnostic signal and sends the preset diagnostic signal to the physical layer device; in response to receiving the returned preset diagnostic signal, a test result is obtained based on the signal integrity of the returned preset diagnostic signal, the test result indicating the connection status between the motherboard and the interface board.

[0026] According to the embodiments of this application, by performing signal integrity analysis on the preset diagnostic signals returned by the received physical layer devices, and indicating the connection status between the motherboard and the interface board with the analysis results, the reliability of the test results of the connection status between the motherboard and the interface board of the switch is ensured. Since the test of the connection status between the motherboard and the interface board of the switch is a test before the switch performs a communication task, it will not affect the normal communication task of the switch, and ensures the reliability of the normal communication task execution of the switch.

[0027] Figure 1 The diagram illustrates a test method for a switch and an application scenario of an electronic device according to an embodiment of this application.

[0028] like Figure 1 As shown, according to the application scenario of this embodiment, the switch includes a motherboard 110 and an interface board 120. A first interface 111 and a first controller 112 are provided on the motherboard 110. A second interface 121 and a physical layer device 122 are provided on the interface board 120. The first controller 112 is connected to the first interface 111, the physical layer device 122 is connected to the second interface 121, and the first interface 111 and the second interface 121 are connected.

[0029] The following will be based on Figure 1 The described scene, through Figure 2 The testing method for the switch according to the embodiments of this application will be described in detail.

[0030] Figure 2 A flowchart of a test method for a switch according to an embodiment of this application is shown.

[0031] like Figure 2As shown, the test method for the switch in this embodiment includes operations S210 to S230, and the transaction processing method can be executed by the first controller.

[0032] When operating S210, with the first interface of the motherboard and the second interface of the interface board connected, the first controller on the motherboard writes a preset value to the first register of the physical layer device on the interface board through the management data input / output interface, so as to set the physical layer device to loopback mode and read the first flag bit signal from the second register of the physical layer device.

[0033] According to an embodiment of this application, a first interface is provided on the main board of the switch, and a second interface is provided on the interface board. The type and specifications of the first and second interfaces are related to the model of the interface board and the application scenario. For example, the first and second interfaces may be standard 8-bit modular interfaces, interfaces connected to high-speed connectors, etc.

[0034] According to an embodiment of this application, a first controller is provided on the main board of the switch, and the first controller can be a Media Access Control (MAC); a physical layer (PHY) device is provided on the interface board, which can be a gigabit / hundred-megabit Ethernet switch, or a device with loopback mode. The first controller can set the physical layer device to loopback mode through the management data input / output interface.

[0035] According to an embodiment of this application, the loopback mode of the physical layer device can be that the physical layer device directly sends the transmitted data signal back to its own receiving end. For example, the first controller sends → the first controller connects with the physical layer device through the first interface and the second interface to form a physical link → the physical layer device loops back → the physical layer device connects with the first controller through the second interface and the first interface to form a physical link → the first controller receives.

[0036] According to an embodiment of this application, the first flag signal indicates whether the operation of setting the physical layer device to loopback mode is successful. That is, different values ​​of the first flag signal correspond to whether the loopback mode setting of the physical layer device is successful or unsuccessful.

[0037] In operation S220, in response to the first flag signal indicating that the loopback mode of the physical layer device has been successfully set, the first controller generates a preset diagnostic signal and sends the preset diagnostic signal to the physical layer device.

[0038] According to an embodiment of this application, the first controller transmits a preset diagnostic signal to the physical layer device through a first interface and a second interface. The preset diagnostic signal can be selected from PRBS7 and PRBS31 in PRBS (Pseudo-Random Binary Sequence). The preset diagnostic signal has a wide spectrum up to the Nyquist frequency and is sensitive to impedance discontinuities. That is, the signal quality of the preset diagnostic signal is easily degraded by impedance abrupt changes in the transmission path. Impedance abrupt changes are impedance discontinuities, which lead to signal distortion and other problems. Because it is sensitive to impedance changes, the preset diagnostic signal can accurately identify physical and electrical anomalies of the first and second interfaces through impedance changes, thereby achieving efficient and high-precision fault diagnosis and status monitoring.

[0039] In operation S230, in response to receiving a returned preset diagnostic signal, the test result is obtained based on the signal integrity of the returned preset diagnostic signal. The test result indicates the connection status between the motherboard and the interface board.

[0040] Since the physical layer device is set to loopback mode, after the receiver of the physical layer device receives the preset diagnostic signal, the transmitter of the physical layer device returns the received preset diagnostic signal to the receiver of the first controller through the second interface and the first interface to obtain the preset diagnostic signal.

[0041] Signal integrity analysis is performed on the returned preset diagnostic signals. This analysis can include analyzing the signal spectrum and frequency response of the transmission path, transmission line effects, etc. Based on the test results, the connection quality between the motherboard and the interface board is determined. For example, when there is a poor connection, nonlinear effects can lead to an increase in signal harmonic components (such as the second and third harmonics), abnormal peaks in the spectrum, and increased contact resistance can introduce thermal noise, resulting in an increase in the spectrum floor noise level.

[0042] According to the embodiments of this application, by performing signal integrity analysis on the preset diagnostic signals returned by the received physical layer devices, and indicating the connection status between the motherboard and the interface board with the analysis results, the reliability of the test results of the connection status between the motherboard and the interface board of the switch is ensured. Since the test of the connection status between the motherboard and the interface board of the switch is a test before the switch performs a communication task, it will not affect the normal communication task of the switch, and ensures the reliability of the normal communication task execution of the switch.

[0043] According to an embodiment of this application, the test method for the switch further includes: a first controller receiving a second flag signal sent by a baseboard management controller disposed on the motherboard; the second flag signal indicating the connection status between the first interface and the second interface; wherein the baseboard management controller reads the second flag signal from a third register of a second controller disposed on the motherboard.

[0044] In the embodiments of this application, a second controller and a baseboard management controller are further provided on the motherboard, and a baseboard management controller is provided on the main board of the switch. The baseboard management controller is connected to the second controller, and the second controller is connected to the first interface.

[0045] When the motherboard is operating stably, the baseboard management controller continuously accesses the third register of the second controller to determine if an interface board is inserted into the motherboard. If an interface board is inserted, the value of the third register for the corresponding slot on the second controller changes. When the baseboard management controller detects a change in the value of the third register of the second controller, the value of the second flag signal also changes.

[0046] The second controller can be a device capable of detecting changes in the level of the input signal. For example, the second controller can be a CPLD (Complex Programmable Logic Device) or an FPGA (Field-Programmable Gate Array). When the second controller is a CPLD, the third register is the in-situ register of the CPLD.

[0047] When the baseboard management controller detects that an interface board has been inserted into the motherboard, it will trigger the diagnostic mode. The baseboard management controller sends a second flag signal to the first controller, which enables the first controller to configure the physical layer in loopback mode through the management data input / output interface.

[0048] According to an embodiment of this application, by continuously accessing the third register of the second controller through the baseboard management controller, connection information can be detected in real time and responded to in a timely manner.

[0049] Figure 3 A schematic diagram of a high-speed connector PIN pin interface according to an embodiment of this application is shown.

[0050] like Figure 3 As shown, the pins in each row of the high-speed connector PIN interface are A1~A9, B1~B9, C1~C9, D1~D9, E1~E9, F1~F9, G1~G9, and H1~H9, for a total of 72 pins. The high-speed connector PIN interface can be used on data center switch motherboards and interface boards. In operation S210, both the first and second interfaces can be selected using the high-speed connector PIN interface. The first and second interfaces can be connected via a high-speed connector, or they can be directly mated together.

[0051] According to an embodiment of this application, the input / output interface of the second controller is grounded to the first pin of the first interface of the motherboard via a resistor; the second pin of the first interface is connected to the power supply; the third pin of the second interface of the interface board and the fourth pin of the second interface are shorted; when the first interface and the second interface are connected, the first pin is connected to the third pin; and the second pin is connected to the fourth pin.

[0052] When there are multiple first interfaces, each first interface corresponds to an input / output interface of the second controller. The connection between each first interface and its corresponding input / output interface is similar and will not be described in detail here.

[0053] Each interface board is equipped with a second interface. When there are multiple interface boards, each first interface is connected to a corresponding second interface. According to the embodiments of this application, since the second controller directly detects the level changes of the input / output interfaces, it can detect the connection status between the first and second interfaces in a timely manner.

[0054] Figure 4 A schematic diagram showing the structure of a motherboard’s first interface and an interface board’s second interface connected by a high-speed connector according to an embodiment of this application is provided.

[0055] like Figure 4 Board 410 can function as a motherboard, while boards 420, 430, and 440 are all interface boards. The second interface on board 420 is J21, on board 430 it is J22, and on board 440 it is J2n. A second controller 411 is located on the motherboard, and it has multiple GPIOs (General-purpose input / output), including GPIO1, GPIO2, ..., GPIOn. The first interfaces include J11, J12, ..., J1n. The power supply is connected to the second pin of J11, and GPIO1 is connected to the first pin of J11. GPIO1 is also connected to one end of resistor R1, and the other end of resistor R1 is grounded. The third pin of J21 is shorted to the fourth pin of J21. The second pin of J11 is connected to the fourth pin of J21; the first pin of J11 is connected to the third pin of J21.

[0056] The power supply is connected to the second pin of J12, GPIO2 is connected to the first pin of J12, GPIO2 is also connected to one end of resistor R2, and the other end of resistor R2 is grounded. The third pin of J22 is shorted to the fourth pin of J22. The second pin of J12 is connected to the fourth pin of J22; the first pin of J12 is connected to the third pin of J22. The power supply is connected to the second pin of J1n, GPIOn is connected to the first pin of J1n, GPIOn is also connected to one end of resistor R3, and the other end of resistor R3 is grounded. The third pin of J2n is shorted to the fourth pin of J2n. The second pin of J1n is connected to the fourth pin of J2n; the first pin of J1n is connected to the third pin of J2n.

[0057] Taking the connection of J11 and J21 as an example, if the second pin of J11 is connected to the fourth pin of J21 through a high-speed connector, and the first pin of J11 is connected to the third pin of J21 through a high-speed connector, J11 and J21 are in a connected state. The register of the corresponding slot of GPIO1 of the second controller 411 will be pulled from high level to low level, thereby causing the value of the third register of the second controller 411 to change.

[0058] The first interface is a high-speed connector female, and the second interface is a high-speed connector male. Boards 420, 430, and 440 use pluggable port cards with the same type of high-speed connector. The connection between the first and second interfaces is similar to the connection between J11 and J21, and other connection cases will not be described in detail here.

[0059] According to an embodiment of this application, taking the connection of J11 and J21 as an example, the second pin of J11 can also be connected to the fourth pin of J21 via a low-speed connector, and the first pin of J11 can be connected to the third pin of J21 via a low-speed connector. Similar to using a high-speed connector for connection, Figure 4 The components in the device can also be connected using a low-speed connector.

[0060] Figure 5 A schematic diagram showing the direct connection between the first interface of the motherboard and the second interface of the interface board according to an embodiment of this application is shown.

[0061] like Figure 5 As shown, board 410 can serve as a motherboard. The connection relationships between the second controller 411, resistors R1, R2, R3, J11, J12, and J1n, and the shorting method of J21 are as follows: Figure 4Similar to the example shown, details will not be repeated here. Board 420 serves as the interface board. The high-speed connector female J11 of the main board directly connects to the high-speed connector male J21 of the interface board, forming the path VCC→J11→J21→J11→R1→GND. The GPIO1 of the second controller 411 will detect a high level. If J11 and J21 are not connected, J11→J21 and J21→J11 are both open circuits, forming an open circuit VCC→J11→J21→J11→R1→GND. The GPIO1 of the second controller 411 will detect a low level. The system can determine whether board 410 and board 420 are assembled and connected by querying the relevant register values ​​of the CPLD.

[0062] According to an embodiment of this application, the first controller is connected to the first interface of the motherboard via a serializer / deserializer; the physical layer devices of the interface board are connected to the second interface of the interface board via a serializer / deserializer.

[0063] With the first and second interfaces connected, the first controller connects to the physical layer device via a serializer / deserializer, the first interface, the second interface, and the serializer / deserializer. The first controller configures the physical layer device and reads its status through the management data input / output interface. If there are multiple first interfaces, the first controller connects to each first interface via a corresponding serializer / deserializer.

[0064] According to embodiments of this application, using a serializer / deserializer to connect devices at both ends can reduce the number of pins used by the devices at both ends and improve the signal transmission speed between the devices at both ends.

[0065] Figure 6 A schematic diagram of the connection between the interface board and the motherboard according to an embodiment of this application is shown.

[0066] like Figure 6As shown, there are multiple interface boards. Board 410 serves as the motherboard, while boards 420, 430, and 440 are all interface boards. Each interface board is equipped with physical layer devices; board 420 has a first physical layer device, board 430 has a second physical layer device, and board 440 has an nth physical layer device. The motherboard has a first controller 412, which connects to the first interface via a serializer / deserializer. When there are multiple first interfaces, the first controller connects to J11, J12, ..., J1n via corresponding serializers / deserializers. J11 and J21, which are connected to the first controller, can be directly connected. J21 connects to the first physical layer device via a serializer / deserializer. The first controller configures the first physical layer device via J11 and J21, setting the first physical layer device to loopback mode and reading the status of the first physical layer device. If the loopback mode setting of the first physical layer device is successful, the controller sends a preset diagnostic signal to the first physical layer device and receives a preset diagnostic signal returned by the first physical layer device.

[0067] The preset diagnostic signal output by the first controller can be input to the first physical layer device in sequence through the first serializer, the first interface, the second interface, and the first deserializer. The preset diagnostic signal returned by the first physical layer device is returned to the first controller in sequence through the second serializer, the second interface, the first interface, and the second deserializer.

[0068] With the first controller having a built-in serialization and deserialization module, the first controller can be directly connected to the first interface. With the physical layer device having a built-in serialization and deserialization module, the physical layer device can be directly connected to the second interface. SerDes technology is used for signal transmission between the first controller and the first interface, and between the physical layer device and the second interface.

[0069] The connection relationships between the first controller 412, J12, ... J1n, J22, ... J2n, the second physical layer device, ... the nth physical layer device are similar to the connection relationships between the first controller 412, J11, J21, and the first physical layer device, and will not be repeated here.

[0070] Figure 7 A flowchart of a test method for a switch according to another embodiment of this application is shown.

[0071] like Figure 7 As shown, the test method for a switch according to another embodiment of this application includes operations S701 to S708.

[0072] When operating the S701, the baseboard management controller determines whether the interface board is inserted into the motherboard. If the interface board is not inserted into the motherboard, the baseboard management controller continues to detect whether the interface board is inserted into the motherboard.

[0073] When operating S702, with the interface board inserted into the motherboard, the baseboard management controller triggers diagnostic mode and sends a second flag signal to the first controller.

[0074] During operation S703, the first controller responds to the received second flag signal, configures the diagnostic signal at the TX (Transmit) terminal, obtains the preset diagnostic signal, and injects the preset diagnostic signal into the SerDes signal channel of the first controller.

[0075] According to the embodiments of this application, the amplitude of the preset diagnostic signal can be set to the reference voltage value of the first controller, or it can be 70%-80% of the normal signal to avoid arc damage when the second interface is not fully inserted into the first interface. The duration of the preset diagnostic signal can be 2μs-10μs to meet the statistical significance requirement.

[0076] According to embodiments of this application, the amplitude of the preset diagnostic signal can be set in the following ways: for example, by accessing the register of the first controller via an SPI or I2C interface to set the output swing of the transmitting end and control the differential output swing. For example, adjusting the pre-emphasis intensity can compensate for high-frequency attenuation. Alternatively, the pre-emphasis and de-emphasis parameters can be adjusted in conjunction with channel loss; for example, increasing the pre-emphasis value during long-distance transmission can increase the amplitude of the high-frequency signal. The current level of the transmitting end can also be set via a current bias register, a register of the first controller. For example, setting the current bias register to its maximum value can increase the output amplitude, but attention must be paid to power consumption and EMI (Electromagnetic Interference) risks.

[0077] When operating S704, the RX (Receive) terminal of the first controller receives the returned preset diagnostic signal.

[0078] According to an embodiment of this application, after a preset diagnostic signal is injected into the SerDes signal channel, the preset diagnostic signal is injected from the TX terminal of the first controller on the motherboard, flows from the motherboard to the interface board through the high-speed connector, enters the RX terminal of the physical layer device on the interface board, loops back to the TX terminal of the physical layer device through the internal loop of the physical layer device, returns from the interface board to the motherboard through the high-speed connector, and finally returns to the RX terminal of the first controller on the motherboard.

[0079] When operating S705, perform signal integrity analysis on the returned preset diagnostic signals to obtain test results.

[0080] According to an embodiment of this application, preset diagnostic signals returned in multiple consecutive cycles are obtained to obtain a signal to be tested; the clock recovery function of the first controller is used to process the signal to be tested to obtain a signal after clock recovery processing; the signal integrity of the signal after clock recovery processing is analyzed to obtain a test result.

[0081] According to an embodiment of this application, the receiving timing is locked using the transmitting clock recovery function of the first controller to eliminate the effect of clock offset on the preset diagnostic signal received by the RX terminal of the first controller.

[0082] According to an embodiment of this application, all preset diagnostic signals sent by the first controller include multiple periods of pseudo-random binary sequence 7 or pseudo-random binary sequence 31. The returned preset diagnostic signals for multiple consecutive periods are the signals returned by all the preset diagnostic signals sent by the first controller.

[0083] According to an embodiment of this application, the clock recovery function is used to process the signal under test, eliminating the influence of clock offset and improving the accuracy of the switch test results.

[0084] When operating S706, determine whether the test results meet the preset conditions.

[0085] According to embodiments of this application, the test results include at least one of amplitude attenuation test results, eye diagram test results, and bit error rate estimation test results.

[0086] The test results can be amplitude attenuation test results, eye diagram test results, or bit error rate (BER) estimation test results; they can also be any two of these results, or a combination of all three. The test results can be selected based on the specific circumstances.

[0087] According to embodiments of this application, the comprehensiveness of switch testing is improved by performing multi-faceted testing on the signal to be tested.

[0088] According to an embodiment of this application, when the test result includes an amplitude attenuation test result, the method for obtaining the test result based on the signal integrity of the returned preset diagnostic signal includes: determining the peak voltage of the signal to be tested; determining the degree of amplitude attenuation based on the ratio of the peak voltage to the reference voltage value of the preset diagnostic signal; and using the degree of amplitude attenuation as the amplitude attenuation test result.

[0089] According to an embodiment of this application, when the amplitude of a preset diagnostic signal is set, the attenuation amount is calculated by formula (1) based on the values ​​of the two registers, according to the amplitude of the preset diagnostic signal configured in the register of the TX terminal of the first controller and the amplitude of the signal to be tested received in the register of the RX terminal of the first controller, and the attenuation amount is used as the amplitude attenuation test result.

[0090] (1)

[0091] in, This is the attenuation amount. The amplitude of the preset diagnostic signal is configured. The amplitude of the received signal to be tested.

[0092] According to embodiments of this application, by evaluating the energy loss of the signal during transmission, the integrity of the signal under test is analyzed, thereby improving the reliability of the test results.

[0093] According to an embodiment of this application, when the test result includes an eye diagram test result, the test result is obtained based on the signal integrity of the returned preset diagnostic signal by: using a first controller to determine the eye diagram height quantization value or the eye diagram width quantization value of the signal to be tested, and using the eye diagram height quantization value as the eye diagram height test result and the eye diagram width quantization value as the eye diagram width test result.

[0094] According to embodiments of this application, the quantized value of the eye diagram height or the quantized value of the eye diagram width of the signal under test can be directly determined using the ADC sampling eye diagram monitoring module built into the first controller. Alternatively, the signal under test can be saved as a time-voltage sequence, divided into units (UI) segments, and the edges of the segmented unit sequences can be aligned. Based on the aligned unit sequences, the quantized values ​​of the eye diagram height and the eye diagram width can be determined.

[0095] According to embodiments of this application, by visualizing the signal quality problem of the signal under test, it is possible to quickly determine whether there is a defect in the transmission path of the signal under test.

[0096] According to an embodiment of this application, when the test results include bit error rate estimation test results, the test results obtained based on the signal integrity of the returned preset diagnostic signal include: determining the total number of transmitted bits and the number of error bits of the signal under test; and determining the bit error rate estimation test results based on the ratio of the number of error bits to the total number of transmitted bits.

[0097] According to an embodiment of this application, the first controller can use a built-in counter to record the number of all returned preset diagnostic signals, and directly read the number of error bits and the total number of bits of all returned preset diagnostic signals, thereby determining the bit error rate estimation test result.

[0098] According to embodiments of this application, by using quantized data to predict the reliability of signal transmission, switch failures caused by sudden bit errors can be avoided in practical applications.

[0099] When operating the S707, if the test results do not meet the preset conditions, an alarm message is generated, and the activation of the first and second interfaces is blocked.

[0100] If the test results do not meet the preset conditions, the first and second interfaces will be prohibited from entering the working state. That is, the first and second interfaces cannot transmit data to avoid data loss, network congestion or even system failure caused by abnormal links entering the network.

[0101] According to embodiments of this application, an alarm message is generated when the amplitude attenuation test result is greater than a preset attenuation amount; or, an alarm message is generated when the eye diagram test result does not meet the corresponding preset standard; or, an alarm message is generated when the bit error rate estimation test result is greater than a preset bit error rate.

[0102] According to an embodiment of this application, the eye diagram test result includes an eye diagram height test result and an eye diagram width test result. An alarm message is generated when the eye diagram height test result is less than a preset eye diagram height threshold; an alarm message is also generated when the eye diagram width test result is less than a preset eye diagram width threshold.

[0103] According to the embodiments of this application, since the same judgment criteria are used when testing each switch, the consistency of switch test results is improved.

[0104] An indicator light is installed on the interface board. After receiving an alarm message, the baseboard management controller controls the indicator light on the interface board to turn red, requiring the staff to check the connection status of the high-speed connector.

[0105] When operating S708, if the test results meet the preset conditions, start the formal link test.

[0106] According to an embodiment of this application, if the signal integrity analysis result of the returned preset diagnostic signal meets the preset conditions, a test success message can be generated. After receiving the test success message, the baseboard management controller controls the indicator light on the interface board to turn green, and at this time, the formal link test is started.

[0107] According to embodiments of this application, the insertion status of the high-speed connector is determined using a power signal. When the interface board is inserted into the motherboard, the level of the third register in the corresponding slot of the second controller changes. Furthermore, the connection status of the high-speed signal link is determined by analyzing the signal integrity of the returned preset diagnostic signal. This advances the diagnostic post-communication detection of the high-speed interconnect of the switch to pre-communication prevention, effectively establishing a connection quality firewall between the physical layer and the protocol layer. Simultaneously, it fully utilizes the existing hardware resources of the motherboard and interface board, eliminating the need for additional expensive testing equipment or hardware architecture modifications. This offers significant advantages such as low cost, convenient deployment, and strong compatibility, providing chip-level native reliability assurance for high-frequency hot-swappable scenarios in data centers.

[0108] This application also provides an electronic device, which includes a motherboard and an interface board. The motherboard is provided with a first controller, which is configured to execute a test method for a switch.

[0109] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0110] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A test method of a switch including a main board and an interface board, the test method comprising: The method comprises: ​ In the case that the first interface of the mainboard and the second interface of the interface board are in a connected state, a first controller arranged on the mainboard writes a preset value to a first register of a physical layer device arranged on the interface board through a management data input and output interface, so as to set the physical layer device to a loopback mode, and reads a first flag bit signal from a second register of the physical layer device; In response to the first flag bit signal representing that the loopback mode setting of the physical layer device is successful, the first controller generates a preset diagnostic signal and sends the preset diagnostic signal to the physical layer device; wherein the amplitude of the preset diagnostic signal is obtained by setting the output swing or pre-emphasis intensity of the sending end of the first controller; or the amplitude of the preset diagnostic signal is obtained by adjusting the pre-emphasis or de-emphasis; or the amplitude of the preset diagnostic signal is obtained by setting the current level of the sending end of the first controller through a current bias register; In response to receiving a returned preset diagnostic signal, a test result is obtained according to the signal integrity of the returned preset diagnostic signal, the test result indicating the connection state between the mainboard and the interface board; wherein the preset diagnostic signal is output by the sending end of the first controller on the mainboard, flows from the mainboard to the interface board, enters the receiving end of the physical layer device of the interface board, is internally looped back to the sending end of the physical layer device, and returns to the receiving end of the first controller of the mainboard from the interface board, so that the first controller of the mainboard receives the returned preset diagnostic signal; The test result is obtained according to the signal integrity of the returned preset diagnostic signal, comprising: obtaining the returned preset diagnostic signal in a plurality of continuous periods to obtain a to-be-tested signal; processing the to-be-tested signal by using the clock recovery function of the first controller to obtain a clock recovery processed signal; analyzing the signal integrity of the clock recovery processed signal to obtain a test result; wherein the preset diagnostic signal is a pseudo-random binary sequence signal; the test result comprises at least one of an amplitude attenuation test result, an eye diagram test result and a bit error rate estimation test result; The determination process of the amplitude attenuation test result comprises: determining the peak voltage of the to-be-tested signal; determining the amplitude attenuation degree according to the ratio of the peak voltage to the reference voltage value of the preset diagnostic signal, and taking the amplitude attenuation degree as the amplitude attenuation test result; the determination process of the eye diagram test result comprises: determining the eye diagram height quantization value or the eye diagram width quantization value of the to-be-tested signal by using the first controller, and taking the eye diagram height quantization value as the eye diagram height test result and the eye diagram width quantization value as the eye diagram width test result; the determination process of the bit error rate estimation test result comprises: determining the total transmission bit number and the error bit number of the to-be-tested signal; determining the bit error rate estimation test result according to the ratio of the error bit number to the total transmission bit number.

2. The method of claim 1, wherein, The method further comprises: generating an alarm information in a case that the test result does not satisfy a preset condition.

3. The method of claim 1, wherein, The method further comprises: The first controller receives a second flag signal sent by a baseboard management controller arranged on the mainboard, and the second flag signal indicates a connection state of the first interface and the second interface. The baseboard management controller reads the second flag signal from a third register of a second controller arranged on the mainboard.

4. The method of claim 2, wherein, The generating of the alarm information in the case that the test result does not satisfy the preset condition comprises: generating the alarm information in a case that the amplitude attenuation test result is greater than a preset attenuation amount; or generating the alarm information in a case that the eye diagram test result does not satisfy a corresponding preset standard; or generating the alarm information in a case that the error rate estimation test result is greater than a preset error rate.

5. An electronic device comprising a main board and an interface board, the main board being provided with a first controller, characterized in that, The first controller is configured to execute the method according to any one of claims 1-4.

6. The electronic device of claim 5, wherein, The mainboard is further arranged with a second controller, an input / output interface of the second controller is grounded via a resistor with a first pin of a first interface of the mainboard; a second pin of the first interface is connected with a power supply; a third pin of a second interface of the interface board and a fourth pin of the second interface are short-circuited; in a case that the first interface and the second interface are in a connected state, the first pin is connected with the third pin, and the second pin is connected with the fourth pin.

7. The electronic device of claim 5, wherein, The first controller is connected with the first interface of the mainboard through a serializer / deserializer, and a physical layer device of the interface board is connected with the second interface of the interface board through a serializer / deserializer.

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