A method for manufacturing a notebook computer printed circuit board

Abstract

The application discloses a notebook computer printed circuit board manufacturing method, comprising: mixing and stirring resin and nano ceramic filler to form a resin solution, coating the resin solution on the surface of a substrate and heating to a semi-cured state to obtain a composite substrate; etching the composite substrate according to a preset layout, alternately stacking a double-sided inner layer circuit substrate and a semi-cured sheet containing glass fiber material and performing vacuum hot pressing treatment to obtain a laminated structure, wherein the number of the double-sided inner layer circuit substrate and the semi-cured sheet is equal; after chemical electroplating treatment of the laminated structure, etching the outer layer surface of the laminated structure according to a preset circuit pattern to form an outer layer circuit structure; coating solder resist ink on the outer layer circuit structure to form a solder resist layer to obtain a notebook computer printed circuit board. The application can significantly improve the interlayer bonding strength of the multilayer printed circuit board, thereby systematically solving the technical problem of insufficient performance stability of high-density circuit boards in the manufacturing process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board manufacturing, and particularly relates to a manufacturing method of a notebook computer printed circuit board. BACKGROUND

[0002] With the rapid development of the notebook computer market, the demand for high performance, thinness and high reliability is increasing. As a core component of notebook computers, printed circuit boards (PCBs) play a crucial role in signal transmission, power management and component connection. Multi-layer PCBs, especially 12-layer PCBs, have become the preferred choice for high-performance notebook computers due to their ability to support high-density circuit layout and excellent electrical performance.

[0003] However, the existing technology faces a core technical problem when manufacturing multi-layer notebook PCBs, which is insufficient interlayer bonding strength. This problem directly affects the structural stability and long-term reliability of the PCB, leading to interlayer peeling or failure under high load operation or complex use environment, making it difficult to meet the requirements of modern notebook computers for high performance and high durability.

[0004] In the existing technology, the manufacturing quality is improved by optimizing a single process step or introducing new equipment, but these improvements often only target a specific link and are difficult to solve the performance stability problem as a whole. For example, the existing technology improves the corrosion resistance of the circuit board by improving the surface treatment process, but cannot effectively solve the reliability problem of interlayer connection; another existing technology improves the fineness of the circuit pattern by improving the processing precision, but may lead to reduced production efficiency due to increased process complexity.

[0005] Therefore, there is an urgent need for a new manufacturing method that can systematically solve the problem of insufficient performance stability in high-density circuit board manufacturing from the perspective of overall process design, to meet the requirements of notebook computers for high performance, thinness and long-term reliability. SUMMARY

[0006] The present application aims to provide a manufacturing method of a notebook computer printed circuit board, which solves the technical problem of insufficient interlayer bonding strength in the existing technology.

[0007] To achieve this goal, the present application adopts the following technical solution:

[0008] A manufacturing method of a notebook computer printed circuit board, comprising:

[0009] mixing and stirring resin and nano-ceramic filler to form a resin solution, coating the resin solution on the surface of a substrate and heating to a semi-cured state to obtain a composite substrate;

[0010] etching the composite substrate according to a preset layout to obtain an inner layer circuit substrate;

[0011] stacking the double-sided inner layer circuit substrate and the prepreg containing glass fiber material alternately and performing vacuum hot pressing treatment to obtain a laminated structure, wherein the number of the double-sided inner layer circuit substrate and the prepreg is equal;

[0012] performing chemical electroplating treatment on the laminated structure, and then etching the outer surface of the laminated structure according to a preset circuit pattern to form an outer layer circuit structure;

[0013] applying solder resist ink on the outer layer circuit structure to form a solder resist layer, thereby obtaining a notebook computer printed circuit board.

[0014] Further, the resin is any one or a mixture of multiple of polyimide resin, epoxy resin or phenolic resin.

[0015] Further, the nano-ceramic filler is any one or a mixture of multiple of aluminum oxide, zirconium oxide, silicon nitride, boron nitride or silicon carbide.

[0016] Further, the substrate is any one of copper foil, aluminum foil or nickel foil.

[0017] Further, the step of mixing the resin and the nano-ceramic filler and stirring to form a resin solution, coating the resin solution on the surface of the substrate and heating to a semi-cured state to obtain a composite substrate, comprises:

[0018] mixing the nano-ceramic filler, epoxy resin and polyimide resin in a mass ratio of 3:1 and placing them in a stirring device for stirring treatment to form a resin solution;

[0019] applying a dilute sulfuric acid solution to the surface of the copper foil substrate for pretreatment, and coating the resin solution on the surface of the pretreated copper foil substrate to obtain a primary coated substrate;

[0020] placing the primary coated substrate in a reaction kettle, baking at 80-90°C for 10-12 minutes, then increasing the temperature to 150-160°C at a rate of 10°C / min and maintaining for 15 minutes to make the resin coating semi-cured, thereby obtaining the composite substrate.

[0021] Further, the step of etching the composite substrate according to a preset layout to obtain an inner layer circuit substrate, comprises:

[0022] applying a dry film photoresist to the surface of the composite substrate and heating at 90-100°C for 20-30 seconds to obtain a photoresist coated substrate;

[0023] performing ultraviolet exposure treatment on the photoresist coated substrate according to a preset layout to obtain an exposed substrate;

[0024] The exposed substrate is developed by a developing device using a 0.8% mass concentration potassium carbonate solution as a developing solution under a constant temperature of 20-25°C to obtain a patterned substrate;

[0025] The patterned substrate is etched in an etching tank under a constant temperature of 30-32°C using a 2.0 mol / L acidic copper sulfate etching solution, and is etched for 15-20 seconds, and then the etching solution flow rate is reduced and etching is performed for 25-30 seconds to obtain a primary circuit substrate;

[0026] The primary circuit substrate is removed from the film under the condition of 40-45°C using a 3% sodium hydroxide solution as a film removal solution to obtain an inner layer circuit substrate.

[0027] Further, the step of alternately stacking the double-sided inner layer circuit substrate and the prepreg containing glass fiber material and performing vacuum hot pressing treatment to obtain a laminated structure, wherein the number of the double-sided inner layer circuit substrate and the prepreg is equal, comprises:

[0028] The prepreg containing glass fiber material is immersed in a mixed solution containing nano-aluminum oxide particles and epoxy resin for impregnation treatment to obtain a modified prepreg, wherein the particle size of the nano-aluminum oxide particles is 20-25 nanometers, and the impregnation time is 10-15 minutes;

[0029] A plurality of modified prepregs and double-sided inner layer circuit substrates are alternately stacked and pressed together using a hot press at 175-180°C and 1.8-2 MPa for 60-80 minutes to obtain a pressed laminated structure;

[0030] The pressed laminated structure is subjected to layer-by-layer scanning treatment using a laser device with a pulse energy of 0.4-0.5 mj to form a plurality of micropores, thereby obtaining a laminated structure with interlayer interconnected channels.

[0031] Further, the step of chemically electroplating the laminated structure, comprises:

[0032] The laminated structure is immersed in a colloidal activation solution containing 0.02-0.03 mol / L palladium chloride and 0.1-0.15 mol / L tin chloride for activation treatment, so that palladium ions form catalytically active sites on the inner wall of the micropores;

[0033] The activated laminated structure is immersed in a chemical copper plating solution containing 0.05-0.06 mol / L copper sulfate, 0.1-0.15 mol / L formaldehyde and a complexing agent, and is reacted at 48-50°C for 15 minutes to obtain a seed layer structure.

[0034] The seed layer structure is placed in an electroplating solution containing 0.2-0.3 mol / L copper sulfate, 0.5-0.6 mol / L sulfuric acid and an additive, and is electroplated at a current density of 1.8-2 A / dm 2 for 50-60 minutes at 25-30°C to obtain a conductive laminated structure.

[0035] Further, the step of etching the outer layer surface of the laminated structure according to a preset circuit pattern to form an outer layer circuit structure comprises:

[0036] A photoresist containing nano-silicon dioxide particles is coated on the outer layer surface of the laminated structure, and is baked at 90-95°C for 5-10 minutes to obtain a photoresist covering structure;

[0037] An etching solution of ferric chloride with a concentration of 3.0 mol / L is used to etch the photoresist covering structure in an etching tank at a constant temperature of 35-40°C to obtain a preliminary outer layer structure;

[0038] A potassium hydroxide solution with a concentration of 5% is used as a degumming solution to degum the preliminary outer layer structure at 50-55°C to obtain an outer layer circuit structure.

[0039] Further, the step of coating a solder resist ink on the outer layer circuit structure to form a solder resist layer to obtain a notebook computer printed circuit board comprises:

[0040] A solder resist ink is coated on the surface of the outer layer circuit structure, and the solder resist ink contains nano-alumina particles, a photosensitizer and a toughening agent to obtain an initial solder resist coating;

[0041] The initial solder resist coating is subjected to ultraviolet exposure treatment using an ultraviolet light source to obtain a patterned solder resist coating;

[0042] After the patterned solder resist coating is subjected to developing treatment using an alkaline developing solution, low-temperature curing treatment is performed at 90-100°C for 10-15 minutes to obtain the notebook computer printed circuit board.

[0043] Compared with the prior art, the present application has the following beneficial effects:

[0044] The notebook computer printed circuit board manufacturing method of the present application effectively enhances the mechanical strength and thermal stability of the substrate by mixing resin and nanoceramic filler to form a high-performance resin solution and preparing a composite substrate; significantly improves the interlayer bonding strength and structural density by alternately stacking double-sided inner layer circuit substrates and semi-cured sheets containing glass fiber material and using vacuum hot pressing technology, thereby effectively preventing interlayer peeling or failure under high load or complex environment (such as high temperature and high humidity); the combination of chemical electroplating and precise etching process makes the fineness and electrical performance of high-density circuit patterns superior, and the application of solder resist layer improves the corrosion resistance and service life of the circuit board.

[0045] In summary, the present application can significantly improve the interlayer bonding strength of the multilayer printed circuit board, thereby systematically solving the overall technical problem of insufficient performance stability of high-density circuit boards during the manufacturing process, and meeting the comprehensive needs of modern notebook computers for high performance, thinness and long-term reliability. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0047] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and are not used to limit the conditions that can be implemented by the present application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0048] Figure 1 The overall steps of the notebook computer printed circuit board manufacturing method are shown in the figure. DETAILED DESCRIPTION

[0049] In order to make the purposes, features and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described below are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0050] In the description of the present application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there can be a component disposed therebetween.

[0051] The technical solutions of the present application will be further illustrated below in conjunction with the drawings and through specific embodiments.

[0052] Reference Figure 1 The present application provides a notebook computer printed circuit board manufacturing method, comprising:

[0053] S1: mixing and stirring resin and nano ceramic filler to form a resin solution, coating the resin solution on the surface of the substrate and heating to a semi-cured state to obtain a composite substrate;

[0054] In step S1, polyimide resin can be selected as the main matrix material, and nano ceramic filler is selected as alumina and boron nitride (mass ratio of 10:1). In actual operation, 1000 grams of polyimide resin, 90 grams of alumina and 9 grams of boron nitride filler can be placed in a high-speed stirring device, the stirring device is operated at a speed of 2000 revolutions per minute, and at the same time, an ultrasonic dispersion device (frequency of 40 kHz) is used for processing for about 30 minutes, so that the nano ceramic filler is uniformly dispersed in the resin, thereby forming a resin solution with no agglomeration and good fluidity. High-purity copper foil (thickness of 12 microns) is used as the substrate, and the resin solution is uniformly coated on the surface of the copper foil by coating equipment, so that the coating thickness is uniform (for example, controlled within the range of 10-15 microns), and the environmental temperature is controlled at 120 degrees Celsius during the coating process. This temperature can make the polyimide resin gradually volatilize the solvent and enter the semi-cured state (i.e. B stage), forming a composite substrate with certain flexibility and adhesion. The coated substrate is subjected to plasma cleaning treatment, and the surface of the substrate is treated by a plasma cleaning device with a power of 500 watts, argon and oxygen mixed plasma (proportion of 3:1) for 5 minutes to remove surface organic contaminants, and at the same time, the surface roughness of the copper foil is increased (for example, the surface roughness Ra is increased from 0.2 microns to 0.5 microns) through physical and chemical action, thereby significantly improving the adhesion of the resin coating to the copper foil. This surface modification effectively reduces the dielectric loss (for example, the dielectric constant is reduced from 4.0 to 3.5), and at the same time, the thermal conductivity is improved (for example, from 0.5 W / m·K to 1.2 W / m·K), thereby obtaining a single-sided copper-clad substrate with low dielectric loss and high thermal conductivity.

[0055] S2: etching the composite substrate according to a preset layout to obtain an inner layer circuit substrate;

[0056] In step S2, the surface of the composite substrate is covered with a high-purity copper foil (for example, 12 microns thick), and in order to form a preset circuit pattern, a dry photoresist film is uniformly coated on the surface of the copper foil in a dust-free environment using a coating device, the thickness of the dry photoresist film is controlled to be 25 microns, and the photoresist film is exposed to ultraviolet light with a wavelength of 365 nanometers according to a 12-layer circuit layout file designed by a computer, this wavelength can effectively excite the photosensitizer in the photoresist to form a high-resolution latent image pattern, the computer-aided design (CAD) file contains circuit layout information, such as a circuit pattern with a line width and a line spacing of 5 microns, for example, in actual operation, the substrate coated with photoresist can be placed in an ultraviolet exposure machine, and a mask can be used to align the pattern in the CAD file, the exposure time is controlled to be less than 10 seconds, so that the photoresist in the exposed area undergoes sufficient photochemical reaction, and the unexposed area remains soluble. A 1% concentration of sodium carbonate solution is used as a developer to remove the photoresist in the unexposed area by spraying or soaking, thereby forming an accurate circuit pattern template on the surface of the substrate, the low concentration of sodium carbonate solution can gently dissolve the unexposed photoresist, while avoiding damage to the photoresist in the exposed area, for example, the substrate can be placed in a developing tank, the temperature of the developing solution is controlled to be 25 degrees Celsius, and the developing time is 60 seconds, after developing, the substrate is rinsed with deionized water to remove residual developing solution, this process makes the circuit pattern template clear and accurate, for example, the formed pattern template can be accurate to 5 microns / 5 microns of line width / line spacing. A 2.5 mol / L acidic copper chloride etching solution is used to etch the exposed copper foil within 30 seconds, the acidic copper chloride etching solution has high copper etching capacity and can complete the etching process in a short time, thereby reducing the lateral erosion of the photoresist template and maintaining the high accuracy of the circuit pattern, then a film remover is used to remove the remaining photoresist, and the substrate is cleaned and dried to obtain an inner layer circuit substrate.

[0057] S3: alternately stacking the double-sided inner layer circuit substrate and the prepreg containing glass fiber material and performing vacuum hot pressing to obtain a laminated structure, wherein the number of double-sided inner layer circuit substrates and prepregs is equal;

[0058] In step S3, the prepreg is a low-flow epoxy resin system containing glass fiber reinforcement, with a thickness controlled at 30 microns, and nano-silica fillers are added to improve the mechanical strength and thermal stability of the material. This prepreg can flow and solidify when heated, thereby bonding multiple layers of substrates together. For example, a prepreg made of E-glass fiber cloth impregnated with epoxy resin containing nano-silica can be used, which has a dielectric constant as low as 3.8, suitable for high-frequency signal transmission, meeting the requirements of notebook computer circuit boards for signal integrity. After preparing the double-sided inner layer circuit substrate and the prepreg, 6 double-sided inner layer circuit substrates and 6 prepregs are alternately stacked in the order of substrate-prepreg-substrate to form a 12-layer structure, which can achieve insulation and bonding between each inner layer circuit substrate through the prepreg, while maintaining symmetry between layers to reduce the risk of warping during hot pressing. After stacking, the stack is pressed by a vacuum hot press at 180 degrees Celsius and 2 megapascals for 90 minutes. This process condition can make the epoxy resin in the prepreg flow and solidify sufficiently, thereby firmly bonding multiple layers of substrates together. At the same time, the vacuum environment effectively removes air bubbles between the layers, avoiding the influence of air bubble defects on the reliability of the circuit board. For example, a multi-layer vacuum hot press can be used to place the stack between stainless steel platens, set the heating rate to 3 degrees Celsius per minute, maintain a constant temperature of 180 degrees Celsius, and press at a uniform pressure of 2 megapascals for 90 minutes. During the pressing process, the vacuum degree is maintained below 10 pascals to ensure that the layers are bubble-free and tightly bonded. After pressing, the temperature is slowly reduced to room temperature to reduce internal stress. The resulting stacked structure has a flat surface and excellent interlayer bonding strength. Interlayer interconnection channels are formed in the stacked structure by laser drilling process. Specifically, a CO2 laser drilling equipment with a wavelength of 10.6 microns is used to scan and drill micro-holes with a diameter of 50 microns at a pulse energy of 0.5 millijoules. These micro-holes serve as interlayer vias to connect circuit patterns on different layers, enabling electrical interconnection of multi-layer circuits. For example, a high-precision CO2 laser drilling machine can be used, with a computer-controlled scanning system drilling according to the pre-set hole layout. The laser pulse frequency is set to 10 kHz, and the single-hole drilling time is controlled within 0.1 seconds to ensure smooth hole walls without burning. The 50-micron micro-hole size can meet the demand of high-density interconnection, and the high precision of laser drilling avoids the hole deviation and substrate damage that may be caused by traditional mechanical drilling.

[0059] S4: After the chemical electroplating treatment of the stacked structure, etching treatment is performed on the outer surface of the stacked structure according to the pre-set circuit pattern to form an outer layer circuit structure;

[0060] In step S4, the purpose of the electroless plating process is to form a uniform conductive layer on the surface and inner wall of the micro-via, to enable electrical connection between the layers of the circuit board and the conductivity of the outer layer circuit. In actual operation, the electroless plating process can include three sub-steps: desmear, electroless copper plating, and electroplating copper. Desmear is to remove residues generated during the drilling process, such as resin debris or glass fiber residue. A potassium permanganate acid solution with a concentration of 0.1 mol / L can be used to clean the inner wall of the micro-via, with a treatment time of about 10 minutes. This solution has strong oxidizing properties and can effectively decompose and remove organic residues generated during drilling, while slightly roughening the surface of the inner wall of the micro-via, thereby enhancing the adhesion of the subsequent copper plating layer. After completing the desmear process, a thin copper seed layer is deposited on the inner wall of the micro-via and the surface of the laminated structure, serving as a conductive basis for subsequent electroplating. Electroless copper plating uses a formaldehyde-containing electroless copper plating solution, and the reaction is carried out at 50°C to deposit a copper layer with a thickness of about 0.5 microns. Formaldehyde acts as a reducing agent in this process, reducing copper ions to metallic copper and depositing them on the surface and wall of the laminated structure. To ensure the uniformity of the copper layer, the pH and temperature of the solution need to be precisely controlled, for example, maintaining a pH of around 12 and ensuring uniform contact of the solution with the surface of the substrate through stirring. After electroless copper plating, the laminated structure enters the electroplating copper stage, using a copper sulfate electroplating solution with a current density of 2 amperes per square decimeter for about 60 minutes, thereby depositing a copper layer with a thickness of about 15 microns on the inner wall of the micro-via and the surface. After completing the electroless plating process, a uniform conductive copper layer has been formed on the surface of the laminated structure and the inner wall of the micro-via, and etching is performed according to the pre-designed circuit pattern to form the outer layer circuit structure. This process can use a combination of photolithography and etching, similar to the etching process for the inner layer circuit substrate in step S2, but with higher complexity and precision requirements for the outer layer circuit. A photosensitive dry film or liquid photoresist is applied to the outer surface of the laminated structure to form a photolithographic protective layer. Then, through the UV exposure and development process, the pre-designed circuit pattern is transferred to the photoresist layer. The pre-designed circuit pattern can be generated by circuit design software such as Altium Designer or Cadence, which includes precise line width and spacing requirements.

[0061] S5: applying a solder resist ink on the outer layer circuit structure to form a solder resist layer, obtaining a notebook computer printed circuit board;

[0062] In step S5, a liquid photosensitive green solder resist ink with a thickness of 20 microns is applied to the surface of the outer layer circuit structure of the circuit board using a coating device. This ink contains nano-aluminum oxide particles with a particle size of 50 nanometers, which significantly improve the wear resistance and thermal stability of the solder resist layer, making it less prone to cracking or peeling during high-temperature soldering or long-term use. The coating device uses screen printing or roller coating technology to evenly cover the surface of the circuit board with the ink. By squeezing the ink through a screen with a pre-designed pattern, the ink is deposited on the surface of the circuit board according to the design requirements. After coating, ultraviolet exposure and development processing are performed. The liquid photosensitive green solder resist ink is a photosensitive material that changes its solubility under ultraviolet light. During the exposure process, the circuit board surface is covered with a mask with a pre-designed pattern. The transparent areas of the mask correspond to the non-soldering areas that need to retain the solder resist layer, while the opaque areas correspond to the soldering areas that need to be exposed, such as pads or via locations. Ultraviolet light is shone through the mask onto the surface of the ink, causing the exposed area of the ink to undergo a photo-curing reaction and become insoluble in the developer, while the unexposed area of the ink remains soluble. Subsequently, through the development process, the circuit board is cleaned with a developer solution (such as sodium carbonate solution) to remove the uncured ink, thereby forming a precise solder resist layer pattern on the surface of the circuit board. After forming the solder resist layer pattern, the solder resist ink is cured by heating it at 150 degrees Celsius for 30 minutes to completely cure the ink and firmly bond it to the surface of the circuit board. The curing process can be carried out in a hot air circulation oven, which can provide uniform temperature distribution to avoid local overheating or deficiency. The exposed soldering areas are treated with a sandblasting technique to optimize the soldering performance. The sandblasting technique uses high-speed injection of fine abrasive materials (such as aluminum oxide particles) to slightly roughen the exposed areas such as pads or vias, increasing the surface roughness and thereby improving the adhesion of the solder and the quality of the soldering. The final notebook computer printed circuit board is obtained.

[0063] In another embodiment, the stacking method can also be another way. In the initial stacking stage, high thermal conductivity nano-ceramic reinforced prepreg is selected as the bottom layer, combined with a thinner double-sided inner layer circuit substrate to enhance the bottom heat dissipation capability; in the middle stacking area, semi-solid sheets with high dielectric constant are introduced and combined with thicker inner layer circuit substrates for asymmetric stacking, where the thickness of the semi-solid sheet gradually increases according to the preset gradient to form a progressive dielectric layer structure, thereby optimizing the stability of high-frequency signal transmission; in the stacking stage close to the outer layer, semi-solid sheets with low thermal expansion coefficient are combined with high-density interconnection inner layer circuit substrates, and the stacking angle is controlled (for example, rotating the stacking between 15° to 30°) to reduce interlayer stress concentration and improve the anti-warping performance; during the stacking process, for different functional areas (such as power area, signal area and ground layer), vertical conduction structures are introduced in specific interlayers through local embedded micro-via technology to enhance the reliability of interlayer electrical connection; the whole stacking process is carried out in a vacuum environment through multi-stage temperature and pressure curve control for hot pressing and curing, where the temperature gradually increases from 120°C to 220°C, and the pressure increases from 0.5 MPa to 2.0 MPa, ensuring that the interlayers are tightly bonded and free of air bubble defects; through this multi-level asymmetric progressive stacking method, the structural strength and thermal management capability of the notebook computer printed circuit board can be effectively improved, and the high-frequency signal integrity and overall circuit performance can be significantly improved, meeting the stringent requirements of high-performance notebook computers for complex circuit boards.

[0064] In another embodiment, a three-dimensional partition composite stacking method can also be used. Specifically, a multi-dimensional stacking blueprint is designed according to the functional partition of the circuit board (such as high-frequency signal area, power distribution area, and low-speed signal area), different material properties and thickness of double-sided inner layer circuit substrates and semi-solid sheets containing glass fibers and nano-reinforced particles are selected for partition composite stacking; in the bottom layer stacking stage, semi-solid sheets with high thermal conductivity and low dielectric loss are combined with thin high-density inner layer circuit substrates, microgroove structures are formed on the substrate surface in advance through laser micro-processing technology to embed heat-conducting metal micro columns, thereby enhancing the local heat dissipation capacity; in the middle layer stacking stage, semi-solid sheets with gradient dielectric constant are introduced, the resin content of each layer of semi-solid sheets (from 30% to 50% gradually) and the glass fiber orientation (the stagger angle is controlled at 45° to 60°) are accurately controlled to form a non-uniform dielectric layer, so as to optimize the impedance matching of high-frequency signals and reduce crosstalk; in the stacking area close to the outer layer, semi-solid sheets with low thermal expansion coefficient are combined with high interconnection density inner layer circuit substrates, and a reinforced fiber grid is embedded in the high stress area through local pressure technology to improve the mechanical impact resistance and warping resistance; during the stacking process, selective electrical connection is realized between different functional partitions, and the signal transmission speed and heat diffusion efficiency are further improved by adding an ultra-thin graphene conductive layer between specific layers; through this partition stacking method, the signal integrity, thermal management efficiency and mechanical stability of the notebook computer printed circuit board can be improved.

[0065] In one embodiment, the resin is any one or a mixture of more than one of polyimide resin, epoxy resin or phenolic resin, the nano-ceramic filler is any one or a mixture of more than one of aluminum oxide, zirconium oxide, silicon nitride, boron nitride or silicon carbide, and the substrate is any one of copper foil, aluminum foil or nickel foil.

[0066] In one embodiment, the step of mixing and stirring the resin and the nano-ceramic filler to form a resin solution, coating the resin solution on the surface of the substrate and heating to a semi-cured state to obtain a composite substrate comprises:

[0067] The nano-ceramic filler is mixed with epoxy resin and polyimide resin at a mass ratio of 3:1 and placed in a stirring device for stirring treatment to form a resin solution;

[0068] A dilute sulfuric acid solution is used to pretreat the surface of the copper foil substrate, and the resin solution is coated on the surface of the pretreated copper foil substrate to obtain a primary coated substrate;

[0069] The primary coated substrate is placed in a reaction kettle, baked at 80-90°C for 10-12 minutes, then heated to 150-160°C at a rate of 10°C / min and kept for 15 minutes to make the resin coating reach a semi-cured state, thereby obtaining the composite substrate.

[0070] In this embodiment, nano-ceramic fillers, epoxy resin, and polyimide resin are used as the main raw materials. The nano-ceramic fillers have high hardness, high thermal stability, and excellent electrical insulation properties. The nano-ceramic fillers, epoxy resin, and polyimide resin are placed in a stirring device in a mass ratio of 3:1 for stirring treatment to form a uniform resin solution, allowing the nano-ceramic fillers to disperse uniformly in the resin matrix and avoid agglomeration. Because of their high specific surface area and high surface energy, nano-particles are prone to agglomeration, which affects the performance of the composite material. Copper foil is used as the substrate and is pre-treated with a dilute sulfuric acid solution. The dilute sulfuric acid solution can effectively remove the oxide layer on the surface of the copper foil and increase the surface roughness through micro-etching, thereby improving the adhesion between the resin and the copper foil. The copper foil is immersed in a dilute sulfuric acid solution (concentration of 5%~10%), and the immersion time may be 30 seconds to 2 minutes, depending on the surface condition of the copper foil. Subsequently, the copper foil is thoroughly washed with deionized water to remove residual acid and dried to ensure a clean and water mark-free surface. The resin solution is coated on the surface of the pre-treated copper foil substrate to obtain a preliminary coating substrate. The coating thickness can be controlled using a cloth machine, and the coating thickness can be adjusted according to the requirements of the final product, for example, in the range of 50~100 microns. The preliminary coating substrate is placed in a reaction kettle for baking to achieve a semi-cured state of the resin coating. The baking is carried out at 80~90℃ for 10~12 minutes, followed by a temperature increase at a rate of 10℃ / min to 150~160℃ and maintained for 15 minutes. The initial 80~90℃ baking stage is mainly to volatilize the solvent in the resin solution and promote the initial crosslinking between resin molecules. The subsequent temperature increase further promotes the curing reaction of the resin. By controlling the temperature increase rate (10℃ / min), the concentration of thermal stress or coating cracking caused by rapid temperature increase can be avoided. After maintaining at 150~160℃ for 15 minutes, the resin coating reaches a semi-cured state, at which point the resin molecules have formed a partial crosslinked network but still retain some flowability, suitable for subsequent processing. It is worth noting that the heat treatment needs to be carried out in a reaction kettle, which indicates that it may be necessary to control environmental conditions such as vacuum or inert gas atmosphere to prevent oxidation of the copper foil at high temperatures or unnecessary side reactions of the resin. After the heat treatment is completed, the composite substrate is slowly cooled to room temperature to avoid the accumulation of internal stress caused by rapid cooling.

[0071] In one embodiment, the step of etching the composite substrate according to a predetermined layout to obtain an inner layer circuit substrate includes:

[0072] A dry film photoresist is applied to the surface of the composite substrate and heated at 90~100℃ for 20~30 seconds to obtain a photoresist-coated substrate.

[0073] The photoresist-coated substrate is subjected to ultraviolet exposure according to a predetermined layout to obtain an exposed substrate.

[0074] The exposed substrate is developed by a developing device using a 0.8% mass concentration potassium carbonate solution as a developing solution under a constant temperature condition of 20-25°C to obtain a patterned substrate;

[0075] The patterned substrate is etched in an etching tank under a constant temperature condition of 30-32°C using an acid copper sulfate etching solution with a concentration of 2.0 mol / L, and is etched for 15-20 seconds, then the etching solution flow rate is reduced and etching is performed for 25-30 seconds to obtain a primary circuit substrate;

[0076] The primary circuit substrate is removed from a film under a condition of 40-45°C using a 3% concentration sodium hydroxide solution as a film removing solution to obtain an inner layer circuit substrate.

[0077] In this embodiment, a dry film photoresist is applied to the surface of the composite substrate and heated at 90-100°C for 20-30 seconds to form a uniform and well-adhered photoresist film on the surface of the composite substrate. The dry film photoresist is a photosensitive material that undergoes a chemical reaction under ultraviolet light exposure, resulting in soluble or insoluble regions. After the coating is complete, the substrate is sent to a heating device and baked at a temperature of 90-100°C for 20-30 seconds. The coated substrate is then subjected to ultraviolet exposure according to the pre-set layout, resulting in an exposed substrate. Ultraviolet exposure transfers the pre-set circuit pattern to the dry film photoresist through a photochemical reaction. The pre-set layout exists in the form of a photomask, which has a precise circuit pattern design engraved on it. Through ultraviolet light exposure, the transparent areas of the photomask allow light to pass through, causing the corresponding areas of the dry film photoresist to undergo a photochemical reaction, while the opaque areas protect the underlying photoresist from being affected. A 0.8% mass concentration potassium carbonate solution is used as the developer, and the exposed substrate is developed at a constant temperature of 20-25°C using a developing device, resulting in a patterned substrate. The purpose of the developing process is to remove the soluble photoresist regions after exposure, thereby forming a patterned photoresist mask on the surface of the substrate that is consistent with the pre-set layout. The potassium carbonate solution as the developer has a mild alkalinity, which can effectively dissolve the photoresist that has undergone a photochemical reaction after exposure, while the photoresist in the unexposed areas remains due to its stable chemical properties. The developing device can use a spraying or soaking method, controlling the flow rate and spraying pressure of the developer to ensure that the developer fully contacts the substrate surface while avoiding physical damage to the photoresist mask. After the developing process, a clear patterned photoresist mask is formed on the surface of the substrate, exposing the copper foil areas that need to be etched. A 2.0 mol / L acidic copper sulfate etching solution is used to etch the patterned substrate in an etching tank at a constant temperature of 30-32°C. The etching process is divided into two stages: first etching for 15-20 seconds, then reducing the flow rate of the etching solution and continuing etching for 25-30 seconds, resulting in a primary circuit substrate. The design of the two-stage etching process is to optimize the etching effect. In the first stage (15-20 seconds), a higher etching solution flow rate can ensure that the etching solution fully contacts the substrate surface, quickly removing the surface copper foil and forming a preliminary circuit outline. Then, by reducing the flow rate and extending the etching time (25-30 seconds), the etching process can be refined to avoid excessive etching that may result in insufficient line width or irregular edges. A constant temperature of 30-32°C can maintain the chemical reaction activity of the etching solution, stabilizing the etching rate and avoiding uneven etching caused by temperature fluctuations. A 3% concentration sodium hydroxide solution is used as the film removal solution to remove the film from the primary circuit substrate at a temperature of 40-45°C, resulting in an inner layer circuit substrate. The purpose of the film removal process is to remove the photoresist mask on the surface of the substrate, exposing the copper circuit pattern formed after etching.The sodium hydroxide solution as a film removing solution can effectively dissolve the dry film photoresist, and has no obvious corrosion effect on the copper circuit. The film removing temperature is controlled at 40-45℃, which can ensure the chemical activity of the film removing solution, quickly dissolve the photoresist, and avoid potential damage to the substrate or circuit caused by high temperature. During the film removing process, soaking or spraying method can be used. By controlling the concentration of the film removing solution and the processing time, the photoresist can be completely removed, and the residues can be avoided to affect the subsequent process. After the film removing is completed, the inner layer circuit pattern on the substrate surface is exposed, which is the inner layer circuit substrate.

[0078] In an embodiment, the step of alternately stacking the double-sided inner layer circuit substrate and the prepreg containing glass fiber material and performing vacuum hot pressing treatment to obtain a laminated structure, wherein the step of equal number of the double-sided inner layer circuit substrate and the prepreg comprises:

[0079] The prepreg containing glass fiber material is immersed in a mixed solution containing nano-alumina particles and epoxy resin for impregnation treatment to obtain a modified prepreg, wherein the particle size of the nano-alumina particles is 20-25 nanometers, and the impregnation time is 10-15 minutes;

[0080] A plurality of the modified prepregs and the double-sided inner layer circuit substrate are alternately stacked and pressed by a hot press at 175-180℃ and 1.8-2MPa for 60-80 minutes to obtain a pressed laminated structure;

[0081] A laser device is used to perform layer-by-layer scanning treatment on the pressed laminated structure with a pulse energy of 0.4-0.5mj to form a plurality of micropores, thereby obtaining a laminated structure with interlayer interconnected channels.

[0082] In this embodiment, the prepreg is a glass fiber-containing epoxy resin composite material in a semi-cured state. The prepreg is immersed in a mixed solution containing nano-alumina particles and epoxy resin for impregnation treatment to obtain a modified prepreg. The nano-alumina particles, with a particle size of only 20-25 nanometers, have a very high specific surface area, which can significantly enhance the thermal conductivity and mechanical strength of the material, and improve the dielectric properties of the prepreg. The prepreg is completely immersed in the solution, and the immersion time is controlled at 10-15 minutes to allow the solution to fully penetrate into the glass fibers, while avoiding changes in material properties due to prolonged immersion. After impregnation, the prepreg is removed and dried to remove excess solvent and maintain the semi-cured state, thereby obtaining a modified prepreg. Multiple modified prepregs are alternately stacked with double-sided inner layer circuit substrates. A double-sided inner layer circuit substrate is placed at the bottom, covered with a modified prepreg, and a second double-sided inner layer circuit substrate is placed on top. This process is repeated until the desired number of layers is reached. During stacking, the layers must be aligned, especially the circuit patterns on the circuit substrates must be consistent with the design requirements, which can be achieved through alignment equipment or optical alignment systems. After stacking, a hot press is used to perform vacuum hot pressing on the entire stacked structure. The temperature is 175-180℃, the pressure is 1.8-2MPa, and the pressing time is 60-80 minutes. The temperature range allows the epoxy resin in the modified prepreg to flow and cure fully, forming a firm interlayer bond. The pressure range ensures that the layers are tightly bonded, eliminating air bubbles and avoiding interlayer voids. The pressing time ensures complete curing of the resin while avoiding material aging due to prolonged time. The vacuum environment and hot pressing process can also effectively reduce oxidation, further improving the quality of the stacked structure. A laser device is used to scan the pressed stacked structure layer by layer to form multiple micro-holes, resulting in a stacked structure with interlayer interconnected channels. The laser device uses a pulse energy of 0.4-0.5mJ to accurately control the size and depth of the micro-holes, avoiding thermal damage to the surrounding material. In specific operations, the laser device scans layer by layer according to the pre-set drilling pattern, which can use ultraviolet laser or carbon dioxide laser due to its high precision and high energy characteristics. The formation of micro-holes not only realizes the physical connection of interlayer circuits, but also provides channels for subsequent electroplating or conductive filling processes.

[0083] In one embodiment, the step of chemically electroplating the stacked structure includes:

[0084] The stacked structure is immersed in a colloidal activation solution containing 0.02-0.03 mol / L palladium chloride and 0.1-0.15 mol / L tin chloride for activation treatment, allowing palladium ions to form catalytically active sites on the inner walls of the micro-holes;

[0085] The activated laminated structure is immersed in a chemical copper plating solution containing 0.05-0.06 mol / L copper sulfate, 0.1-0.15 mol / L formaldehyde and a complexing agent, and reacted at 48-50°C for 15 minutes to obtain a seed layer structure;

[0086] The seed layer structure is placed in an electroplating solution containing 0.2-0.3 mol / L copper sulfate, 0.5-0.6 mol / L sulfuric acid and an additive, and electroplated at a current density of 1.8-2 A / dm 2 at 25-30°C for 50-60 minutes to obtain a conductive laminated structure.

[0087] In this embodiment, the laminated structure is immersed in a colloidal activation solution containing 0.02-0.03 mol / L palladium chloride and 0.1-0.15 mol / L tin chloride for activation treatment, to form catalytically active sites on the inner wall and surface of the micropores of the laminated structure. Palladium chloride (PdCl2) acts as a catalyst precursor, and together with tin chloride (SnCl2) in the colloidal activation solution, forms a colloidal palladium-tin complex. The tin chloride acts as a stabilizer to prevent the palladium ions from aggregating too quickly, and through an oxidation-reduction reaction (e.g. Sn 2+ is oxidized to Sn 4+ ), the palladium ions (Pd 2+ ) are reduced to metallic palladium (Pd 0) and adsorbed on the surface of the stacked structure and the inner wall of the micropores in the form of nanoparticles. These palladium particles have high catalytic activity, thereby triggering the deposition of copper. The concentration of palladium chloride in the activation solution is 0.02-0.03 mol / L, and the concentration of tin chloride is 0.1-0.15 mol / L. This concentration range allows the palladium particles to be uniformly distributed and have sufficient catalytic activity, while avoiding colloidal instability or cost waste due to excessive concentration. The activation treatment is carried out at room temperature or slightly above room temperature, and the stacked structure needs to be soaked for a sufficient time (several minutes) and the inner wall of the micropores needs to be fully contacted with the activation solution to achieve uniform distribution of catalytic sites. After treatment, the stacked structure needs to be washed with deionized water to remove excess colloidal particles and residual ions. The activated stacked structure is immersed in a chemical copper plating solution containing 0.05-0.06 mol / L copper sulfate, 0.1-0.15 mol / L formaldehyde, and a complexing agent at 48-50°C for 15 minutes to form a seed layer structure. This chemical copper plating step utilizes the principle of electroless deposition, which triggers the reduction reaction of copper ions through the catalyst (i.e., the palladium particles deposited in the previous step) to form a thin and uniform copper seed layer. The main components of the chemical copper plating solution include copper sulfate (CuSO4) as the source of copper ions, formaldehyde (HCHO) as the reducing agent, and a complexing agent to stabilize the solution and control the reaction rate. The concentration of copper sulfate is controlled at 0.05-0.06 mol / L, which can provide an appropriate amount of copper ions to moderate the deposition rate, while avoiding solution instability or rough copper layer due to excessive concentration. The concentration of formaldehyde is 0.1-0.15 mol / L, which provides sufficient reducing power, which is oxidized to formic acid under the action of palladium catalysts, while Cu 2+ is reduced to metallic copper (Cu 0), deposited on the surface of the laminated structure. Complexing agents (such as EDTA or potassium sodium tartrate) prevent copper ions from precipitating prematurely in the solution by forming complexes with them, while adjusting the deposition rate to make the copper layer uniform and dense. The reaction temperature is controlled at 48-50°C, which can accelerate the redox reaction of formaldehyde, while avoiding solution decomposition or copper layer quality decline due to excessive temperature. The reaction time is 15 minutes, which is sufficient to form a seed layer with moderate thickness (0.5-2 microns). The seed layer structure is placed in an electroplating solution containing 0.2-0.3 mol / L copper sulfate, 0.5-0.6 mol / L sulfuric acid and additives, and is electroplated at a current density of 1.8-2 A / dm2 at 25-30°C for 50-60 minutes to obtain the final conductive laminated structure. This copper electroplating step further thickens the copper layer by applying an external current, forming a conductive layer with excellent electrical conductivity and mechanical strength. In the electroplating solution, the copper sulfate concentration is 0.2-0.3 mol / L, providing sufficient copper ions to support efficient electrodeposition; the sulfuric acid concentration is 0.5-0.6 mol / L, increasing the solution's conductivity while maintaining an acidic environment to prevent copper ion hydrolysis. Additives (including brighteners, levelers and inhibitors, etc.) can improve the surface smoothness of the copper layer, reduce pinholes or cracks, and improve the uniformity of the deposition. The current density is 1.8-2 A / dm 2 This range allows for rapid deposition of the copper layer while avoiding burning or roughness due to excessive current. The electroplating temperature is controlled at 25-30°C, which helps maintain solution stability and copper layer quality while facilitating operation. The electroplating time is 50-60 minutes, which can form a copper layer with moderate thickness to meet the requirements of the conductive laminated structure in terms of electrical conductivity and durability. During electroplating, appropriate electrodes (such as soluble copper anodes) are used and the solution is circulated to stabilize the copper ion concentration and ensure uniform deposition. After electroplating, the laminated structure needs to be cleaned and dried to remove residual electroplating solution and prevent oxidation.

[0088] In an embodiment, the step of etching the outer layer surface of the laminated structure according to a predetermined circuit pattern to form an outer layer circuit structure comprises:

[0089] A photoresist containing nano-silicon dioxide particles is applied to the outer layer surface of the laminated structure and baked at 90-95°C for 5-10 minutes to obtain a photoresist cover structure;

[0090] An etching solution of 3.0 mol / L ferric chloride is used to etch the photoresist cover structure in an etching tank at a constant temperature of 35-40°C to obtain a preliminary outer layer structure;

[0091] A 5% potassium hydroxide solution is used as a stripping agent to strip the preliminary outer layer structure at 50-55°C to obtain an outer layer circuit structure.

[0092] In this embodiment, the photoresist containing nanosilica particles is applied to the outer surface of the laminated structure to form a uniform photoresist film on the surface of the laminated structure. The photoresist is a photosensitive material, and the nanosilica particles in it can enhance the physical properties of the photoresist. When applying the photoresist, a spin coating technique can be used. The laminated structure is placed on a high-speed spin coater, and the photoresist is uniformly distributed on the surface under the action of centrifugal force. After the coating is completed, the laminated structure covered with photoresist is baked at a temperature of 90-95°C for 5-10 minutes. By baking in this specific temperature range, volatile components in the photoresist are effectively removed, while avoiding high temperatures that can cause thermal decomposition or performance degradation of the photoresist. A ferric chloride etching solution with a concentration of 3.0 mol / L is used to etch the photoresist-covered structure in an etching tank at a constant temperature of 35-40°C to form a preliminary outer layer structure. The material on the outer surface of the laminated structure is selectively removed according to the pre-set circuit pattern to form the required circuit structure. A ferric chloride etching solution with a concentration of 3.0 mol / L can provide sufficient chemical activity to quickly etch the metal, while avoiding high concentrations that can cause the etching rate to be too fast or uneven. Etching in an etching tank at a constant temperature of 35-40°C can stabilize the chemical reaction rate of the etching solution, while reducing the impact of temperature fluctuations on etching accuracy. The etching tank is equipped with a constant temperature control system, which maintains temperature stability through a circulating water bath or heating device. After etching is completed, the photoresist layer remaining on the preliminary outer layer structure is removed by stripping to expose the final outer layer circuit structure. A 5% potassium hydroxide solution is used as a stripping agent to perform stripping at a temperature of 50-55°C. Potassium hydroxide solution is a strong alkaline stripper that can effectively dissolve photoresist. The alkaline solution can chemically react with the organic components in the photoresist, quickly decompose and remove the photoresist layer. The stripping temperature is controlled at 50-55°C, which can accelerate the stripping reaction and avoid potential damage to the laminated structure or circuit pattern caused by high temperature. After stripping is completed, the outer surface of the laminated structure will completely expose the pre-set circuit pattern to form the final outer layer circuit structure.

[0093] It is worth noting that the preset circuit pattern in the above embodiment can be designed in advance by computer and a mask plate is made. The design process can be completed in computer-aided design (CAD) software, such as professional tools like Altium Designer, Cadence or EAGLE. The designer draws the wiring pattern of the outer circuit according to the electrical performance requirements and physical size limitations of the circuit board, including conductive lines, pads, vias and other key features. During the drawing process, the designer makes the solder resist layer cover the non-soldering area accurately while exposing the pads and vias that need to be soldered according to the coverage of the solder resist layer. In order to achieve this goal, the designer generates a special layer for the solder resist layer in the CAD software, which defines the areas that need to be covered and exposed by the solder resist ink, forming a solder resist opening pattern.

[0094] In an embodiment, the step of coating the solder resist ink on the outer circuit structure to form a solder resist layer to obtain a notebook computer printed circuit board comprises:

[0095] Coating the solder resist ink on the surface of the outer circuit structure, the solder resist ink comprising nano-aluminum oxide particles, a photosensitizer and a toughening agent, to obtain an initial solder resist coating;

[0096] Using an ultraviolet light source to perform ultraviolet exposure treatment on the initial solder resist coating to obtain a patterned solder resist coating;

[0097] After developing the patterned solder resist coating using an alkaline developing solution, performing low-temperature curing treatment at 90-100°C for 10-15 minutes to obtain the notebook computer printed circuit board.

[0098] In this embodiment, the outer layer circuit structure is formed by etching the copper foil on the substrate, and the solder resist ink is applied by screen printing or spraying technology, which can make the ink evenly cover the non-soldering area, while avoiding covering the pads or vias that need to be soldered. The solder resist ink contains nano-alumina particles, photosensitizer and toughening agent. The nano-alumina particles can significantly improve the wear resistance and heat resistance of the solder resist layer. The addition of photosensitizer makes the ink have the characteristics of light curing, and the toughening agent enhances the flexibility of the solder resist layer, preventing it from cracking under thermal expansion and contraction or mechanical stress. After the coating is completed, a uniform thin film will be formed on the surface of the circuit board. A photolithography device and a pre-designed mask are used. The mask contains patterns corresponding to the circuit board design, allowing ultraviolet light to selectively pass through and irradiate the initial solder resist coating. Because the solder resist ink contains photosensitizer, it will undergo a photochemical reaction under ultraviolet light, causing the exposed area of the ink molecules to cross-link and solidify, forming a structure that is insoluble in the developer, while the unexposed area of the ink remains soluble. In actual operation, the wavelength and intensity of the ultraviolet light source need to be accurately controlled according to the characteristics of the solder resist ink. The wavelength is in the range of 350-400 nanometers, and the exposure time is adjusted according to the thickness of the ink and the sensitivity of the photosensitizer. After exposure, the initial solder resist coating is divided into solidified and un-solidified areas, forming a preliminary patterned solder resist coating. The development process removes the un-solidified ink by placing the circuit board in an alkaline developer solution using a spraying or soaking method. The developer can be a sodium carbonate or sodium hydroxide solution, and its concentration and temperature need to be optimized according to the chemical properties of the ink. The developer will dissolve the unexposed area of the ink, while the patterned area after solidification will remain on the surface of the circuit board, forming a clear solder resist layer pattern. After development, the circuit board will be cleaned and dried to remove residual developer and moisture. The subsequent low-temperature curing process is carried out at a temperature of 90-100°C for 10-15 minutes, which aims to further enhance the physical and chemical stability of the solder resist layer. Low-temperature curing not only hardens the solder resist layer completely, but also improves its adhesion to the surface of the circuit board, while avoiding potential damage to other components of the circuit board (such as the substrate or copper foil) caused by high temperature. Curing is usually done in an oven, and the precise control of temperature and time can be achieved through programmed equipment to ensure the repeatability and consistency of the process. After curing, the solder resist layer is finally formed, covering the non-soldering area of the circuit board, exposing the pads and vias, and thus obtaining a notebook computer printed circuit board that meets the design requirements.

[0099] The above-described embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of manufacturing a notebook computer printed circuit board, characterized by, The method comprises the following steps: mixing and stirring the resin and the nanoceramic filler to form a resin solution, coating the resin solution on the surface of a substrate and heating to a semi-cured state to obtain a composite substrate; etching the composite substrate according to a preset layout to obtain an inner layer circuit substrate; alternately stacking the double-sided inner layer circuit substrate and a prepreg containing glass fiber material and performing vacuum hot pressing to obtain a laminated structure, wherein the number of the double-sided inner layer circuit substrate and the prepreg is equal; after chemical electroplating treatment of the laminated structure, etching the outer surface of the laminated structure according to a preset circuit pattern to form an outer layer circuit structure; coating a solder resist ink on the outer layer circuit structure to form a solder resist layer to obtain a notebook computer printed circuit board; the step of mixing and stirring the resin and the nanoceramic filler to form a resin solution, coating the resin solution on the surface of a substrate and heating to a semi-cured state to obtain a composite substrate comprises: mixing the nanoceramic filler, epoxy resin and polyimide resin in a mass ratio of 3:1 in a stirring device to form a resin solution; pretreating the surface of a copper foil substrate with a dilute sulfuric acid solution, coating the resin solution on the surface of the pretreated copper foil substrate to obtain a primary coated substrate; placing the primary coated substrate in a reaction kettle, baking at 80-90°C for 10-12 minutes, then increasing the temperature to 150-160°C at a rate of 10°C / min and maintaining for 15 minutes to make the resin coating reach a semi-cured state to obtain the composite substrate; the step of alternately stacking the double-sided inner layer circuit substrate and a prepreg containing glass fiber material and performing vacuum hot pressing to obtain a laminated structure, wherein the number of the double-sided inner layer circuit substrate and the prepreg is equal, comprises: immersing the prepreg containing glass fiber material in a mixed solution containing nano-alumina particles and epoxy resin for impregnation treatment to obtain a modified prepreg, wherein the particle size of the nano-alumina particles is 20-25 nanometers and the impregnation time is 10-15 minutes; alternately stacking a plurality of the modified prepreg and the double-sided inner layer circuit substrate and using a hot press to press at 175-180°C and 1.8-2 MPa for 60-80 minutes to obtain a pressed laminated structure; using a laser device to perform layer-by-layer scanning treatment on the pressed laminated structure at a pulse energy of 0.4-0.5 mj to form a plurality of micropores to obtain a laminated structure with interlayer interconnected channels.

2. The method of manufacturing a notebook computer printed circuit board according to claim 1, wherein The resin is any one or a mixture of multiple of polyimide resin, epoxy resin or phenolic resin.

3. The method of manufacturing a notebook computer printed circuit board according to claim 1, wherein The nanoceramic filler is any one or a mixture of multiple of alumina, zirconia, silicon nitride, boron nitride or silicon carbide.

4. The method of manufacturing a notebook computer printed circuit board according to claim 1, wherein The step of etching the composite substrate according to a preset layout to obtain an inner layer circuit substrate comprises: coating a dry film photoresist on the surface of the composite substrate and heating at 90-100°C for 20-30 seconds to obtain a photoresist coated substrate; performing ultraviolet exposure treatment on the photoresist coated substrate according to a preset layout to obtain an exposed substrate; The exposed substrate is developed by a developing device using a 0.8% mass concentration potassium carbonate solution as a developing solution under constant temperature conditions of 20-25°C to obtain a patterned substrate; The patterned substrate is etched in an etching tank under constant temperature conditions of 30-32°C using a 2.0 mol / L acidic copper sulfate etching solution, first for 15-20 seconds, then for 25-30 seconds by reducing the flow rate of the etching solution to obtain a primary circuit substrate; The primary circuit substrate is subjected to a film removal treatment using a 3% sodium hydroxide solution as a film removal solution under conditions of 40-45°C to obtain an inner layer circuit substrate.

5. The method of manufacturing a notebook computer printed circuit board according to claim 1, wherein, The step of subjecting the laminated structure to a chemical plating treatment comprises: The laminated structure is immersed in a colloidal activation solution containing 0.02-0.03 mol / L palladium chloride and 0.1-0.15 mol / L tin chloride for activation treatment, so that palladium ions form catalytically active sites on the inner wall and surface of the micropores; The laminated structure after activation treatment is immersed in a chemical copper plating solution containing 0.05-0.06 mol / L copper sulfate, 0.1-0.15 mol / L formaldehyde and a complexing agent, and is reacted at 48-50°C for 15 minutes to obtain a seed layer structure; The seed layer structure is placed in an electroplating bath containing 0.2 to 0.3 mol / L copper sulfate, 0.5 to 0.6 mol / L sulfuric acid and an additive, at a current density of 1.8 to 2 A / dm 2 for 50 to 60 minutes at 25 to 30 °C to obtain a conductive stack structure.

6. The method of manufacturing a notebook computer printed circuit board according to claim 1, wherein The step of etching the outer surface of the laminated structure according to a predetermined circuit pattern to form an outer layer circuit structure comprises: A photoresist containing nano-silicon dioxide particles is coated on the outer surface of the laminated structure, and is baked at 90-95°C for 5-10 minutes to obtain a photoresist covering structure; The photoresist covering structure is subjected to etching treatment using a 3.0 mol / L ferric chloride etching solution in an etching tank under constant temperature conditions of 35-40°C to obtain a preliminary outer layer structure; The preliminary outer layer structure is subjected to a photoresist removal treatment using a 5% potassium hydroxide solution as a photoresist removal solution under conditions of 50-55°C to obtain an outer layer circuit structure.

7. The method of manufacturing a notebook computer printed circuit board according to claim 1, wherein The step of coating a solder resist ink on the outer layer circuit structure to form a solder resist layer to obtain a notebook computer printed circuit board comprises: A solder resist ink is coated on the surface of the outer layer circuit structure, and the solder resist ink contains nano-alumina particles, a photosensitizer and a toughening agent to obtain an initial solder resist coating layer; The initial solder resist coating layer is subjected to ultraviolet exposure treatment using an ultraviolet light source to obtain a patterned solder resist coating layer; After the patterned solder resist coating layer is subjected to developing treatment using an alkaline developing solution, low-temperature curing treatment is performed at 90-100°C for 10-15 minutes to obtain the notebook computer printed circuit board.

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