2T0C storage unit, preparation method thereof and 2T0C storage array

Abstract

The invention discloses a 2T0C storage unit, a preparation method thereof and a 2T0C storage array. The 2T0C storage unit comprises a gate stack, a source stack, a drain stack and an active region stack, the gate stack comprises a vertically-through first gate, and a second gate dielectric layer and a second semiconductor thin film layer which wrap the first gate in sequence; the source electrode stack comprises a vertically-through second source electrode, and a third semiconductor thin film layer and a third gate dielectric layer which wrap the second source electrode in sequence; the drain electrode stack comprises a second drain electrode which is through up and down, and a fourth semiconductor film layer and a fourth gate dielectric layer which wrap the second drain electrode in sequence; the active region stack comprises a first insulating layer, a second insulating layer, a first conductor layer, a first gate dielectric layer, a first semiconductor film layer, a third insulating layer, a first source electrode, a fourth insulating layer and a fifth insulating layer. According to the invention, the problem that 3D vertical stacking integration is difficult to carry out on the 2T0C storage unit is solved.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular to a 2T0C memory cell and a preparation method thereof, and a 2T0C memory array. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a volatile, dynamically refreshed, destructive write and read semiconductor memory. Conventional DRAM memory cells consist of a single transistor and a single capacitor, known as the 1T1C (1Transistor1Capacitor) DRAM cell design. As memory products continue to evolve toward higher capacity and higher density, the number of capacitors in conventional DRAM arrays has increased dramatically, while device size has decreased significantly. These changes have placed demands on capacitor scalability, which is difficult to achieve with conventional DRAM process scaling.

[0003] Currently, there is a 2T0C (2Transistor 0Capacitor) DRAM cell structure design that uses two transistors to form the memory cell instead of capacitors. In this DRAM cell design, the first transistor is responsible for write operations, and the second transistor is responsible for read operations. The drain of the first transistor is connected to the gate of the second transistor. This 2T0C DRAM cell architecture eliminates the presence of capacitors in the memory cell, overcoming a series of issues that arise with conventional DRAM memory cells during process scaling. Furthermore, the transistors in this DRAM cell use indium gallium zinc oxide (IGZO) as the channel layer material. The channel layers of the two transistors and the connection between them serve as the cell's storage node, replacing the capacitor structure of conventional DRAM cells. This design makes the DRAM memory cell's read operation more controllable, eliminating the need for destructive reads, and reduces cell leakage, giving the cell the advantages of long retention time and ease of scaling.

[0004] However, the current 2T0C-DRAM cell structure still has some issues that hinder its manufacturing and application. One concern is the asymmetric connection between the two transistors in the cell structure—the drain of the write transistor is connected to the gate of the read transistor. This connection makes it difficult to adjust the transistor channel structure and implement 3D stacking integration. This hinders the high-density application and performance optimization of 2T0C-DRAM. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a 2T0C memory cell and a method for manufacturing the same, and a 2T0C memory array, so as to solve the problem that 2T0C memory cells are difficult to integrate in 3D vertical stacking.

[0006] The technical solutions of the present invention are as follows:

[0007] A 2T0C memory cell comprises a gate stack, a source stack, a drain stack, and an active region stack surrounding the gate stack, the source stack, and the drain stack;

[0008] The gate stack includes: a first gate, a second gate dielectric layer, and a second semiconductor thin film layer; the first gate is vertically connected, and the second gate dielectric layer and the second semiconductor thin film layer sequentially wrap the first gate from the inside to the outside;

[0009] The source electrode stack comprises: a second source electrode, a third semiconductor thin film layer and a third gate dielectric layer; the second source electrode is vertically connected, and the third semiconductor thin film layer and the third gate dielectric layer sequentially wrap the second source electrode from the inside to the outside;

[0010] The drain stack comprises: a second drain, a fourth semiconductor thin film layer and a fourth gate dielectric layer; the second drain is through-through, and the fourth semiconductor thin film layer and the fourth gate dielectric layer sequentially wrap the second drain from the inside to the outside;

[0011] The active area stack includes: a first insulating layer, a second insulating layer, a first conductor layer, a first gate dielectric layer, a first semiconductor thin film layer, a third insulating layer, a first source, a fourth insulating layer and a fifth insulating layer; the second insulating layer and the first conductor layer are located above the first insulating layer and are connected to the first insulating layer; the first gate dielectric layer and the first semiconductor thin film layer are located between the source stack and the drain stack, and are stacked on the first conductor layer from bottom to top; the third insulating layer is located above the second insulating layer, the first conductor layer, the first gate dielectric layer and the first semiconductor thin film layer and is connected to the second insulating layer, the first conductor layer, the first gate dielectric layer and the first semiconductor thin film layer; the first source and the fourth insulating layer are located above the third insulating layer and are connected to the third insulating layer; the fifth insulating layer is located above the first source and the fourth insulating layer and is connected to the first source and the fourth insulating layer.

[0012] Optionally, the first gate has a circular cross-section, comprises a first exposed section, a first transition section, and a first middle section, the first exposed section and the first middle section being connected by the first transition section, the second gate dielectric layer and the second semiconductor thin film layer sequentially wrapping the first middle section and the first transition section from the inside out, and being symmetrically distributed about the central axis of the first gate; the diameter of the first middle section is larger than the diameter of the first exposed section;

[0013] The second source electrode has a circular cross-section, comprises a second exposed section, a second transition section, and a second middle section, the second exposed section and the second middle section being connected by the second transition section, the third semiconductor thin film layer and the third gate dielectric layer sequentially wrapping the second middle section and the second transition section from the inside out, and being symmetrically distributed about the central axis of the second source electrode; the diameter of the second middle section is larger than the diameter of the second exposed section;

[0014] The cross-section of the second drain is circular, and the second drain includes a third exposed section, a third transition section and a third middle section. The third exposed section and the third middle section are connected by the third transition section. The fourth semiconductor thin film layer and the fourth gate dielectric layer sequentially wrap the second middle section and the second transition section from the inside to the outside, and are axially symmetrically distributed with the central axis of the second drain; the diameter of the third middle section is larger than the diameter of the third exposed section.

[0015] Optionally, the upper and lower directions of the first middle section, the second middle section and the third middle section are parallel; the second insulating layer, the first conductor layer, the first gate dielectric layer, the first semiconductor thin film layer, the third insulating layer, the first source electrode and the fourth insulating layer are arranged within the upper and lower directions of the first middle section, the second middle section and the third middle section.

[0016] Optionally, the first insulating layer and the fifth insulating layer cover the first exposed section, the second exposed section, the third exposed section, the first middle section, the second middle section and the third middle section.

[0017] Optionally, the first gate dielectric layer is connected to the third gate dielectric layer and the fourth gate dielectric layer, and the first semiconductor thin film layer is connected to the third semiconductor thin film layer and the fourth semiconductor thin film layer; the thickness of the first gate dielectric layer is greater than the thickness of the first semiconductor thin film layer.

[0018] Optionally, the first conductor layer is arranged around the gate stack, the source stack and the drain stack, and is connected to the second semiconductor thin film layer, the third gate dielectric layer and the fourth gate dielectric layer; the second insulating layer is not connected to the gate stack, the source stack and the drain stack; the fourth insulating layer is arranged around the source stack and the drain stack, and is connected to the third gate dielectric layer and the fourth gate dielectric layer, and is not connected to the gate stack; the first source is arranged around the gate stack, and is connected to the second semiconductor thin film layer, and is not connected to the source stack and the drain stack.

[0019] Optionally, the thicknesses of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer are the same, the thickness of the first semiconductor thin film layer is greater than the thicknesses of the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer, and the thicknesses of the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer are the same.

[0020] Optionally, the thickness of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer is less than or equal to the thickness of the first semiconductor thin film layer, the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer; the thickness of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer is greater than or equal to half the thickness of the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer.

[0021] Optionally, the thickness of the first source electrode and the fourth insulating layer is the same; the thickness of the second insulating layer, the first conductor layer, the third insulating layer, the first source electrode and the fourth insulating layer are all greater than or equal to 5 times the thickness of the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer.

[0022] Optionally, the minimum distance between the source stack and the drain stack is greater than or equal to 5 times the thickness of the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer; the minimum distance between the gate stack and any one of the source stack or the drain stack is greater than or equal to 2 times the minimum distance between the source stack and the drain stack.

[0023] Optionally, the second source and the second drain have the same shape; the second gate dielectric layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer have the same shape; the second semiconductor thin film layer, the third gate dielectric layer and the fourth gate dielectric layer have the same shape.

[0024] The present invention also provides a method for preparing a 2TOC memory cell, comprising the following steps:

[0025] Providing a semiconductor substrate, forming a first insulating layer on the surface of the semiconductor substrate, and covering the upper surface of the first insulating layer with a second insulating layer;

[0026] forming a first opening on the surface of the second insulating layer and passing through the second insulating layer vertically, and forming a first conductor layer in the first opening and completely filling the first opening;

[0027] forming a first gate dielectric layer and a first semiconductor thin film layer in sequence on the surface of the first conductor layer, wherein the first gate dielectric layer partially covers the upper surface of the first conductor layer, and the first semiconductor thin film layer partially covers the upper surface of the first gate dielectric layer;

[0028] forming a third insulating layer on the surfaces of the first conductor layer, the first gate dielectric layer and the first semiconductor thin film layer, wherein the third insulating layer completely covers the upper surfaces of the first conductor layer, the first gate dielectric layer and the first semiconductor thin film layer;

[0029] forming a first source electrode on the surface of the third insulating layer, the first source electrode completely covering the upper surface of the third insulating layer; forming a second opening on the surface of the first source electrode, the second opening penetrating the first source electrode from top to bottom, and forming a fourth insulating layer in the second opening, the fourth insulating layer completely filling the second opening;

[0030] forming a fifth insulating layer on the surface of the first source electrode and the fourth insulating layer, the fifth insulating layer completely covering the upper surface of the first source electrode and the fourth insulating layer; forming a third opening on the surface of the fifth insulating layer, the third opening being located inside the first conductor layer and the first source electrode, and penetrating vertically through the fifth insulating layer, the first source electrode, the third insulating layer, the first conductor layer, and the first insulating layer;

[0031] Etching the third insulating layer in the middle of the third opening to form a fourth opening, wherein the fourth opening surrounds the third opening, the central axis of the fourth opening is consistent with the central axis of the third opening, and the fourth opening vertically penetrates the third insulating layer; etching the first insulating layer, the first conductor layer, the third insulating layer, the first source electrode, and the fifth insulating layer with the fourth opening as the starting point to form a fifth opening, wherein the fifth opening surrounds the third opening, the central axis of the fifth opening is consistent with the central axis of the third opening, and the fifth opening vertically penetrates the first conductor layer, the third insulating layer, and the first source electrode, but does not penetrate the first insulating layer and the fifth insulating layer;

[0032] forming a second semiconductor thin film layer on the surfaces of the third opening, the fourth opening, and the fifth opening, wherein the second semiconductor thin film layer covers all surfaces of the third opening, the fourth opening, and the fifth opening, and the thickness on the surfaces of the fourth opening and the fifth opening is greater than the thickness on the surface of the third opening; etching a portion of the second semiconductor thin film layer, wherein the second semiconductor thin film layer covers all surfaces of the fourth opening and the fifth opening;

[0033] forming a second gate dielectric layer on the surface of the second semiconductor thin film layer and the third opening, wherein the second gate dielectric layer covers all surfaces of the second semiconductor thin film layer and the third opening, and the thickness on the surface of the second semiconductor thin film layer is greater than the thickness on the surface of the third opening; etching the second gate dielectric layer so that the second gate dielectric layer covers the surface of the second semiconductor thin film layer;

[0034] Filling the third opening, the fourth opening, and the fifth opening to form a first gate, wherein the first gate covers the side surfaces of the first insulating layer and the fifth insulating layer and the exposed surface of the second gate dielectric layer;

[0035] forming a sixth opening and a seventh opening on the surface of the fifth insulating layer, the sixth opening and the seventh opening being located inside the first conductor layer and the fourth insulating layer, and vertically penetrating the fifth insulating layer, the fourth insulating layer, the third insulating layer, the first gate dielectric layer, the first conductor layer, and the first insulating layer, but not penetrating the first semiconductor thin film layer;

[0036] Etching the third insulating layer in the sixth opening to form an eighth opening, and etching the third insulating layer in the seventh opening to form a ninth opening, wherein the eighth opening surrounds the sixth opening, and its central axis is aligned with the central axis of the sixth opening, and vertically penetrates the third insulating layer; and the ninth opening surrounds the seventh opening, and its central axis is aligned with the central axis of the seventh opening, and vertically penetrates the third insulating layer;

[0037] The first insulating layer, the first conductor layer, the first gate dielectric layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are etched starting from the eighth opening and the ninth opening to form a tenth opening and an eleventh opening, wherein the tenth opening surrounds the sixth opening and has a central axis that is consistent with the central axis of the sixth opening, and vertically penetrates the first conductor layer, the first gate dielectric layer, the third insulating layer, and the fourth insulating layer, but does not penetrate the first insulating layer, the first semiconductor thin film layer, and the fifth insulating layer; and the eleventh opening surrounds the seventh opening and has a central axis that is consistent with the central axis of the seventh opening, and vertically penetrates the first conductor layer, the first gate dielectric layer, the third insulating layer, and the fourth insulating layer, but does not penetrate the first insulating layer, the first semiconductor thin film layer, and the fifth insulating layer.

[0038] A third gate dielectric layer is formed on the surfaces of the first semiconductor thin film layer, the sixth opening, the eighth opening, and the tenth opening, and a fourth gate dielectric layer is formed on the surfaces of the first semiconductor thin film layer, the seventh opening, the ninth opening, and the eleventh opening, wherein the third gate dielectric layer covers a portion of the exposed surface of the first semiconductor thin film layer and all surfaces of the sixth opening, the eighth opening, and the tenth opening, and the thickness at the surfaces of the eighth opening and the tenth opening is greater than the thickness at the surfaces of the first semiconductor thin film layer and the sixth opening; the fourth gate dielectric layer covers a portion of the exposed surface of the first semiconductor thin film layer and all surfaces of the seventh opening, the ninth opening, and the eleventh opening, and the thickness at the surfaces of the ninth opening and the eleventh opening is greater than the thickness at the surfaces of the first semiconductor thin film layer and the seventh opening;

[0039] Etching the third gate dielectric layer and the fourth gate dielectric layer so that the third gate dielectric layer covers all surfaces of the eighth opening and the tenth opening, and the fourth gate dielectric layer covers all surfaces of the ninth opening and the eleventh opening;

[0040] forming a third semiconductor thin film layer on the surface of the first semiconductor thin film layer, the third gate dielectric layer, and the sixth opening, and forming a fourth semiconductor thin film layer on the surface of the first semiconductor thin film layer, the fourth gate dielectric layer, and the seventh opening, wherein the third semiconductor thin film layer covers a portion of the exposed surface of the first semiconductor thin film layer and all surfaces of the third gate dielectric layer and the sixth opening, and a thickness on the surface of the third gate dielectric layer is greater than a thickness on the surface of the first semiconductor thin film layer and the sixth opening, and the fourth semiconductor thin film layer covers a portion of the exposed surface of the first semiconductor thin film layer and all surfaces of the fourth gate dielectric layer and the seventh opening, and a thickness on the surface of the fourth gate dielectric layer is greater than a thickness on the surface of the first semiconductor thin film layer and the seventh opening;

[0041] Etching the first semiconductor thin film layer, the third semiconductor thin film layer, and the fourth semiconductor thin film layer so that the third semiconductor thin film layer covers the surface of the third gate dielectric layer, and the fourth semiconductor thin film layer covers the surface of the fourth gate dielectric layer; and the side surfaces of the first semiconductor thin film layer at the eighth opening and the ninth opening are flush with the surfaces of the third semiconductor thin film layer and the fourth semiconductor thin film layer, respectively;

[0042] The sixth opening, the eighth opening and the tenth opening are filled to form a second source, and the seventh opening, the ninth opening and the eleventh opening are filled to form a second drain. The second source covers part of the side surfaces of the first insulating layer and the fifth insulating layer, part of the exposed surface of the first semiconductor thin film layer and the entire exposed surface of the third semiconductor thin film layer. The second drain covers part of the side surfaces of the first insulating layer and the fifth insulating layer, part of the exposed surface of the first semiconductor thin film layer and the entire exposed surface of the fourth semiconductor thin film layer.

[0043] The present invention further provides a 2T0C memory array comprising a plurality of the above-described 2T0C memory cells.

[0044] The technical solution of the present invention, through the above-described structural design, can construct a properly functioning 2TOC memory cell having a write transistor gate region and channel layer, as well as a read transistor channel layer and source / drain region. Furthermore, the vertically continuous design of the first gate, second source, and second drain enables the 2TOC memory cell of this solution to be capable of 3D stacking, thereby improving the 3D stacking capabilities of multiple 2TOC memory cells of this solution, thereby enhancing overall storage integration and read / write efficiency, and reducing the complexity of peripheral circuits. The larger diameters of the first, second, and third middle sections ensure that the semiconductor thin film layers and gate dielectric layers in the gate stack, source stack, and drain stack are manufactured according to ideal shapes, while also increasing the contact area between portions of the semiconductor thin film layer and gate dielectric layer and the first conductor layer, first gate dielectric layer, first semiconductor thin film layer, and first source, thereby preventing transistor damage due to disconnection. This improves the transmission stability of the transistor's source, drain, and channel layer, thereby enhancing the stability of the storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0046] Figure 1FIG. 1 is a schematic structural diagram of an embodiment of a 2T0C memory cell according to the present invention.

[0047] Figure 2 FIG. 1 is a schematic structural diagram of a manufacturing process of an embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0048] Figure 3 FIG. 1 is a schematic structural diagram of the manufacturing process of another embodiment of the method for preparing a 2TOC memory cell of the present invention.

[0049] Figure 4 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0050] Figure 5 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0051] Figure 6 FIG. 1 is a schematic structural diagram of the manufacturing process of another embodiment of the method for preparing a 2TOC memory cell of the present invention.

[0052] Figure 7 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0053] Figure 8 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0054] Figure 9 FIG. 1 is a schematic structural diagram of the manufacturing process of another embodiment of the method for preparing a 2TOC memory cell of the present invention.

[0055] Figure 10 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0056] Figure 11 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0057] Figure 12 FIG. 1 is a schematic structural diagram of the manufacturing process of another embodiment of the method for preparing a 2TOC memory cell of the present invention.

[0058] Figure 13 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0059] Figure 14 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0060] Figure 15FIG. 1 is a schematic structural diagram of the manufacturing process of another embodiment of the method for preparing a 2TOC memory cell of the present invention.

[0061] Figure 16 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0062] Figure 17 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0063] Figure 18 FIG. 1 is a schematic structural diagram of the manufacturing process of another embodiment of the method for preparing a 2TOC memory cell of the present invention.

[0064] Figure 19 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0065] Figure 20 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0066] Figure 21 FIG. 1 is a schematic structural diagram of the manufacturing process of another embodiment of the method for preparing a 2TOC memory cell of the present invention.

[0067] Figure 22 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0068] Figure 23 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0069] Figure 24 FIG. 1 is a schematic structural diagram of the manufacturing process of another embodiment of the method for preparing a 2TOC memory cell of the present invention.

[0070] Figure 25 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0071] Figure 26 FIG. 1 is a schematic structural diagram of a manufacturing process of another embodiment of a method for preparing a 2TOC memory cell according to the present invention.

[0072] Figure 27 FIG. 1 is a schematic structural diagram of the manufacturing process of another embodiment of the method for preparing a 2TOC memory cell of the present invention.

[0073] Figure 28 FIG. 1 is a schematic structural diagram of an embodiment of a 2T0C memory array according to the present invention.

[0074] Explanation of the accompanying drawings: 101, first insulating layer; 102, second insulating layer; 103, first conductor layer; 104, first gate dielectric layer; 105, first semiconductor thin film layer; 106, third insulating layer; 107, first source electrode; 108, fourth insulating layer; 109, fifth insulating layer; 201, second gate dielectric layer; 202, second semiconductor thin film layer; 203, third semiconductor thin film layer; 204, third gate dielectric layer; 205, fourth semiconductor thin film layer; 206, fourth gate dielectric layer; 207, first gate electrode; 208, second source electrode; 209, second drain electrode. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0076] In the embodiments and patent claims, unless otherwise specified herein, the words "a," "an," "the," and "the" may include plural forms. If the embodiments of the present invention include descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features.

[0077] It should be further understood that the term "comprising" as used in the description of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" as used herein can include wireless connections or wireless couplings. The term "and / or" as used herein includes all or any units and all combinations of one or more associated listed items.

[0078] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0079] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0080] Dynamic Random Access Memory (DRAM) is a volatile, dynamically refreshed, destructive write and read semiconductor memory. Conventional DRAM memory cells consist of a single transistor and a single capacitor, known as the 1T1C (1Transistor1Capacitor) DRAM cell design. As memory products continue to evolve toward higher capacity and higher density, the number of capacitors in conventional DRAM arrays has increased dramatically, while device size has decreased significantly. These changes have placed demands on capacitor scalability, which is difficult to achieve with conventional DRAM process scaling.

[0081] Currently, there is a 2T0C (2Transistor0Capacitor) DRAM cell structure design that eliminates the use of capacitors and instead utilizes two transistors to form the memory cell. In this DRAM cell design, the first transistor is responsible for write operations, while the second transistor is responsible for read operations. The drain of the first transistor is connected to the gate of the second transistor. This 2T0C DRAM cell architecture eliminates the presence of capacitors in the memory cell, overcoming a series of issues that arise with conventional DRAM memory cells during process scaling. Furthermore, the transistors in this DRAM cell use indium gallium zinc oxide (IGZO) as the channel layer material. The channel layers of the two transistors and the connection between them serve as the cell's storage node, replacing the capacitor structure of conventional DRAM cells. This design makes the DRAM cell's read operation more controllable, eliminating the need for destructive reads, and reduces cell leakage, resulting in long retention times and ease of scaling.

[0082] However, the current 2T0C-DRAM cell structure still has some issues that hinder its manufacturing and application. One concern is the asymmetric connection between the two transistors in the cell structure—the drain of the write transistor is connected to the gate of the read transistor. This connection makes it difficult to adjust the transistor channel structure and implement 3D stacking integration. This hinders the high-density application and performance optimization of 2T0C-DRAM.

[0083] Furthermore, 2T0C-DRAM memory cells require more wire connections and a more complex connection method. This leads to more significant potential for sneak current and voltage drop when forming a 2T0C-DRAM memory array, resulting in the device lacking ideal read power consumption and accuracy. Furthermore, the complex structure of 2T0C-DRAM memory cells and the asymmetric connection between the two transistors make further 3D integration of these memory cells difficult, limiting their further application and process optimization.

[0084] To solve the above problems, the present invention proposes a 2T0C memory cell.

[0085] Reference Figure 1 In one embodiment, the 2T0C memory cell includes a gate stack, a source stack, a drain stack, and an active region stack surrounding the gate stack, the source stack, and the drain stack;

[0086] The gate stack includes: a first gate 207, a second gate dielectric layer 201, and a second semiconductor thin film layer 202; the first gate 207 is continuous from top to bottom, and the second gate dielectric layer 201 and the second semiconductor thin film layer 202 sequentially wrap the first gate 207 from inside to outside;

[0087] The source stack includes: a second source electrode 208, a third semiconductor thin film layer 203 and a third gate dielectric layer 204; the second source electrode 208 is through-through, and the third semiconductor thin film layer 203 and the third gate dielectric layer 204 sequentially wrap the second source electrode 208 from the inside to the outside;

[0088] The drain stack includes: a second drain electrode 209, a fourth semiconductor thin film layer 205 and a fourth gate dielectric layer 206; the second drain electrode 209 is continuous from top to bottom, and the fourth semiconductor thin film layer 205 and the fourth gate dielectric layer 206 sequentially wrap the second drain electrode 209 from inside to outside;

[0089] The active area stack includes: a first insulating layer 101, a second insulating layer 102, a first conductor layer 103, a first gate dielectric layer 104, a first semiconductor thin film layer 105, a third insulating layer 106, a first source 107, a fourth insulating layer 108 and a fifth insulating layer 109; the second insulating layer 102 and the first conductor layer 103 are located above the first insulating layer 101 and connected to the first insulating layer 101; the first gate dielectric layer 104 and the first semiconductor thin film layer 105 are located between the source stack and the drain stack, and are stacked in sequence from bottom to top above the first conductor layer 103; the third insulating layer 106 and the first source 107 are located above the first conductor layer 108 ... Layer 106 is located above the second insulating layer 102, the first conductor layer 103, the first gate dielectric layer 104 and the first semiconductor thin film layer 105 and is connected to the second insulating layer 102, the first conductor layer 103, the first gate dielectric layer 104 and the first semiconductor thin film layer 105; the first source 107 and the fourth insulating layer 108 are located above the third insulating layer 106 and are connected to the third insulating layer 106; the fifth insulating layer 109 is located above the first source 107 and the fourth insulating layer 108 and is connected to the first source 107 and the fourth insulating layer 108.

[0090] Further, refer to Figure 1 In one embodiment, the cross-section of the first gate 207 is circular. The first gate 207 includes a first exposed section, a first transition section, and a first middle section. The first exposed section and the first middle section are connected by the first transition section. The second gate dielectric layer 201 and the second semiconductor thin film layer 202 sequentially wrap the first middle section and the first transition section from the inside to the outside, and are symmetrically distributed about the central axis of the first gate 207. The diameter of the first middle section is larger than the diameter of the first exposed section.

[0091] The second source electrode 208 has a circular cross-section and includes a second exposed section, a second transition section, and a second middle section. The second exposed section and the second middle section are connected by the second transition section. The third semiconductor thin film layer 203 and the third gate dielectric layer 204 sequentially wrap the second middle section and the second transition section from the inside out and are symmetrically distributed about the central axis of the second source electrode 208. The diameter of the second middle section is larger than the diameter of the second exposed section.

[0092] The second drain electrode 209 has a circular cross-section and includes a third exposed section, a third transition section, and a third middle section. The third exposed section and the third middle section are connected by the third transition section. The fourth semiconductor thin film layer 205 and the fourth gate dielectric layer 206 sequentially wrap the second middle section and the second transition section from the inside out and are symmetrically distributed about the central axis of the second drain electrode 209. The diameter of the third middle section is larger than the diameter of the third exposed section.

[0093] The first middle section, the second middle section, and the third middle section are vertically parallel; the second insulating layer 102, the first conductor layer 103, the first gate dielectric layer 104, the first semiconductor thin film layer 105, the third insulating layer 106, the first source electrode 107, and the fourth insulating layer 108 are arranged within the vertical range of the first middle section, the second middle section, and the third middle section;

[0094] The first insulating layer 101 and the fifth insulating layer 109 cover the first exposed section, the second exposed section, the third exposed section, the first middle section, the second middle section, and the third middle section;

[0095] The first gate dielectric layer 104 is connected to the third gate dielectric layer 204 and the fourth gate dielectric layer 206 , and the first semiconductor thin film layer 105 is connected to the third semiconductor thin film layer 203 and the fourth semiconductor thin film layer 205 ; the thickness of the first gate dielectric layer 104 is greater than that of the first semiconductor thin film layer 105 .

[0096] In this embodiment, the first gate 207, the second source 208, and the second drain 209 can be designed to pass through the entire memory cell structure from top to bottom, and have a circular cross-section, so that multiple 2T0C memory cells can be easily stacked and connected. In the gate stack, the first exposed section of the first gate 207 can be divided into two sections, upper and lower, and the first transition section can also be divided into two sections, upper and lower. The upper section of the first exposed section is connected to the first middle section through the upper section of the first transition section, and the lower section of the first exposed section is connected to the first middle section through the lower section of the first transition section. For details, please refer to Figure 1The first exposed section of the first gate 207 is the portion of the first gate 207 that is not enclosed by the third semiconductor thin film layer 203 and the third gate dielectric layer 204. The cross-sectional diameter of the first middle section is greater than the cross-sectional diameter of the first exposed section, and the cross-sectional diameter of the first exposed section increases from the upper and lower sections to the diameter of the first middle section. The portion with the increased diameter is the first transition section. The design of the second exposed section, the second transition section, and the second middle section of the second source 208, as well as the design of the third exposed section, the third transition section, and the third middle section of the second drain 209 can all refer to the first gate 207 and will not be described in detail here. In addition, the first middle section, the second middle section, and the third middle section are located on the same horizontal plane, the first exposed section, the second exposed section, and the third exposed section are located on the same horizontal plane, and the first transition section, the second transition section, and the third transition section are located on the same horizontal plane.

[0097] In the structure of the active area stack, the first insulating layer 101 is located at the bottom of the active area stack; in the direction perpendicular to the horizontal plane, the upper surfaces of the second insulating layer 102 and the first conductive layer 103 coincide with the bottom of the first middle section, the bottom of the second middle section, and the bottom of the third middle section and are included in the sections, the second insulating layer 102 is not in contact with the gate stack, the source stack, and the drain stack, and the first conductive layer 103 includes the gate stack, the source stack, and the drain stack in the horizontal direction and is respectively connected to the second semiconductor thin film layer 202, the second middle section, and the third middle section. The third gate dielectric layer 204 and the fourth gate dielectric layer 206 partially contact each other on their sides, and the second insulating layer 102 extends in the horizontal direction; the first gate dielectric layer 104 and the first semiconductor thin film layer 105 are located between the source stack and the drain stack, and are stacked sequentially from bottom to top above the first conductor layer 103; the first semiconductor thin film layer 105 contacts the upper surface of the first gate dielectric layer 104, penetrates the third gate dielectric layer 204 and the fourth gate dielectric layer 206, and connects the third semiconductor thin film layer 203 and the fourth semiconductor thin film layer 205. It should be noted that Figure 1This is a cross-sectional view of a 2T0C memory cell. In the direction perpendicular to the cross-section, the width of the first gate dielectric layer 104 is consistent with the width of the source stack and the drain stack, and the width of the first semiconductor thin film layer 105 is smaller than the width of the first gate dielectric layer 104. In this way, the first semiconductor thin film layer 105 does not separate the third gate dielectric layer 204 and the fourth gate dielectric layer 206 from top to bottom. The third insulating layer 106 is located above the second insulating layer 102, the first conductor layer 103, the first gate dielectric layer 104 and the first semiconductor thin film layer 105 and contacts the exposed upper surfaces of the second insulating layer 102, the first conductor layer 103, the first gate dielectric layer 104 and the first semiconductor thin film layer 105. The third insulating layer 106 is included in the first middle section, the second middle section and the third middle section in the direction perpendicular to the horizontal plane. The third insulating layer 106 includes the gate stack, the source stack and the drain stack in the horizontal direction and contacts part of the side surfaces of the second semiconductor thin film layer 202, the third gate dielectric layer 204 and the fourth gate dielectric layer 206 respectively.

[0098] The first source 107 and the fourth insulating layer 108 are located above the third insulating layer 106 and in contact with the upper surface of the third insulating layer 106. The upper surfaces of the first source 107 and the fourth insulating layer 108 are located on the same horizontal plane. In the direction perpendicular to the horizontal plane, the upper surfaces of the first source 107 and the fourth insulating layer 108 coincide with the tops of the first middle segment, the second middle segment and the third middle segment, and are included in the segments. The first source 107 includes the gate stack in the horizontal direction and contacts part of the side surface of the second semiconductor thin film layer 202. The fourth insulating layer 108 includes the source stack and the drain stack in the horizontal direction and contacts part of the side surfaces of the third gate dielectric layer 204 and the fourth gate dielectric layer 206, respectively. The first source 107 can extend in the horizontal direction.

[0099] The fifth insulating layer 109 is located above the first source electrode 107 and the fourth insulating layer 108 and contacts the upper surfaces of the first source electrode 107 and the fourth insulating layer 108. The fifth insulating layer 109 is located at the top of the active area stack and vertically includes the first exposed segment, the second exposed segment, the upper segments of the third exposed segment, and the first transition segment, the second transition segment, and the upper segments of the third transition segment. In the horizontal plane, the portion formed by the second insulating layer 102, the first conductive layer 103, the first gate dielectric layer 104, the first semiconductor thin film layer 105, the third insulating layer 106, the first source electrode 107, and the fourth insulating layer 108 is coplanar with the first middle segment, the second middle segment, and the third middle segment and does not contact the first gate electrode 207, the second source electrode 208, and the second drain electrode 209. It should be noted that the third insulating layer 106 can be made of a different material from the other insulating layers to meet the manufacturing process requirements for some etching steps in the gate stack, source stack, and drain stack, as well as the semiconductor thin film layer and gate dielectric layer.

[0100] In the 2T0C memory cell, the first gate 207 is a write word line, the second source 208 is a read word line, the second drain 209 is a read bit line, and the first source 107 is a write bit line. The write word line, the read word line, and the read bit line extend in a direction perpendicular to the horizontal plane; the write bit line extends in the left and right directions of the cross section.

[0101] In addition, the first gate 207, the second source 208 and the second drain 209 are all axially symmetrically distributed with respect to the central axis, and the diameters of the first exposed section, the second exposed section and the third exposed section are the same, and the diameters of the first middle section, the second middle section and the third middle section are the same; in the first transition section, the second transition section and the third transition section, taking the first gate 207 as an example, the slope from the diameter of the first exposed section to the diameter of the first middle section is moderate, that is, the vertical distance from the top of the first middle section to the bottom of the upper section of the first exposed section and from the bottom of the first middle section to the top of the lower section of the first exposed section is not less than 100 nm, and the difference between the diameter of the first middle section and the diameters of the upper and lower sections of the first exposed section is not less than 200 nm.

[0102] The technical solution of the present invention, through the above-described structural design, can construct a properly functioning 2TOC memory cell having a write transistor gate region and channel layer, as well as a read transistor channel layer and source / drain region. Furthermore, the vertically continuous design of the first gate 207, the second source 208, and the second drain 209 enables the 2TOC memory cell of this solution to be capable of 3D stacking, thereby improving the 3D stacking capability of multiple 2TOC memory cells of this solution, thereby enhancing overall storage integration and read / write efficiency, and reducing the complexity of peripheral circuits. The larger diameters of the first, second, and third middle sections ensure that the semiconductor thin film layers and gate dielectric layers in the gate stack, source stack, and drain stack are manufactured in an ideal shape, while also increasing the contact area between some semiconductor thin film layers and gate dielectric layers and the first conductor layer 103, the first gate dielectric layer 104, the first semiconductor thin film layer 105, and the first source 107, thereby preventing transistor damage due to disconnection. This improves the transmission stability of the transistor's source, drain, and channel layers, thereby enhancing the stability of the storage system.

[0103] Therefore, this solution replaces the partial planar structure of the original 2T0C memory cell with a gate stack, source stack, and drain stack, forming a vertical channel layer and a through-hole portion of the gate, source, and drain, thereby increasing the device density horizontally. It should also be noted that in conventional 2T0C-DRAM memory arrays, each memory cell must be electrically connected to all word and bit lines. This results in a large number of electrical connection points on a line distributing a certain amount of voltage, resulting in a drop in the operating voltage of the memory cell at the end of the line. Furthermore, the four word and bit lines occupy a large amount of space and are prone to interference, especially when 3D stacking is used. This solution embeds the circuits directly into the memory structure, with the first gate 207 serving as the write word line, the second source 208 as the read word line, the second drain 209 as the read bit line, and the first source 107 as the write bit line. This eliminates the need for separate electrical connections and eliminates interference between different circuits.

[0104] In addition, refer to Figure 1 In one embodiment, the second gate dielectric layer 201 and the second semiconductor thin film layer 202 in the gate stack cover the first transition section of the first gate 207, and the thickness gradually decreases from the first middle section to the upper and lower sections of the first exposed section; the third semiconductor thin film layer 203 and the third gate dielectric layer 204 in the source stack cover the second transition section of the second source 208, and the thickness gradually decreases from the second middle section to the upper and lower sections of the second exposed section; the fourth semiconductor thin film layer 205 and the fourth gate dielectric layer 206 in the drain stack cover the third transition section, and the thickness gradually decreases from the third middle section to the upper and lower sections of the third exposed section; the thinner areas of the first gate 207, the second source 208 and the second drain 209, namely the first exposed section, the second exposed section, and the third exposed section, have a diameter range of 100-200 nm.

[0105] This embodiment, through the above-described structural design, ensures the proper operation of the gate stack, source stack, and drain stack. The transition section dimensions are designed to prevent direct contact between the first gate 207 and the first source 107, and between the first gate 207, the second source 208, and the second drain 209 and the first conductor layer 103. This ensures the proper operation of the transistors in the 2TOC memory cell and prevents short circuits from preventing the cell from performing normal read and write operations. Reducing the thickness of the corresponding semiconductor thin film layers and gate dielectric layers in the gate stack, source stack, and drain stack is a corresponding etching step in the process flow.

[0106] Reference Figure 1In one embodiment, the first conductor layer 103 is arranged around the gate stack, the source stack and the drain stack, and is connected to the second semiconductor thin film layer 202, the third gate dielectric layer 204 and the fourth gate dielectric layer 206; the second insulating layer 102 is not connected to the gate stack, the source stack and the drain stack; the fourth insulating layer 108 is arranged around the source stack and the drain stack, and is connected to the third gate dielectric layer 204 and the fourth gate dielectric layer 206, and is not connected to the gate stack; the first source 107 is arranged around the gate stack and is connected to the second semiconductor thin film layer 202, and is not connected to the source stack and the drain stack.

[0107] In this embodiment, the minimum distance between the boundary of the third gate dielectric layer 204 and the boundary of the fourth gate dielectric layer 206 is not less than 100 nm, and the minimum distance between the boundary of the second semiconductor thin film layer 202 and the boundary of the third gate dielectric layer 204 or the fourth gate dielectric layer 206 is not less than 200 nm; in the horizontal plane direction, the shape of the first conductor layer 103 completely includes the gate stack, the source stack and the drain stack, and all boundaries do not touch the middle boundary of the gate stack, the source stack and the drain stack; in the horizontal direction, the shape of the first source 107 completely includes the gate stack and all boundaries do not touch the middle boundary of the gate stack, the shape of the fourth insulating layer 108 completely includes the source stack and the drain stack, and all boundaries of the fourth insulating layer 108 do not touch the source stack. The middle sections of the stack and the drain stack are in contact with each other, and the distances from the contact surfaces of the first source 107 and the fourth insulating layer 108 to the boundaries of the gate stack and the source stack are not less than 100 nm; without considering the first gate dielectric layer 104 and the first semiconductor thin film layer 105, the thicknesses of the second insulating layer 102, the first conductor layer 103, the third insulating layer 106, the first source 107 and the fourth insulating layer 108 are all the same; the first insulating layer 101 and the fifth insulating layer 109 completely cover the upper and lower sections of the exposed sections of the gate stack, source stack and drain stack as well as the transition section, so that the second gate dielectric layer 201, the second semiconductor thin film layer 202, the third semiconductor thin film layer 203, the third gate dielectric layer 204, the fourth semiconductor thin film layer 205 and the fourth gate dielectric layer 206 are not exposed.

[0108] It should be noted that the present application, through the above-described structural design, can construct an active region stack that can function properly, so that the gate stack, source stack, and drain stack can normally transmit data with other parts of the memory cell, thereby normally completing the operation of the write transistor, storage node, and read transistor of the 2TOC memory cell. In addition, the source stack, drain stack, and gate stack do not need to be arranged on the same straight line. This solution only arranges the three on a straight line for the convenience of illustrating the structure. In actual applications, the positional relationship of the various parts of the gate stack, source stack, and drain stack in the planar direction can be changed according to the needs of improving arrangement efficiency and facilitating process operation. It is only necessary to ensure the positional relationship between the source stack and drain stack and the connection relationship between the first gate dielectric layer 104, the first semiconductor thin film layer 105, and the first conductor layer 103 and the gate stack, source stack, and drain stack. Specifically, the drain stack can be moved along an arc with the source stack as the center, while maintaining a certain distance from the gate stack (this distance is not less than the distance between the gate stack and the source stack).

[0109] In one embodiment, the first gate dielectric layer 104, the second gate dielectric layer 201, the third gate dielectric layer 204, and the fourth gate dielectric layer 206 have the same thickness; the first semiconductor thin film layer 105 has a thickness greater than that of the second semiconductor thin film layer 202, the third semiconductor thin film layer 203, and the fourth semiconductor thin film layer 205; and the second semiconductor thin film layer 202, the third semiconductor thin film layer 203, and the fourth semiconductor thin film layer 205 have the same thickness;

[0110] The thickness of the first gate dielectric layer 104, the second gate dielectric layer 201, the third gate dielectric layer 204, and the fourth gate dielectric layer 206 is less than or equal to the thickness of the first semiconductor thin film layer 105, the second semiconductor thin film layer 202, the third semiconductor thin film layer 203, and the fourth semiconductor thin film layer 205; the thickness of the first gate dielectric layer 104, the second gate dielectric layer 201, the third gate dielectric layer 204, and the fourth gate dielectric layer 206 is greater than or equal to half the thickness of the second semiconductor thin film layer 202, the third semiconductor thin film layer 203, and the fourth semiconductor thin film layer 205;

[0111] The first source electrode 107 and the fourth insulating layer 108 have the same thickness; the thickness of the second insulating layer 102, the first conductive layer 103, the third insulating layer 106, the first source electrode 107 and the fourth insulating layer 108 are all greater than or equal to 5 times the thickness of the second semiconductor thin film layer 202, the third semiconductor thin film layer 203 and the fourth semiconductor thin film layer 205;

[0112] The minimum distance between the source stack and the drain stack is greater than or equal to 5 times the thickness of the second semiconductor thin film layer 202, the third semiconductor thin film layer 203, and the fourth semiconductor thin film layer 205; the minimum distance between the gate stack and either the source stack or the drain stack is greater than or equal to 2 times the minimum distance between the source stack and the drain stack;

[0113] The second source 208 and the second drain 209 have the same shape; the second gate dielectric layer 201, the third semiconductor thin film layer 203 and the fourth semiconductor thin film layer 205 have the same shape; the second semiconductor thin film layer 202, the third gate dielectric layer 204 and the fourth gate dielectric layer 206 have the same shape.

[0114] In this embodiment, the first gate dielectric layer 104, the second gate dielectric layer 201, the third gate dielectric layer 204, and the fourth gate dielectric layer 206 have the same thickness, ranging from 5 to 10 nm. The second semiconductor thin film layer 202, the third semiconductor thin film layer 203, and the fourth semiconductor thin film layer 205 have the same thickness, ranging from 10 to 20 nm. The thickness of the first semiconductor thin film layer 105 ranges from 20 to 30 nm. The thickness of the second insulating layer 102, the thicker regions of the first conductor layer 103, the third insulating layer 106, the first source electrode 107, and the thicker regions of the fourth insulating layer 108 range from 100 to 200 nm. Due to the influence of the first gate dielectric layer 104 and the first semiconductor thin film layer 105, the thickness of the thinner regions of the first conductor layer 103 and the thinner regions of the fourth insulating layer 108 (i.e., the regions horizontally overlapping with the first gate dielectric layer 104 and the first semiconductor thin film layer 105) is no less than 80 nm. Through the above-described structural design, this solution enables the write and read transistors of the 2TOC memory cell to function properly and transmit data, thereby ensuring the proper operation of the 2TOC memory cell. The first semiconductor thin film layer 105 has a greater thickness to ensure that during the subsequent deposition and etching of the second source electrode 208, the second drain electrode 209, the third gate dielectric layer 204, the fourth gate dielectric layer 206, the third semiconductor thin film layer 203, and the fourth semiconductor thin film layer 205, the first semiconductor thin film layer 105 maintains its shape within the etched space and does not lose its original shape due to excessive wear during the etching of the source, drain, and gate dielectric layers. The shape of the first gate electrode 207 may not be exactly the same as that of the second source electrode 208 and the second drain electrode 209, but the manufacturing process is essentially the same, resulting in similar shapes: tapered at the ends and thicker in the middle, with a transitional diameter from the ends to the middle. This conformal configuration ensures stable and consistent transistor performance in the 2TOC memory cell and reduces parameter setting issues in the process flow.

[0115] It should be noted that the insulating layer in this embodiment is a structure that fills the gaps between the various components of the 2TOC memory cell. It supports subsequent process flows, supports the various components of the memory cell, and provides electrical insulation between the various components and between different cells. Therefore, the first insulating layer 101, the second insulating layer 102, the fourth insulating layer 108, and the fifth insulating layer 109 can be made of any of ethyl silicate, phosphate glass, doped silica glass, borophosphosilicate glass, or silazane polymer ceramics. At least the first insulating layer 101 and the fifth insulating layer 109 should be made of the same material. The third insulating layer 106 should be made of silicon nitride to enable independent etching of this layer, thereby meeting the specific manufacturing process requirements of the 2TOC memory cell.

[0116] The gate, source, and drain are the terminals that make up the transistor and interact with the outside world for data. The gate controls the channel carrier density by applying a controllable electric field, the source is the inflow terminal for carriers, and the drain is the outflow terminal for carriers. Inside the 2T0C memory cell, the drain of the write transistor is directly connected to the gate of the read transistor. Therefore, the memory cell has a total of four data interaction terminals, namely the gate of the write transistor (i.e., the first gate 207 in this solution), the source of the write transistor (i.e., the first source 107 in this solution), the source of the read transistor (i.e., the second source 208 in this solution), and the drain of the read transistor (i.e., the second drain 209 in this solution). Therefore, the first source 107, the first gate 207, the second source 208, and the second drain 209 can each independently use one of the metals such as gold, platinum, tungsten, and nickel as a material.

[0117] The gate dielectric layer is primarily used to prevent leakage current between the gate and the semiconductor thin film layer due to the thinness of the semiconductor thin film layer. In this embodiment, the second gate dielectric layer 201 serves as the gate dielectric layer of the write transistor of the 2TOC memory cell, while the first gate dielectric layer 104, the third gate dielectric layer 204, and the fourth gate dielectric layer 206 are connected and serve as the gate dielectric layer of the read transistor. In this embodiment, the second gate dielectric layer 201 can be made of a metal oxide such as aluminum oxide, silicon oxide, or hafnium oxide, while the first gate dielectric layer 104, the third gate dielectric layer 204, and the fourth gate dielectric layer 206 can be made of the same metal oxide such as aluminum oxide, silicon oxide, or hafnium oxide.

[0118] Semiconductor thin film layers are key materials for the normal operation of transistors and for the storage of electrical signal data in memory cells. In this embodiment, the second semiconductor thin film layer 202 serves as the semiconductor thin film layer for the write transistor of the memory cell, while the first semiconductor thin film layer 105, the third semiconductor thin film layer 203, and the fourth semiconductor thin film layer 205 are connected and serve as the semiconductor thin film layer for the read transistor. In this embodiment, the second semiconductor thin film layer 202 can be made of one of indium gallium zinc oxide (IGZO) and indium tin oxide (ITO). The first semiconductor thin film layer 105, the third semiconductor thin film layer 203, and the fourth semiconductor thin film layer 205 can also be made of the same material.

[0119] The first conductive layer 103 is composed of the drain of the write transistor and the gate of the read transistor of the 2T0C memory cell and serves as the storage node of the 2T0C memory cell. When the 2T0C memory cell performs a read operation, it receives charge from the source of the write transistor and stores it between the channel layers of the write and read transistors, controlling the state of the channel layer of the read transistor during the read operation. In this embodiment, the first conductive layer 103 can be made of a metal such as gold, platinum, tungsten, or nickel.

[0120] In order to better illustrate the technical concept of the technical solution of the present invention, Figure 1 The working process of the 2TOC memory cell of the present invention is described with reference to the structural description in the above embodiment.

[0121] In the 2TOC memory cell of the present invention, the first conductive layer 103 serves as both the drain of the write transistor and the gate of the read transistor, and as the storage node for the data in the memory cell. By applying an electrical signal to the gate and source of the write transistor, the charge in the gate capacitance of the read transistor is changed, thereby affecting the resistance between the source and drain of the read transistor, thereby achieving the switching and differentiation of data "0" and "1". The specific principles are as follows:

[0122] Writing "1" process: applying a positive bias turn-on voltage (this voltage is greater than the threshold voltage VTH of the write transistor) to the first gate 207 (write word line) to turn on the write transistor, and applying a positive bias write voltage to the first source 107 (write bit line) to inject charge into the first conductor layer 103. After the charge injection is completed, the voltage applied to the first source 107 is removed, and a negative bias holding voltage is applied to the first gate 207 to suppress the leakage current that may occur in the write transistor due to the material properties of the semiconductor thin film layer. At this time, the charge injected into the first conductor layer 103 is discharged into the second semiconductor thin film layer 202 and the third semiconductor thin film layer 203. The read transistor semiconductor thin film layer composed of the thin film layer 203, the first semiconductor thin film layer 105, and the fourth semiconductor thin film layer 205 is separated from other conductive structures and serves as a storage node to store the "1" state. This portion of charge will slowly lose over time. When the charge amount decreases to a certain level, the storage node will lose the stored "1" state. At this time, the charge of the storage array needs to be refreshed to restore the charge storage state of the storage node. Compared with ordinary DRAM storage cells, this cycle is significantly longer, so the data retention capability and data refresh load are significantly better than those of ordinary DRAM storage cells.

[0123] Reading "1": A positive bias read voltage is applied to the second source 208 (read word line). Due to the presence of a certain charge in the first conductive layer 103, the read transistor remains in the open state, i.e., the fourth semiconductor thin film layer 205 remains open. At this time, current flows from the second source 208 through the fourth semiconductor thin film layer 205 to the second drain 209 (read bit line). A read current is obtained at the second drain 209. This current can be amplified and identified by the peripheral circuit to complete the "1" reading process.

[0124] Writing "0" process: a positive bias turn-on voltage (this voltage is greater than the threshold voltage VTH of the write transistor) is applied to the first gate 207 (write word line) to turn on the write transistor, and a negative bias write voltage is applied to the first source 107 (write bit line) to extract charge from the first conductor layer 103. After the charge extraction is completed, the voltage applied to the first source 107 is removed, and a negative bias hold voltage is applied to the first gate 207 (this is consistent with the writing "1" process only for the convenience of control settings). At this time, there is no charge in the first conductor layer 103, and it is used as a storage node to store the "0" state;

[0125] During the reading "0" process, a positive bias reading voltage is applied to the second source 208 (read word line). Since there is no charge in the first conductor layer 103, the reading transistor remains in the off state, that is, the fourth semiconductor thin film layer 205 remains closed. At this time, the current cannot flow from the second source 208 to the second drain 209 (read bit line) through the fourth semiconductor thin film layer 205, that is, there is no reading current at the second drain 209. The reading "0" process is then completed after being recognized by the peripheral circuit.

[0126] The present invention also provides a method for preparing a 2TOC memory cell.

[0127] In one embodiment, a method for manufacturing a 2TOC memory cell includes the following steps:

[0128] S1. Set up a semiconductor substrate, form a first insulating layer 101 on the surface of the semiconductor substrate, and cover the upper surface of the first insulating layer 101 with a second insulating layer 102; the specific preparation process can refer to Figure 2 and Figure 3 .

[0129] S2, forming a first opening on the surface of the second insulating layer 102 that passes through the second insulating layer 102, and forming a first conductor layer 103 in the first opening that completely fills the first opening; the specific preparation process can refer to Figure 4 and Figure 5 .

[0130] S3, forming a first gate dielectric layer 104 and a first semiconductor thin film layer 105 in sequence on the surface of the first conductor layer 103, wherein the first gate dielectric layer 104 partially covers the upper surface of the first conductor layer 103, and the first semiconductor thin film layer 105 partially covers the upper surface of the first gate dielectric layer 104; the specific preparation process can be referred to Figure 6 .

[0131] S4, forming a third insulating layer 106 on the surface of the first conductor layer 103, the first gate dielectric layer 104 and the first semiconductor thin film layer 105, wherein the third insulating layer 106 completely covers the upper surface of the first conductor layer 103, the first gate dielectric layer 104 and the first semiconductor thin film layer 105; the specific preparation process can be referred to Figure 7 .

[0132] S5, forming a first source electrode 107 on the surface of the third insulating layer 106, wherein the first source electrode 107 completely covers the upper surface of the third insulating layer 106; forming a second opening on the surface of the first source electrode 107, wherein the second opening passes through the first source electrode 107 from top to bottom, and forming a fourth insulating layer 108 in the second opening, wherein the fourth insulating layer 108 completely fills the second opening; the specific preparation process can be referred to Figure 8 、 Figure 9 and Figure 10 .

[0133] S6, forming a fifth insulating layer 109 on the surface of the first source 107 and the fourth insulating layer 108, wherein the fifth insulating layer 109 completely covers the upper surface of the first source 107 and the fourth insulating layer 108; forming a third opening on the surface of the fifth insulating layer 109, wherein the third opening is located inside the first conductor layer 103 and the first source 107, and passes through the fifth insulating layer 109, the first source 107, the third insulating layer 106, the first conductor layer 103 and the first insulating layer 101; the specific preparation process can be referred to Figure 11 and Figure 12 .

[0134] S7. Etch the third insulating layer 106 in the middle of the third opening to form a fourth opening, the fourth opening surrounds the third opening and the central axis is consistent with the central axis of the third opening, and passes through the third insulating layer 106 from top to bottom; take the fourth opening as the starting point to etch the first insulating layer 101, the first conductor layer 103, the third insulating layer 106, the first source 107 and the fifth insulating layer 109 to form a fifth opening, the fifth opening surrounds the third opening and the central axis is consistent with the central axis of the third opening, and passes through the first conductor layer 103, the third insulating layer 106 and the first source 107 from top to bottom, but does not pass through the first insulating layer 101 and the fifth insulating layer 109; the specific preparation process can be referred to Figure 13 and Figure 14 .

[0135] S8, forming a second semiconductor thin film layer 202 on the surfaces of the third opening, the fourth opening and the fifth opening, wherein the second semiconductor thin film layer 202 covers all surfaces of the third opening, the fourth opening and the fifth opening, and the thickness on the surfaces of the fourth opening and the fifth opening is greater than the thickness on the surface of the third opening; etching a portion of the second semiconductor thin film layer 202, wherein the second semiconductor thin film layer 202 covers all surfaces of the fourth opening and the fifth opening; the specific preparation process can be referred to Figure 15 and Figure 16 .

[0136] S9, forming a second gate dielectric layer 201 on the surface of the second semiconductor thin film layer 202 and the third opening, wherein the second gate dielectric layer 201 covers all surfaces of the second semiconductor thin film layer 202 and the third opening, and the thickness on the surface of the second semiconductor thin film layer 202 is greater than the thickness on the surface of the third opening; etching the second gate dielectric layer 201 so that the second gate dielectric layer 201 covers the surface of the second semiconductor thin film layer 202; the specific preparation process can be referred to Figure 17 and Figure 18 .

[0137] S10, filling the third opening, the fourth opening and the fifth opening to form a first gate 207, the first gate 207 covers the side surfaces of the first insulating layer 101 and the fifth insulating layer 109 and the exposed surface of the second gate dielectric layer 201; the specific preparation process can refer to Figure 19 .

[0138] S11, forming a sixth opening and a seventh opening on the surface of the fifth insulating layer 109, wherein the sixth opening and the seventh opening are located inside the first conductor layer 103 and the fourth insulating layer 108, and penetrate the fifth insulating layer 109, the fourth insulating layer 108, the third insulating layer 106, the first gate dielectric layer 104, the first conductor layer 103 and the first insulating layer 101 from top to bottom, but do not penetrate the first semiconductor thin film layer 105; the specific preparation process can be referred to Figure 20 .

[0139] S12, etching the third insulating layer 106 in the sixth opening to form an eighth opening, etching the third insulating layer 106 in the seventh opening to form a ninth opening, the eighth opening surrounds the sixth opening and the central axis is consistent with the central axis of the sixth opening, and passes through the third insulating layer 106 from top to bottom, the ninth opening surrounds the seventh opening and the central axis is consistent with the central axis of the seventh opening, and passes through the third insulating layer 106 from top to bottom; the specific preparation process can be referred to Figure 21 .

[0140] S13. Taking the eighth opening and the ninth opening as starting points, the first insulating layer 101, the first conductor layer 103, the first gate dielectric layer 104, the third insulating layer 106, the fourth insulating layer 108 and the fifth insulating layer 109 are etched to form a tenth opening and an eleventh opening. The tenth opening surrounds the sixth opening and its central axis is consistent with the central axis of the sixth opening, and passes through the first conductor layer 103, the first gate dielectric layer 104, the third insulating layer 106 and the fourth insulating layer 108 from top to bottom, but does not pass through the first insulating layer 101, the first semiconductor thin film layer 105 and the fifth insulating layer 109. The eleventh opening surrounds the seventh opening and its central axis is consistent with the central axis of the seventh opening, and passes through the first conductor layer 103, the first gate dielectric layer 104, the third insulating layer 106 and the fourth insulating layer 108 from top to bottom, but does not pass through the first insulating layer 101, the first semiconductor thin film layer 105 and the fifth insulating layer 109. The specific preparation process can be referred to Figure 22 .

[0141] S14. A third gate dielectric layer 204 is formed on the surfaces of the first semiconductor thin film layer 105, the sixth opening, the eighth opening and the tenth opening, and a fourth gate dielectric layer 206 is formed on the surfaces of the first semiconductor thin film layer 105, the seventh opening, the ninth opening and the eleventh opening, wherein the third gate dielectric layer 204 covers a portion of the exposed surface of the first semiconductor thin film layer 105 and all surfaces of the sixth opening, the eighth opening and the tenth opening, and the thickness at the surfaces of the eighth opening and the tenth opening is greater than the thickness at the surfaces of the first semiconductor thin film layer 105 and the sixth opening, and the fourth gate dielectric layer 206 covers a portion of the exposed surface of the first semiconductor thin film layer 105 and all surfaces of the seventh opening, the ninth opening and the eleventh opening, and the thickness at the surfaces of the ninth opening and the eleventh opening is greater than the thickness at the surfaces of the first semiconductor thin film layer 105 and the seventh opening; the specific preparation process can be referred to Figure 23 .

[0142] S15, etching the third gate dielectric layer 204 and the fourth gate dielectric layer 206, so that the third gate dielectric layer 204 covers all surfaces of the eighth opening and the tenth opening, and the fourth gate dielectric layer 206 covers all surfaces of the ninth opening and the eleventh opening; the specific preparation process can be referred to Figure 24 .

[0143] S16. A third semiconductor thin film layer 203 is formed on the surface of the first semiconductor thin film layer 105, the third gate dielectric layer 204 and the sixth opening, and a fourth semiconductor thin film layer 205 is formed on the surface of the first semiconductor thin film layer 105, the fourth gate dielectric layer 206 and the seventh opening, wherein the third semiconductor thin film layer 203 covers a portion of the exposed surface of the first semiconductor thin film layer 105 and all surfaces of the third gate dielectric layer 204 and the sixth opening, and the thickness on the surface of the third gate dielectric layer 204 is greater than the thickness on the surface of the first semiconductor thin film layer 105 and the sixth opening, and the fourth semiconductor thin film layer 205 covers a portion of the exposed surface of the first semiconductor thin film layer 105 and all surfaces of the fourth gate dielectric layer 206 and the seventh opening, and the thickness on the surface of the fourth gate dielectric layer 206 is greater than the thickness on the surface of the first semiconductor thin film layer 105 and the seventh opening; the specific preparation process can be referred to Figure 25 .

[0144] S17, etching the first semiconductor thin film layer 105, the third semiconductor thin film layer 203 and the fourth semiconductor thin film layer 205, so that the third semiconductor thin film layer 203 covers the surface of the third gate dielectric layer 204, and the fourth semiconductor thin film layer 205 covers the surface of the fourth gate dielectric layer 206; the side surfaces of the first semiconductor thin film layer 105 at the eighth opening and the ninth opening are flush with the surfaces of the third semiconductor thin film layer 203 and the fourth semiconductor thin film layer 205 respectively; the specific preparation process can be referred to Figure 26 .

[0145] S18, filling the sixth opening, the eighth opening and the tenth opening to form a second source 208, filling the seventh opening, the ninth opening and the eleventh opening to form a second drain 209, the second source 208 covers part of the side surface of the first insulating layer 101 and the fifth insulating layer 109, part of the exposed surface of the first semiconductor thin film layer 105 and the entire exposed surface of the third semiconductor thin film layer 203, the second drain 209 covers part of the side surface of the first insulating layer 101 and the fifth insulating layer 109, part of the exposed surface of the first semiconductor thin film layer 105 and the entire exposed surface of the fourth semiconductor thin film layer 205. The specific preparation process can be referred to Figure 27 .

[0146] It should be noted that Figures 2 to 27 The manufacturing diagram shown in Figure 1 The basic spatial relationships of the 2T0C memory cell shown in the diagram are provided as a guide. This is primarily for the purpose of illustrating the structure and does not necessarily imply that the gate stack, source stack, and drain stack within the memory cell must be manufactured according to the illustrated spatial relationships. In actual applications, the planar relationships of the gate stack, source stack, and drain stack shown in the layout may be modified to improve layout efficiency and facilitate process operation.

[0147] The present invention also provides a 2T0C storage array.

[0148] Reference Figure 28 In one embodiment, a 2T0C memory array includes a plurality of 2T0C memory cells as described above.

[0149] In this embodiment, a 2T0C memory array comprises: a provided substrate and a newly added insulating layer above the substrate and below the memory cell array to prevent leakage from electrodes into the substrate; a plurality of 2T0C memory strings arranged in parallel in a horizontal direction; each 2T0C memory string comprising a plurality of 2T0C memory cells arranged in series perpendicular to the horizontal direction, wherein the first gate, second source, and second drain of the plurality of 2T0C memory cells are combined into a single structure. Vertical metal interconnects, respectively connected to the first gate, second source, and second drain of each topmost 2T0C memory cell, may be arranged between the 2T0C memory cells perpendicular to the cross-sectional direction and flush with the insulating layer in a plane aligned with the first source, thereby separating each row of 2T0C memory cells in the horizontal direction. The active area stack of the memory array may be provided with an extension portion, the extension portion being stepped, with each layer protruding progressively more from top to bottom, the extension portion consisting solely of the first source, the third insulating layer, and the second insulating layer, and the extension portion being used for metal interconnection. The memory array further includes vertical metal interconnects, each connected to a first source electrode in an extension of the active area stack of each memory array layer. The memory array further includes an insulating layer that fully encapsulates each of the vertical metal interconnects and the extension of the active area stack of each memory array layer. The first gate, second source, and second drain of the plurality of 2TOC memory cells are combined into a single structure. Specifically, this can be achieved through a manufacturing process where, after the stacking step of the multiple active areas is completed, an opening is formed that penetrates all of the stacks, thereby forming the first gate, second source, and second drain of the multi-layer array as a whole.

[0150] In one embodiment, the first insulating layer and the fifth insulating layer of two adjacent 2T0C memory cells in a 2T0C memory array are combined into a single structure, and their thicknesses can be adjusted appropriately to improve vertical space utilization of the memory array. The newly added insulating layer structure in the memory array should be made of the same material as the first and fifth insulating layers. All vertical metal interconnects are made of one of metals, such as gold, platinum, tungsten, and nickel.

[0151] In one embodiment, the 2T0C memory array further includes: a plurality of write word lines, write bit lines, read word lines, and read bit lines; wherein each write word line is formed by connecting all first gates in each memory string in series and is connected to an external circuit via a corresponding vertical metal interconnection device; each write bit line is formed by connecting all first sources in each row of memory cells in a horizontal direction in series and is connected to an external circuit via a corresponding vertical metal interconnection device; each read word line is formed by connecting all second sources in each memory string in series and is connected to an external circuit via a corresponding vertical metal interconnection device; and each read bit line is formed by connecting all second drains in each memory string in series and is connected to an external circuit via a corresponding vertical metal interconnection device.

[0152] It should be noted that the 2T0C memory array in this solution can be 3D integrated. The basic manufacturing process for 3D integration includes: providing a substrate; forming an insulating layer above the substrate; sequentially forming several layers of the 2T0C memory array above the insulating layer, wherein the fourth insulating layer and the insulating layer used to separate each row of memory cells in the horizontal direction can be formed in the same step. The first source electrode, the third insulating layer, and the second insulating layer in the active area must extend horizontally for a distance on one side; forming a protective layer above the completed 2T0C memory array and etching the extended portions of the first source electrode, the third insulating layer, and the second insulating layer. This step is repeated, gradually reducing the coverage of the protective layer from the boundary of the extended side toward the memory array area with each operation, thereby sequentially etching to form a stepped stack of active area extensions of the memory array layer; completing the formation of the remaining insulating layer; etching the insulating layer and forming all vertical metal interconnects. As such, the 2T0C memory array in this solution has high 3D integration potential, helping to achieve high storage density, low power consumption, and high read / write speeds.

[0153] It is understandable that, since the 2T0C memory array of the present invention uses the aforementioned 2T0C memory cell, the embodiments of the 2T0C memory array of the present invention include all technical solutions of all the embodiments of the aforementioned 2T0C memory cell, and the technical effects achieved are also identical, which will not be further elaborated here.

[0154] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A 2T0C memory cell, characterized in that: The device comprises a gate stack, a source stack, a drain stack, and an active region stack surrounding the gate stack, the source stack, and the drain stack; The gate stack includes: a first gate, a second gate dielectric layer, and a second semiconductor thin film layer; the first gate is vertically connected, and the second gate dielectric layer and the second semiconductor thin film layer sequentially wrap the first gate from the inside to the outside; The source electrode stack comprises: a second source electrode, a third semiconductor thin film layer and a third gate dielectric layer; the second source electrode is vertically connected, and the third semiconductor thin film layer and the third gate dielectric layer sequentially wrap the second source electrode from the inside to the outside; The drain stack comprises: a second drain, a fourth semiconductor thin film layer and a fourth gate dielectric layer; the second drain is through-through, and the fourth semiconductor thin film layer and the fourth gate dielectric layer sequentially wrap the second drain from the inside to the outside; The active area stack includes: a first insulating layer, a second insulating layer, a first conductor layer, a first gate dielectric layer, a first semiconductor thin film layer, a third insulating layer, a first source, a fourth insulating layer and a fifth insulating layer; the second insulating layer and the first conductor layer are located above the first insulating layer and are connected to the first insulating layer; the first gate dielectric layer and the first semiconductor thin film layer are located between the source stack and the drain stack, and are stacked on the first conductor layer from bottom to top; the third insulating layer is located above the second insulating layer, the first conductor layer, the first gate dielectric layer and the first semiconductor thin film layer and is connected to the second insulating layer, the first conductor layer, the first gate dielectric layer and the first semiconductor thin film layer; the first source and the fourth insulating layer are located above the third insulating layer and are connected to the third insulating layer; the fifth insulating layer is located above the first source and the fourth insulating layer and is connected to the first source and the fourth insulating layer.

2. The 2T0C memory cell according to claim 1, wherein: The first gate has a circular cross-section and includes a first exposed section, a first transition section, and a first middle section. The first exposed section and the first middle section are connected by the first transition section. The second gate dielectric layer and the second semiconductor thin film layer sequentially wrap the first middle section and the first transition section from the inside out and are symmetrically distributed about the central axis of the first gate. The diameter of the first middle section is larger than the diameter of the first exposed section. The second source electrode has a circular cross-section, comprises a second exposed section, a second transition section, and a second middle section, the second exposed section and the second middle section being connected by the second transition section, the third semiconductor thin film layer and the third gate dielectric layer sequentially wrapping the second middle section and the second transition section from the inside out, and being symmetrically distributed about the central axis of the second source electrode; the diameter of the second middle section is larger than the diameter of the second exposed section; The cross-section of the second drain is circular, and the second drain includes a third exposed section, a third transition section and a third middle section. The third exposed section and the third middle section are connected by the third transition section. The fourth semiconductor thin film layer and the fourth gate dielectric layer sequentially wrap the second middle section and the second transition section from the inside to the outside, and are axially symmetrically distributed with the central axis of the second drain; the diameter of the third middle section is larger than the diameter of the third exposed section.

3. The 2TOC memory cell according to claim 2, wherein: The first middle section, the second middle section and the third middle section are in parallel in the up-down direction; the second insulating layer, the first conductor layer, the first gate dielectric layer, the first semiconductor thin film layer, the third insulating layer, the first source electrode and the fourth insulating layer are arranged within the up-down direction range of the first middle section, the second middle section and the third middle section.

4. The 2TOC memory cell according to claim 2, wherein: The first insulating layer and the fifth insulating layer cover the first exposed segment, the second exposed segment, the third exposed segment, the first middle segment, the second middle segment, and the third middle segment.

5. The 2TOC memory cell according to claim 1 , wherein: The first gate dielectric layer is connected to the third gate dielectric layer and the fourth gate dielectric layer, and the first semiconductor thin film layer is connected to the third semiconductor thin film layer and the fourth semiconductor thin film layer; the thickness of the first gate dielectric layer is greater than that of the first semiconductor thin film layer.

6. The 2TOC memory cell according to claim 1, wherein: The first conductor layer is arranged around the gate stack, the source stack and the drain stack, and is connected to the second semiconductor thin film layer, the third gate dielectric layer and the fourth gate dielectric layer; The second insulating layer is not connected to the gate stack, the source stack and the drain stack; the fourth insulating layer is arranged around the source stack and the drain stack, and is connected to the third gate dielectric layer and the fourth gate dielectric layer, and is not connected to the gate stack; the first source is arranged around the gate stack and is connected to the second semiconductor thin film layer, and is not connected to the source stack and the drain stack.

7. The 2TOC memory cell according to claim 1, wherein: The thickness of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer are the same, the thickness of the first semiconductor thin film layer is greater than the thickness of the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer, and the thickness of the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer are the same.

8. The 2TOC memory cell according to claim 7, wherein: The thicknesses of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer, and the fourth gate dielectric layer are less than or equal to the thicknesses of the first semiconductor thin film layer, the second semiconductor thin film layer, the third semiconductor thin film layer, and the fourth semiconductor thin film layer; The thickness of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer is greater than or equal to half the thickness of the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer.

9. The 2TOC memory cell according to claim 1, wherein: The thickness of the first source electrode and the fourth insulating layer is the same; the thickness of the second insulating layer, the first conductor layer, the third insulating layer, the first source electrode and the fourth insulating layer are all greater than or equal to 5 times the thickness of the second semiconductor thin film layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer.

10. The 2TOC memory cell according to claim 1, wherein: The minimum distance between the source stack and the drain stack is greater than or equal to 5 times the thickness of the second semiconductor thin film layer, the third semiconductor thin film layer, and the fourth semiconductor thin film layer; A minimum distance between the gate stack and either the source stack or the drain stack is greater than or equal to twice a minimum distance between the source stack and the drain stack.

11. The 2TOC memory cell according to claim 1 , wherein: The second source electrode and the second drain electrode have the same shape; the second gate dielectric layer, the third semiconductor thin film layer and the fourth semiconductor thin film layer have the same shape; the second semiconductor thin film layer, the third gate dielectric layer and the fourth gate dielectric layer have the same shape.

12. A method for preparing a 2TOC memory cell, characterized in that: The following steps are involved: Providing a semiconductor substrate, forming a first insulating layer on the surface of the semiconductor substrate, and covering the upper surface of the first insulating layer with a second insulating layer; forming a first opening on the surface of the second insulating layer and passing through the second insulating layer vertically, and forming a first conductor layer in the first opening and completely filling the first opening; forming a first gate dielectric layer and a first semiconductor thin film layer in sequence on the surface of the first conductor layer, wherein the first gate dielectric layer partially covers the upper surface of the first conductor layer, and the first semiconductor thin film layer partially covers the upper surface of the first gate dielectric layer; forming a third insulating layer on the surfaces of the first conductor layer, the first gate dielectric layer and the first semiconductor thin film layer, wherein the third insulating layer completely covers the upper surfaces of the first conductor layer, the first gate dielectric layer and the first semiconductor thin film layer; forming a first source electrode on the surface of the third insulating layer, wherein the first source electrode completely covers the upper surface of the third insulating layer; forming a second opening on the surface of the first source electrode, the second opening penetrating the first source electrode from top to bottom, and forming a fourth insulating layer in the second opening, the fourth insulating layer completely filling the second opening; forming a fifth insulating layer on the surface of the first source electrode and the fourth insulating layer, wherein the fifth insulating layer completely covers the upper surface of the first source electrode and the fourth insulating layer; forming a third opening on the surface of the fifth insulating layer, wherein the third opening is located inside the first conductor layer and the first source electrode, and passes through the fifth insulating layer, the first source electrode, the third insulating layer, the first conductor layer, and the first insulating layer; Etching the third insulating layer in the middle of the third opening to form a fourth opening, wherein the fourth opening surrounds the third opening and has a central axis that is consistent with the central axis of the third opening, and passes through the third insulating layer from top to bottom; Etching the first insulating layer, the first conductive layer, the third insulating layer, the first source electrode, and the fifth insulating layer starting from the fourth opening to form a fifth opening, wherein the fifth opening surrounds the third opening and has a central axis aligned with the central axis of the third opening, and vertically penetrates the first conductive layer, the third insulating layer, and the first source electrode, but does not penetrate the first insulating layer and the fifth insulating layer; forming a second semiconductor thin film layer on the surfaces of the third opening, the fourth opening, and the fifth opening, wherein the second semiconductor thin film layer covers all surfaces of the third opening, the fourth opening, and the fifth opening, and the thickness of the second semiconductor thin film layer on the surfaces of the fourth opening and the fifth opening is greater than the thickness on the surface of the third opening; etching a portion of the second semiconductor thin film layer, where the second semiconductor thin film layer covers all surfaces of the fourth opening and the fifth opening; forming a second gate dielectric layer on the second semiconductor thin film layer and the surface of the third opening, wherein the second gate dielectric layer covers all surfaces of the second semiconductor thin film layer and the third opening, and the thickness of the second gate dielectric layer on the surface of the second semiconductor thin film layer is greater than the thickness on the surface of the third opening; etching the second gate dielectric layer so that the second gate dielectric layer covers the surface of the second semiconductor thin film layer; Filling the third opening, the fourth opening, and the fifth opening to form a first gate, wherein the first gate covers the side surfaces of the first insulating layer and the fifth insulating layer and the exposed surface of the second gate dielectric layer; forming a sixth opening and a seventh opening on the surface of the fifth insulating layer, the sixth opening and the seventh opening being located inside the first conductor layer and the fourth insulating layer, and vertically penetrating the fifth insulating layer, the fourth insulating layer, the third insulating layer, the first gate dielectric layer, the first conductor layer, and the first insulating layer, but not penetrating the first semiconductor thin film layer; Etching the third insulating layer in the sixth opening to form an eighth opening, and etching the third insulating layer in the seventh opening to form a ninth opening, wherein the eighth opening surrounds the sixth opening, and its central axis is aligned with the central axis of the sixth opening, and vertically penetrates the third insulating layer; and the ninth opening surrounds the seventh opening, and its central axis is aligned with the central axis of the seventh opening, and vertically penetrates the third insulating layer; The first insulating layer, the first conductor layer, the first gate dielectric layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are etched starting from the eighth opening and the ninth opening to form a tenth opening and an eleventh opening, wherein the tenth opening surrounds the sixth opening and has a central axis that is consistent with the central axis of the sixth opening, and vertically penetrates the first conductor layer, the first gate dielectric layer, the third insulating layer, and the fourth insulating layer, but does not penetrate the first insulating layer, the first semiconductor thin film layer, and the fifth insulating layer; and the eleventh opening surrounds the seventh opening and has a central axis that is consistent with the central axis of the seventh opening, and vertically penetrates the first conductor layer, the first gate dielectric layer, the third insulating layer, and the fourth insulating layer, but does not penetrate the first insulating layer, the first semiconductor thin film layer, and the fifth insulating layer. A third gate dielectric layer is formed on the surfaces of the first semiconductor thin film layer, the sixth opening, the eighth opening, and the tenth opening, and a fourth gate dielectric layer is formed on the surfaces of the first semiconductor thin film layer, the seventh opening, the ninth opening, and the eleventh opening, wherein the third gate dielectric layer covers a portion of the exposed surface of the first semiconductor thin film layer and all surfaces of the sixth opening, the eighth opening, and the tenth opening, and the thickness at the surfaces of the eighth opening and the tenth opening is greater than the thickness at the surfaces of the first semiconductor thin film layer and the sixth opening; the fourth gate dielectric layer covers a portion of the exposed surface of the first semiconductor thin film layer and all surfaces of the seventh opening, the ninth opening, and the eleventh opening, and the thickness at the surfaces of the ninth opening and the eleventh opening is greater than the thickness at the surfaces of the first semiconductor thin film layer and the seventh opening; Etching the third gate dielectric layer and the fourth gate dielectric layer so that the third gate dielectric layer covers all surfaces of the eighth opening and the tenth opening, and the fourth gate dielectric layer covers all surfaces of the ninth opening and the eleventh opening; forming a third semiconductor thin film layer on the surface of the first semiconductor thin film layer, the third gate dielectric layer, and the sixth opening, and forming a fourth semiconductor thin film layer on the surface of the first semiconductor thin film layer, the fourth gate dielectric layer, and the seventh opening, wherein the third semiconductor thin film layer covers a portion of the exposed surface of the first semiconductor thin film layer and all surfaces of the third gate dielectric layer and the sixth opening, and a thickness on the surface of the third gate dielectric layer is greater than a thickness on the surface of the first semiconductor thin film layer and the sixth opening, and the fourth semiconductor thin film layer covers a portion of the exposed surface of the first semiconductor thin film layer and all surfaces of the fourth gate dielectric layer and the seventh opening, and a thickness on the surface of the fourth gate dielectric layer is greater than a thickness on the surface of the first semiconductor thin film layer and the seventh opening; Etching the first semiconductor thin film layer, the third semiconductor thin film layer, and the fourth semiconductor thin film layer so that the third semiconductor thin film layer covers the surface of the third gate dielectric layer, and the fourth semiconductor thin film layer covers the surface of the fourth gate dielectric layer; The side surfaces of the first semiconductor thin film layer at the eighth opening and the ninth opening are flush with the surfaces of the third semiconductor thin film layer and the fourth semiconductor thin film layer respectively; The sixth opening, the eighth opening and the tenth opening are filled to form a second source, and the seventh opening, the ninth opening and the eleventh opening are filled to form a second drain. The second source covers part of the side surfaces of the first insulating layer and the fifth insulating layer, part of the exposed surface of the first semiconductor thin film layer and the entire exposed surface of the third semiconductor thin film layer. The second drain covers part of the side surfaces of the first insulating layer and the fifth insulating layer, part of the exposed surface of the first semiconductor thin film layer and the entire exposed surface of the fourth semiconductor thin film layer.

13. A 2T0C storage array, characterized in that: The device comprises a plurality of 2T0C memory cells according to any one of claims 1 to 12.

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