Semiconductor structure and forming method thereof
By introducing a stress buffer layer into the bit line structure and controlling its stress gradient, the defect problem that the bit line structure is prone to cause in the process technology is solved, and the product yield is improved.
Patent Information
- Application Number
- CN202510899503.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-30
- Publication Date
- 2025-10-03
AI Technical Summary
The bit line structure is prone to structural defects during the manufacturing process, resulting in low product yield.
A stress buffer layer is formed on the first conductive layer, wherein the stress of the stress buffer layer increases sequentially from the side close to the substrate to the side away from the substrate, and a conductive material layer is filled after forming a contact groove by etching, and finally the top surface of the conductive material layer is made flush with the top surface of the first conductive layer.
Effectively disperse and release thermal and mechanical stresses during the process, reduce the risk of cracking of the conductive layer, reduce structural defects, and improve product yield.
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Figure CN120751701A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] Memory is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and fast transmission speed. Bit lines are critical components in memory. However, due to manufacturing process limitations, they are prone to structural defects, resulting in low product yield.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention
[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can reduce structural defects and improve product yield.
[0005] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:
[0006] forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate and a first conductive layer formed on the substrate, the substrate comprising a plurality of active regions spaced apart;
[0007] forming a stress buffer layer on the first conductive layer, wherein the stress of at least a portion of the stress buffer layer increases sequentially in a direction perpendicular to the surface of the substrate and from a side close to the substrate to a side away from the substrate;
[0008] Etching the stress buffer layer, the first conductive layer, and the active area to form a contact groove;
[0009] forming a conductive material layer on a side of the stress buffer layer away from the substrate, wherein the conductive material layer fills the contact groove;
[0010] The conductive material layer on top of the stress buffer layer is removed, and the top surface of the conductive material layer in the contact groove is flush with the top surface of the first conductive layer, and the remaining conductive material layer is used as the second conductive layer.
[0011] In an exemplary embodiment of the present disclosure, forming a stress buffer layer on the first conductive layer, wherein the stress of at least a portion of the stress buffer layer increases sequentially in a direction perpendicular to the surface of the substrate and from a side close to the substrate to a side away from the substrate, includes:
[0012] forming a first sub-stress buffer layer on the first conductive layer, wherein the stress of the first sub-stress buffer layer is a first stress value;
[0013] forming a second sub-stress buffer layer on the first sub-stress buffer layer, wherein the stress of the second sub-stress buffer layer increases in a direction perpendicular to the surface of the substrate and from a side close to the substrate to a side away from the substrate, and a minimum value of the stress in the second sub-stress buffer layer is greater than or equal to the first stress value;
[0014] A third sub-stress buffer layer is formed on the second sub-stress buffer layer, wherein the stress of the third sub-stress buffer layer is a second stress value, and the second stress value is greater than or equal to the maximum stress value of the second sub-stress buffer layer.
[0015] In an exemplary embodiment of the present disclosure, the first stress value is 0.8 GPa to 1 GPa; and / or the second stress value is 1.2 GPa to 1.5 GPa.
[0016] In an exemplary embodiment of the present disclosure, the thickness of the first sub-stress buffer layer is 9nm to 11nm; and / or the thickness of the second sub-stress buffer layer is 1.5nm to 3.5nm; and / or the thickness of the third sub-stress buffer layer is 19nm to 21nm.
[0017] In an exemplary embodiment of the present disclosure, the materials of the first sub-stress buffer layer, the second sub-stress buffer layer and the third sub-stress buffer layer are all silicon carbide nitride, the nitrogen content of the first sub-stress buffer layer is higher than the maximum nitrogen content of the second sub-stress buffer layer and / or the nitrogen content of the third sub-stress buffer layer; the carbon content of the third sub-stress buffer layer is higher than the maximum carbon content of the second sub-stress buffer layer and / or the carbon content of the first sub-stress buffer layer; in a direction perpendicular to the surface of the substrate, and in a direction from a side close to the substrate to a side away from the substrate, the nitrogen content in the second sub-stress buffer layer decreases successively, and the carbon content in the second sub-stress buffer layer increases successively.
[0018] In an exemplary embodiment of the present disclosure, the nitrogen content of the first sub-stress buffer layer is 35at% to 40at%; and / or, the carbon content of the first sub-stress buffer layer is 9at% to 10at%; and / or, the nitrogen content of the third sub-stress buffer layer is 8at% to 10at%; and / or, the carbon content of the third sub-stress buffer layer is 15at% to 25at%.
[0019] In an exemplary embodiment of the present disclosure, removing the conductive material layer located on top of the stress buffer layer and making the top surface of the conductive material layer located in the contact groove flush with the top surface of the first conductive layer includes:
[0020] performing preliminary etching on the conductive material layer so that the conductive material layer is flush with the surface of the stress buffer layer away from the substrate;
[0021] The conductive material layer remaining after the preliminary etching is further etched so that a top surface of the conductive material layer remaining after the further etching is flush with a top surface of the first conductive layer.
[0022] In an exemplary embodiment of the present disclosure, the forming method further includes:
[0023] After forming the second conductive layer, the stress buffer layer is removed.
[0024] In an exemplary embodiment of the present disclosure, the forming method further includes:
[0025] After removing the stress buffer layer, forming a bit line material layer on the surface of the structure formed by the first conductive layer and the second conductive layer;
[0026] The bit line material layer, the first conductive layer, and the second conductive layer are etched to form a bit line.
[0027] In an exemplary embodiment of the present disclosure, before forming the conductive material layer, the forming method further includes:
[0028] forming a protective layer on the sidewall of the contact groove, and filling the contact groove with the protective layer with the conductive material layer;
[0029] When removing the stress buffer layer, removing the protective layer located on the sidewall portion of the contact groove surrounded by the stress buffer layer;
[0030] The bit line material layer is formed on a surface of a structure formed by the first conductive layer, the second conductive layer and the remaining protective layer;
[0031] When etching the bit line material layer, the first conductive layer, and the second conductive layer, the remaining protection layer is removed.
[0032] In an exemplary embodiment of the present disclosure, pores are formed in the first conductive layer in a direction from the side wall of the first conductive layer to the central axis of the first conductive layer, or no pores are formed in the first conductive layer in a direction from the side wall of the first conductive layer to the central axis of the first conductive layer.
[0033] In an exemplary embodiment of the present disclosure, after the stress buffer layer is removed, no cracks are formed on the surface of the first conductive layer.
[0034] According to one aspect of the present disclosure, a semiconductor structure is provided, wherein the semiconductor structure is formed by any one of the above-mentioned methods for forming a semiconductor structure.
[0035] The semiconductor structure and its formation method disclosed herein form a stress buffer layer on the first conductive layer, and the stress in at least a portion of the stress buffer layer increases sequentially in a direction from the side close to the substrate to the side away from the substrate. This allows for the effective dispersion and release of thermal and mechanical stresses generated during the process by a stress gradient transition during the removal of the conductive material layer located on top of the stress buffer layer and alignment of the top surface of the conductive material layer located within the contact groove with the top surface of the first conductive layer. This reduces the risk of cracking of the first conductive layer due to stress concentration during the manufacturing process (particularly during the etching step of the conductive material layer). Furthermore, the stress buffer layer provides a stable stress state during the manufacturing process, effectively reducing the phenomenon of insufficient local removal of the conductive material layer due to stress anomalies, deformation of the stress buffer layer, or damage (cracks, fragments) to the first conductive layer, thereby helping to reduce structural defects and improve product yield.
[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.
[0038] Figure 1 Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.
[0039] Figure 2 Schematic diagram of an initial semiconductor structure in an embodiment of the present disclosure.
[0040] Figure 3 FIG. 1 is a schematic diagram of an initial semiconductor structure and a stress buffer layer in an embodiment of the present disclosure.
[0041] Figure 4 FIG. 1 is a schematic diagram of an initial semiconductor structure and a stress buffer layer in another embodiment of the present disclosure.
[0042] Figure 5Schematic diagram of a contact groove in one embodiment of the present disclosure.
[0043] Figure 6 Schematic diagram of a conductive material layer in one embodiment of the present disclosure.
[0044] Figure 7 Schematic diagram of the structure after step S150 is completed in one embodiment of the present disclosure.
[0045] Figure 8 3 is a schematic diagram of a structure after step S310 is completed in one embodiment of the present disclosure.
[0046] Figure 9 Schematic diagram of the structure after the stress buffer layer is removed in one embodiment of the present disclosure.
[0047] Figure 10 4 is a schematic diagram of a structure after step S410 is completed in one embodiment of the present disclosure.
[0048] Figure 11 4 is a schematic diagram of a structure after step S420 is completed in one embodiment of the present disclosure.
[0049] Figure 12 This is a schematic diagram of the structure before removing the protective layer on the bottom surface of the contact groove in one embodiment of the present disclosure.
[0050] Figure 13 Schematic diagram of the structure of the protection layer and the bit line material layer in one embodiment of the present disclosure.
[0051] Description of reference numerals:
[0052] 1. Initial semiconductor structure; 11. Substrate; 111. Active area; 112. Trench isolation structure; 12. First conductive layer; 13. Insulating layer; 131. First insulating layer; 132. Second insulating layer; 101. Contact groove; 2. Stress buffer layer; 21. First sub-stress buffer layer; 22. Second sub-stress buffer layer; 23. Third sub-stress buffer layer; 3. Second conductive layer; 310. Conductive material layer; 4. Bit line; 410. Bit line material layer; 411. First material layer; 412. Second material layer; 413. Third material layer; 5. Protective layer. DETAILED DESCRIPTION
[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
[0054] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.
[0055] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.
[0056] The bitline is one of the core components of a memory device. It primarily consists of a first portion located on top of the active area and connected to the active area via a bitline contact structure, and a second portion located on top of a shallow trench isolation structure between the active areas. The first portion, the second portion, and the bitline contact structure all include a conductive layer. The conductive layer of the first portion is in contact and communication with the conductive layer in the bitline contact structure. During the manufacturing process, a first conductive material layer is first formed to form the conductive layer corresponding to the second portion. The first conductive material layer is then etched to form a contact portion that exposes the active area. Finally, a second conductive material layer is formed within the contact portion to form the conductive layer corresponding to the first portion. However, when forming the second conductive material layer, the stress generated during the manufacturing process can easily cause defects such as cracks to appear within the previously deposited first conductive material layer, thereby affecting the etching performance of the second conductive material layer and causing the second conductive material layer to be under-etched. At the same time, after the contact portion is formed, the sidewalls of the first conductive material layer are exposed and easily damaged by the residual etching gas, resulting in pores; the subsequently deposited bit line material (such as titanium nitride) easily fills the pores, causing a short circuit between the bit line and the subsequently manufactured capacitor or between the bit lines, resulting in a low product yield.
[0057] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, the forming method includes steps S110 to S150, wherein:
[0058] Step S110 , forming an initial semiconductor structure, the initial semiconductor structure including a substrate and a first conductive layer formed on the substrate, the substrate including a plurality of active regions spaced apart;
[0059] Step S120, forming a stress buffer layer on the first conductive layer, wherein the stress in at least a portion of the stress buffer layer increases sequentially in a direction perpendicular to the surface of the substrate and from a side close to the substrate to a side away from the substrate;
[0060] Step S130 , etching the stress buffer layer, the first conductive layer, and the active region to form contact trenches;
[0061] Step S140 , forming a conductive material layer on a side of the stress buffer layer away from the substrate, wherein the conductive material layer fills the contact groove;
[0062] Step S150 , removing the conductive material layer on top of the stress buffer layer, and making the top surface of the conductive material layer in the contact groove flush with the top surface of the first conductive layer, and using the remaining conductive material layer as the second conductive layer.
[0063] The method for forming a semiconductor structure disclosed herein forms a stress buffer layer on the first conductive layer, and the stress in at least a portion of the stress buffer layer increases sequentially in a direction from the side close to the substrate to the side away from the substrate. This allows for the thermal and mechanical stresses generated during the process to be effectively dispersed and released through a stress gradient transition during the removal of the conductive material layer located on top of the stress buffer layer and alignment of the top surface of the conductive material layer located within the contact groove with the top surface of the first conductive layer. This reduces the risk of cracking of the first conductive layer due to stress concentration during the manufacturing process (particularly during the etching step of the conductive material layer). Furthermore, the stress buffer layer provides a stable stress state during the manufacturing process, effectively reducing the phenomenon of insufficient local removal of the conductive material layer due to stress anomalies, deformation of the stress buffer layer, or damage (cracks, fragments) to the first conductive layer, thereby helping to reduce structural defects and improve product yield.
[0064] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:
[0065] like Figure 1 As shown, in step S110 , an initial semiconductor structure is formed. The initial semiconductor structure includes a substrate and a first conductive layer formed on the substrate. The substrate includes a plurality of active regions distributed at intervals.
[0066] The substrate 11 may include a base and a trench isolation structure 112. The base may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is imposed on the shape and material of the base.
[0067] In some embodiments of the present disclosure, Figure 2 As shown, the substrate may be a silicon substrate having a trench isolation structure 112 formed therein. The trench isolation structure 112 may be formed by forming a trench in the substrate and then filling the trench with an isolation material layer. The material of the trench isolation structure 112 may include silicon nitride or silicon oxide, etc., which are not particularly limited herein. The trench isolation structure 112 can separate multiple active areas 111 on the substrate.
[0068] In some embodiments of the present disclosure, the substrate 11 may further include an insulating layer 13. The insulating layer 13 may cover the surface of the structure formed by the trench isolation structure 112 and the active area 111. The insulating layer 13 may be used to isolate the active area 111 from the bit line 4 subsequently formed on the substrate 11. The insulating layer 13 may be made of an insulating material, for example, one or more of silicon nitride, silicon oxide, silicon carbide, or silicon oxynitride. In an exemplary embodiment of the present disclosure, the insulating layer 13 may be a composite film structure, for example, it may include a first insulating layer 131 and a second insulating layer 132. The first insulating layer 131 may be made of silicon oxide, and the second insulating layer 132 may be made of silicon nitride.
[0069] The material of the first conductive layer 12 can be polysilicon, which can be doped to improve its conductivity. The first conductive layer 12 can be formed on the substrate 11 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. For example, the first conductive layer 12 can be formed on the insulating layer 13.
[0070] like Figure 1 As shown, in step S120, a stress buffer layer 2 is formed on the first conductive layer 12. In a direction perpendicular to the surface of the substrate 11 and from a side close to the substrate 11 to a side away from the substrate 11, the stress of at least a portion of the stress buffer layer 2 increases sequentially, as shown in FIG. Figure 3 shown.
[0071] The material of the stress buffer layer 2 can be silicon carbide nitride. The stress buffer layer 2 can be formed on the first conductive layer 12 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, the carbon content and nitrogen content in the final stress buffer layer 2 can be controlled by controlling the content of different precursors (e.g., silane or silicon tetrachloride, methane or ethane or propane, ammonia). The carbon content and nitrogen content in the stress buffer layer 2 can directly determine the stress, hardness, and density in the stress buffer layer 2. In other words, the stress, hardness, and density of different regions in the stress buffer layer 2 can be precisely controlled by controlling the carbon content and nitrogen content in the final stress buffer layer 2.
[0072] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 3 As shown, the stress buffer layer 2 can be a single-layer film structure, and the stress in the stress buffer layer 2 increases linearly in a direction perpendicular to the surface of the substrate 11 and from the side close to the substrate 11 to the side away from the substrate 11. That is, during the process of forming the stress buffer layer 2, the content of the carbon-containing gas (e.g., methane, ethane, or propane) in the precursor increases, while the content of the nitrogen-containing gas (e.g., ammonia) decreases. For example, at the beginning of the deposition to form the stress buffer layer 2, the carbon content in the precursor can be 9at% to 10at%. As the deposition process proceeds, the carbon content in the precursor gradually increases linearly, and near the end of the deposition process, the carbon content in the precursor can reach 15at% to 25at%. At the same time, at the beginning of the deposition to form the stress buffer layer 2, the nitrogen content in the precursor can be 35at% to 40at%. As the deposition process proceeds, the nitrogen content in the precursor gradually decreases linearly, and near the end of the deposition process, the nitrogen content in the precursor can be 8at% to 10at%.
[0073] In an exemplary embodiment of the present disclosure, Figure 4 As shown, the stress buffer layer 2 may be a composite film structure composed of multiple film layers. The stress buffer layer 2 is formed on the first conductive layer 12. In a direction perpendicular to the surface of the substrate 11 and from a side close to the substrate 11 to a side away from the substrate 11, the stress in at least a portion of the stress buffer layer 2 increases sequentially (i.e., step S120). The process may include steps S210 to S230, wherein:
[0074] In step S210 , a first sub-stress buffer layer 21 is formed on the first conductive layer 12 . The stress of the first sub-stress buffer layer 21 is a first stress value.
[0075] The material of the first sub-stress buffer layer 21 may be silicon carbide nitride. The first stress value may be a relatively small stress value, so that in the subsequent process of removing the conductive material layer, the stress in the first sub-stress buffer layer 21 that is in direct contact with the first conductive layer 12 is small, and the stress acting on the first conductive layer 12 is also small, which can reduce the risk of cracking of the first conductive layer 12 due to stress concentration, and help improve product yield. For example, the first stress value may be 0.8GPa~1GPa; for example, the first stress value may be 0.8GPa, 0.85GPa, 0.9GPa, 0.95GPa or 1GPa. It should be noted that when the first stress value is 0.8GPa~1GPa, the density of the first sub-stress buffer layer 21 is 3.2g / cm 3 ~3.4g / cm 3 ; At the same time, the lattice constant in the first sub-stress buffer layer 21 is 0.428nm.
[0076] The thickness of the first sub-stress buffer layer 21 can be between 9 nm and 11 nm. For example, its thickness can be 9 nm, 9.5 nm, 10 nm, 10.5 nm, or 11 nm. Of course, the thickness of the first sub-stress buffer layer 21 can also be other values and is not specifically limited here. That is, the first sub-stress buffer layer 21 has a certain thickness, thereby providing a stable and low stress value in the area adjacent to the first conductive layer 12, thereby reducing the risk of cracking in the first conductive layer 12 due to stress fluctuations during subsequent etching.
[0077] In an exemplary embodiment of the present disclosure, the first sub-stress buffer layer 21 can be formed on the first conductive layer 12 by low-pressure chemical vapor deposition (LPCVD) at a temperature of 550° C. to 600° C. During this process, the nitrogen content in the precursor can be 35 at % to 40 at %, and the carbon content in the precursor can be 9 at % to 10 at %. As a result, the nitrogen content in the finally formed first sub-stress buffer layer 21 can be 35 at % to 40 at %, and the carbon content in the finally formed first sub-stress buffer layer 21 can be 9 at % to 10 at %.
[0078] For example, the nitrogen content in the finally formed first sub-stress buffer layer 21 may be 35at%, and the carbon content may be 9at%; alternatively, the nitrogen content in the finally formed first sub-stress buffer layer 21 may be 36at%, and the carbon content may be 9.2at%; alternatively, the nitrogen content in the finally formed first sub-stress buffer layer 21 may be 37at%, and the carbon content may be 9.4at%; alternatively, the nitrogen content in the finally formed first sub-stress buffer layer 21 may be 38at%, and the carbon content may be 9.6at%; alternatively, the nitrogen content in the finally formed first sub-stress buffer layer 21 may be 39at%, and the carbon content may be 9.8at%; alternatively, the nitrogen content in the finally formed first sub-stress buffer layer 21 may be 40at%, and the carbon content may be 10at%.
[0079] In step S220, a second sub-stress buffer layer 22 is formed on the first sub-stress buffer layer 21. In a direction perpendicular to the surface of the substrate 11 and in a direction from the side close to the substrate 11 to the side away from the substrate 11, the stress of the second sub-stress buffer layer 22 increases successively, and the minimum value of the stress in the second sub-stress buffer layer 22 is greater than or equal to the first stress value.
[0080] The material of the second sub-stress buffer layer 22 can also be silicon carbide nitride. The stress of the second sub-stress buffer layer 22 can gradually increase linearly. The increase in the stress of the second sub-stress buffer layer 22 helps to enhance the hardness of the stress buffer layer 2, making it less likely to deform during the subsequent process of removing part of the conductive material layer to form the second conductive layer 3, allowing it to be used as a mask.
[0081] In an exemplary embodiment of the present disclosure, a second sub-stress buffer layer 22 can be formed on the first sub-stress buffer layer 21 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. During this process, the stress of different thickness areas in the second sub-stress buffer layer 22 can be controlled by adjusting the carbon content and nitrogen content in the precursor during the formation of the second sub-stress buffer layer 22.
[0082] For example, during the formation of the second sub-stress buffer layer 22, as the deposition time increases, the nitrogen content in the precursor gradually decreases, while the carbon content in the precursor gradually increases. Furthermore, the nitrogen content in the first sub-stress buffer layer 21 is greater than or equal to the maximum nitrogen content in the second sub-stress buffer layer 22, and the carbon content in the first sub-stress buffer layer 21 is less than or equal to the minimum carbon content in the second sub-stress buffer layer 22. By adjusting the nitrogen and carbon contents in the precursor during the deposition process, the nitrogen content in the second sub-stress buffer layer 22 decreases, while the carbon content in the second sub-stress buffer layer 22 increases, in a direction perpendicular to the surface of the substrate 11 and from the side close to the substrate 11 to the side away from the substrate 11. Consequently, the stress in the second sub-stress buffer layer 22 increases linearly in a direction perpendicular to the surface of the substrate 11 and from the side close to the substrate 11 to the side away from the substrate 11.
[0083] The thickness of the second stress buffer layer 22 may be 1.5 nm to 3.5 nm. For example, the thickness may be 1.5 nm, 2 nm, 2.5 nm, 3 nm, or 3.5 nm. Of course, the thickness of the second stress buffer layer 22 may also be other values and is not particularly limited here.
[0084] In an exemplary embodiment of the present disclosure, during the formation of the second sub-stress buffer layer 22, as the deposition time increases, the nitrogen content in the precursor can gradually decrease from 35at% to 40at% to 8at% to 10at%; at the same time, the carbon content in the precursor can gradually increase from 9at% to 10at% to 15at% to 25at%.
[0085] For example, the nitrogen content in the precursor may be gradually reduced from 35 at% to 8 at%, and the carbon content in the precursor may be gradually increased from 9 at% to 15 at%. Alternatively, the nitrogen content in the precursor may be gradually reduced from 36 at% to 8.4 at%, and the carbon content in the precursor may be gradually increased from 9.2 at% to 17 at%. Alternatively, the nitrogen content in the precursor may be gradually reduced from 37 at% to 8.8 at%, and the carbon content in the precursor may be gradually increased from 9.4 at% to 19 at%. Alternatively, the nitrogen content in the precursor may be gradually decreased from 38 at% to 9.2 at%, and the carbon content in the precursor may be gradually increased from 9.6 at% to 21 at%; alternatively, the nitrogen content in the precursor may be gradually decreased from 39 at% to 9.6 at%, and the carbon content in the precursor may be gradually increased from 9.8 at% to 23 at%; alternatively, the nitrogen content in the precursor may be gradually decreased from 40 at% to 10 at%, and the carbon content in the precursor may be gradually increased from 10 at% to 25 at%.
[0086] In step S230 , a third sub-stress buffer layer 23 is formed on the second sub-stress buffer layer 22 . The stress of the third sub-stress buffer layer 23 is a second stress value, which is greater than or equal to the maximum stress value of the second sub-stress buffer layer 22 .
[0087] The material of the third sub-stress buffer layer 23 can also be silicon carbide nitride. The third stress value can be a relatively large stress value, so that during the subsequent removal of the conductive material layer, the stress in the third sub-stress buffer layer 23 is relatively large, the hardness is relatively large, and it is not easily deformed. This allows the stress buffer layer 2 of the present disclosure to be reused as a mask layer and / or an etch stop layer, effectively reducing the phenomenon of insufficient local removal of the conductive material layer due to stress anomalies, deformation of the stress buffer layer 2, or damage (cracks, fragments) to the first conductive layer 12, thereby helping to reduce structural defects and improve product yield. It helps to improve product yield.
[0088] For example, the second stress value may be 1.2 GPa to 1.5 GPa; for example, the second stress value may be 1.2 GPa, 1.3 GPa, 1.4 GPa or 1.5 GPa. It should be noted that when the second stress value is 1.2 GPa to 1.5 GPa, the density of the third sub-stress buffer layer 23 is 2.8 g / cm 3 ~3.1g / cm 3 ; At the same time, the lattice constant in the third sub-stress buffer layer 23 is 0.436nm.
[0089] The thickness of the third sub-stress buffer layer 23 can be greater than that of the first sub-stress buffer layer 21 to further improve the hardness of the stress buffer layer 2. For example, the thickness of the third sub-stress buffer layer 23 can be 19 nm to 21 nm. For example, the thickness can be 19 nm, 19.5 nm, 20 nm, 20.5 nm, or 21 nm. Of course, the thickness of the third sub-stress buffer layer 23 can also be other values and is not particularly limited here.
[0090] In an exemplary embodiment of the present disclosure, the third sub-stress buffer layer 23 can be formed on the second sub-stress buffer layer 22 by plasma-enhanced chemical vapor deposition (PECVD) at a temperature of 380° C. to 420° C. During this process, the nitrogen content of the precursor can be 8 at % to 10 at %, and the carbon content of the precursor can be 15 at % to 25 at %. As a result, the nitrogen content of the finally formed third sub-stress buffer layer 23 can be 8 at % to 10 at %, and the carbon content of the finally formed third sub-stress buffer layer 23 can be 15 at % to 25 at %. That is, the nitrogen content of the first sub-stress buffer layer 21 is higher than the nitrogen content of the third sub-stress buffer layer 23; and the carbon content of the third sub-stress buffer layer 23 is higher than the maximum carbon content of the second sub-stress buffer layer 22 and / or the carbon content of the first sub-stress buffer layer 21.
[0091] For example, the nitrogen content in the finally formed third sub-stress buffer layer 23 may be 8 at%, and the carbon content may be 15 at%; alternatively, the nitrogen content in the finally formed third sub-stress buffer layer 23 may be 8.5 at%, and the carbon content may be 17.5 at%; alternatively, the nitrogen content in the finally formed third sub-stress buffer layer 23 may be 9 at%, and the carbon content may be 20 at%; alternatively, the nitrogen content in the finally formed third sub-stress buffer layer 23 may be 9.5 at%, and the carbon content may be 22.5 at%; alternatively, the nitrogen content in the finally formed third sub-stress buffer layer 23 may be 10 at%, and the carbon content may be 25 at%.
[0092] It should be noted that, since the stress of the second sub-stress buffer layer 22 arranged between the first sub-stress buffer layer 21 and the third sub-stress buffer layer 23 gradually increases from the side close to the first sub-stress buffer layer 21 to the side close to the third sub-stress buffer layer 23, the stress distribution in the stress buffer layer 2 can be optimized through the gradient change of the stress in the second sub-stress buffer layer 22, and the probability of peeling or cracking inside the stress buffer layer 2 due to the large stress difference between the first sub-stress buffer layer 21 and the third sub-stress buffer layer 23 can be reduced.
[0093] like Figure 1 As shown, in step S130 , the stress buffer layer 2 , the first conductive layer 12 and the active region 111 are etched to form the contact trench 101 .
[0094] like Figure 5 As shown, a dry etching process can be used to etch the stress buffer layer 2, the first conductive layer 12, and the active area 111, thereby forming a contact groove 101 that exposes the top of the active area 111. It should be noted that the contact groove 101 can be recessed into the active area 111. That is, the bottom surface of the contact groove 101 can be lower than the top surface of the adjacent active area 111. In an exemplary embodiment of the present disclosure, there can be multiple contact grooves 101, and one contact groove 101 can be formed on each active area 111.
[0095] like Figure 1 As shown, in step S140, a conductive material layer 310 is formed on the side of the stress buffer layer 2 away from the substrate 11, and the conductive material layer fills the contact groove 101, as shown in FIG. Figure 6 shown.
[0096] In an exemplary embodiment of the present disclosure, the material of the conductive material layer 310 may be polysilicon, for example, it may be doped polysilicon. The conductive material layer 310 may be formed on the side of the stress buffer layer 2 (e.g., the third sub-stress buffer layer 23) away from the substrate 11 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, the conductive material layer 310 may fill the contact grooves 101. That is, the conductive material layer 310 may cover the stress buffer layer 2 and fill each contact groove 101. It should be noted that after the conductive material layer 310 is formed, its surface may be subjected to chemical mechanical polishing so that the conductive material layer 310 has a relatively flat surface, so as to provide a flat process benchmark for subsequent process steps, thereby reducing the process difficulty of subsequent processes.
[0097] like Figure 1 As shown, in step S150, the conductive material layer 310 located on the top of the stress buffer layer 2 is removed, and the top surface of the conductive material layer 310 located in the contact groove 101 is flush with the top surface of the first conductive layer 12, and the remaining conductive material layer 310 is used as the second conductive layer 3. In one embodiment of the present disclosure, the structure after completing step S150 is as shown in FIG. Figure 7 shown.
[0098] In an exemplary embodiment of the present disclosure, the second conductive layer 3 can be formed by etching. For example, removing the conductive material layer 310 located on top of the stress buffer layer 2 and making the top surface of the conductive material layer 310 located in the contact groove 101 flush with the top surface of the first conductive layer 12 (i.e., step S150) can include steps S310 and S320, wherein:
[0099] In step S310, the conductive material layer 310 is preliminarily etched to make the conductive material layer 310 flush with the surface of the stress buffer layer 2 away from the substrate 11. In one embodiment of the present disclosure, the structure after completing step S310 is as follows: Figure 8 shown.
[0100] A dry etching process can be used to perform preliminary etching on the conductive material layer 310. During this process, since the stress and hardness of the portion of the stress buffer layer 2 close to the conductive material layer 310 (for example, the third sub-stress buffer layer 23) are relatively large, it is not easy to deform during the etching process and can be used as an etching stop layer to facilitate precise control of the thickness and surface morphology of the remaining film layer after etching.
[0101] In step S310 , the conductive material layer 310 remaining after the initial etching is further etched so that the top surface of the conductive material layer 310 remaining after the further etching is flush with the top surface of the first conductive layer 12 .
[0102] The dry etching process can be continued to etch the conductive material layer 310 remaining after the initial etching again, so that the top surface of the conductive material layer 310 remaining after etching is flush with the top surface of the first conductive layer 12 (eg Figure 7 As shown), during this process, the stress buffer layer 2 can be used as a mask. Since the stress of at least part of the stress buffer layer 2 increases successively in the direction from the side close to the substrate 11 to the side away from the substrate, the thermal stress and mechanical stress generated by the process can be effectively dispersed and released through the stress gradient transition during the etching of the conductive material layer 310 again, which can reduce the risk of cracking of the first conductive layer 12 due to stress concentration during the manufacturing process (especially the etching step of the conductive material layer 310). At the same time, during the etching process, the stress buffer layer 2 can provide an environment with a stable stress state, which can effectively reduce the phenomenon of insufficient etching of the conductive material layer 310 due to stress abnormalities, deformation of the stress buffer layer 2 or damage (cracks, fragments) of the first conductive layer 12, thereby helping to reduce structural defects and improve product yield.
[0103] In an exemplary embodiment of the present disclosure, after forming the second conductive layer 3, the stress buffer layer 2 can be removed to expose the surface of the first conductive layer 12. At this time, no cracks are formed on the surface of the first conductive layer 12. For the structure after removing the stress buffer layer 2, please refer to Figure 9 For example, the stress buffer layer 2 can be removed by etching. The etching gas or etching solution used in the etching process can be determined according to the materials of the stress buffer layer 2 and other surrounding structures. As long as the stress buffer layer 2 can be removed without damaging (or slightly damaging but not affecting the structural performance) other structures, the etching gas or etching solution can be used.
[0104] In an exemplary embodiment of the present disclosure, the forming method of the present disclosure may further include step S410 and step S420, wherein:
[0105] Step S410: After removing the stress buffer layer 2, a bit line material layer 410 is formed on the surface of the structure formed by the first conductive layer 12 and the second conductive layer 3. In one embodiment of the present disclosure, the structure after completing step S410 is as follows: Figure 10 shown.
[0106] The bitline material layer may be a composite film layer structure composed of multiple film layers. For example, the bitline material layer 410 may include a first material layer 411, a second material layer 412, and a third material layer 413 distributed in sequence along a direction perpendicular to the surface of the substrate 11, wherein the first material layer 411 is located on the surface of the first conductive layer 12. The material of the first material layer 411 may be a conductive material with an ion blocking function, so as to prevent metal ions and / or dopant ions in subsequently formed film layers from diffusing into the first conductive layer 12, thereby helping to improve device reliability. For example, the material may be titanium nitride. The second material layer 412 may be a material with strong conductive properties, for example, tungsten. The material of the third material layer 413 may be an insulating material, for example, silicon nitride.
[0107] The first material layer 411 , the second material layer 412 and the third material layer 413 may be sequentially formed on the surface of the structure formed by the first conductive layer 12 and the second conductive layer 3 by chemical vapor deposition, physical vapor deposition or atomic layer deposition.
[0108] Step S420, etching the bit line material layer 410, the first conductive layer 12, and the second conductive layer 3 to form the bit line 4. In one embodiment of the present disclosure, the structure after completing step S420 is as follows: Figure 11 shown.
[0109] A dry etching process can be used to etch the bit line material layer 410, the first conductive layer 12, and the second conductive layer 3 located on the substrate 11, thereby forming the bit line 4. It should be noted that the second conductive layer 3 remaining in the contact trench 101 after etching can serve as the contact structure between the bit line 4 and the active area 111. It should be noted that during the process of forming the bit line 4, any non-separate film layers in the insulating layer 13 located on the substrate can also be etched simultaneously. For example, the second insulating layer 132 in the insulating layer 13 can be etched.
[0110] In an exemplary embodiment of the present disclosure, before forming the conductive material layer 310, a protective layer 5 may be formed on the sidewall of the contact groove 101, and the conductive material layer 310 fills the contact groove 101 with the protective layer 5. The structure after forming the protective layer 5 in an embodiment of the present disclosure is as follows: Figure 12 shown.
[0111] The material of the protective layer 5 can be silicon nitride, and the thickness of the protective layer can be 2 nm to 3 nm. For example, the thickness can be 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm, or 3 nm. The protective layer 5 can be formed on the inner wall of the contact groove 101 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The protective layer 5 on the bottom surface of the contact groove 101 can then be removed, leaving only the protective layer 5 on the sidewalls of the contact groove 101. In other words, the protective layer 5 can conformally cover the sidewalls of the contact groove 101, while exposing the bottom surface of the contact groove 101.
[0112] The first conductive layer 12 exposed in the sidewall region of the contact trench 101 can be protected by the protective layer 5 to reduce the probability of pores forming in the first conductive layer 12 exposed in the sidewall region of the contact trench 101 due to the influence of residual etching gas during the etching process to form the contact trench 101. This can further reduce the risk of short circuits between adjacent bit lines 4 or between a bit line and a subsequently fabricated capacitor due to the conductive material (e.g., titanium nitride or tungsten) in the subsequently deposited bit line material layer 410 filling the pores, thereby helping to improve product yield. In some embodiments of the present disclosure, the protective layer 5 can be formed on the sidewall of the contact trench 101 by a plasma nitridation process.
[0113] It should be noted that in the present disclosure, if the protective layer 5 is not formed on the sidewalls of the contact groove 101 before forming the conductive material layer 310, pores may be formed in the first conductive layer 12 in the direction from the sidewalls of the first conductive layer 12 to the central axis of the first conductive layer 12. If the protective layer 5 is formed on the sidewalls of the contact groove 101 before forming the conductive material layer 310, no pores are formed in the first conductive layer 12 in the direction from the sidewalls of the first conductive layer 12 to the central axis of the first conductive layer 12, and the product yield is higher.
[0114] In an exemplary embodiment of the present disclosure, when the stress buffer layer 2 is removed, the protection layer 5 located on the sidewall portion of the contact groove 101 surrounded by the stress buffer layer 2 may also be removed.
[0115] like Figure 13 As shown, the bit line material layer 410 can be formed on the surface of the structure composed of the first conductive layer 12, the second conductive layer 3 and the remaining protection layer 5. When the bit line material layer 410, the first conductive layer 12 and the second conductive layer 3 are etched, the remaining protection layer 5 can be removed at the same time.
[0116] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.
[0117] The present disclosure provides a semiconductor structure, which can be formed by the method for forming a semiconductor structure in any of the above embodiments.
[0118] The specific details and manufacturing processes of each part of the above-mentioned semiconductor structure have been described in detail in the corresponding method for forming the semiconductor structure, and therefore, they will not be repeated here.
[0119] For example, the semiconductor structure may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, it may also be other storage devices, which are not listed here one by one.
[0120] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate and a first conductive layer formed on the substrate, the substrate comprising a plurality of active regions spaced apart; forming a stress buffer layer on the first conductive layer, wherein the stress of at least a portion of the stress buffer layer increases sequentially in a direction perpendicular to the surface of the substrate and from a side close to the substrate to a side away from the substrate; Etching the stress buffer layer, the first conductive layer, and the active area to form a contact groove; forming a conductive material layer on a side of the stress buffer layer away from the substrate, wherein the conductive material layer fills the contact groove; The conductive material layer on top of the stress buffer layer is removed, and the top surface of the conductive material layer in the contact groove is flush with the top surface of the first conductive layer, and the remaining conductive material layer is used as the second conductive layer.
2. The forming method according to claim 1, wherein: The step of forming a stress buffer layer on the first conductive layer, wherein the stress of at least a portion of the stress buffer layer increases sequentially in a direction perpendicular to the surface of the substrate and from a side close to the substrate to a side away from the substrate, comprises: forming a first sub-stress buffer layer on the first conductive layer, wherein the stress of the first sub-stress buffer layer is a first stress value; forming a second sub-stress buffer layer on the first sub-stress buffer layer, wherein the stress of the second sub-stress buffer layer increases in a direction perpendicular to the surface of the substrate and from a side close to the substrate to a side away from the substrate, and a minimum value of the stress in the second sub-stress buffer layer is greater than or equal to the first stress value; A third sub-stress buffer layer is formed on the second sub-stress buffer layer, wherein the stress of the third sub-stress buffer layer is a second stress value, and the second stress value is greater than or equal to the maximum stress value of the second sub-stress buffer layer.
3. The forming method according to claim 2, wherein: The first stress value is 0.8 GPa to 1 GPa; and / or the second stress value is 1.2 GPa to 1.5 GPa.
4. The forming method according to claim 2, wherein: The thickness of the first sub-stress buffer layer is 9 nm to 11 nm; and / or the thickness of the second sub-stress buffer layer is 1.5 nm to 3.5 nm; and / or the thickness of the third sub-stress buffer layer is 19 nm to 21 nm.
5. The forming method according to claim 2, wherein: The materials of the first sub-stress buffer layer, the second sub-stress buffer layer, and the third sub-stress buffer layer are all silicon carbide nitride. The nitrogen content of the first sub-stress buffer layer is higher than the maximum nitrogen content of the second sub-stress buffer layer and / or the nitrogen content of the third sub-stress buffer layer; the carbon content of the third sub-stress buffer layer is higher than the maximum carbon content of the second sub-stress buffer layer and / or the carbon content of the first sub-stress buffer layer; in a direction perpendicular to the surface of the substrate and in a direction from a side close to the substrate to a side away from the substrate, the nitrogen content in the second sub-stress buffer layer decreases successively, and the carbon content in the second sub-stress buffer layer increases successively.
6. The forming method according to claim 5, wherein: The nitrogen content of the first sub-stress buffer layer is 35at% to 40at%; and / or, the carbon content of the first sub-stress buffer layer is 9at% to 10at%; and / or, the nitrogen content of the third sub-stress buffer layer is 8at% to 10at%; and / or, the carbon content of the third sub-stress buffer layer is 15at% to 25at%.
7. The forming method according to claim 1, wherein: The removing of the conductive material layer located on top of the stress buffer layer and making the top surface of the conductive material layer located in the contact groove flush with the top surface of the first conductive layer comprises: performing preliminary etching on the conductive material layer so that the conductive material layer is flush with the surface of the stress buffer layer away from the substrate; The conductive material layer remaining after the preliminary etching is further etched so that a top surface of the conductive material layer remaining after the further etching is flush with a top surface of the first conductive layer.
8. The forming method according to any one of claims 1 to 7, characterized in that: The forming method further comprises: After forming the second conductive layer, the stress buffer layer is removed.
9. The forming method according to claim 8, wherein: The forming method further comprises: After removing the stress buffer layer, forming a bit line material layer on the surface of the structure formed by the first conductive layer and the second conductive layer; The bit line material layer, the first conductive layer, and the second conductive layer are etched to form a bit line.
10. The forming method according to claim 9, wherein: Before forming the conductive material layer, the forming method further includes: forming a protective layer on the sidewall of the contact groove, and filling the contact groove with the protective layer with the conductive material layer; When removing the stress buffer layer, removing the protective layer located on the sidewall portion of the contact groove surrounded by the stress buffer layer; The bit line material layer is formed on a surface of a structure formed by the first conductive layer, the second conductive layer and the remaining protective layer; When etching the bit line material layer, the first conductive layer, and the second conductive layer, the remaining protection layer is removed.
11. The forming method according to claim 10, wherein: Pores are formed in the first conductive layer in a direction from the sidewall of the first conductive layer to the central axis of the first conductive layer, or no pores are formed in the first conductive layer in a direction from the sidewall of the first conductive layer to the central axis of the first conductive layer.
12. The forming method according to claim 8, wherein: After the stress buffer layer is removed, no cracks are formed on the surface of the first conductive layer.
13. A semiconductor structure, characterized in that The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 12.