Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the device comprises a substrate which is provided with a first surface, and the substrate is provided with a first doping type; the source region structures are located in the substrate at intervals, and the second surfaces of the source region structures are located in the first surface; the gate structure is positioned on the first surface and covers partial surfaces of the plurality of source region structures; the anti-static structure is located on the side, away from the substrate, of the gate structure, the anti-static structure comprises a plurality of first doping layers and second doping layers which are stacked in a staggered mode in the direction, pointing to the gate structure, of the substrate, the first doping layers are of the second doping type, and the second doping layers are of the first doping type. According to the trench gate structure, the electrostatic current is released through the antistatic structure, the gate oxide layer of the gate structure can be protected, it is ensured that the gate oxide layer is not broken down under high electrostatic voltage, the antistatic capability of the trench gate structure is improved, and then the problem that the antistatic breakdown capability of the gate of the semiconductor device in the related technology is low is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Power MOSFETs, with their low forward voltage drop, high switching speed, and easy gate control, are crucial semiconductor devices in power electronics applications. The gate's static resistance is directly related to the chip area and gate oxide thickness. SiC MOS devices, limited by their material and process characteristics, have small chip areas and thin gate oxide thicknesses, resulting in poor gate static breakdown resistance. With the increasing application of SiC MOS devices, new SiC MOS devices with high static resistance are emerging. However, these new SiC MOS devices exhibit high switching losses and are susceptible to gate breakdown under high-frequency operating conditions.

[0003] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country to those skilled in the art. Summary of the Invention

[0004] The main purpose of the present application is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem of low gate anti-static breakdown capability of semiconductor devices in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor device is provided, including: a substrate having a first surface, the substrate having a first doping type; a plurality of source region structures, spaced apart in the substrate, the second surfaces of the source region structures being located in the first surface; a gate structure, located on the first surface and covering partial surfaces of the plurality of source region structures; an antistatic structure, located on the side of the gate structure away from the substrate, in the direction from the substrate to the gate structure, the antistatic structure including a plurality of staggered first doping layers and second doping layers, the first doping layer having the second doping type, and the second doping layer having the first doping type.

[0006] Optionally, the antistatic structure further includes a third doping layer, which is located at the outermost side of the antistatic structure in the direction along the substrate pointing to the gate structure. The third doping layer has the first doping type, and the doping concentration of the third doping layer is different from that of the second doping layer.

[0007] Optionally, the third doping layer includes a first sub-doping layer and a second sub-doping layer, wherein the second sub-doping layer is located at the outermost side of the antistatic structure in the direction along the substrate pointing to the gate structure, the first sub-doping layer is located on the side of the second sub-doping layer close to the substrate, the doping concentration of the second sub-doping layer is higher than the doping concentration of the first sub-doping layer, and the doping concentration of the first sub-doping layer is lower than the doping concentration of the second doping layer.

[0008] Optionally, the first source region structure in the source region structure includes: a first well region, a first doping region and a second doping region, wherein a side surface of the first well region close to the gate structure is in contact with the gate structure, the first doping region and the second doping region respectively, and the first well region has the second doping type; in a first direction, the first doping region is in contact with the first well region and the second doping region, the first doping region has the first doping type, the first direction has an angle with the direction of the substrate pointing to the gate structure, and the second doping region has the second doping type.

[0009] Optionally, the semiconductor device further includes an insulating layer, which is located on both sides of the gate structure and the antistatic structure in the first direction, the first source region structure in the source region structure has a first doping region and a second doping region, the insulating layer covers the first doping region, the first doping region has the first doping type, the second doping region has the second doping type, and the first direction has an angle with the direction of the substrate pointing to the gate structure.

[0010] Optionally, the semiconductor device further includes an anode metal layer and a cathode metal layer, wherein the anode metal layer covers the antistatic structure, the insulating layer and part of the source region structure; and the cathode metal layer is located on a side of the substrate away from the first surface.

[0011] Optionally, projections of the first doping layer and the second doping layer on the first surface overlap with a projection of the gate structure on the first surface.

[0012] According to another aspect of the present application, a method for preparing a semiconductor device is provided, which is used to prepare the semiconductor device, and the method comprises: providing a substrate, the substrate having a first surface, the substrate having a first doping type; forming a plurality of source region structures at intervals in the substrate, the second surface of the source region structure being located in the first surface; forming a gate structure on the first surface, the gate structure covering partial surfaces of the plurality of source region structures; forming an antistatic structure on a side of the gate structure away from the substrate, the antistatic structure comprising a plurality of staggered first doping layers and second doping layers in a direction from the substrate to the gate structure, the first doping layer having the second doping type, and the second doping layer having the first doping type.

[0013] Optionally, the step of forming a plurality of the source region structures includes: performing first ion implantation at intervals in the substrate to form a plurality of first well regions, the first well regions having the second doping type; performing second ion implantation in the plurality of the first well regions to form a plurality of first doping regions, the first doping regions and the first well regions both having a surface located in the first surface, the first doping regions having the first doping type; performing third ion implantation in one of the first doping regions to form a second doping region, in a first direction, the first doping region contacts the first well region and the second doping region, the second doping region has the second doping type, and the first direction has an angle with the direction of the substrate pointing to the gate structure.

[0014] Optionally, the step of forming an antistatic structure includes: alternately depositing the material of the first doping layer and the material of the second doping layer on the side of the prepared gate structure away from the substrate to form a first doping preparatory layer and a second doping preparatory layer; performing an etching process on the first doping preparatory layer, the second doping preparatory layer and the prepared gate structure to obtain the first doping layer, the second doping layer and the gate structure, wherein the first doping layer covers the gate structure.

[0015] Applying the technical solution of the present application, the semiconductor device of the present application includes a substrate, multiple source region structures, a gate structure and an antistatic structure, wherein the antistatic structure is formed on the gate structure to enhance the antistatic capability of the gate of the semiconductor device, wherein the antistatic structure comprises a first doping layer and a second doping layer alternately stacked, the doping types of the first doping layer and the second doping layer are opposite, and multiple PN junction structures are formed between the multiple first doping layers and the multiple second doping layers. When the gate voltage exceeds the safety threshold, the multiple PN junctions will be turned on, and the current will be released through the antistatic structure to protect the gate oxide layer of the gate structure, ensuring that the gate oxide layer is not broken down under high electrostatic voltage, thereby enhancing the antistatic capability of the trench gate structure, and thus solving the problem of low gate antistatic breakdown capability of semiconductor devices in related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0017] Figure 1 A schematic cross-sectional structure diagram of a first semiconductor device proposed according to an embodiment of the present application is shown;

[0018] Figure 2 A schematic cross-sectional structure diagram of a second semiconductor device proposed according to an embodiment of the present application is shown;

[0019] Figure 3 A schematic cross-sectional structure diagram of a third semiconductor device proposed according to an embodiment of the present application is shown;

[0020] Figure 4 A schematic diagram of a process for preparing a semiconductor device according to an embodiment of the present application is shown;

[0021] Figure 5 The figure shows a schematic cross-sectional structure diagram of a substrate after forming a first well region in a method for manufacturing a semiconductor device;

[0022] Figure 6 Shown in Figure 5 A schematic diagram of the cross-sectional structure of the substrate after the first doping region is formed in the first well region formed in the substrate;

[0023] Figure 7 Shown in Figure 6 A schematic diagram of the cross-sectional structure of the substrate after the second doping region is formed in the first doping region formed in the substrate;

[0024] Figure 8 Shown in Figure 7A schematic cross-sectional structure diagram of a substrate after a preliminary gate structure and a preliminary antistatic structure are formed on the substrate;

[0025] Figure 9 Shows the Figure 8 Schematic diagram of the cross-sectional structure of the substrate after the preliminary gate structure and the preliminary antistatic structure are etched to obtain the gate structure and the antistatic structure.

[0026] The above drawings include the following reference numerals:

[0027] 10. Base; 11. Substrate; 12. Epitaxial layer; 20. Source region structure; 21. First source region structure; 22. Second source region structure; 211. First well region; 212. First doped region; 213. Second doped region; 30. Gate structure; 31. Gate oxide layer; 32. Gate; 300. Preparatory gate structure; 310. Preparatory gate oxide layer; 320. Preparatory gate; 40. Antistatic structure; 41. First doped layer; 410. First doped preparatory layer; 42. Second doped layer; 420. Second doped preparatory layer; 43. Third doped layer; 431. First sub-doped layer; 432. Second sub-doped layer; 50. Insulating layer; 60. Anode metal layer; 70. Cathode metal layer. DETAILED DESCRIPTION

[0028] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0029] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0030] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0031] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being “on” another element, the element may be directly on the other element or intervening elements may be present. Furthermore, in the specification and claims, when it is described that an element is “connected to” another element, the element may be “directly connected to” the other element or “connected to” the other element through a third element.

[0032] As described in the background, prior art SiC MOS devices are limited by material and process characteristics, resulting in small chip areas, thin gate oxide layers, and poor gate electrostatic breakdown resistance. As SiC MOS devices become increasingly widely used, new SiC MOS devices with high electrostatic resistance continue to emerge. However, these new SiC MOS devices exhibit high switching losses and are susceptible to gate breakdown under high-frequency operating conditions. To address the low gate electrostatic breakdown resistance of prior art semiconductor devices, embodiments of the present application provide a semiconductor device and a method for preparing the same.

[0033] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0034] According to one embodiment of the present application, a semiconductor device is provided, such as Figures 1 to 3 As shown, it includes: a substrate 10 having a first surface, the substrate 10 having a first doping type; a plurality of source region structures 20, which are spaced apart in the substrate 10, and the second surface of the source region structure 20 is located in the first surface; a gate structure 30, which is located on the first surface and covers part of the surface of the plurality of source region structures 20; an antistatic structure 40, which is located on the side of the gate structure 30 away from the substrate 10, and in the direction of the substrate 10 pointing to the gate structure 30, the antistatic structure 40 includes a plurality of staggered first doping layers 41 and second doping layers 42, the first doping layer 41 having the second doping type, and the second doping layer 42 having the first doping type.

[0035] The antistatic capability of a semiconductor device's gate can be enhanced by forming an antistatic structure on top of a gate structure. The antistatic structure comprises alternating first and second doped layers, each having opposite doping types. Multiple PN junction structures are formed between the multiple first and second doped layers. When the gate voltage exceeds a safety threshold, the multiple PN junctions conduct. Leveraging the reverse breakdown characteristics of the PN junctions, when a preset electrostatic voltage threshold is exceeded, the electrostatic energy can be rapidly discharged, thereby protecting the gate oxide layer from damage. Current passing through the antistatic structure releases the electrostatic current, protecting the gate oxide layer of the gate structure and ensuring that the gate oxide layer does not breakdown under high electrostatic voltages, thereby enhancing the antistatic capability of the trench gate structure. Furthermore, when the number of first and second doped layers stacked is more than two (PNPN or PNPNPN), the structure can be PNPN or PNPNPN. When the gate voltage exceeds the preset threshold, the structure rapidly conducts, dissipating excess electrostatic energy and protecting the gate oxide layer from damage. This semiconductor device can address the problem of low gate antistatic breakdown capability in semiconductor devices in the related art.

[0036] The above-mentioned source region structure is formed by ion implantation from the first surface into the substrate. After the source region structure is formed, the portion of the first surface having the source region structure is the second surface of the source region structure, and the portion of the surface not having the source region structure is still the first surface of the substrate. The second surface and the first surface are located on the same surface, but are divided differently. The upper surface of the source region structure is divided into the second surface, and the upper surface of the substrate where the source region structure is not formed is divided into the first surface.

[0037] In the above embodiment, if Figures 1 to 3 As shown, gate structure 30 includes a gate oxide layer 31 and a gate 32. Gate oxide layer 31 is located on substrate 10, and gate 32 is located on the side of gate oxide layer 31 facing away from substrate 10. Gate 32 can be made of polysilicon with an N-type doping type, while gate oxide layer 31 can be made of silicon dioxide with a thickness of 30nm-60nm. Gate structure 30 is used for gate signal transmission. By controlling the thickness of the gate oxide layer, efficient control of the channel can be achieved. Reasonable adjustment of the gate structure not only reduces switching time, but also improves the radiation resistance of the device and enhances the reliability of the device.

[0038] Because ordinary silicon semiconductor devices have higher channel mobility, their gate oxide layers can usually be relatively thick, typically 90-120nm. However, since semiconductor devices have lower channel mobility than silicon semiconductor devices, their gate oxide layers are usually thinner to ensure lower channel resistance. This means that ordinary silicon semiconductor devices do not require special gate electrostatic discharge (ESD) to achieve higher gate ESD tolerance. Therefore, the ESD structure of silicon semiconductor devices usually does not protect the gate, but protects the entire device structure. The ESD structure in this application is mainly to protect and improve the ESD level of the gate structure.

[0039] In the above embodiment, the substrate material can be silicon carbide, which can make the device have high thermal conductivity and high breakdown field strength, and is suitable for manufacturing high performance devices that can work in high temperature and high pressure environments. Figures 1 to 3 As shown, the base 10 includes a substrate 11 and an epitaxial layer 12. The doping concentration of the substrate 11 is higher than that of the epitaxial layer 12. The high doping concentration of the substrate 11 can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. The substrate 11 can also absorb carriers from the epitaxial layer 12, further reducing the on-resistance. The lower doping concentration of the epitaxial layer 12 can provide greater carrier mobility when the device is turned on, thereby reducing the on-resistance.

[0040] In the above embodiment, the first and second doped layers are relatively thin and meet the withstand voltage requirements of the PN junction at the target ESD level (similar in principle to a Zener diode), thereby improving the gate's electrostatic resistance. When the first and second doped layers are relatively thin, soft breakdown can occur. When the transient voltage is excessive (or when the gate voltage exceeds a safe range), the PNP directly conducts, and due to the low energy, no damage is caused to the device. Furthermore, the integrated NPNP structure (where the first N is the gate) turns on, releasing current through the PN junction, protecting the gate oxide layer from breakdown and improving the trench gate structure's anti-static capability.

[0041] In the above embodiments, the first doping type may be N-type doping or P-type doping, and the second doping type may be P-type doping or N-type doping, for example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. The N-type doping element may be a pentavalent element including any one of phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element may be a trivalent element including any one of boron (B), aluminum (Al), and gallium (Ga), and this application does not impose any specific limitations.

[0042] In some optional embodiments, such as Figure 2 and Figure 3As shown, the antistatic structure 40 further includes a third doping layer 43, which is located at the outermost side of the antistatic structure 40 in the direction from the substrate 10 to the gate structure 30. The third doping layer 43 has a first doping type, and the doping concentration of the third doping layer 43 is different from that of the second doping layer 42. Figure 2 Adding an N-type third doped layer 43 to the NPNP structure in the embodiment can increase the voltage drop at the antistatic structure 40, thereby generating a larger threshold voltage that can drive the gate oxide layer 31 to turn on smoothly, allowing the semiconductor device to conduct. This avoids the situation where the voltage drop generated by the NPNP structure is small, the threshold voltage generated is insufficient to turn on the gate oxide layer 31, and thus the gate oxide layer 31 cannot form a channel with the source region structure 20, and the semiconductor device cannot conduct. Moreover, by having different doping concentrations in the third doped layer 43 and the second doped layer 42, the concentration of the third doped layer 43 can be reasonably set, making the performance of all aspects of the entire device more comprehensive.

[0043] In some optional embodiments, such as Figure 2 and Figure 3 As shown, the third doped layer 43 includes a first sub-doped layer 431 and a second sub-doped layer 432, wherein the second sub-doped layer 432 is located at the outermost side of the anti-static structure 40 in the direction along the substrate 10 toward the gate structure 30, and the first sub-doped layer 431 is located on the side of the second sub-doped layer 432 close to the substrate 10. The doping concentration of the second sub-doped layer 432 is higher than the doping concentration of the first sub-doped layer 431, and the doping concentration of the first sub-doped layer 431 is lower than the doping concentration of the second sub-doped layer 432. Disposing the first sub-doped layer 431 with a lower concentration on the side of the second sub-doped layer 432 close to the substrate 10 can increase the resistance of the anti-static structure 40, thereby increasing the voltage drop and raising the threshold voltage to enable smooth device turn-on. Disposing the second sub-doped layer 432 with a higher concentration on the outermost side of the anti-static structure 40 will contact the metal electrode of the subsequent device, which can reduce the contact resistance and enable the gate structure 30 to have lower switching energy consumption in high-resistance or high-frequency applications.

[0044] In the above embodiment, the doping concentration of the first sub-doping layer shown can have different thicknesses and doping concentrations according to the requirements of different threshold voltages and electrostatic levels. Therefore, during normal operation (non-static and other large voltage shocks, when at normal operating voltage), the electrical isolation of the gate and the source can be guaranteed, and the effectiveness of the threshold voltage and the integrity of the gate control capability can be guaranteed.

[0045] In some optional embodiments, such as Figure 3As shown, the first source region structure 21 in the source region structure includes: a first well region 211, a first doping region 212, and a second doping region 213. The surface of the first well region 211 on the side closest to the gate structure 30 contacts the gate structure 30, the first doping region 212, and the second doping region 213, respectively. The first well region 211 has the second doping type. In a first direction X, the first doping region 212 contacts the first well region 211 and the second doping region 213. The first doping region 212 has the first doping type. The first direction X forms an angle with the direction from the substrate 10 toward the gate structure 30. The second doping region 213 has the second doping type. A complex multi-region doping pattern is employed, wherein the first well region 211 is P-type, the first doping region 212 is N-type, and the second doping region 213 is P-type. The doping concentration of the second doping region 213 is higher than that of the first well region 211. The second doping region 213 contacts the source metal of the device, which can reduce the source electrode contact resistance of the device and improve carrier efficiency.

[0046] And there are parasitic transistors in the semiconductor device. For example, the NPN parasitic transistor can be formed by the N-type substrate, the P-type first well region and the N-type first doped region under the gate structure. When the voltage and current in these regions reach specific conditions, the parasitic transistor may enter the on state and form a self-sustaining current path. This process is the latch-up effect. The introduction of the second doped region can serve as a "circuit breaker" in this current path. When the voltage difference between the source and the drain reaches a certain threshold, the PN junction formed by the second doped region and the N-type first doped region will undergo reverse breakdown, allowing current to pass, thereby breaking the self-sustaining current path. This design ensures that even under extreme conditions, the device can release additional current through a safe path, prevent the occurrence of latch-up effects, and protect the overall safety and performance of the device. Such as Figure 3 As shown, the source region structure of the device further includes a second source region structure 22 . The second source region structure 22 includes a first doping region 212 and a first well region 211 , but does not include a third doping region.

[0047] The junction depth of the first well region can be 0.7-1.5 μm, and the doping concentration can be 10 18 -10 19 cm 2 This can help to carry higher voltages and avoid internal short circuits or avalanche breakdown at high voltages. The junction depth of the first doped region is usually 0.1-0.4μm, and the doping concentration can be 10 19This reduces the source-substrate contact resistance, thereby reducing source losses in the device's on-state, accelerating carrier movement, reducing switching times, and lowering switching losses. The junction depth of the second doped region can be greater than or equal to that of the first doped region, with a junction depth of 0.7-1.5 μm. This allows for a better formation of an effective PN junction with the N-type first doped region, controlling the current path and preventing short circuits or latch-up.

[0048] In some optional embodiments, such as Figures 1 to 3 As shown, the semiconductor device further includes an insulating layer 50, which is located on both sides of the gate structure 30 and the anti-static structure 40 in the first direction X. The first source region structure 21 in the source region structure 20 has a first doping region 212 and a second doping region 213. The insulating layer 50 covers the first doping region 212. The first doping region 212 has a first doping type, and the second doping region 213 has a second doping type. The first direction X and the direction of the substrate 10 pointing to the gate structure 30 form an angle. When the first doping region 212 in the first source region structure 21 is set not to contact the electrode, the current of the parasitic transistor will flow through the second doping region 213, so that the second doping region 213 can maximize the reduction of the risk of latch-up effect in the device. The insulating layer strengthens the electrical isolation between the side of the anti-static structure 40 and the electrode, which can improve the stability of the device in long-term use.

[0049] In the above optional embodiment, the material of the insulating layer may be silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride and the like, and the thickness may be 0.3-0.8 μm, which is not specifically limited in this application.

[0050] In some optional embodiments, such as Figures 1 to 3 As shown, the semiconductor device further includes an anode metal layer 60 and a cathode metal layer 70, wherein the anode metal layer 60 covers the antistatic structure 40, the insulating layer 50 and a portion of the source region structure 20; the cathode metal layer 70 is located on the side of the substrate 10 away from the first surface. Figure 3 As shown, an ohmic contact is formed between the anode metal layer 60 and the third doped layer 43, and an ohmic contact is also formed between the anode metal layer 60 and the second doped region 213, thereby improving the current flow efficiency. The arrangement of the anode metal layer 60 and the cathode metal layer 70 can improve the electrode contact efficiency of the semiconductor device, while ensuring the charge balance of the device under different operating modes. The anode metal layer 60 covers the third doped layer 43 and part of the source region structure 20, which can provide a low-impedance path for the device and accelerate the static discharge of the antistatic structure 40. The cathode metal layer 70 is placed on the other side of the substrate 10, which can enhance the heat dissipation capability of the device, reduce the operating temperature, and extend the life of the device.

[0051] In the above embodiments, the materials of the anode metal layer and the cathode metal layer may be any one or more of Ni, Cu, Ag, Mo, Ta and Au, which are not specifically limited in this application.

[0052] In some optional embodiments, the projections of the first doped layer and the second doped layer on the first surface overlap with the projection of the gate structure on the first surface. This allows the first doped layer, the second doped layer, and the gate structure to be formed using a single mask during device fabrication, saving costs and process steps.

[0053] The overlapping first doping layer and the second doping layer in the semiconductor device proposed in the present application may also have more overlaps, and is not limited to that shown in the drawings. The entire thickness of the final device may be 30-200 μm.

[0054] According to another embodiment of the present application, a method for preparing a semiconductor device is provided. Figure 4 FIG. 1 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present application. Figure 4 As shown, the preparation method is used to prepare a semiconductor device, and the preparation method includes:

[0055] Step S1, providing a substrate, wherein the substrate has a first surface and a first doping type;

[0056] Specifically, the base includes a substrate and an epitaxial layer. The doping concentration of the substrate is higher than that of the epitaxial layer. The high doping concentration of the substrate can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. The substrate can also absorb carriers from the epitaxial layer, further reducing the on-resistance.

[0057] Step S2, forming a plurality of source region structures at intervals in the substrate, wherein the second surfaces of the source region structures are located within the first surface;

[0058] Specifically, the source region structure includes a first source region structure and a second source region structure. The first source region structure includes a first well region, a first doped region, and a second doped region, while the second source region structure includes a first well region and a first doped region. The source region structure can regulate the current flow of the device, and the second doped region provided in the first source region structure can also prevent the device from experiencing latch-up.

[0059] Step S3, forming a gate structure on the first surface, wherein the gate structure covers a portion of the surface of the plurality of source region structures;

[0060] Specifically, the gate structure includes a gate oxide layer and a gate. The gate oxide layer may be made of silicon dioxide and may have a thickness of 30 nm to 60 nm. The gate may be made of polysilicon and may be used for gate signal transmission.

[0061] In step S4, an antistatic structure is formed on the side of the gate structure facing away from the substrate. In the direction from the substrate to the gate structure, the antistatic structure includes a plurality of staggered first doping layers and second doping layers, wherein the first doping layers have the second doping type and the second doping layers have the first doping type.

[0062] Specifically, the thicknesses of the first doping layer and the second doping layer are relatively thin and meet the withstand voltage requirement of the PN junction under the target ESD level, thereby improving the electrostatic level of the gate.

[0063] The semiconductor device prepared according to the above-mentioned preparation method has an antistatic structure. The antistatic structure includes alternating first and second doped layers, wherein the first and second doped layers have opposite doping types. Multiple PN junction structures are formed between the multiple first doped layers and the multiple second doped layers. When the gate voltage exceeds a safety threshold, the multiple PN junctions are turned on. Utilizing the reverse breakdown characteristics of the PN junctions, when a preset electrostatic voltage threshold is exceeded, the electrostatic energy can be rapidly discharged, thereby protecting the gate oxide layer from damage. Current passing through the antistatic structure releases the electrostatic current, protecting the gate oxide layer of the gate structure, ensuring that the gate oxide layer does not break down under high electrostatic voltages, and improving the antistatic capability of the trench gate structure. When the number of first and second doped layers stacked is more than two (PNPN or PNPNPN), the structure can be PNPN or PNPNPN. When the gate voltage exceeds the preset threshold, the structure can be turned on rapidly to discharge excess electrostatic energy, thereby protecting the gate oxide layer from damage. The above-mentioned semiconductor device can solve the problem of low gate antistatic breakdown capability of semiconductor devices in the related art.

[0064] In some optional embodiments, the step of forming a plurality of source region structures includes: Figure 5 As shown, a first ion implantation is performed at intervals in the substrate 10 to form a plurality of first well regions 211. The first well regions 211 have a second doping type; the second doping type may be P-type. The first well regions help to spatially isolate the source region and the gate, thereby reducing lateral leakage current. The substrate 10 includes a substrate 11 and an epitaxial layer 12. The plurality of first well regions 211 are formed in the epitaxial layer 12. Figure 6 As shown, a second ion implantation is performed in each of the plurality of first well regions 211 to form a plurality of first doped regions 212. Both the first doped regions 212 and the first well region 211 have surfaces located in the first surface, and the first doped regions 212 have a first doping type. N-type ion implantation is further performed in the P-type first well region to form a first doped region. The introduction of the N-type first doped region reduces the resistance between the source and the channel, while also maintaining good isolation from the well region, thereby enhancing the conductive performance and electrical isolation of the device. Figure 7As shown, a third ion implantation is performed in one of the first doped regions 212 to form a second doped region 213. In a first direction X, the first doped region 212 contacts the first well region 211 and the second doped region 213. The second doped region 213 has the second doping type. The first direction X forms an angle with the direction of the substrate 10 toward the gate structure. By further performing P-type ion implantation in the first doped region (N-type) to form the second doped region, the device can safely release excess electrostatic current even under extreme conditions, preventing latch-up. The source region structure comprising the first doped region 212, the second doped region 213, and the first well region 211 is the first source region structure 21, and the other is the second source region structure 22.

[0065] In some optional embodiments, the step of forming the antistatic structure includes: Figure 8 As shown, materials for the first doping layer and the second doping layer are alternately deposited on the side of the preliminary gate structure 300 facing away from the substrate 10 to form a first doping preliminary layer 410 and a second doping preliminary layer 420. The preliminary gate structure 300 includes a preliminary gate oxide layer 310 and a preliminary gate 320. The multiple layers of the first doping preliminary layer 410 and the second doping preliminary layer 420 form a PNPN structure (more layers may form a similar PNPNPNPN structure). As an anti-static structure, the PNPN structure can quickly turn on when the gate voltage reaches a preset ESD threshold (e.g., ±2000V), protecting the gate oxide layer from electrostatic damage.

[0066] like Figure 9 As shown, the first doped preliminary layer, the second doped preliminary layer, and the preliminary gate structure are etched once to obtain the first doped layer 41, the second doped layer 42, and the gate structure 30 (the gate structure 30 includes a gate oxide layer 31 and a gate 32). The first doped layer 41 covers the gate structure 30. The gate structure 30 and the antistatic structure 40 can be formed simultaneously through a single etching process using a single mask, which can save process steps and reduce costs.

[0067] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The semiconductor device and the manufacturing method thereof proposed in the above embodiments of the present application can achieve the following technical effects:

[0069] 1) The semiconductor device of the present application forms an antistatic structure on top of the gate structure to enhance the antistatic capability of the semiconductor device's gate. The antistatic structure comprises alternating first and second doped layers, each having opposite doping types. Multiple PN junction structures are formed between the multiple first and second doped layers. When the gate voltage exceeds a safety threshold, the multiple PN junctions conduct. Utilizing the reverse breakdown characteristics of the PN junctions, when the preset electrostatic voltage threshold is exceeded, the electrostatic energy can be rapidly discharged, thereby protecting the gate oxide layer from damage. Current passing through the antistatic structure releases the electrostatic current, protecting the gate oxide layer of the gate structure and ensuring that the gate oxide layer does not breakdown under high electrostatic voltages, thereby enhancing the antistatic capability of the trench gate structure. Furthermore, when the number of first and second doped layers stacked is more than two, the structure can be PNPN or PNPNPN. When the gate voltage exceeds the preset threshold, the structure rapidly conducts, discharging excess electrostatic energy and protecting the gate oxide layer from damage. The above-described semiconductor device can address the problem of low gate antistatic breakdown capability of semiconductor devices in the related art.

[0070] 2) This application incorporates a second doped region within one of the source regions of the semiconductor device, creating a PN junction between the second doped region and the first doped region. When the transient voltage is excessive, the device can release static current through the PN junction's safe conduction path, preventing latch-up. The third doped region not only prevents the device from failing to turn on due to a low threshold voltage but also reduces contact resistance with the electrode, lowering switching losses.

[0071] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first surface, the substrate having a first doping type; A plurality of source region structures are spaced apart and located in the substrate, and the second surfaces of the source region structures are located in the first surface; a gate structure, located on the first surface and covering a portion of the surfaces of the plurality of source region structures; An antistatic structure is located on the side of the gate structure away from the substrate, and in the direction from the substrate to the gate structure, the antistatic structure includes a plurality of staggered first doping layers and second doping layers, the first doping layers have the second doping type, and the second doping layers have the first doping type.

2. The semiconductor device according to claim 1, wherein The antistatic structure further includes a third doping layer, which is located at the outermost side of the antistatic structure in a direction from the substrate to the gate structure. The third doping layer has the first doping type, and the doping concentration of the third doping layer is different from that of the second doping layer.

3. The semiconductor device according to claim 2, wherein The third doping layer includes a first sub-doping layer and a second sub-doping layer, wherein: The second sub-doping layer is located at the outermost side of the antistatic structure in the direction along the substrate pointing to the gate structure, the first sub-doping layer is located on the side of the second sub-doping layer close to the substrate, the doping concentration of the second sub-doping layer is higher than the doping concentration of the first sub-doping layer, and the doping concentration of the first sub-doping layer is lower than the doping concentration of the second doping layer.

4. The semiconductor device according to claim 1, wherein The first source region structure in the source region structure includes: a first well region, a first doping region and a second doping region, wherein: A surface of the first well region close to the gate structure is in contact with the gate structure, the first doping region and the second doping region respectively, and the first well region has the second doping type; In a first direction, the first doping region contacts the first well region and the second doping region, the first doping region has the first doping type, the first direction and the direction of the substrate pointing to the gate structure have an angle, and the second doping region has the second doping type.

5. The semiconductor device according to claim 1, wherein The semiconductor device also includes an insulating layer, which is located on both sides of the gate structure and the antistatic structure in a first direction. The first source region structure in the source region structure has a first doping region and a second doping region. The insulating layer covers the first doping region, the first doping region has the first doping type, and the second doping region has the second doping type. The first direction has an angle with the direction of the substrate pointing to the gate structure.

6. The semiconductor device according to claim 5, wherein The semiconductor device further comprises an anode metal layer and a cathode metal layer, wherein: The anode metal layer covers the antistatic structure, the insulating layer and part of the source region structure; The cathode metal layer is located on a side of the substrate facing away from the first surface.

7. The semiconductor device according to claim 1, wherein Projections of the first doping layer and the second doping layer on the first surface overlap with a projection of the gate structure on the first surface.

8. A method for preparing a semiconductor device, characterized in that: The preparation method is used to prepare the semiconductor device according to any one of claims 1 to 7, and the preparation method comprises: Providing a substrate, wherein the substrate has a first surface and the substrate has a first doping type; forming a plurality of source region structures spaced apart in the substrate, wherein the second surfaces of the source region structures are located within the first surface; forming a gate structure on the first surface, wherein the gate structure covers a portion of the surfaces of the plurality of source region structures; An antistatic structure is formed on the side of the gate structure facing away from the substrate. In the direction from the substrate to the gate structure, the antistatic structure includes a plurality of staggered first doping layers and second doping layers, wherein the first doping layers have the second doping type and the second doping layers have the first doping type.

9. The preparation method according to claim 8, characterized in that The step of forming a plurality of source region structures comprises: Performing first ion implantation in the substrate at intervals to form a plurality of first well regions, wherein the first well regions have the second doping type; Performing a second ion implantation in each of the first well regions to form a plurality of first doped regions, wherein the first doped regions and the first well region both have surfaces located within the first surface, and the first doped regions have the first doping type; A third ion implantation is performed in one of the first doping regions to form a second doping region. In a first direction, the first doping region is in contact with the first well region and the second doping region. The second doping region has the second doping type. The first direction forms an angle with a direction of the substrate pointing to the gate structure.

10. The preparation method according to claim 8, characterized in that The steps of forming the antistatic structure include: Alternately depositing the material of the first doping layer and the material of the second doping layer on a side of the preliminary gate structure facing away from the substrate to form a first doping preliminary layer and a second doping preliminary layer; The first doping preparation layer, the second doping preparation layer and the prepared gate structure are etched once to obtain the first doping layer, the second doping layer and the gate structure, wherein the first doping layer covers the gate structure.

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