Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a central region and an edge region, and the edge region surrounds the central region; the channel layer is located in the substrate in the central region, and the top of the channel layer is flush with the top of the substrate; and the filling layer is located in the substrate of the edge region. The filling layer is located in the substrate of the edge region, and the edge region surrounds the central region, namely, the edge region is located at the edge of the substrate, so that the problem that the channel layer at the edge of the substrate is exposed in the subsequent process is solved, the risk that the processing cavity is polluted by the channel layer in the subsequent process is reduced, and the processing efficiency is improved. Therefore, different processes can use the processing cavity in a mixed manner, the equipment sharing rate is improved, and the economical efficiency of the technological process is improved; meanwhile, the channel layer and the filling layer are formed in the groove in the substrate, so that the filling layer is formed in the edge region of the substrate, exposure of the edge region can be realized, the chip yield loss of the edge region is improved, and the number of available chips is effectively increased.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) has also been shortening. As a result, the distance between the device's source and drain electrodes has also shortened, weakening the gate structure's ability to control the channel. It has also become increasingly difficult to pinch off the channel with the gate voltage, making subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to reduce the impact of the short channel effect, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field-Effect Transistors (FinFETs). In FinFETs, the gate structure is a three-dimensional fin structure. Compared with planar MOSFETs, this structure increases the control area of ​​the channel, greatly enhancing the gate's control over the channel, thereby effectively suppressing the short channel effect; and compared to other devices, FinFETs have better compatibility with existing integrated circuit manufacturing.

[0004] However, the current process for forming the fin portion of the FinFET still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which improves the economic efficiency of the process while improving the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a central region and an edge region, the edge region surrounding the central region; a channel layer located in the substrate in the central region, and the top of the channel layer is flush with the top of the substrate; and a filling layer located in the substrate in the edge region.

[0007] An embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a central region and an edge region, the edge region surrounding the central region; forming grooves in the substrate in the central region and the edge region; forming a channel layer in the groove in the central region; and forming a filling layer in the groove in the edge region.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] An embodiment of the present invention provides a semiconductor structure in which a substrate includes a central region and an edge region, wherein the edge region surrounds the central region; a channel layer is located in the substrate in the central region, and the top of the channel layer is flush with the top of the substrate; and a filling layer is located in the substrate in the edge region. In this embodiment, since the filling layer is located in the substrate in the edge region, and the edge region surrounds the central region, that is, the edge region is located at the edge of the substrate, the problem of the channel layer being exposed at the edge of the substrate is improved in subsequent process steps, and the risk of the channel layer contaminating the processing chamber in subsequent processes is reduced, thereby enabling different processes to mix and use the processing chamber, improving the equipment sharing rate, and thus improving the economic efficiency of the process; at the same time, the channel layer and the filling layer are formed in a groove in the substrate, so by forming the filling layer in the edge region of the substrate, the edge region can be exposed, the chip yield loss in the edge region can be improved, and the number of available chips (die) can be effectively increased (for example, it can be increased by 19%).

[0010] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein grooves are formed in a substrate in a central region and an edge region; a channel layer is formed in the groove in the central region; and a filling layer is formed in the groove in the edge region. In the embodiment of the present invention, since the filling layer is located in the substrate in the edge region, and the edge region surrounds the central region, that is, the edge region is located at the edge of the substrate, the problem of the channel layer being exposed at the edge of the substrate is improved in subsequent process steps, and the risk of the channel layer contaminating the processing chamber in subsequent processes is reduced, thereby enabling different processes to mix and use the processing chamber, improving the equipment sharing rate, and thus improving the economy of the process steps; at the same time, the channel layer and the filling layer are formed in the groove in the substrate, so by forming the filling layer in the edge region of the substrate, the edge region can be exposed, the chip yield loss in the edge region is improved, and the number of available chips is effectively increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural diagram of a semiconductor structure;

[0012] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 3 to 181 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0014] Figure 19 A comparison chart of data obtained after testing the number of available chips using a semiconductor structure formed using an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The performance of current semiconductor structures needs to be improved. This paper analyzes the reasons why the performance of semiconductor structures needs to be improved by combining a method for forming a semiconductor structure.

[0016] Figure 1 It is a structural diagram of a semiconductor structure.

[0017] refer to Figure 1 The semiconductor structure includes: a substrate 10, the substrate 10 including a central region I' and an edge region II', the edge region II' surrounding the central region I'; a channel layer 11, located in the substrate 10 in the central region I' and the edge region II'.

[0018] Research has found that in subsequent process steps, since the channel layer 11 at the edge of the substrate 10 is easily exposed, the processing chamber is easily contaminated by the exposed channel layer 11 during subsequent process steps. The contaminated processing chamber cannot produce other products, so the equipment cannot be shared, thereby reducing the economic efficiency of the process.

[0019] In the prior art, there are two methods for reducing the risk of exposure of the channel layer 11 in the edge region II' of the substrate 10. One method is to not expose the edge region II' of the substrate 10 during the process of forming a groove for accommodating the channel layer 11 in the substrate 10, that is, the channel layer 11 is not formed in the edge region II' of the substrate 10. However, this method can easily lead to the inability to form a chip in the edge region II' of the substrate 10, thereby resulting in a large loss in chip yield. Another method is to cover the edge region II' of the substrate 10 with a negative photoresist and the central region I' of the substrate 10 with a positive photoresist during the process of forming a groove for accommodating the channel layer 11 in the substrate 10. In this way, after the exposure and development process of the substrate 10, the negative photoresist on the edge region II' of the substrate 10 is not removed, that is, the channel layer 11 is not formed in the edge region II' of the substrate 10. However, this method can not only easily lead to a large loss in chip yield, but also easily lead to light leakage problems inside the chip.

[0020] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a central area and an edge area, the edge area surrounding the central area; a channel layer located in the substrate in the central area, and the top of the channel layer is flush with the top of the substrate; a filling layer located in the substrate in the edge area.

[0021] In the solution disclosed in the embodiment of the present invention, since the filling layer is located in the substrate in the edge area, and the edge area surrounds the central area, that is, the edge area is located at the edge of the substrate, therefore, in the subsequent process, the problem of the channel layer being exposed at the edge of the substrate is improved, and the risk of the channel layer contaminating the processing chamber in the subsequent process is reduced, so that different processes can be mixed to use the processing chamber, thereby improving the equipment sharing rate and thus improving the economy of the process; at the same time, the channel layer and the filling layer are formed in the groove in the substrate, so by forming the filling layer in the edge area of ​​the substrate, the edge area can be exposed, the chip yield loss in the edge area is improved, and the number of available chips is effectively increased (for example, it can be increased by 19%).

[0022] Specifically, the number of available chips refers to the number of chips with complete graphics and normal electrical properties.

[0023] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] Figure 2 FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

[0025] refer to Figure 2 The semiconductor structure includes: a substrate 20, the substrate 20 including a central region i and an edge region ii, the edge region ii surrounding the central region i; a channel layer 21 located in the substrate 20 in the central region i, and the top of the channel layer 21 is flush with the top of the substrate 20; a filling layer 22 located in the substrate 20 in the edge region ii.

[0026] The substrate 20 is used to provide an operating basis for a semiconductor structure formation process.

[0027] In this embodiment, the substrate 20 is a silicon substrate. In other embodiments, the substrate material may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other substrate types. In this embodiment, the substrate 20 is used to form a fin field-effect transistor.

[0028] The central area i is used to provide a process platform for forming the channel layer 21 .

[0029] The edge region ii is used to provide a process platform for forming the filling layer 22 .

[0030] In this embodiment, the edge region ii is located 147 mm to 150 mm from the center of the substrate 20. If the edge region ii exceeds the above range, that is, the area of ​​the edge region ii becomes larger, which may easily lead to the reduction of the area of ​​the central region i, that is, the number of chips formed in the central region i is reduced, thereby reducing the yield of the wafer.

[0031] Correspondingly, the central region i is the remaining region of the substrate 20 surrounded by the edge region ii.

[0032] The channel layer 21 is used to provide a conductive channel when the semiconductor device is working.

[0033] The material of the channel layer 21 can be one or more of silicon, silicon-germanium, germanium, and Group III-V semiconductor materials. The material of the channel layer 21 is determined based on the channel conductivity type and performance requirements of the transistor. In this embodiment, the material of the channel layer 21 is silicon-germanium. As an example, a P-type transistor is subsequently formed using the channel layer 21 made of silicon-germanium.

[0034] It should be noted that silicon germanium is a commonly used material for the channel layer 21 , and thus has the characteristic of low process cost.

[0035] The filling layer 22 is located in the substrate 20 in the edge region ii.

[0036] Since the filling layer 22 is located in the edge area ii of the substrate 20, and the edge area ii surrounds the central area i, that is, the edge area ii is located at the edge of the substrate 20, therefore, in the subsequent process, the problem of the channel layer 21 being exposed at the edge of the substrate 20 is improved, and the risk of the exposed channel layer 21 contaminating the processing chamber in the subsequent process is reduced, so that different processes can be mixed to use the processing chamber, improve the equipment sharing rate, and thus improve the economy of the process; at the same time, the channel layer 21 and the filling layer 22 are formed in the groove in the substrate 20, so by forming the filling layer 22 in the edge area ii of the substrate 20, the edge area ii can be exposed, the chip yield loss in the edge area ii is improved, and the number of available chips is effectively increased.

[0037] refer to Figure 19 , Figure 19 This is a data comparison chart obtained after using the semiconductor structure of the embodiment of the present invention to detect the number of available chips. Figure 19 The middle horizontal axis represents three situations: the edge of the substrate 20 is not exposed and the equipment can be shared, the edge of the substrate 20 is exposed and edge processed and the equipment can be shared, and the entire substrate 20 is exposed and the equipment is not shared. The main vertical axis 1 represents the normalized value of the number of available chips, the secondary vertical axis 2 represents the wafer area loss rate, the solid line L1 represents the normalized value of the number of available chips, and the dotted line L2 represents the wafer area loss rate.

[0038] Among them, the edge of the substrate 20 is exposed and processed, and the equipment can share the semiconductor structure of the embodiment of the present invention. The remaining two situations are used as comparison situations. Figure 19 The L1 line in FIG. 1 shows that the semiconductor structure of this embodiment increases the number of available chips by 19% compared to a semiconductor structure in which the edges of substrate 20 are not exposed and equipment can be shared. Furthermore, it helps reduce wafer area loss. Furthermore, compared to a semiconductor structure in which the entire substrate 20 is exposed and equipment cannot be shared, the semiconductor structure of this embodiment enables equipment sharing, allowing different processes to mix and match processing chambers, increasing equipment sharing and, in turn, improving process economics.

[0039] In this embodiment, the filling layer 22 includes: a top filling layer 23, located in the substrate 20 in the edge area ii; a second stop layer 24, conformally covering the bottom surface and side walls of the top filling layer 23; and a second buffer layer 25, conformally covering the bottom surface and side walls of the second stop layer 24.

[0040] The second buffer layer 25 is used to improve the stress mismatch problem between the substrate 20 and the second stop layer 24 , thereby improving the adhesion between the substrate 20 and the second stop layer 24 .

[0041] In the process of forming the filling layer 22, the material layer above the top of the substrate 20 is usually removed. The second stop layer 24 is used to prevent excessive removal of the second buffer layer 25 and the substrate 20 during the formation of the filling layer 22, thereby protecting the flatness of the surface of the substrate 20.

[0042] The filling layer 22 is formed in the groove in the substrate 20 , and the top filling layer 23 is used to fill the remaining space of the groove in the substrate 20 , thereby reducing the risk of cracking in subsequent process steps.

[0043] Specifically, the materials of the top filling layer 23 and the second buffer layer 25 both include silicon oxide, and the material of the second stop layer 24 includes silicon nitride.

[0044] It should be noted that since silicon oxide and silicon nitride are common semiconductor materials, the cost of using them in semiconductor manufacturing processes is low, and the impact on the entire process flow is relatively small. In addition, introducing silicon oxide between silicon and silicon nitride can prevent interfacial reaction between silicon and silicon nitride, improve the stability of the interface, thereby reducing the stress on the interface, and further improving the adhesion between silicon and silicon nitride, that is, improving the adhesion between the substrate 20 and the second stop layer 24. Therefore, the materials of the top filling layer 23 and the second buffer layer 25 both include silicon oxide, and the material of the second stop layer 24 includes silicon nitride.

[0045] It is understandable that in other embodiments, the filling layer may also be made of other materials that can meet the filling requirements.

[0046] In this embodiment, the semiconductor structure further includes an alignment mark layer (not shown) located in the substrate 20 . The alignment mark layer is also located in the substrate 20 in the edge region ii and serves as the filling layer 22 .

[0047] The alignment mark layer is used as a mark for the overlay alignment of a subsequent partial photolithography mask. Specifically, the alignment mark layer is a zero mark.

[0048] In this embodiment, the alignment mark layer and the filling layer 22 are formed in the same process step, which is beneficial to reducing process complexity and process cost.

[0049] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 18 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0050] refer to Figure 3 , providing a substrate 30, wherein the substrate 30 includes a central region I and an edge region II, wherein the edge region II surrounds the central region I.

[0051] The substrate 30 is used to provide an operating basis for the formation process of the semiconductor structure.

[0052] In this embodiment, the substrate 30 is a silicon substrate. In other embodiments, the substrate material may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other substrate types. In this embodiment, the substrate 30 is used to form a fin field-effect transistor.

[0053] The central area I is used to provide a process platform for the subsequent formation of a channel layer.

[0054] The edge region II is used to provide a process platform for the subsequent formation of a filling layer.

[0055] In this embodiment, the edge region II is located 147 mm to 150 mm from the center of the substrate 30. If the edge region II exceeds the above range, that is, the area of ​​the edge region II becomes larger, which can easily lead to the reduction of the area of ​​the central region I, that is, the number of chips formed in the central region I decreases, thereby reducing the yield of the wafer.

[0056] Correspondingly, the central region I is the remaining region of the substrate 30 surrounded by the edge region II.

[0057] Combined with reference Figure 4 To reference Figure 7 , grooves 38 are formed in the substrate 30 in the central area I and the edge area II.

[0058] In this embodiment, the groove 38 is used to fill the channel layer in the central area I and the filling layer in the edge area II.

[0059] It should be noted that the method of forming the groove 38 includes patterning the substrate 30 through a photolithography process and an etching process. The photolithography process and the etching process have the characteristics of high process maturity and low process cost.

[0060] In this embodiment, the step of forming the groove 38 on the substrate includes: forming a patterned first hard mask layer 36 on the substrate 30, the first hard mask layer 36 including: a first stop layer 36B, located on the top of the substrate 30; a pattern transfer layer 36C, located on the top of the first stop layer 36B; a first buffer layer 36D, located on the top of the pattern transfer layer 36C; using the first hard mask layer 36 as a mask, patterning the substrate 30 to form the groove 38.

[0061] In this embodiment, the patterned first hard mask layer 36 is used as a mask for patterning the substrate 30 .

[0062] Specifically, the first hard mask layer 36 includes: a first stop layer 36B, located on the top of the substrate 30; a pattern transfer layer 36C, located on the top of the first stop layer 36B; a first buffer layer 36D, located on the top of the pattern transfer layer 36C; wherein the first stop layer 36B is used to prevent excessive removal of the substrate 30 during the formation of the groove 38 and protect the surface of the substrate 30; the pattern transfer layer 36C is used to transfer the pattern of the patterned mask layer 37 to the first stop layer 36B; the first buffer layer 36D is used to improve the adhesion between the pattern transfer layer 36C and the mask layer 37.

[0063] In this embodiment, the material of the first stop layer 36B and the material of the first buffer layer 36D both include silicon oxide, and the material of the pattern transfer layer 36C includes silicon nitride.

[0064] It should be noted that silicon oxide is a commonly used material for the first stop layer 36B and the first buffer layer 36D, and thus has the characteristic of low process cost; silicon nitride is a commonly used material for the pattern transfer layer 36C, and thus the process of using silicon nitride is mature, thereby reducing process cost.

[0065] refer to Figure 4 Before forming the first hard mask layer 36 , the method further includes: forming a first hard mask material layer 36A on the substrate 30 .

[0066] The first hard mask material layer 36A is used to provide a process basis for subsequently forming a first hard mask layer.

[0067] In this embodiment, the first hard mask layer 36 includes: a first stop layer 36B, a pattern transfer layer 36C located on top of the first stop layer 36B, and a first buffer layer 36D located on top of the pattern transfer layer 36C. Therefore, the first hard mask material layer 36A correspondingly includes a first stop material layer (not labeled), a pattern transfer material layer (not labeled) and a first buffer material layer (not labeled) stacked in sequence from bottom to top.

[0068] As an example, after forming the groove 38 , the first stop layer 36B and the pattern transfer layer 36C are retained.

[0069] refer to Figure 5 , a patterned mask layer 37 is formed on top of the first hard mask material layer 36A.

[0070] The patterned mask layer 37 is used as a mask for patterning the first hard mask material layer 36A. As an example, the material of the mask layer 37 includes photoresist.

[0071] Accordingly, reference Figure 6 In the step of forming the first hard mask layer 36, the patterned mask layer 37 is used as a mask to pattern the first hard mask material layer 36A, the first stop material layer is patterned into the first stop layer 36B, the pattern transfer material layer is patterned into the pattern transfer layer 36C, and the first buffer material layer is patterned into the first buffer layer 36D.

[0072] As an example, in the step of forming the first hard mask layer 36 , the patterned mask layer 37 is used as a mask to sequentially etch the first buffer material layer, the pattern transfer material layer and the first stop material layer from top to bottom through a dry etching process.

[0073] Combined with reference Figure 8 To reference Figure 15 , a channel layer 31 is formed in the groove 38 of the central area I.

[0074] The channel layer 31 is used to provide a conductive channel when the semiconductor device is in operation.

[0075] The material of the channel layer 31 can also be one or more of silicon, silicon-germanium, germanium, and Group III-V semiconductor materials. The material of the channel layer 31 is determined based on the channel conductivity type and performance requirements of the transistor. In this embodiment, the material of the channel layer 31 is silicon-germanium. As an example, a P-type transistor is subsequently formed using the channel layer 31 made of silicon-germanium.

[0076] It should be noted that silicon germanium is a commonly used material for the channel layer 31 , and thus has the characteristic of low process cost.

[0077] Combined with reference Figure 14 and Figure 15 The step of forming the channel layer 31 in the groove 38 of the central region I includes: Figure 14 As shown, the channel material layer 31A is filled in the groove 38 of the central area I; Figure 15 As shown, the top surface of the channel material layer 31 is planarized, and a channel layer 31 is formed in the groove 38 of the central area I.

[0078] It should be noted that planarizing the top surface of the channel material layer 31A is beneficial to improving the reliability of the subsequent patterning process.

[0079] Specifically, the process of planarizing the top surface of the channel material layer 31A includes a chemical mechanical polishing process.

[0080] The chemical mechanical polishing process can reduce surface roughness, improve device reliability, speed, and yield, and improve step coverage and remove surface defects. Consequently, a relatively flat surface can be obtained, which serves as the top surface of the channel material layer 31A, with a low probability of surface damage.

[0081] Continue to refer Figure 14 Before planarizing the top surface of the channel material layer 31A, the method further includes: removing the pattern transfer layer 36C.

[0082] Specifically, by removing the pattern transfer layer 36C, more of the channel material layer 31A is exposed, thereby improving the efficiency of the subsequent planarization process on the channel material layer 31A. Furthermore, by removing the pattern transfer layer 36C, the first stop layer 36B is exposed. Therefore, during the subsequent planarization process, excessive wear of the top surface of the channel material layer 31A is prevented, thereby improving the uniformity of the device structure. Furthermore, the surface of the substrate 30 beneath the first stop layer 36B is effectively protected from damage, thereby improving the performance of the semiconductor structure.

[0083] In this embodiment, the pattern transfer layer 36C is removed by a wet process.

[0084] For this reason, Figure 15 As shown, after the pattern transfer layer 36C is removed, the top surface of the channel material layer 31A is planarized with the top surface of the first stop layer 36B as a stop position.

[0085] It should be noted that, in conjunction with the reference Figure 8In the step of filling the groove 38 in the central area I with the channel material layer 31A, the groove 38 in the edge area II is also filled with the channel material layer 31A.

[0086] Therefore, combined with reference Figures 9 to 13 Before planarizing the top surface of the channel material layer 31A, the method further includes: removing the channel material layer 31A in the groove 38 of the edge region II.

[0087] It should be noted that filling the grooves 38 in the central region I and the edge region II with the channel material layer 31A and then removing the channel material layer 31A in the grooves 38 in the edge region II can reduce process complexity.

[0088] In this embodiment, the process of removing the channel material layer 31A in the edge region II includes a wet etching process.

[0089] Specifically, the wet etching process has the characteristic of isotropic etching, which is conducive to completely removing the channel material layer 31A in the edge area II. Moreover, the wet etching process can easily obtain a larger etching selectivity, which is conducive to reducing damage to other film layers in the process of removing the channel material layer 31A in the edge area II.

[0090] Specifically, the step of removing the channel material layer 31A in the groove 38 of the edge region II includes: Figure 9 As shown, a second hard mask material layer 51A is formed on top of the channel material layer 31A; Figure 10 As shown, a patterned pattern definition layer 52 is formed on top of the second hard mask material layer 51A; Figure 11 As shown, the pattern definition layer 52 is used as a mask to pattern the second hard mask material layer 51A to form a second hard mask layer 51, and the second hard mask layer 51 exposes the channel material layer 31A in the groove 38 of the edge region II; Figure 13 As shown, the second hard mask layer 51 is used as a mask to remove the channel material layer 31A in the groove 38 of the edge region II; Figure 12 As shown, after forming the second hard mask layer 51 and before removing the channel material layer 31A in the groove 38 of the edge region II, the method further includes: removing the pattern definition layer 52 .

[0091] Specifically, the pattern definition layer 52 is used as a mask for patterning the second hard mask material layer 51A; when removing the channel material layer 31A in the groove 38 of the edge area II, the second hard mask layer 51 is used to protect the channel material layer 31A in the groove 38 of the center area I.

[0092] In this embodiment, the material of the pattern definition layer 52 includes amorphous carbon, and the material of the second hard mask layer 51 includes silicon oxide.

[0093] It should be noted that since a wet etching process is used to remove the channel material layer 31A in the groove 38 of the edge area II, the etching solution of the wet etching process is corrosive, and the second hard mask layer 51 has strong chemical stability, and is therefore not easily corroded by the etching solution, thereby being able to protect the channel material layer 31A in the groove 38 of the central area I.

[0094] It should be noted that in the process of patterning the second hard mask material layer 51A to form the second hard mask layer 51, impurities are likely to remain on the pattern definition layer 52. Therefore, after forming the second hard mask layer 51, before removing the channel material layer 31A in the groove 38 of the edge area II, the pattern definition layer 52 needs to be removed, thereby improving the accuracy and reliability of subsequent processes.

[0095] Combined with reference Figures 16 to 18 , a filling layer 32 is formed in the groove 38 of the edge region II.

[0096] It should be noted that since the filling layer 32 is located in the edge area II of the substrate 30, and the edge area II surrounds the central area I, that is, the edge area II is located at the edge of the substrate 30, therefore, in the subsequent process, the problem of the channel layer 31 being exposed at the edge of the substrate 30 is improved, and the risk of the exposed channel layer 31 contaminating the processing chamber in the subsequent process is reduced, so that different processes can be mixed to use the processing chamber, improve the equipment sharing rate, and thus improve the economy of the process; at the same time, the channel layer 31 and the filling layer 32 are formed in the groove 38 in the substrate 30, so by forming the filling layer 32 in the edge area II of the substrate 30, the edge area II can be exposed, the chip yield loss in the edge area II is improved, and the number of available chips is effectively increased.

[0097] refer to Figure 19 , Figure 19 This is a data comparison chart obtained after using the semiconductor structure of the embodiment of the present invention to detect the number of available chips. Figure 19 The middle horizontal axis represents three situations: the edge of the substrate 30 is not exposed and the equipment can be shared, the edge of the substrate 30 is exposed and edge processed and the equipment can be shared, and the entire substrate 30 is exposed and the equipment is not shared. The main vertical axis 1 represents the normalized value of the number of available chips, the secondary vertical axis 2 represents the wafer area loss rate, the solid line L1 represents the normalized value of the number of available chips, and the dotted line L2 represents the wafer area loss rate.

[0098] Among them, the edge of the substrate 30 is exposed and processed, and the equipment can share the semiconductor structure of the embodiment of the present invention. The remaining two situations are used as comparison situations. Figure 19 The L1 line in FIG. 1 shows that the semiconductor structure of this embodiment increases the number of available chips by 19% compared to a semiconductor structure in which the edges of substrate 30 are not exposed and equipment can be shared. Furthermore, it helps reduce wafer area loss. Furthermore, compared to a semiconductor structure in which the entire substrate 30 is exposed and equipment cannot be shared, the semiconductor structure of this embodiment enables equipment sharing, allowing different processes to mix and match processing chambers, increasing equipment sharing and, in turn, improving process economics.

[0099] In this embodiment, the step of forming the filling layer 32 in the groove 38 of the edge region II includes: Figure 16 As shown in FIG, an initial filling material layer 32A is formed on the substrate 30, the initial filling material layer 32A covers the top of the channel layer 31 in the central area I, and the initial filling material layer 32A also fills the groove 38 in the edge area II; Figure 17 As shown, the initial filling material layer 32A is planarized to form a filling material layer 32B; Figure 18 As shown, after the planarization process, the channel layer 31 and the filling material layer 32B above the top of the substrate 30 are removed, and the remaining filling material layer 32B in the groove 38 of the edge region II serves as the filling layer 32 .

[0100] Specifically, the initial filling material layer 32A is planarized, i.e., a portion of the initial filling material layer 32A is removed. This, on the one hand, saves time for subsequent processes, thereby improving the production efficiency of the semiconductor structure. On the other hand, the subsequent process time is shortened, thereby reducing the loss of forming the filling layer 32, thereby reducing the impact on subsequent processes.

[0101] In this embodiment, the filling layer 32 includes: a second buffer layer 35, conformally covering the sidewalls and bottom of the groove 38 in the edge area II; a second stop layer 34, conformally covering the top of the second buffer layer 35; and a top filling layer 33, located on the top of the second stop layer 34.

[0102] The second buffer layer 35 is used to improve the stress mismatch between the substrate 30 and the second stop layer 34 , thereby improving the adhesion between the substrate 30 and the second stop layer 34 .

[0103] In the process of forming the filling layer 32 , the material layer above the top of the substrate 30 is usually removed. The second stop layer 34 is used to prevent excessive removal of the second buffer layer 35 and the substrate 30 during the formation of the filling layer 32 , thereby protecting the flatness of the surface of the substrate 30 .

[0104] The filling layer 32 is formed in the groove 38 in the substrate 30 , and the top filling layer 33 is used to fill the remaining space of the groove 38 in the substrate 30 , thereby reducing the risk of cracking in subsequent process steps.

[0105] Therefore, in this embodiment, the materials of the top filling layer 33 and the second buffer layer 35 both include silicon oxide, and the material of the second stop layer 34 includes silicon nitride.

[0106] It should be noted that since silicon oxide and silicon nitride are common semiconductor materials, the cost of using them in semiconductor manufacturing processes is low, and the impact on the entire process flow is relatively small. In addition, introducing silicon oxide between silicon and silicon nitride can prevent interfacial reaction between silicon and silicon nitride, improve the stability of the interface, thereby reducing the stress on the interface, and further improving the adhesion between silicon and silicon nitride, that is, improving the adhesion between the substrate 30 and the second stop layer 34. Therefore, the materials of the top filling layer 33 and the second buffer layer 35 both include silicon oxide, and the material of the second stop layer 34 includes silicon nitride.

[0107] It is understandable that in other embodiments, the filling layer may also be made of other materials that can meet the filling requirements.

[0108] Accordingly, the initial filling material layer 32A is planarized using the top surface of the second stop layer 34 as a stop position.

[0109] In this embodiment, the planarization process is a chemical mechanical polishing process.

[0110] In this embodiment, the process of removing the channel layer 31 and the filling material layer 32B above the top of the substrate 30 includes a wet etching process.

[0111] Specifically, the wet etching process has the characteristics of isotropic etching, which is conducive to cleanly removing the channel layer 31 and the filling material layer 32B on the top of the substrate 30. Moreover, the wet etching process can easily obtain a larger etching selectivity, which is conducive to reducing damage to other film layers in the process of removing the channel layer 31 and the filling material layer 32B on the top of the substrate 30.

[0112] In this embodiment, before forming the grooves 38 in the substrate of the central area I and the edge area II, it also includes: forming an alignment mark groove in the substrate 30 (not shown); in the step of forming the filling layer 32 in the groove 38 of the edge area II, an alignment mark layer (not shown) is also formed in the alignment mark groove.

[0113] The alignment mark layer is used as a mark for the overlay alignment of the subsequent partial photolithography mask. Specifically, the alignment mark layer is a zeroth mark.

[0114] In this embodiment, the filling layer 32 is formed by utilizing the process of forming the alignment mark layer, which is beneficial to reducing the process complexity and the process cost.

[0115] It should be noted that the semiconductor structure provided by the embodiment of the present invention can be formed by the formation method described in the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure according to the embodiment of the present invention, reference can be made to the corresponding description in the above embodiment.

[0116] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a central region and an edge region, wherein the edge region surrounds the central region; a channel layer, located in the substrate in the central region, with a top of the channel layer flush with a top of the substrate; A filling layer is located in the substrate in the edge area.

2. The semiconductor structure according to claim 1, wherein The edge region is located 147 mm to 150 mm from the center of the substrate.

3. The semiconductor structure according to claim 1, wherein: The material of the channel layer includes silicon germanium.

4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes an alignment mark layer located in the substrate. The alignment mark layer is also located in the substrate in the edge region and serves as the filling layer.

5. The semiconductor structure according to claim 1 or 4, wherein: The filling layer includes: a top filling layer located in the substrate of the edge region; a second stop layer conformally covering the bottom surface and sidewalls of the top filling layer; and a second buffer layer conformally covering the bottom surface and sidewalls of the second stop layer.

6. The semiconductor structure according to claim 5, wherein: The materials of the top filling layer and the second buffer layer both include silicon oxide, and the material of the second stop layer includes silicon nitride.

7. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a central region and an edge region, the edge region surrounding the central region; forming grooves in the substrate in the central region and the edge region; forming a channel layer in the groove of the central region; A filling layer is formed in the groove of the edge region.

8. The method for forming a semiconductor structure according to claim 7, wherein: The edge region is located 147 mm to 150 mm from the center of the substrate.

9. The method for forming a semiconductor structure according to claim 7, wherein: The grooves are formed by patterning the substrate through photolithography and etching processes.

10. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming a channel layer in the groove of the central region includes: filling the groove in the central region with a channel material layer; A top surface of the channel material layer is planarized to form a channel layer in the groove in the central area.

11. The method for forming a semiconductor structure according to claim 10, wherein: The step of forming a groove on the substrate includes: forming a patterned first hard mask layer on the substrate, the first hard mask layer including: a first stop layer located on the top of the substrate; a pattern transfer layer located on the top of the first stop layer; and a first buffer layer located on the top of the pattern transfer layer; Using the first hard mask layer as a mask, patterning the substrate to form a groove; Before the top surface of the channel material layer is planarized, the method further includes: removing the pattern transfer layer; The top surface of the channel material layer is planarized with the top surface of the first stop layer being used as a stop position.

12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the first stop layer and the material of the first buffer layer both include silicon oxide, and the material of the pattern transfer layer includes silicon nitride.

13. The method for forming a semiconductor structure according to claim 10 or 11, wherein: In the step of filling the grooves in the central region with the channel material layer, the grooves in the edge region are also filled with the channel material layer; Before the top surface of the channel material layer is planarized, the method further includes: removing the channel material layer in the groove in the edge area.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process of removing the channel material layer in the edge region includes a wet etching process.

15. The method for forming a semiconductor structure according to claim 13, wherein: The step of removing the channel material layer in the groove of the edge area includes: forming a second hard mask material layer on top of the channel material layer; forming a patterned pattern definition layer on top of the second hard mask material layer; Using the pattern definition layer as a mask, patterning the second hard mask material layer to form a second hard mask layer, wherein the second hard mask layer exposes the channel material layer in the groove of the edge region; Using the second hard mask layer as a mask, removing the channel material layer in the groove of the edge region; After forming the second hard mask layer and before removing the channel material layer in the groove of the edge region, the method further includes: removing the pattern definition layer.

16. The method for forming a semiconductor structure according to claim 7, wherein: Before forming the grooves in the substrate in the central area and the edge area, the method further includes: forming an alignment mark groove in the substrate; In the step of forming a filling layer in the groove of the edge region, an alignment mark layer is also formed in the alignment mark groove.

17. The method for forming a semiconductor structure according to claim 7 or 16, wherein: The step of forming a filling layer in the groove of the edge area includes: forming an initial filling material layer on the substrate, wherein the initial filling material layer covers the top of the channel layer in the central area and also fills the groove in the edge area; performing a planarization process on the initial filling material layer to form a filling material layer; After the planarization process, the channel layer and the filling material layer above the top of the substrate are removed, and the remaining filling material layer in the groove of the edge area serves as a filling layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: The filling layer includes: a second buffer layer conformally covering the sidewalls and bottom of the groove in the edge area; a second stop layer conformally covering the top of the second buffer layer; and a top filling layer located on the top of the second stop layer. The initial filling material layer is planarized by using the top surface of the second stop layer as a stop position.

19. The method for forming a semiconductor structure according to claim 18, wherein: The materials of the top filling layer and the second buffer layer both include silicon oxide, and the material of the second stop layer includes silicon nitride.

20. The method for forming a semiconductor structure according to claim 17, wherein: The process of removing the channel layer and the filling material layer above the top of the substrate includes a wet etching process.

Images