Preparation method of semiconductor device and semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device and the semiconductor device. The preparation method of the semiconductor device comprises the following steps: providing a preset substrate; wherein the preset substrate comprises an active region, a gate electrode located above the active region and side walls on the two sides of the gate electrode; performing back etching on the gate electrode to form a groove; filling the groove with a decomposable sacrificial material to form a sacrificial layer; depositing a shielding layer; the sacrificial layer is decomposed into gas which is volatilized through the shielding layer to form an air gap structure. According to the invention, the relative area between the gate electrode and the contact hole is reduced, the stray capacitance between the gate electrode and the contact hole is reduced, the performance of the semiconductor device is improved, the preparation cost is reduced, the stray capacitance between the gate electrode and the contact hole can be reduced under various wafer manufacturing processes, and the universality is high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device and the semiconductor device. Background Art

[0002] At present, the distance between the metal gate and the contact hole of the semiconductor device prepared by the relevant semiconductor device preparation technology is large, and the parasitic capacitance between the metal gate and the contact hole is small. When the wafer process is a mature process of 28nm process and above, the distance between the contact hole and the gate is large, and the parasitic capacitance between the two is small and can be ignored. However, when the wafer process is miniaturized to below 14nm process and the distance between the contact hole and the gate is reduced to about 10nm, the contact hole becomes a long and thin strip, resulting in an increase in the parasitic capacitance area between the contact hole and the gate. When the distance between the contact hole and the gate is reduced and the parasitic capacitance area is increased, the parasitic capacitance between the contact hole and the gate is significantly increased, affecting the performance of the semiconductor device.

[0003] In order to reduce the parasitic capacitance between the contact hole and the gate, the relevant semiconductor device manufacturing technology usually uses sidewalls made of low dielectric constant materials on both sides of the gate. However, when the wafer process continues to shrink, a large parasitic capacitance will still be generated between the contact hole and the gate. The research and development of sidewall materials with lower dielectric constants requires a lot of manpower and material resources, and the R&D cost is high. Therefore, the method of reducing the parasitic capacitance between the metal gate and the contact hole in the relevant semiconductor device manufacturing technology still has the problem of being unable to be applied to multiple wafer processes and having low versatility. Summary of the Invention

[0004] In view of this, the object of the present invention is to provide a method for preparing a semiconductor device and a semiconductor device, which reduces the relative area between the metal gate and the contact hole, reduces the parasitic capacitance between the metal gate and the contact hole, and improves the performance of the semiconductor device.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing a preset substrate; wherein the preset substrate includes an active area, a gate electrode located above the active area, and sidewalls on both sides of the gate electrode;

[0008] Etching back the gate electrode to form a groove;

[0009] Filling the groove with a decomposable sacrificial material to form a sacrificial layer; wherein the surface of the sacrificial layer is flush with the surface of the sidewall;

[0010] Deposition of shielding layers;

[0011] The sacrificial layer is decomposed into gas which volatilizes through the shielding layer to form an air gap structure.

[0012] Furthermore, an embodiment of the present invention provides a first possible implementation of the first aspect, wherein the method for preparing the semiconductor device further includes:

[0013] forming a second interlayer dielectric layer above the shielding layer;

[0014] Etching contact holes on both sides of the gate electrode until the source and drain electrodes on both sides of the active area are exposed;

[0015] The contact hole is filled with a conductive material to form a contact hole electrode.

[0016] Furthermore, an embodiment of the present invention provides a second possible implementation of the first aspect, wherein the step of forming the preset substrate includes:

[0017] forming a dummy gate structure above the active region of the substrate;

[0018] forming sidewalls made of a low dielectric constant material on both sides of the dummy gate structure;

[0019] Depositing a first interlayer dielectric layer at a position on the surface of the substrate where the dummy gate structure and the sidewall spacer are not formed;

[0020] The dummy gate structure is removed and a conductive material is filled to form the gate electrode.

[0021] Furthermore, an embodiment of the present invention provides a third possible implementation of the first aspect, wherein the material of the sacrificial layer includes polypropylene carbonate.

[0022] Furthermore, an embodiment of the present invention provides a fourth possible implementation of the first aspect, wherein the step of filling the groove with a decomposable sacrificial material to form a sacrificial layer includes:

[0023] The polypropylene carbonate material is filled into the groove and cured to form the sacrificial layer.

[0024] In a second aspect, an embodiment of the present invention further provides a semiconductor device, comprising: a substrate, a gate electrode, a spacer, and a shielding layer;

[0025] The gate electrode is located above the active area of ​​the substrate;

[0026] The sidewall spacers are located on both sides of the gate electrode, and the height of the sidewall spacers is higher than the height of the gate electrode;

[0027] The shielding layer is located above the gate electrode and the sidewall, and an air gap structure is formed among the shielding layer, the sidewall and the gate electrode.

[0028] Furthermore, an embodiment of the present invention provides a first possible implementation of the second aspect, wherein the semiconductor device further comprises: a first interlayer dielectric layer, a second interlayer dielectric layer, and a contact hole electrode;

[0029] The first interlayer dielectric layer is located above the source and drain electrodes; the second interlayer dielectric layer is located above the shielding layer;

[0030] The contact hole electrodes are located on both sides of the gate electrode, and the contact hole electrodes penetrate the second interlayer dielectric layer, the shielding layer and the first interlayer dielectric layer.

[0031] Furthermore, an embodiment of the present invention provides a second possible implementation of the second aspect, wherein the material of the shielding layer includes silicon nitride or silicon carbon nitride.

[0032] Furthermore, an embodiment of the present invention provides a third possible implementation of the second aspect, wherein the material of the sidewall spacer includes SiBCN or SiOCN.

[0033] Furthermore, an embodiment of the present invention provides a fourth possible implementation of the second aspect, wherein the material of the first interlayer dielectric layer includes silicon oxide, and the material of the second interlayer dielectric layer includes silicon oxide.

[0034] An embodiment of the present invention provides a method for manufacturing a semiconductor device and a semiconductor device. The method comprises: providing a predetermined substrate; wherein the predetermined substrate comprises an active area, a gate electrode located above the active area, and sidewalls on both sides of the gate electrode; etching back the gate electrode to form a groove; filling the groove with a decomposable sacrificial material to form a sacrificial layer; wherein the surface of the sacrificial layer is flush with the surface of the sidewalls; depositing a shielding layer; and allowing the sacrificial layer to decompose into a gas that evaporates through the shielding layer to form an air gap structure. The present invention reduces the height of the metal gate by etching back the gate electrode to form a groove. By depositing a decomposable sacrificial material at the position of the groove and, after covering it with the shielding layer, allowing the decomposable sacrificial material to decompose into a gas that evaporates, an air gap structure is formed at the top of the metal gate. This reduces the relative area between the metal gate and the contact hole, reduces the parasitic capacitance between the metal gate and the contact hole, improves the performance of the semiconductor device, reduces the manufacturing cost, and can reduce the parasitic capacitance between the metal gate and the contact hole under various wafer manufacturing processes, thus having high versatility.

[0035] Other features and advantages of the embodiments of the present invention will be described in the following description, or some features and advantages can be inferred or determined without doubt from the description, or can be learned by implementing the above-mentioned technologies of the embodiments of the present invention.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 shows a schematic diagram of the structure of a related semiconductor device;

[0039] Figure 2 A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention is shown;

[0040] Figure 3a A schematic diagram of a preset base structure provided by an embodiment of the present invention is shown;

[0041] Figure 3b to Figure 3g A flowchart of manufacturing a semiconductor device provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0043] See for example Figure 1 As shown in the schematic diagram of the related semiconductor device structure, the preparation process of the related semiconductor device preparation technology includes: gate deposition and etching on the active area 100 of the substrate, depositing low dielectric constant material on both sides of the gate to form sidewalls 103, depositing a first interlayer dielectric layer 104 on the source and drain 101, removing the polysilicon gate to fill the gate electrode 102, depositing a gate shield layer 105 to protect the gate electrode 102, continuing to deposit the first interlayer dielectric layer 104, etching contact holes 106 on the first interlayer dielectric layer 104 and filling them with metal materials to form a semiconductor device.

[0044] Related semiconductor device manufacturing technologies typically use low-dielectric-constant sidewall materials to reduce the parasitic capacitance between the metal gate and the contact hole. For example, low-dielectric-constant materials such as SiBCN or SiOCN are used to form the sidewalls. The dielectric constant of SiBCN is 5.0 to 5.2, and the dielectric constant of SiOCN is 4.1 to 5.2. However, as wafer manufacturing processes continue to shrink, a large parasitic capacitance will still be generated between the metal gate and the contact hole. The development of sidewall materials with lower dielectric constants faces many difficulties, making the manufacturing cost of semiconductor devices higher. Therefore, the methods used in related semiconductor device manufacturing technologies to reduce the parasitic capacitance between the metal gate and the contact hole are not applicable to a variety of wafer manufacturing processes, resulting in low versatility.

[0045] In order to improve the above problems, embodiments of the present invention provide a method for manufacturing a semiconductor device and a semiconductor device. The embodiments of the present invention are described in detail below.

[0046] This embodiment provides a method for preparing a semiconductor device, which can be applied to semiconductor process equipment. Figure 2 The method for preparing a semiconductor device shown in the flowchart includes the following steps:

[0047] Step S202, providing a preset substrate;

[0048] See for example Figure 3a As shown in the schematic diagram of the preset substrate structure, the preset substrate includes an active area 100, a gate electrode 102 located above the active area 100, and sidewalls 103 on both sides of the gate electrode 102, wherein the gate electrode 102 can be made of metal material, for example.

[0049] Step S204, etching back the gate electrode to form a groove;

[0050] See for example Figure 3b to Figure 3g As shown in the preparation flow chart of the semiconductor device, the gate electrode 102 of the preset substrate is etched back to form a groove 302 to reduce the height of the gate electrode 102. The depth of the groove 302 is less than the depth of the gate electrode 102, that is, only a portion of the gate electrode 102 is etched.

[0051] In one embodiment, the depth of the groove may range from the depth of the gate electrode before etching*30% to the depth of the gate electrode before etching*50%.

[0052] When groove etching is performed on the gate electrode, by etching back 30% to 50% of the depth of the gate electrode, the height of the gate electrode can be effectively reduced, thereby reducing the relative area and parasitic capacitance between the gate electrode and the contact hole, and avoiding the low height of the gate electrode affecting the device performance.

[0053] Step S206 , filling the groove with a decomposable sacrificial material to form a sacrificial layer;

[0054] like Figure 3c As shown, a decomposable sacrificial material is filled into the groove 302 to form a sacrificial layer 303, and the upper surface of the sacrificial layer 303 is flush with the upper surface of the sidewall 103;

[0055] Step S208, depositing a shielding layer;

[0056] like Figure 3d As shown, a shielding layer 304 is deposited on the sacrificial layer 303 to provide support after the air gap structure is formed in the sacrificial layer 303. The shielding layer 304 may include a porous structure to facilitate the volatilization of gases decomposed from the sacrificial layer 303 through the shielding layer 304. The thickness of the shielding layer 304 may be within 10 nm.

[0057] In step S210 , the sacrificial layer is decomposed into gas, which volatilizes through the shielding layer to form an air gap structure.

[0058] For example, the sacrificial layer may be decomposed into gas through an annealing process.

[0059] like Figure 3e As shown, the wafer is heated to a decomposition temperature and maintained for a predetermined time, causing the sacrificial layer 303 to gradually decompose into gas, which is then volatilized through the shielding layer 304 to form an air gap structure 305. The decomposition temperature is the temperature at which the sacrificial layer 303 can decompose into gas, and the predetermined time is related to the decomposition rate of the sacrificial layer 303 and the thickness of the shielding layer 304. By decomposing the sacrificial layer 303 to form the air gap structure 305, the height of the metal gate is reduced. Since the air gap structure is an insulating material with the lowest dielectric constant, the dielectric constant between the gate and the contact hole is reduced, and the relative area between the gate and the contact hole is reduced, further reducing the parasitic capacitance between the gate and the contact hole, thereby improving the overall RC delay of the device.

[0060] The preparation method of the above-mentioned semiconductor device provided in this embodiment reduces the height of the metal gate by etching back the gate electrode to form a groove, and forms an air gap structure on the top of the metal gate by depositing a decomposable sacrificial material at the position of the groove and decomposing the decomposable sacrificial material into gas and volatilizing it after covering the shielding layer, thereby reducing the relative area between the metal gate and the contact hole, reducing the parasitic capacitance between the metal gate and the contact hole, improving the performance of the semiconductor device, reducing the preparation cost, and being able to reduce the parasitic capacitance between the metal gate and the contact hole under various wafer processes, with high versatility.

[0061] In one embodiment, the method for preparing a semiconductor device provided in this embodiment further includes:

[0062] forming a second interlayer dielectric layer above the shielding layer;

[0063] Contact holes are etched on both sides of the gate electrode until the source and drain electrodes on both sides of the active area are exposed;

[0064] The contact hole is filled with a conductive material to form a contact hole electrode, wherein the conductive material may be, for example, a metal material.

[0065] like Figure 3f As shown, an interlayer dielectric layer is continuously deposited above the shielding layer 304 to form a second interlayer dielectric layer 306, and contact holes are etched on both sides of the gate electrode 102 until the source and drain electrodes 101 on both sides of the active area 100 are exposed. The height of the contact holes obtained by etching is the sum of the heights of the first interlayer dielectric layer 301, the shielding layer 304, and the second interlayer dielectric layer 306. A conductive material is filled into the contact holes to form contact hole electrodes 106, thereby forming a final semiconductor device.

[0066] In one embodiment, this embodiment provides a specific implementation of forming a preset substrate:

[0067] forming a dummy gate structure above the active region of the substrate;

[0068] forming sidewalls of a low dielectric constant material on both sides of the dummy gate structure;

[0069] Depositing a first interlayer dielectric layer at a position on the substrate surface where the dummy gate structure and the low-k dielectric constant sidewall are not formed;

[0070] The dummy gate structure is removed and a conductive material is filled to form a gate electrode.

[0071] The dummy gate structure is deposited and etched on the active area 100. The dummy gate structure can be a polysilicon gate. A low dielectric constant material is deposited on both sides of the dummy gate structure to form a sidewall 103. Then, a first interlayer dielectric layer 301 is deposited on the source and drain 101. The surface of the sidewall 103 is flush with the surface of the first interlayer dielectric layer 301. The dummy gate structure is then etched away and the gate electrode 102 is filled to form a structure as shown in FIG. Figure 3a The preset base shown.

[0072] In one embodiment, the material of the sacrificial layer provided in this embodiment includes polypropylene carbonate.

[0073] The material of the sacrificial layer can be other materials that can be thermally decomposed to form gas, such as polypropylene carbonate; it can also be a material that can be photodecomposed to form gas, and the light irradiation annealing process on the wafer can decompose the sacrificial layer into gas and volatilize it.

[0074] In one embodiment, this embodiment provides a specific implementation of filling the groove with a decomposable sacrificial material to form a sacrificial layer:

[0075] The groove is filled with polypropylene carbonate material and cured to form a sacrificial layer.

[0076] The groove is filled with a polypropylene carbonate material and heated to a curing temperature for curing to form a solid sacrificial layer. The curing temperature is lower than the decomposition temperature of the decomposable sacrificial material, and the heating and curing does not cause the decomposable sacrificial material to decompose.

[0077] The method for preparing the above-mentioned semiconductor device provided in this embodiment reduces the height of the gate electrode by introducing an air gap structure. Since the air gap structure is an insulating material with the lowest dielectric constant, the dielectric constant between the gate and the contact hole is reduced, and the relative area between the gate and the contact hole is reduced, so that the parasitic capacitance between the gate and the contact hole is further reduced, thereby improving the overall RC delay of the semiconductor device and enhancing the performance of the semiconductor device.

[0078] Based on the above embodiment, this embodiment provides an example of applying the above method for preparing a semiconductor device to reduce the parasitic capacitance between the gate and the contact hole of the semiconductor device, such as Figure 3b to Figure 3g Please refer to the following steps for details:

[0079] Step 1, etching back the gate electrode 102 of the predetermined substrate to form a groove 302;

[0080] Step 2: Fill the groove 302 with a decomposable sacrificial material to form a sacrificial layer 303 , and make the surface of the sacrificial layer 303 flush with the surface of the first interlayer dielectric layer 301 ;

[0081] Step 3, depositing a shielding layer 304 on the surfaces of the sacrificial layer 303 and the first interlayer dielectric layer 301;

[0082] Step 4: performing an annealing process to gradually decompose the sacrificial layer 303 into gas, which is then volatilized through the shielding layer 304 to form an air gap structure 305;

[0083] Step 5: Continue depositing an interlayer dielectric layer on the shielding layer 304 to form a second interlayer dielectric layer 306;

[0084] In step 6, contact holes are etched on both sides of the gate electrode 102 and a conductive material is filled into the contact holes to form contact hole electrodes 106, thereby forming a final semiconductor device.

[0085] Corresponding to the method for preparing the semiconductor device provided in the above embodiment, an embodiment of the present invention provides a semiconductor device, which is prepared by the method for preparing the semiconductor device provided in the above embodiment, see Figure 3g The semiconductor device structure schematic diagram shown in FIG. 1 includes: a substrate, a gate electrode 102 , a spacer 103 and a shielding layer 304 ;

[0086] like Figure 3g As shown, the gate electrode 102 is located above the active area 100 of the substrate; the sidewalls 103 are located on both sides of the gate electrode 102, and the height of the sidewalls 103 is higher than the height of the gate electrode 102; the shielding layer 304 is located above the gate electrode 102 and the sidewalls 103, and an air gap structure 305 is formed between the shielding layer 304, the sidewalls 103 and the gate electrode 102.

[0087] In one embodiment, Figure 3g As shown, the semiconductor device provided in this embodiment further includes: a first interlayer dielectric layer 301, a second interlayer dielectric layer 306 and a contact hole electrode 106;

[0088] The first interlayer dielectric layer 301 is located above the source and drain electrodes 101 ; the second interlayer dielectric layer 306 is located above the shielding layer 304 ;

[0089] The contact hole electrodes 106 are located on both sides of the gate electrode 102 , and the contact hole electrodes penetrate the second interlayer dielectric layer 306 , the shielding layer 304 and the first interlayer dielectric layer 301 .

[0090] In one embodiment, the material of the shielding layer provided in this embodiment includes silicon nitride or silicon carbon nitride.

[0091] In one embodiment, the material of the sidewall spacer provided in this embodiment includes SiBCN or SiOCN.

[0092] In one implementation, the material of the first interlayer dielectric layer provided in this embodiment includes silicon oxide, and the material of the second interlayer dielectric layer includes silicon oxide.

[0093] In one implementation, the substrate provided in this embodiment includes a silicon substrate.

[0094] The semiconductor device provided in this embodiment has the same implementation principle and technical effects as those of the aforementioned embodiments. For the sake of brief description, for matters not mentioned in the semiconductor device embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0095] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0096] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0097] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a preset substrate; wherein the preset substrate includes an active area, a gate electrode located above the active area, and sidewalls on both sides of the gate electrode; Etching back the gate electrode to form a groove; Filling the groove with a decomposable sacrificial material to form a sacrificial layer; wherein the surface of the sacrificial layer is flush with the surface of the sidewall; Deposition of shielding layers; The sacrificial layer is decomposed into gas which volatilizes through the shielding layer to form an air gap structure.

2. The method for preparing a semiconductor device according to claim 1, wherein: Also includes: forming a second interlayer dielectric layer above the shielding layer; Etching contact holes on both sides of the gate electrode until the source and drain electrodes on both sides of the active area are exposed; The contact hole is filled with a conductive material to form a contact hole electrode.

3. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming the preset substrate includes: forming a dummy gate structure above the active region of the substrate; forming sidewalls made of a low dielectric constant material on both sides of the dummy gate structure; Depositing a first interlayer dielectric layer at a position on the surface of the substrate where the dummy gate structure and the sidewall spacer are not formed; The dummy gate structure is removed and a conductive material is filled to form the gate electrode.

4. The method for preparing a semiconductor device according to claim 1, wherein: The material of the sacrificial layer includes polypropylene carbonate.

5. The method for preparing a semiconductor device according to claim 4, wherein: Filling the groove with a decomposable sacrificial material to form a sacrificial layer comprises: The polypropylene carbonate material is filled into the groove and cured to form the sacrificial layer.

6. A semiconductor device, characterized in that: include: Substrate, gate electrode, sidewall and shielding layer; The gate electrode is located above the active area of ​​the substrate; The sidewall spacers are located on both sides of the gate electrode, and the height of the sidewall spacers is higher than the height of the gate electrode; The shielding layer is located above the gate electrode and the sidewall, and an air gap structure is formed among the shielding layer, the sidewall and the gate electrode.

7. The semiconductor device according to claim 6, wherein: Also includes: a first interlayer dielectric layer, a second interlayer dielectric layer and a contact hole electrode; The first interlayer dielectric layer is located above the source and drain electrodes; The second interlayer dielectric layer is located above the shielding layer; The contact hole electrodes are located on both sides of the gate electrode, and the contact hole electrodes penetrate the second interlayer dielectric layer, the shielding layer and the first interlayer dielectric layer.

8. The semiconductor device according to claim 6, wherein: The shielding layer is made of silicon nitride or silicon carbon nitride.

9. The semiconductor device according to claim 6, wherein: The material of the sidewall spacer includes SiBCN or SiOCN.

10. The semiconductor device according to claim 7, wherein The material of the first interlayer dielectric layer includes silicon oxide, and the material of the second interlayer dielectric layer includes silicon oxide.

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