Formation method of semiconductor device
By forming semiconductor fin trenches in the isolation layer and alternately stacking semiconductor layers, the problem of performance degradation in the all-around gate field-effect transistor process is solved, achieving higher device performance and stability.
Patent Information
- Application Number
- CN202410354627.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-26
- Publication Date
- 2025-10-03
AI Technical Summary
The existing all-around gate field-effect transistor process is complex, resulting in reduced semiconductor device performance, especially increased silicon germanium surface roughness and defect state density, which affect device performance.
First, a semiconductor fin trench is formed in the isolation layer, and then stacked layers of the first semiconductor layer and the second semiconductor layer are alternately stacked in the trench, avoiding the etching step and optimizing the process.
By avoiding etching damage, the performance of the semiconductor device is optimized, the on-state current is increased, and the stability of the threshold voltage is reduced.
Smart Images
Figure CN120751759A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor device. Background Art
[0002] As traditional metal oxide field-effect transistors (MOSFETs) and fin field-effect transistors (FinFETs) continue to shrink in size, edge effects and short-channel effects are becoming increasingly pronounced, making them unable to meet the demands of high-performance, high-reliability, and low-power electronic products. Gate-all-around field-effect transistors (GAAFETs), with their superior control over the semiconductor device channel, have been widely adopted by the industry.
[0003] However, the process of manufacturing a gate-all-around field-effect transistor is relatively complex, and the performance of the semiconductor device may be degraded during the manufacturing process. Summary of the Invention
[0004] The technical problem solved by the present invention is to optimize the performance of a semiconductor device by providing a method for forming a semiconductor device.
[0005] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate to form a plurality of sacrificial semiconductor fins located on the substrate; forming an isolation layer filled between the sacrificial semiconductor fins; removing a portion of the height of the sacrificial semiconductor fins to form a semiconductor fin groove located in the isolation layer; forming a stacked layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked in the semiconductor fin groove; removing a portion of the thickness of the isolation layer to make the stacked layer protrude from the remaining isolation layer to form a semiconductor fin.
[0006] Optionally, the step of forming the first semiconductor layer or the second semiconductor layer includes: forming a semiconductor material layer; performing a first planarization process on the semiconductor material layer; and etching back the semiconductor material layer that has undergone the first planarization process.
[0007] Optionally, the semiconductor material layer is formed by selective epitaxial growth.
[0008] Optionally, in the step of forming the semiconductor material layer, the thickness of the semiconductor material layer is in the range of 5 nanometers to 10 nanometers.
[0009] Optionally, the first semiconductor layer is a silicon layer, and the second semiconductor layer is a silicon germanium layer; or, the first semiconductor layer is a silicon germanium layer, and the second semiconductor layer is a silicon layer.
[0010] Optionally, the formation method further includes: removing the silicon germanium layer to form a full surround gate surrounding the silicon layer.
[0011] Optionally, the total number of the first semiconductor layer and the second semiconductor layer in the stacked layer is not less than 6 layers.
[0012] Optionally, the semiconductor fin trench depth is within a range of greater than or equal to 60 nanometers and less than or equal to 70 nanometers.
[0013] Optionally, the formation method further includes: forming a liner layer on the sidewalls of the sacrificial semiconductor fins before forming an isolation layer after forming a plurality of sacrificial semiconductor fins; in the step of removing a portion of the height of the sacrificial semiconductor fins, the liner layer on the sidewalls of the sacrificial semiconductor fins is also removed, and the liner layer on the sidewalls of the remaining sacrificial semiconductor fins is retained.
[0014] Optionally, the step of removing a portion of the height of the sacrificial semiconductor fin further includes: performing a second planarization process on the isolation layer using the sacrificial semiconductor fin as a stop layer.
[0015] Optionally, the first planarization process and the second planarization process are chemical mechanical polishing.
[0016] Optionally, the isolation layer is formed by flowable chemical vapor deposition.
[0017] Optionally, the material of the isolation layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.
[0018] Optionally, the liner layer is formed by atomic layer deposition.
[0019] Optionally, the material of the liner layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, and silicon oxynitride.
[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0021] In an embodiment of the present invention, a semiconductor fin trench is first formed in an isolation layer, and then a stacked layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked is formed in the semiconductor fin trench. Compared with the prior art process of forming a stacked layer by etching the first semiconductor layer and the second semiconductor layer, in this embodiment, the first semiconductor layer or the second semiconductor layer is formed in the space enclosed by the semiconductor fin trench, and no etching step is required, so it is not easily damaged during the process, thereby optimizing the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.
[0023] Figures 1 to 7 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0024] Figures 8 to 19 It is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0025] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0026] As described in the background art, the prior art all-around gate field effect transistor manufacturing process may cause the problem of reduced performance of semiconductor devices. Figures 1 to 7 The semiconductor structure formation method shown in the figure analyzes the reasons why the performance of semiconductor devices is reduced due to the manufacturing process. The semiconductor structure formation method mainly includes the following steps:
[0027] like Figure 1 As shown, a substrate 100 is provided, and an alternating stacking structure of a first semiconductor material layer 101 and a second semiconductor material layer 102 is sequentially formed on the surface of the substrate 100, wherein the first semiconductor material layer 101 is made of silicon germanium and the second semiconductor material layer 102 is made of silicon.
[0028] Continue to refer Figure 1 A hard mask M0 is formed on the second semiconductor material layer 102. The hard mask M0 comprises, from bottom to top, a first mask layer 103, a second mask layer 104, and a third mask layer 105. A photoresist is coated on the surface of the third mask layer 105 to form a photoresist pattern G0.
[0029] like Figure 2 As shown, the pattern of the photoresist pattern G0 is transferred to the hard mask M0 to pattern the hard mask M0 to form a hard mask pattern M1. The hard mask pattern M1 includes a first mask layer pattern M10, a second hard mask pattern M11 and a third hard mask pattern M12.
[0030] like Figure 3 As shown, substrate 100, first semiconductor material layer 101, and second semiconductor material layer 102 are patterned using hard mask pattern M1 to form fin structure 106. After patterning of first semiconductor material layer 101, side etching occurs, forming recess 107. The patterning process uses hydrogen to etch first semiconductor material layer 101 and second semiconductor material layer 102. After etching, substrate 100 is cleaned and the next step is entered.
[0031] like Figure 4 As shown, a dielectric layer 108 is formed to cover the hard mask pattern M1 and the fin structure 106 .
[0032] like Figure 5 As shown, an insulating isolation layer 109 covering the fin structure 106 and a planarization layer 110 covering the insulating isolation layer 109 are formed.
[0033] like Figure 6 As shown, the insulating isolation layer 109 and the planarization layer 110 are planarized until the dielectric layer 108 is exposed.
[0034] like Figure 7 As shown, the first hard mask pattern M1, part of the dielectric layer 108 and part of the insulating isolation layer 109 are removed to form an isolation material layer 110 consisting of the dielectric layer 108 and the insulating isolation layer 109, and the fin structure 106 is exposed; after removal, cleaning is performed and the next process is entered.
[0035] During the process of forming the fin structure 106, the etching gas hydrogen has a higher etching ratio than the first semiconductor material layer 101 and the second semiconductor material layer 102. However, during the hydrogen etching process, the silicon germanium of the first semiconductor material layer 101 is prone to side etching problems, resulting in increased surface roughness of the silicon germanium and increased defect state density, thereby reducing the performance of the semiconductor device (such as reduced on-state current and increased threshold voltage). In addition, the rough silicon germanium is easily oxidized to form silicon germanium oxide, which is easily soluble in water. During the cleaning process, the side etching of the silicon germanium is further exacerbated, thereby forming a recess 107. In this way, during the subsequent dummy gate removal process, the dummy gate material is likely to remain in the recess 107, which also reduces the performance of the semiconductor device.
[0036] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, the method comprising: providing a substrate, forming a plurality of sacrificial semiconductor fins on the substrate; forming an isolation layer to fill between the sacrificial semiconductor fins; removing a portion of the height of the sacrificial semiconductor fins to form a semiconductor fin trench in the isolation layer; forming a stacked layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked in the semiconductor fin trench; and removing a portion of the thickness of the isolation layer so that the stacked layer protrudes from the remaining isolation layer to form a semiconductor fin. In an embodiment of the present invention, a semiconductor fin trench is first formed in the isolation layer, and then a stacked layer in which a first semiconductor layer and a second semiconductor layer are alternately stacked in the semiconductor fin trench is formed. Since there is no need to form the stacked layer by etching the first semiconductor layer and the second semiconductor layer, the first semiconductor layer or the second semiconductor layer is less likely to be damaged during the process, thereby optimizing the performance of the semiconductor device.
[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0038] refer to Figures 8 to 19 It is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.
[0039] refer to Figures 8 to 10 A substrate 200 is provided, and a plurality of sacrificial semiconductor fins 201 are formed on the substrate 200. The plurality of sacrificial semiconductor fins 201 are used to pre-occupy spatial positions for the subsequent formation of semiconductor fins. It should be noted that for the sake of simplicity and clarity of the drawings, all embodiments of the present invention are illustrated using four sacrificial semiconductor fins 201 as an example, and the present invention is not limited thereto.
[0040] In this embodiment, the substrate 200 is used to provide a process platform for forming a semiconductor structure. The substrate 200 is a silicon substrate, and the material of the substrate 200 is single crystal silicon. In other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. The substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 is formed on the surface of the substrate 200 to improve the quality of pattern transfer.
[0041] In this embodiment, the sacrificial semiconductor fin 201 and the substrate 200 are integrally formed. The sacrificial semiconductor fin 201 is made of the same material as the substrate 200, namely silicon. In other embodiments, the sacrificial semiconductor fin 201 may be made of a different material than the substrate 200, for example, one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
[0042] refer to Figure 8 The specific process of forming a plurality of sacrificial semiconductor fins 201 on the substrate 200 includes: forming a hard mask Y1 for patterning the substrate 200 on the surface of the substrate 200, the hard mask including a first mask layer Y10, a second mask layer Y11 and a third mask layer Y12 sequentially located on the substrate 200, coating a layer of photoresist (not shown) on the surface of the third mask layer Y12, and patterning the photoresist by exposure and development to form a photoresist pattern J1.
[0043] refer to Figure 9 , the photoresist pattern J1 is transferred to the hard mask Y1 to form a hard mask pattern Y2, wherein the hard mask pattern Y2 includes a first mask layer pattern Y20, a second mask layer pattern Y21 and a third mask layer pattern Y22 sequentially located on the substrate 200.
[0044] refer to Figure 10 The hard mask pattern Y2 is transferred onto the substrate 200, and a portion of the substrate 200 is etched using a dry or wet etching process to form the plurality of sacrificial semiconductor fins 201. In this embodiment, the hard mask pattern Y2 is retained after the plurality of sacrificial semiconductor fins 201 are formed. In other embodiments, the hard mask pattern Y2 is removed after the plurality of sacrificial semiconductor fins 201 are formed.
[0045] It should be noted that the hard mask Y1 is less affected by semiconductor processing. For example, after high-temperature processing, the hard mask pattern Y2 formed is less susceptible to deformation and has a high degree of refinement. Therefore, the provision of the hard mask Y1 can ensure the pattern quality when it is transferred to the substrate 200. In other embodiments, patterning without a hard mask is also possible.
[0046] refer to Figure 11 , forming an isolation layer 202 between the sacrificial semiconductor fins 201. The isolation layer 202 is used to provide insulation between the semiconductor fins and also serves as the boundary of the semiconductor fin trench 205 when a portion of the sacrificial semiconductor fins 201 is subsequently removed, thereby enclosing the semiconductor fin trench 205 and facilitating the formation of a stacked layer within the semiconductor fin trench 205. Specifically, the isolation layer 202 also provides a process foundation for subsequently replacing the sacrificial semiconductor fins 201 with the stacked layer. Furthermore, the isolation layer 202 prevents external impurities from entering the semiconductor structure through the bottom of the substrate 200 and causing semiconductor device failure.
[0047] In this embodiment, the material of the isolation layer 202 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. The isolation layer material must have good chemical stability and strong isolation capability. As an example, the material of the isolation layer 202 is silicon oxide.
[0048] In actual processing, to ensure that the isolation layer 202 has good coverage and strong high-aspect-ratio filling capabilities, a flowable chemical vapor deposition (FCVD) process is used in the method for forming the isolation layer 202. The flowable chemical vapor deposition method includes the following steps: placing the substrate 200 on a stage in a deposition chamber, introducing gases such as an aminosilane compound and a nitrogen-containing compound into the deposition chamber, and using a thermal energy source or a plasma energy source to provide energy to cause the gases in the chamber to decompose and combine, thereby forming a relatively fluid silicon-containing film on the substrate 200, thereby forming the isolation layer 202, such as a silicon nitride material.
[0049] In this embodiment, after the flowable chemical vapor deposition (FCVD) process is adopted, the isolation layer 202 is subjected to an annealing process to improve the density of the isolation layer 202 film, that is, to harden the isolation layer 202 .
[0050] Continue to refer Figure 11 After forming a plurality of sacrificial semiconductor fins 201 and before forming an isolation layer 202, a liner layer 203 is formed on the sidewalls of the sacrificial semiconductor fins 201; the liner layer 203 is used to repair damage to the surface of the sacrificial semiconductor fins 201 during the process, which is conducive to the subsequent formation of smooth semiconductor trench sidewalls.
[0051] In this embodiment, the material of the liner layer 203 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, and silicon oxynitride. As an example, the material of the liner layer 203 is silicon nitride.
[0052] In this embodiment, the liner layer 203 is formed by atomic layer deposition (ALD) to cover the sidewalls of the sacrificial semiconductor fin 201 and the hard mask layer pattern Y2. ALD offers advantages such as thin and uniform films with a dense structure, no pinholes, and good adhesion to the sacrificial semiconductor fin 201.
[0053] Continue to refer Figure 11 After the step of forming the isolation layer 202 , the method further includes forming a first flat layer 204 covering the isolation layer 202 , where the first flat layer 204 is used to flatten the surface of the isolation layer 202 .
[0054] In this embodiment, the material of the first planar layer includes one or more of silicon oxide, silicon carbonitride, silicon carbon oxynitride, and silicon oxynitride. As an example, the material of the first planar layer 204 is silicon oxide.
[0055] In this embodiment, the first planar layer 204 is formed by chemical vapor deposition.
[0056] It should be noted that if the thickness of the first planarization layer 204 is too large, the process time for forming the first planarization layer will be increased, and if the thickness of the first planarization layer is too small, it will not be conducive to flattening the surface of the isolation layer 202. In this embodiment, the thickness of the first planarization layer 204 is within the range of 50 angstroms to 200 angstroms.
[0057] refer to Figures 12 to 13 , a portion of the height of the sacrificial semiconductor fin 201 is removed to form a semiconductor fin trench 205 located in the isolation layer 202; the formed semiconductor fin trench 205 is used to provide a position space for forming a semiconductor fin.
[0058] Continue to refer Figure 12 Before the step of removing a portion of the height of the sacrificial semiconductor fin 201, the method further includes: using the sacrificial semiconductor fin 201 as a stop layer, performing a second planarization process on the first planarization layer 204, the isolation layer 202 and the hard mask layer pattern Y2 to expose the surface of the sacrificial semiconductor fin 201 to be removed, thereby providing a process window for the subsequent removal of a portion of the height of the sacrificial semiconductor fin 201 and a portion of the liner layer 203.
[0059] In this embodiment, the second planarization process is a chemical mechanical polishing process.
[0060] Continue to refer Figure 13 The sacrificial semiconductor fin 201 is partially removed by dry etching to form a semiconductor fin trench 205 in the isolation layer 202. Because the dry etching process has a fast etching rate and the surface of the formed pattern is smooth, it provides a better contact interface for the subsequent process of forming a film layer.
[0061] It should be noted that if the depth of the semiconductor fin trench 205 is too great, the process time required to remove the sacrificial semiconductor fin 201 is increased. If the depth of the semiconductor fin trench 205 is too small, it will not provide the required space for the stacked layers, affecting the on-state current of the semiconductor transistor. In this embodiment, the depth of the semiconductor fin trench 205 is within a range of greater than or equal to 60 nanometers and less than or equal to 70 nanometers.
[0062] Continue to refer Figure 13 In the step of removing a portion of the height of the sacrificial semiconductor fin 201 , the liner layer 203 on the sidewall of the sacrificial semiconductor fin is also removed, and the liner layer on the sidewall of the remaining sacrificial semiconductor fin is retained.
[0063] refer to Figure 14It should be noted that, in this embodiment, before forming the first semiconductor layer and the second semiconductor layer, a second flattening layer 206 may be formed at the bottom of the semiconductor fin trench 205 to provide a flat surface for the subsequent formation of the first semiconductor layer or the second semiconductor layer. The second flattening layer 206 covers the remaining sacrificial semiconductor fin 201 and the liner layer 203 on its sidewalls.
[0064] In this embodiment, the material of the second flat layer 206 is the same as that of the substrate 200. In other embodiments, the material of the second flat layer 206 and that of the substrate 200 may be different.
[0065] In this embodiment, the second planarization layer material is formed by an epitaxial growth process, the second planarization layer material is subjected to a third planarization process, and the second planarization layer material subjected to the third planarization process is etched back to form the second planarization layer 206. The third planarization process is chemical mechanical polishing.
[0066] It should be noted that if the thickness of the second planar layer 206 is too large, the film forming process time will be increased. If the thickness of the second planar layer 206 is too small, the planarization effect will be easily affected. In this embodiment, the thickness of the second planar layer 206 is in the range of 5 nanometers to 10 nanometers.
[0067] refer to Figures 15 to 17 A stacked layer 209 consisting of alternating first and second semiconductor layers 207 and 208 is formed in the semiconductor fin trench 205. The first semiconductor layer 207 is used to form the channel of the semiconductor transistor, and the second semiconductor layer 208 is a sacrificial layer used to define the distance between adjacent channels of the subsequently formed GAA gate transistor. It should be noted that, as another embodiment, the second semiconductor layer 208 can be used to form the conduction channel of the semiconductor transistor, with the corresponding first semiconductor layer 207 serving as a sacrificial layer.
[0068] The first semiconductor layer 207 and the second semiconductor layer 208 have different functions and are accordingly made of different materials. In this embodiment, the first semiconductor layer 207 may be a silicon layer, and the second semiconductor layer 208 may be a silicon-germanium layer; alternatively, the first semiconductor layer 207 may be a silicon-germanium layer, and the second semiconductor layer 208 may be a silicon layer. In other embodiments, the sacrificial layers in the first semiconductor layer 207 and the second semiconductor layer 208 may also include other materials, such as one or more of silicon carbide, gallium nitride, gallium phosphide, indium phosphide, indium arsenide, gallium arsenide, and indium gallium.
[0069] For the convenience of description, the present invention is described by taking the first semiconductor layer 207 as a silicon layer and the second semiconductor layer 208 as a silicon germanium layer, that is, the second semiconductor layer 208 as a sacrificial layer as an example.
[0070] In this embodiment, the steps of forming the first semiconductor layer 207 or the second semiconductor layer 208 include: forming a semiconductor material layer; performing a first planarization process on the semiconductor material layer; and etching back the semiconductor material layer after the first planarization process.
[0071] Continue to refer Figure 15 , the first semiconductor layer 207 can be formed on the surface of the second flat layer 206 through a selective epitaxial process. The film layer grown by the selective epitaxial process has a uniform thickness and a dense structure. In addition, when the selective epitaxial process is adopted, the first semiconductor layer 207 is only formed on the surface of the second flat layer 206 at the bottom of the semiconductor fin trench 205, and is not formed on the sidewall and surface of the isolation layer 202, thereby having better film formation quality.
[0072] The first semiconductor layer 207 is subjected to a first planarization process to smooth the surface of the semiconductor material layer, thereby providing a flat film-forming interface for subsequent processes. Specifically, the first planarization process is chemical mechanical polishing.
[0073] The first semiconductor layer 207 that has undergone the first planarization process is etched back to obtain a first semiconductor layer of a preset thickness. Specifically, the etch back is a dry etching process.
[0074] Continue to refer Figure 16 In this embodiment, the second semiconductor layer 208 can be formed on the surface of the first semiconductor layer 207 through a selective epitaxial process; the second semiconductor layer 208 is subjected to a first planarization process; and the second semiconductor layer 208 subjected to the first planarization process is etched back. The first planarization process is chemical mechanical polishing, and the etch back is a dry etching process. The specific process and advantages of forming the second semiconductor layer 207 are similar and will not be repeated here.
[0075] Continue to refer Figure 17 The above-mentioned process steps of forming the first semiconductor layer 207 and the second semiconductor layer 208 are repeated, and the formed semiconductor material layer is subjected to a first planarization and etching back process to form a stacked layer 209 composed of the first semiconductor layer 207 and the second semiconductor layer 208 alternately stacked. The number of repetitions can be set according to specifications such as the number of channels in the stacked layer 209.
[0076] It should be noted that if the total number of first and second semiconductor layers in the stack 209 (i.e., the total number of layers in the stack 209) is too small, the on-state current may be affected and fail to meet the design specifications. If the total number of first and second semiconductor layers in the stack 209 is too large, the number of repetitions may be excessive, affecting process efficiency. In this embodiment, the total number of first and second semiconductor layers in the stack 209 (i.e., the total number of layers in the stack 209) is no less than six.
[0077] It should be noted that in the step of forming the semiconductor material layer, if the thickness of the first semiconductor layer 207 is too large, the process time of forming the first semiconductor layer will be increased. If the thickness of the first semiconductor layer 207 is too small, it will be easily removed or damaged during the chemical mechanical polishing process or the back etching process, affecting the on-state current of the semiconductor device. In this embodiment, the thickness of the first semiconductor layer material 207 is in the range of 5 nanometers to 10 nanometers.
[0078] It should be noted that if the thickness of the second semiconductor layer 208 is too large, the process time for forming and removing the second semiconductor layer will be increased. If the thickness of the second semiconductor layer 208 is small, it will be easily removed or damaged during the chemical mechanical polishing process or the back etching process, and the vertical distance between the first semiconductor layers 207 cannot be guaranteed. For example, it will affect the film formation space of the gate and gate oxide layer of the semiconductor device, thereby affecting the performance of the semiconductor device. In this embodiment, the thickness of the first semiconductor layer material 207 is in the range of 5 nanometers to 10 nanometers.
[0079] refer to Figure 18 , a portion of the isolation layer 202 is removed so that the stacked layer 209 protrudes from the remaining isolation layer 202 to form a semiconductor fin 210 .
[0080] In this embodiment, a dry or wet etching process is used to remove a portion of the isolation layer 202, exposing the stacked layer 209 and forming the semiconductor fin 210. The stacked layer 209 protrudes from the remaining isolation layer 202. The remaining isolation layer 202 and the liner layer 203 remaining on the sidewalls of the sacrificial semiconductor fin constitute the insulating isolation layer 211.
[0081] refer to Figure 19 In this embodiment, the first semiconductor layer 207 is a silicon layer, and the second semiconductor layer 208 is a silicon germanium layer. The silicon germanium layer is removed (i.e., the second semiconductor layer 208 is removed) to form a full surround gate 212 surrounding the silicon layer (i.e., surrounding the first semiconductor layer 207).
[0082] In this embodiment, the silicon germanium layer of the second semiconductor layer 208 is removed using a dry or wet etching process to provide space for forming the fully enclosed gate 212. The step of forming the fully enclosed gate 212 includes forming a gate dielectric layer (not shown) surrounding and covering the silicon layer of the first semiconductor layer 207, and a gate electrode layer (not shown) covering the gate dielectric layer. The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the silicon layer of the first semiconductor layer 207, and the gate electrode layer is used to electrically connect the fully enclosed gate to an external circuit.
[0083] In this embodiment, the material of the gate electrode layer includes one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.
[0084] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or aluminum oxide. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include the gate oxide layer.
[0085] It should be noted that, before forming the full surround gate 212 , the process also includes forming a source / drain doping layer, a sidewall layer between the source / drain doping layer and the gate structure layer, and the like.
[0086] In summary, in the semiconductor structure formation method provided by the embodiment of the present invention, a plurality of sacrificial semiconductor fins are formed on the substrate; an isolation layer is formed to fill between the sacrificial semiconductor fins; a portion of the height of the sacrificial semiconductor fins is removed to form a semiconductor fin trench located in the isolation layer; a stacked layer of alternating first and second semiconductor layers is formed in the semiconductor fin trench; and a portion of the thickness of the isolation layer is removed so that the stacked layer protrudes from the remaining isolation layer to form the semiconductor fin. In the embodiment of the present invention, semiconductor fin trenches are first formed in the isolation layer, and then a stacked layer of alternating first and second semiconductor layers is formed in the semiconductor fin trenches. Since there is no need to form the stacked layer by etching the first and second semiconductor layers, the first semiconductor layer or the second semiconductor layer is not easily damaged during the process, thereby optimizing the performance of the semiconductor device.
[0087] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.
Claims
1. A method for forming a semiconductor device, characterized in that: include: providing a substrate; forming a plurality of sacrificial semiconductor fins on the substrate; forming an isolation layer filled between the sacrificial semiconductor fins; removing a portion of the height of the sacrificial semiconductor fin to form a semiconductor fin trench in the isolation layer; forming a stacked layer in which first semiconductor layers and second semiconductor layers are alternately stacked in the semiconductor fin trench; A portion of the isolation layer is removed to allow the stacked layer to protrude from the remaining isolation layer, thereby forming a semiconductor fin.
2. The forming method according to claim 1, wherein: The step of forming the first semiconductor layer or the second semiconductor layer includes: forming a semiconductor material layer; performing a first planarization process on the semiconductor material layer; The semiconductor material layer that has undergone the first planarization process is etched back.
3. The forming method according to claim 2, wherein: The semiconductor material layer is formed by selective epitaxial growth.
4. The forming method according to claim 2, wherein: In the step of forming the semiconductor material layer, the thickness of the semiconductor material layer is in the range of 5 nanometers to 10 nanometers.
5. The forming method according to claim 1, wherein: The first semiconductor layer is a silicon layer, and the second semiconductor layer is a silicon germanium layer; or the first semiconductor layer is a silicon germanium layer, and the second semiconductor layer is a silicon layer.
6. The forming method according to claim 5, wherein: The forming method further includes: removing the silicon germanium layer to form a full surround gate surrounding the silicon layer.
7. The forming method according to claim 1, wherein: The total number of the first semiconductor layer and the second semiconductor layer in the stacked layer is not less than 6 layers.
8. The forming method according to claim 1, wherein: The semiconductor fin trench depth is within a range of greater than or equal to 60 nanometers and less than or equal to 70 nanometers.
9. The forming method according to claim 1, wherein: The forming method further includes: forming a liner layer on the sidewalls of the sacrificial semiconductor fins after forming the plurality of sacrificial semiconductor fins and before forming the isolation layer; The step of removing a portion of the height of the sacrificial semiconductor fin also removes the liner layer on the sidewall of the sacrificial semiconductor fin, and retains the liner layer on the sidewall of the remaining sacrificial semiconductor fin.
10. The forming method according to claim 9, wherein: The liner layer is formed by atomic layer deposition.
11. The forming method according to claim 9, wherein: The material of the liner layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, and silicon oxynitride.
12. The forming method according to claim 1, wherein: The step of removing a portion of the height of the sacrificial semiconductor fin further includes: performing a second planarization process on the isolation layer using the sacrificial semiconductor fin as a stop layer.
13. The forming method according to claim 12, wherein: The first planarization process and the second planarization process are chemical mechanical polishing.
14. The forming method according to claim 1, wherein: The isolation layer is formed by flowable chemical vapor deposition.
15. The forming method according to claim 1, wherein: The material of the isolation layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.