Array substrate, preparation method thereof and flat panel detector

Abstract

The invention discloses an array substrate and a preparation method thereof and a flat panel detector, and mainly relates to the technical field of photoelectricity, an active switch layer internally comprises at least one active switch, a photodiode layer internally comprises at least one photodiode, and a signal transmission line layer internally comprises at least one signal transmission line. The active switch, the photodiode and the signal transmission line are connected in sequence; the photodiode comprises an N-type doped layer, a composite intrinsic layer and a P-type doped layer, the composite intrinsic layer is arranged between the N-type doped layer and the P-type doped layer, the N-type doped layer is connected with the active switch, the P-type doped layer is connected with the signal transmission line, the composite intrinsic layer comprises a main body intrinsic layer and a first buffer intrinsic layer, the first buffer intrinsic layer is arranged on the main body intrinsic layer, and the second buffer intrinsic layer is arranged on the main body intrinsic layer. And the crystallization rate of the first buffer intrinsic layer is higher than that of the main body intrinsic layer, so that the generation amount of dark current can be reduced through the design.

Description

Technical Field

[0001] The present application relates to the field of optoelectronic technology, and in particular to an array substrate and a preparation method thereof, and a flat panel detector. Background Art

[0002] Because photodiodes are fabricated using semiconductor materials and their production equipment is compatible with array substrate production equipment, photodiodes have recently begun to be manufactured using array substrates and are widely used in invisible light sensing flat-panel devices. Due to their high sensitivity, wide dynamic range, and excellent linear response characteristics, photodiodes have found widespread application in a variety of fields, including medical imaging and security testing.

[0003] However, existing photodiodes have the phenomenon of dark current, which will generate noise and thus have a negative impact on imaging quality and detection accuracy. Therefore, how to reduce the dark current of photodiodes has become a technical problem that needs to be solved urgently. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate and a preparation method thereof and a flat panel detector, which can reduce the amount of dark current generated.

[0005] The present application discloses an array substrate, comprising an active switch layer, a photodiode layer, a signal transmission line layer, and a light conversion layer. The photodiode layer, the signal transmission line layer, and the light conversion layer are sequentially arranged on the active switch layer. The active switch layer includes at least one active switch, the photodiode layer includes at least one photodiode, and the signal transmission line layer includes at least one signal transmission line. The active switch, the photodiode, and the signal transmission line are sequentially connected.

[0006] The photodiode includes an N-type doped layer, a composite intrinsic layer and a P-type doped layer, the composite intrinsic layer is arranged between the N-type doped layer and the P-type doped layer, the N-type doped layer is connected to the active switch, and the P-type doped layer is connected to the signal transmission line. The composite intrinsic layer includes a main intrinsic layer and a first buffer intrinsic layer, the first buffer intrinsic layer is arranged on the main intrinsic layer, and the crystallization rate of the first buffer intrinsic layer is higher than the crystallization rate of the main intrinsic layer.

[0007] Optionally, the N-type doped layer, the first buffer intrinsic layer, the main intrinsic layer and the P-type doped layer are stacked in sequence on the active switching layer.

[0008] Optionally, the N-type doped layer, the main intrinsic layer, the first buffer intrinsic layer and the P-type doped layer are stacked in sequence on the active switching layer.

[0009] Optionally, the composite intrinsic layer also includes a second buffer intrinsic layer, and the N-type doped layer, the first buffer intrinsic layer, the main intrinsic layer, the second buffer intrinsic layer and the P-type doped layer are stacked in sequence on the active switching layer; the crystallization rate of the second buffer intrinsic layer is higher than the crystallization rate of the main intrinsic layer.

[0010] Optionally, the first buffer intrinsic layer includes a first sub-buffer microcrystalline silicon and a second sub-buffer microcrystalline silicon, the second sub-buffer microcrystalline silicon is located between the first sub-buffer microcrystalline silicon and the main intrinsic layer, and the crystallization rate of the first sub-buffer microcrystalline silicon is higher than the crystallization rate of the second sub-buffer microcrystalline silicon;

[0011] Optionally, the second buffer intrinsic layer includes a third sub-buffer microcrystalline silicon and a fourth sub-buffer microcrystalline silicon, the third sub-buffer microcrystalline silicon is located between the fourth sub-buffer microcrystalline silicon and the main intrinsic layer, and the crystallization rate of the fourth sub-buffer microcrystalline silicon is higher than the crystallization rate of the third sub-buffer microcrystalline silicon.

[0012] Optionally, the thickness of the second buffer intrinsic layer is greater than the thickness of the first buffer intrinsic layer.

[0013] Optionally, the thickness of the first sub-buffer microcrystalline silicon is smaller than the thickness of the second sub-buffer microcrystalline silicon; and the thickness of the fourth sub-buffer microcrystalline silicon is smaller than the thickness of the third sub-buffer microcrystalline silicon.

[0014] The present application also discloses a method for preparing an array substrate, which includes:

[0015] forming a photodiode layer on the active switching layer;

[0016] forming a signal transmission line layer on the photodiode layer;

[0017] forming a light conversion layer on the signal transmission line layer;

[0018] The photodiode includes an N-type doped layer, a composite intrinsic layer and a P-type doped layer, the composite intrinsic layer is arranged between the N-type doped layer and the P-type doped layer, the N-type doped layer is connected to the active switch, and the P-type doped layer is connected to the signal transmission line. The composite intrinsic layer includes a main intrinsic layer and a first buffer intrinsic layer, the first buffer intrinsic layer is arranged on the main intrinsic layer, and the crystallization rate of the first buffer intrinsic layer is higher than the crystallization rate of the main intrinsic layer.

[0019] The present application also discloses a flat panel detector, which includes a signal processing unit and an array substrate. The signal processing unit is connected to the array substrate and is used to receive and process signals output by the array substrate.

[0020] Compared with the existing array substrate solution, the present application sets a composite intrinsic layer between the N-type doped layer and the P-type doped layer, and the composite intrinsic layer includes a main intrinsic layer and a first buffer intrinsic layer, and the crystallization rate of the first buffer intrinsic layer is higher than the crystallization rate of the main intrinsic layer, so that electrons are not easily gathered between the main intrinsic layer and the N-type doped layer, or holes are not easily gathered between the main intrinsic layer and the P-type doped layer. In this way, the electron-hole pairs excited by the light that is not converted by the light conversion layer can be avoided from recombining with it, thereby reducing the amount of dark current generated. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without inventive work. In the drawings:

[0022] Figure 1 is a schematic diagram of a flat panel detector according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of a first array substrate according to the first embodiment of the present application;

[0024] Figure 3 This is a schematic diagram of a first flat layer and a second flat layer according to the first embodiment of the present application;

[0025] Figure 4 is a schematic diagram of the second array substrate of the first embodiment of the present application;

[0026] Figure 5 is a schematic diagram of an array substrate according to a second embodiment of the present application;

[0027] Figure 6 is a schematic diagram of an array substrate according to a third embodiment of the present application;

[0028] Figure 7 This is a schematic diagram of a method for preparing an array substrate according to an embodiment of the present application.

[0029] Among them, 10, flat panel detector; 20, signal processing unit; 30, scan drive unit; 100, array substrate; 200, active switch layer; 210, active switch; 230, substrate; 231, first metal layer; 232, first insulating layer; 233, second metal layer; 234, second insulating layer; 235, first transparent electrode layer; 236, first transparent electrode; 300, photodiode layer; 310, photodiode; 320, N-type doped layer; 330, composite intrinsic layer; 340, first buffer intrinsic layer; 341, first sub Buffer microcrystalline silicon; 342, second sub-buffer microcrystalline silicon; 350, second buffer intrinsic layer; 351, third sub-buffer microcrystalline silicon; 352, fourth sub-buffer microcrystalline silicon; 370, main intrinsic layer; 360, P-type doped layer; 400, signal transmission line layer; 410, signal transmission line; 420, light-shielding metal block; 510, second transparent electrode layer; 511, second transparent electrode; 520, third insulating layer; 530, first flat layer; 540, fourth insulating layer; 550, second flat layer; 600, light conversion layer; 700, pixel unit area. DETAILED DESCRIPTION

[0030] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative. However, the present application can be implemented in many alternative forms and should not be construed as being limited to the embodiments described herein.

[0031] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate relative importance or implicitly specify the quantity of the technical features indicated. Therefore, unless otherwise specified, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features; "plurality" means two or more. The term "comprising" and any variations thereof are intended to be non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0032] In addition, terms indicating orientation or positional relationships such as “center,” “lateral,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside” are described based on the orientation or relative positional relationships shown in the accompanying drawings. They are merely simplified descriptions for the convenience of describing the present application, and do not indicate that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0033] Furthermore, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly, and may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on specific circumstances.

[0034] The present application is described in detail below with reference to the accompanying drawings and optional embodiments.

[0035] Figure 1 is a schematic diagram of a flat panel detector according to an embodiment of the present application, such as Figure 1 As shown, the present application discloses a flat panel detector 10 , which includes a signal processing unit 20 and an array substrate 100 . The signal processing unit 20 is connected to the array substrate 100 and is used to receive and process signals output by the array substrate 100 .

[0036] The flat panel detector 10 may be an X-ray detection device. The flat panel detector 10 further includes a scan driving unit 30 . The scan driving unit 30 is connected to the array substrate 100 .

[0037] Exemplarily, after receiving the invisible light, the array substrate 100 converts the invisible light into visible light, and then generates corresponding charges according to the intensity of the visible light. The scanning drive unit 30 controls the array substrate 100 to output the generated charges to the signal processing unit 20, and then the voltage is converted into a digital signal with a depth of 14-16 bits through the ADC (analog-to-digital converter).

[0038] The present application also discloses an array substrate 100, which can be used in the flat panel detector 10 described above. The present application provides the following design for the array substrate 100, which is specifically described through several embodiments:

[0039] Example 1:

[0040] Figure 2 is a schematic diagram of the first array substrate of the first embodiment of the present application, as shown in FIG. Figure 2As shown, the present application discloses an array substrate 100, which includes an active switching layer 200, a photodiode layer 300, a signal transmission line layer 400 and a light conversion layer 600. The photodiode layer 300, the signal transmission line layer 400 and the light conversion layer 600 are arranged in sequence on the active switching layer 200, and the active switching layer 200 includes at least one active switch 210, the photodiode layer 300 includes at least one photodiode 310, and the signal transmission line layer 400 includes at least one signal transmission line 410. The active switch 210, the photodiode 310 and the signal transmission line 410 are connected in sequence.

[0041] The photodiode 310 includes an N-type doped layer 320, a composite intrinsic layer 330 and a P-type doped layer 360. The composite intrinsic layer 330 is arranged between the N-type doped layer 320 and the P-type doped layer 360. The N-type doped layer 320 is connected to the active switch 210, and the P-type doped layer 360 is connected to the signal transmission line 410. The composite intrinsic layer 330 includes a main intrinsic layer 370 and a first buffer intrinsic layer 340. The first buffer intrinsic layer 340 is arranged on the main intrinsic layer 370. The crystallization rate of the first buffer intrinsic layer 340 is higher than the crystallization rate of the main intrinsic layer 370.

[0042] Exemplarily, the active switch layer 200 includes a substrate 230, a first metal layer 231, a first insulating layer 232, a second metal layer 233, a second insulating layer 234, and a first transparent electrode layer 235, wherein the first metal layer 231, the first insulating layer 232, the second metal layer 233, the second insulating layer 234, and the first transparent electrode layer 235 are sequentially arranged on the substrate 230, and the first transparent electrode layer 235 includes a plurality of first transparent electrodes 236, each of which is connected to an active switch 210.

[0043] Exemplarily, the active switch 210 can be a top-gate active switch 210 or a bottom-gate active switch 210, and there is no limitation here. This application takes the shape of the active switch 210 as a top-gate active switch 210 as an example. A scan line is also provided in the active switch layer 200, and the scan line can be provided in the first metal layer 231 or in the second metal layer 233, and there is no limitation here.

[0044] A second transparent electrode layer 510, a third insulating layer 520 and a first flat layer 530 are further included between the photodiode layer 300 and the signal transmission line layer 400. The second transparent electrode layer 510, the third insulating layer 520 and the first flat layer 530 are sequentially arranged on the photodiode layer 300. The second transparent electrode layer 510 includes a plurality of second transparent electrodes 511, and each second transparent electrode 511 is arranged on the P-type doped layer 360.

[0045] A fourth insulating layer 540 and a second planar layer 550 are further included between the signal transmission line layer 400 and the optical conversion layer 600 . The fourth insulating layer 540 and the second planar layer 550 are sequentially disposed on the signal transmission line layer 400 .

[0046] The scan lines and data lines of the array substrate 100 are arranged vertically and horizontally to divide a plurality of pixel unit areas 700. The scan lines are connected to the active switches 210 in the pixel unit areas 700 arranged in rows, the data lines are connected to the active switches 210 in the pixel unit areas 700 arranged vertically, and the signal transmission lines 410 are connected to the second transparent electrodes 511 of the photodiodes 310 in the pixel unit areas 700 arranged vertically.

[0047] In addition, the signal transmission line layer 400 also includes a light-shielding metal block 420, and the orthographic projection of the light-shielding metal block 420 on the substrate 230 covers the orthographic projection of the active switch 210 on the substrate 230. In simple terms, the light-shielding metal block 420 is located directly above the active switch 210, thereby avoiding the influence of the photocurrent generated on the active switch 210.

[0048] Exemplarily, when light converted by the light conversion layer 600 is irradiated onto the photodiode 310 , electron-hole pairs are excited, and a large number of electrons move toward the N-type doped layer 320 , and a large number of holes move toward the P-type doped layer 360 . However, since the existing photodiode has only N-type doped layers 320 and P-type doped layers 360 on both sides of the main intrinsic layer 370, there are many defects at the interfaces between the N-type doped layer 320 and the main intrinsic layer 370 and between the main intrinsic layer 370 and the P-type intrinsic layer, which leads to electrons gathering at the interface between the main intrinsic layer 370 and the N-type doped layer 320, and holes gathering at the interface between the main intrinsic layer 370 and the P-type doped layer 360. Under high temperature and other conditions, the N-type doped layer 320, the P-type doped layer 360 and the main intrinsic layer 370 will excite new electron-hole pairs and recombine with the electrons and holes gathered at the interface between the main intrinsic layer 370 and the N-type doped layer 320, the P-type doped layer 360, thereby resulting in a large dark current.

[0049] Compared with the existing array substrate 100, the present application sets a composite intrinsic layer 330 between the N-type doped layer 320 and the P-type doped layer 360, and the composite intrinsic layer 330 includes a main intrinsic layer 370 and a first buffer intrinsic layer 340, and the crystallization rate of the first buffer intrinsic layer 340 is higher than the crystallization rate of the main intrinsic layer 370, so that electrons are not easily gathered between the main intrinsic layer 370 and the N-type doped layer 320, or holes are not easily gathered between the main intrinsic layer 370 and the P-type doped layer 360, so that the electron-hole pairs excited by the light that is not converted by the light conversion layer 600 can be avoided from recombining with it, thereby reducing the amount of dark current generated.

[0050] In this embodiment, the composite intrinsic layer 330 also includes a second buffer intrinsic layer 350, and the N-type doped layer 320, the first buffer intrinsic layer 340, the main intrinsic layer 370, the second buffer intrinsic layer 350 and the P-type doped layer 360 are stacked in sequence on the active switching layer 200; the crystallization rate of the second buffer intrinsic layer 350 is higher than the crystallization rate of the main intrinsic layer 370.

[0051] In simple terms, in this embodiment, a buffer intrinsic layer is provided between the N-type doping layer 320 and the main intrinsic layer 370 , and between the P-type doping layer 360 and the main intrinsic layer 370 .

[0052] The main intrinsic layer 370 can be understood as an amorphous silicon intrinsic layer, and the first buffer intrinsic layer 340 and the second buffer intrinsic layer 350 can be understood as microcrystalline silicon intrinsic layers. The amorphous silicon intrinsic layer has a relatively uniform structure overall, without obvious distinction between grains and grain boundaries. The atomic density and bonding state are relatively consistent across the layer. The crystallization rate of the amorphous silicon intrinsic layer is extremely low, almost negligible, and it can be considered to be composed entirely of an amorphous phase. The microcrystalline silicon intrinsic layer, due to its inclusion of grains and grain boundaries, has a certain degree of microstructural heterogeneity and a certain degree of crystallization rate.

[0053] Therefore, in this embodiment, a first buffer intrinsic layer 340 is set between the N-type doped layer 320 and the main intrinsic layer 370, thereby reducing the electron accumulation between the N-type doped layer 320 and the main intrinsic layer 370, thereby reducing the recombination probability and thus reducing the dark current; and a second buffer intrinsic layer 350 is set between the P-type doped layer 360 and the main intrinsic layer 370, thereby reducing the hole accumulation between the P-type doped layer 360 and the main intrinsic layer 370, thereby reducing the recombination probability and thus reducing the dark current.

[0054] Moreover, the first buffer intrinsic layer 340 includes a first sub-buffer microcrystalline silicon 341 and a second sub-buffer microcrystalline silicon 342 , wherein the second sub-buffer microcrystalline silicon 342 is located between the first sub-buffer microcrystalline silicon 341 and the main intrinsic layer 370 , and the crystallization rate of the first sub-buffer microcrystalline silicon 341 is higher than the crystallization rate of the second sub-buffer microcrystalline silicon 342 .

[0055] Exemplarily, the crystallization rate of the first sub-buffer microcrystalline silicon 341 is 55%-65%, and the crystallization rate of the second sub-buffer microcrystalline silicon 342 is 35%-45%. Exemplarily, the crystallization rate of the second sub-buffer microcrystalline silicon 342 is 60%, and the crystallization rate of the second sub-buffer microcrystalline silicon 342 is 40%.

[0056] The crystallization ratio is defined as the percentage of grains. The grain size of the first sub-buffer microcrystalline silicon 341 is larger than that of the second buffer microcrystalline silicon, and there are fewer grain boundary defects. The transmission resistance of electrons at the interface between the N-type doped layer 320 and the first sub-buffer microcrystalline silicon 341 is small, so electrons can easily pass through the first sub-buffer microcrystalline silicon 341 between the N-type doped layer 320. This reduces the accumulation of electrons at the interface, reduces the increase in the recombination probability, and avoids dark current.

[0057] The second buffer microcrystalline silicon has a low crystallization rate, a higher proportion of amorphous phase, and an increased density of defects such as tail states and dangling bonds. This can form a barrier gradient for electron-hole pair transmission between the first buffer microcrystalline silicon and the second buffer microcrystalline silicon, thereby suppressing the diffusion of a small number of electron-hole pairs, i.e., holes, in the main intrinsic layer 370 to the N-type doped layer 320, thereby suppressing dark current.

[0058] Simply put, the crystallization rate of the first buffer microcrystalline silicon drops from 60% to 40% from the second buffer microcrystalline silicon, forming a "unidirectional conduction" trend of electron-hole pair transmission, that is, electrons can easily move from the N-type doped layer 320 to the I-type doped layer, while holes are difficult to diffuse from the I-doped layer to the N-type doped layer 320, thereby reducing dark current.

[0059] Moreover, the high crystallization rate of the first buffer microcrystalline silicon reduces grain boundary defects, reduces the diffusion of dopants from the N-type doped layer 320 to the main intrinsic layer 370, and avoids the formation of deep energy level traps by dopants in the main intrinsic layer 370, which will capture electron-hole pairs and increase dark current. The defects such as dangling bonds in the amorphous phase of the second buffer microcrystalline silicon provide a certain trap state density for capturing a small number of holes generated by thermal excitation in the main intrinsic layer 370, and preventing them from diffusing into the N-type doped layer 320 to form dark current.

[0060] The second buffer intrinsic layer 350 includes a third sub-buffer microcrystalline silicon 351 and a fourth sub-buffer microcrystalline silicon 352 . The third sub-buffer microcrystalline silicon 351 is located between the fourth sub-buffer microcrystalline silicon 352 and the main intrinsic layer 370 , and the crystallization rate of the fourth sub-buffer microcrystalline silicon 352 is higher than the crystallization rate of the third sub-buffer microcrystalline silicon 351 .

[0061] The third sub-buffer microcrystalline silicon 351 has a high crystallinity. This high crystallinity means a higher proportion of crystal grains and fewer grain boundary defects. This reduces the resistance to hole transmission between the P-type doped layer 360 and the main intrinsic layer 370, facilitating hole passage between the P-type doped layer 360 and the main intrinsic layer 370 and reducing hole accumulation at the interface. For electrons thermally excited in the main intrinsic layer 370, the low conduction band floor in the high crystallinity region creates a "potential barrier" for electron transmission, inhibiting the diffusion of thermally excited electrons into the P-type doped layer 360 and thus reducing leakage current.

[0062] The fourth sub-buffer microcrystalline silicon 352 is a low crystallization rate region with a high proportion of amorphous phase and a high density of defects such as tail states and dangling bonds. It can serve as an electron trap to capture thermally excited electrons in the main intrinsic layer 370, causing them to recombine within the fourth sub-buffer microcrystalline silicon 352 instead of diffusing to the P-type doped layer 360 to form dark current.

[0063] From the fourth sub-buffer microcrystalline silicon 352 to the third sub-buffer microcrystalline silicon 351, the crystallization rate drops from 70% to 30%, forming a "one-way valve" effect in which holes can easily pass through but electrons are difficult to diffuse in the opposite direction, directly reducing the electron diffusion component in the dark current.

[0064] Moreover, the crystallization rate from the fourth sub-buffer microcrystalline silicon 352 to the third sub-buffer microcrystalline silicon 351 is reduced from 70% to 30%, and the corresponding conduction band bottom gradually moves upward, forming an energy step barrier for electrons in the second buffer intrinsic layer 350. This structure requires electrons to overcome multiple potential barriers to diffuse from the main intrinsic layer 370 to the P-type doped layer 360, effectively reducing the diffusion current; and when holes are transmitted from the P-type doped layer 360 to the main intrinsic layer 370, due to the gentle gradient of the valence band top, efficient transmission can still be maintained.

[0065] Furthermore, the fourth sub-buffer microcrystalline silicon 352 has a high crystallization rate, which reduces grain boundary defects, lowers the diffusion rate of the dopant from the P-type doping layer 360 to the main intrinsic layer 370 , reduces the interface state density, and suppresses carrier recombination.

[0066] The thickness of the second buffer intrinsic layer 350 is greater than that of the first buffer intrinsic layer 340 . The thickness of the first sub-buffer microcrystalline silicon 341 is less than that of the second sub-buffer microcrystalline silicon 342 . The thickness of the fourth sub-buffer microcrystalline silicon 352 is less than that of the third sub-buffer microcrystalline silicon 351 .

[0067] Exemplarily, the thickness of the first sub-buffer microcrystalline silicon 341 is 15-25 nm, the thickness of the second sub-buffer microcrystalline silicon 342 is 25 nm-35 nm, the thickness of the third sub-buffer microcrystalline silicon 351 is 30 nm-40 nm, and the thickness of the fourth sub-buffer microcrystalline silicon 352 is 20-30 nm.

[0068] For example, the thickness of the first sub-buffer microcrystalline silicon 341 is 20 nm, the thickness of the second sub-buffer microcrystalline silicon 342 is 30 nm, the thickness of the third sub-buffer microcrystalline silicon 351 is 35 nm, and the thickness of the fourth sub-buffer microcrystalline silicon 352 is 25 nm. The first buffer microcrystalline silicon effectively isolates the high defect states introduced by the N-type doped layer 320 during doping. The second buffer microcrystalline silicon maintains high purity with the main intrinsic layer 370 to reduce dark current. The thin thickness of the fourth sub-buffer microcrystalline silicon 352 ensures that holes quickly pass through the high crystallization rate region, avoiding recombination caused by excessively long transmission paths. At the same time, the thin buffer layer reduces carriers generated by self-thermal excitation. The thicker third sub-buffer microcrystalline silicon 351 utilizes the high defect state density of the low crystallization rate to form an "electron blocking layer", extending the electron diffusion path and increasing the capture probability, allowing them to fully recombine within the buffer layer.

[0069] Figure 3 Schematic diagram of a first flat layer and a second flat layer according to the first embodiment of the present application. Figure 3 As shown, the direction indicated by the arrow in the figure indicates the propagation direction of part of the light. Since there is a problem of interference between the light of adjacent pixel unit areas 700, that is, for example, in two adjacent pixel unit areas 700, the light converted by the light conversion layer 600 in one pixel unit area 700 is likely to irradiate the photodiode 310 in the other pixel unit area 700. Therefore, by preventing the light converted by the light conversion layer 600 in one pixel unit area 700 from irradiating the photodiode 310 in the other pixel unit area 700, the accuracy of the flat panel detector 10 is improved, as follows:

[0070] A second transparent electrode layer 510, a third insulating layer 520 and a first flat layer 530 are further included between the photodiode layer 300 and the signal transmission line layer 400. The second transparent electrode layer 510, the third insulating layer 520 and the first flat layer 530 are sequentially arranged on the photodiode layer 300. A fourth insulating layer 540 and a second flat layer 550 are further included between the signal transmission line layer 400 and the light conversion layer 600. The fourth insulating layer 540 and the second flat layer 550 are sequentially arranged on the signal transmission line layer 400. The light refractive index of the second flat layer 550, the fourth insulating layer 540 and the first flat layer 530 increases sequentially.

[0071] That is, in the present application, the light refractive index of the second flat layer 550, the fourth insulating layer 540, and the first flat layer 530 is increased sequentially, so that the large-angle light converted from the light conversion layer 600 in one of the pixel unit areas 700 undergoes a first downward refraction when passing through the junction of the second flat layer 550 and the fourth insulating layer 540, and then undergoes a second downward refraction when passing through the fourth insulating layer 540 and the first flat layer 530, so that the large-angle light is converted into vertically downward light, thereby preventing the light converted from the light conversion layer 600 in one of the pixel unit areas 700 from irradiating the photodiode 310 in another pixel unit area 700, thereby improving the accuracy of the flat panel detector 10.

[0072] Figure 4 is a schematic diagram of the second array substrate of the first embodiment of the present application, such as Figure 4 As shown, unlike the first array substrate 100, the N-type doped layer 320 and the P-type doped layer 360 of the photodiode 310 of the second array substrate 100 are horizontally arranged. Specifically, the N-type doped layer 320 and the P-type doped layer 360 are both arranged on the side of the main intrinsic layer 370 away from the active switching layer 200, and the composite intrinsic layer 330 also includes a second buffer intrinsic layer 350. The first buffer intrinsic layer 340 is located between the N-type doped layer 320 and the main intrinsic layer 370, and the second buffer intrinsic layer 350 is located between the P-type doped layer 360 and the main intrinsic layer 370.

[0073] Compared with the first array substrate 100 scheme of the first embodiment, the second sub-buffer microcrystalline silicon 342 and the third sub-buffer microcrystalline silicon 351 of the second array substrate 100 are both underneath the main intrinsic layer 370, and the first sub-buffer microcrystalline silicon 341 and the fourth sub-buffer microcrystalline silicon 352 are both underneath microcrystalline silicon, so the prepared second sub-buffer microcrystalline silicon 342 and the third sub-buffer microcrystalline silicon 351 will not be affected by the difference in the underlying materials.

[0074] Example 2:

[0075] Figure 5 is a schematic diagram of an array substrate according to the second embodiment of the present application. Figure 5 As shown, unlike the first embodiment, this embodiment is only provided with a first buffer intrinsic layer 340 between the N-type doped layer 320 and the main intrinsic layer 370. Specifically, the N-type doped layer 320, the first buffer intrinsic layer 340, the main intrinsic layer 370 and the P-type doped layer 360 are stacked in sequence on the active switching layer 200.

[0076] Compared with the solution of the first embodiment, the second embodiment only provides a first buffer intrinsic layer 340 between the N-type doped layer 320 and the main intrinsic layer 370 , which can reduce the manufacturing process, improve the manufacturing efficiency, and reduce the production cost.

[0077] Example 3:

[0078] Figure 6 is a schematic diagram of an array substrate according to the third embodiment of the present application, as shown in FIG. Figure 6 As shown, unlike the first embodiment, this embodiment is only provided with a first buffer intrinsic layer 340 between the P-type doped layer 360 and the main intrinsic layer 370. Specifically, the N-type doped layer 320, the main intrinsic layer 370, the first buffer intrinsic layer 340 and the P-type doped layer 360 are stacked in sequence on the active switching layer 200.

[0079] Compared with the solution of the first embodiment, the third embodiment only provides a first buffer intrinsic layer 340 between the P-type doped layer 360 and the main intrinsic layer 370 , which can reduce the manufacturing process, improve the manufacturing efficiency, and reduce the production cost.

[0080] Figure 7 FIG. 1 is a schematic diagram of a method for preparing an array substrate according to an embodiment of the present application. Figure 7 As shown, the present application also discloses a method for preparing an array substrate 100, and the method for preparing the array substrate 100 includes:

[0081] S1: forming a photodiode layer on the active switching layer;

[0082] S2: forming a signal transmission line layer on the photodiode layer;

[0083] S3: forming a light conversion layer on the signal transmission line layer;

[0084] In which, the photodiode 310 includes an N-type doped layer 320, a composite intrinsic layer 330 and a P-type doped layer 360, the composite intrinsic layer 330 is arranged between the N-type doped layer 320 and the P-type doped layer 360, the N-type doped layer 320 is connected to the active switch 210, and the P-type doped layer 360 is connected to the signal transmission line 410, the composite intrinsic layer 330 includes a main intrinsic layer 370 and a first buffer intrinsic layer 340, the first buffer intrinsic layer 340 is arranged on the main intrinsic layer 370, and the crystallization rate of the first buffer intrinsic layer 340 is higher than the crystallization rate of the main intrinsic layer 370.

[0085] The preparation scheme of the array substrate 100 of the present application is to set a composite intrinsic layer 330 between the N-type doped layer 320 and the P-type doped layer 360, and the composite intrinsic layer 330 includes a main intrinsic layer 370 and a first buffer intrinsic layer 340, and the crystallization rate of the first buffer intrinsic layer 340 is higher than the crystallization rate of the main intrinsic layer 370, so that electrons are not easily gathered between the main intrinsic layer 370 and the N-type doped layer 320, or holes are not easily gathered between the main intrinsic layer 370 and the P-type doped layer 360. In this way, the electron-hole pairs excited by the light that is not converted by the light conversion layer can be avoided from recombining with it, thereby reducing the amount of dark current generated.

[0086] S1: The step of forming a photodiode layer on the active switching layer includes:

[0087] S111: forming an N-type doped layer on the active switch layer;

[0088] For example, silane (SiH4), phosphine (PH3), and hydrogen (H2) are used as reaction gases to deposit the N-type doped layer 320 on the active switching layer 200 using PECVD (Plasma Enhanced Chemical Vapor Deposition). The deposition temperature is maintained at 200°C to 300°C, and the deposition time is controlled to ensure that the thickness of the N-type doped layer 320 reaches 50nm to 150nm.

[0089] S112: forming a first buffer intrinsic layer on the N-type doped layer;

[0090] S113: forming a main intrinsic layer on the first buffer intrinsic layer;

[0091] For example, a PECVD method can be used to deposit the main intrinsic layer 370 on the first buffer intrinsic layer 340 using silane (SiH4) and hydrogen (H2) as reaction gases. The deposition temperature is set at 200-300°C, and the deposition time is controlled to achieve a thickness of 0.8μm-1.5μm for the main intrinsic layer 370.

[0092] S114: forming a second buffer intrinsic layer on the main intrinsic layer;

[0093] S115: forming a P-type doped layer on the second buffer intrinsic layer to form a photodiode;

[0094] For example, a P-type doped layer 360 is deposited on the second buffer intrinsic layer 350 using PECVD using silane (SiH4), borane (B2H6), and hydrogen (H2) as reaction gases. The deposition temperature is maintained at 200°C-300°C, and the deposition time is controlled so that the thickness of the P-type doped layer 360 reaches 50nm-150nm.

[0095] Wherein, S112: the step of forming a first buffer intrinsic layer on the N-type doped layer includes:

[0096] S1121: forming a first sub-buffer microcrystalline silicon on the N-type doped layer;

[0097] S1122: forming a second sub-buffer microcrystalline silicon on the first sub-buffer microcrystalline silicon to form a first buffer intrinsic layer;

[0098] For example, a first sub-buffer microcrystalline silicon 341 and a second sub-buffer microcrystalline silicon 342 are deposited on the N-type doped layer 320 using a PECVD method. Silane (SiH4), hydrogen (H2), and methane (CH4) are used as the reaction gases. By precisely adjusting the gas flow ratio and deposition time, the thicknesses of the first sub-buffer microcrystalline silicon 341 and the second sub-buffer microcrystalline silicon 342 are 20 nm and 30 nm, respectively, and the crystallization ratios are 60% and 40%, respectively.

[0099] S114: The step of forming a second buffer intrinsic layer on the main intrinsic layer includes:

[0100] S1141: forming a third sub-buffer microcrystalline silicon on the main intrinsic layer;

[0101] S1142: forming a fourth sub-buffer microcrystalline silicon on the third sub-buffer microcrystalline silicon to form a second buffer intrinsic layer;

[0102] Exemplarily, a PECVD method is used to deposit a third sub-buffer microcrystalline silicon 351 and a fourth sub-buffer microcrystalline silicon 352 on the main intrinsic layer 370. The reaction gases are silane (SiH4), hydrogen (H2), and methane (CH4). By precisely adjusting the gas flow ratio and deposition time, the thickness of the third sub-buffer microcrystalline silicon 351 and the fourth sub-buffer microcrystalline silicon 352 are 25nm and 35nm, respectively, and the crystallization ratio is 70% and 30%, respectively.

[0103] S2: The step of forming a signal transmission line layer on the photodiode layer further includes:

[0104] S21: forming a second transparent electrode layer on the photodiode layer;

[0105] For example, the second transparent electrode layer 510 is deposited on the photodiode layer 300 by electron beam evaporation. Transparent electrode materials can be selected and the evaporation rate and time can be precisely controlled to make the thickness of the second transparent electrode layer 510 reach 50nm-100nm.

[0106] S22: forming a third insulating layer on the second transparent electrode layer;

[0107] S23: forming a first planarization layer on the third insulating layer;

[0108] S24: forming a signal transmission line layer on the first planar layer, wherein the signal transmission line layer further includes a light-shielding metal block and a signal transmission line, wherein the orthographic projection of the light-shielding metal block on the substrate covers the orthographic projection of the active switch on the substrate, and the signal transmission line is connected to the second transparent electrode;

[0109] Then, annealing treatment is performed with the annealing temperature set at 150°C-250°C and the annealing time being 1 hour-3 hours to eliminate internal stress and optimize material properties.

[0110] S3: The step of forming a light conversion layer on the signal transmission line layer further includes:

[0111] S31: forming a fourth insulating layer on the signal transmission line layer;

[0112] S32: forming a second planarization layer on the fourth insulating layer;

[0113] S33: forming a light conversion layer on the second planar layer.

[0114] It should be noted that the limitations on the steps involved in this solution do not limit the order of the steps without affecting the implementation of the specific solution. The steps written in front can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be deemed to fall within the scope of protection of this application.

[0115] The above content is a further detailed description of the present application in conjunction with specific optional implementation methods, and the specific implementation of the present application cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, they can make several simple deductions or substitutions without departing from the concept of the present application, which should be considered to fall within the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes an active switch layer, a photodiode layer, a signal transmission line layer, and a light conversion layer. The photodiode layer, the signal transmission line layer, and the light conversion layer are sequentially arranged on the active switch layer. The active switch layer includes at least one active switch, the photodiode layer includes at least one photodiode, and the signal transmission line layer includes at least one signal transmission line. The active switch, the photodiode, and the signal transmission line are sequentially connected. The photodiode includes an N-type doped layer, a composite intrinsic layer and a P-type doped layer, the composite intrinsic layer is arranged between the N-type doped layer and the P-type doped layer, the N-type doped layer is connected to the active switch, and the P-type doped layer is connected to the signal transmission line. The composite intrinsic layer includes a main intrinsic layer and a first buffer intrinsic layer, the first buffer intrinsic layer is arranged on the main intrinsic layer, and the crystallization rate of the first buffer intrinsic layer is higher than the crystallization rate of the main intrinsic layer.

2. The array substrate according to claim 1, wherein: The N-type doped layer, the first buffer intrinsic layer, the main intrinsic layer and the P-type doped layer are sequentially stacked on the active switching layer.

3. The array substrate according to claim 1, wherein: The N-type doped layer, the main intrinsic layer, the first buffer intrinsic layer and the P-type doped layer are sequentially stacked on the active switching layer.

4. The array substrate according to claim 2, wherein: The composite intrinsic layer further includes a second buffer intrinsic layer, and the N-type doped layer, the first buffer intrinsic layer, the main intrinsic layer, the second buffer intrinsic layer and the P-type doped layer are sequentially stacked on the active switching layer; The crystallization rate of the second buffer intrinsic layer is higher than that of the main intrinsic layer.

5. The array substrate according to claim 4, wherein: The first buffer intrinsic layer includes a first sub-buffer microcrystalline silicon and a second sub-buffer microcrystalline silicon. The second sub-buffer microcrystalline silicon is located between the first sub-buffer microcrystalline silicon and the main intrinsic layer. The crystallization rate of the first sub-buffer microcrystalline silicon is higher than that of the second sub-buffer microcrystalline silicon.

6. The array substrate according to claim 5, wherein: The second buffer intrinsic layer includes a third sub-buffer microcrystalline silicon and a fourth sub-buffer microcrystalline silicon. The third sub-buffer microcrystalline silicon is located between the fourth sub-buffer microcrystalline silicon and the main intrinsic layer, and the crystallization rate of the fourth sub-buffer microcrystalline silicon is higher than that of the third sub-buffer microcrystalline silicon.

7. The array substrate according to claim 4, wherein: The thickness of the second buffer intrinsic layer is greater than that of the first buffer intrinsic layer.

8. The array substrate according to claim 6, wherein: The thickness of the first sub-buffer microcrystalline silicon is smaller than the thickness of the second sub-buffer microcrystalline silicon; and the thickness of the fourth sub-buffer microcrystalline silicon is smaller than the thickness of the third sub-buffer microcrystalline silicon.

9. A method for preparing an array substrate, characterized in that: The method for preparing the array substrate includes: forming a photodiode layer on the active switching layer; forming a signal transmission line layer on the photodiode layer; forming a light conversion layer on the signal transmission line layer; The photodiode includes an N-type doped layer, a composite intrinsic layer and a P-type doped layer, the composite intrinsic layer is arranged between the N-type doped layer and the P-type doped layer, the N-type doped layer is connected to the active switch, and the P-type doped layer is connected to the signal transmission line. The composite intrinsic layer includes a main intrinsic layer and a first buffer intrinsic layer, the first buffer intrinsic layer is arranged on the main intrinsic layer, and the crystallization rate of the first buffer intrinsic layer is higher than the crystallization rate of the main intrinsic layer.

10. A flat panel detector, characterized in that: The flat panel detector comprises a signal processing unit and the array substrate according to any one of claims 1 to 8, wherein the signal processing unit is connected to the array substrate and is configured to receive and process signals output by the array substrate.

Images