Solar cell and preparation method thereof

Abstract

The invention relates to a solar cell and a preparation method thereof. A solar cell comprises a silicon wafer, a passivation contact structure and an electrode pattern, wherein the passivation contact structure and the electrode pattern are arranged on the back face of the silicon wafer. The passivation contact structure comprises a first silicon oxide layer and a doped polycrystalline silicon layer which are arranged in the first region and are sequentially stacked in the direction gradually away from the silicon wafer; the second silicon dioxide layer and the doped silicide layer are arranged in the second region and are sequentially stacked in the direction gradually away from the silicon wafer; wherein the first region is the region where the electrode pattern is located, the second region at least comprises other regions, except the region where the electrode pattern is located, of the solar cell, and ohmic contact is formed between the electrode pattern and the doped polycrystalline silicon layer. The solar cell is beneficial for further improving the photoelectric conversion efficiency of the cell.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] In the current passivation contact structure of solar cells, the polysilicon layer has severe parasitic absorption of light. If the polysilicon layer is grown too thick on the entire surface of the silicon wafer, the battery's utilization of light will be greatly reduced, thereby reducing the battery's short-circuit current. How to effectively reduce the recombination of metal and non-metal areas while ensuring the battery's utilization of light and improving battery efficiency has become an urgent problem that needs to be solved. Summary of the Invention

[0003] Based on this, it is necessary to provide a solar cell and a preparation method thereof that can improve light utilization and cell efficiency.

[0004] In a first aspect, the present application provides a solar cell comprising a silicon wafer, a passivation contact structure disposed on the back side of the silicon wafer, and an electrode pattern;

[0005] The passivation contact structure includes a first silicon oxide layer and a doped polysilicon layer disposed in a first region and sequentially stacked in a direction gradually away from the silicon wafer; a second silicon oxide layer and a doped silicide layer disposed in a second region and sequentially stacked in a direction gradually away from the silicon wafer;

[0006] The first region is the region where the electrode pattern is located, the second region at least includes the remaining regions of the solar cell except the region where the electrode pattern is located, and the electrode pattern forms an ohmic contact with the doped polysilicon layer.

[0007] In some embodiments, the second region further includes: a region where the electrode pattern is located;

[0008] The second silicon oxide layer and the doped silicide layer further extend to cover a side of the doped polysilicon layer away from the silicon wafer.

[0009] In some embodiments, the thickness of the doped polysilicon layer is greater than the thickness of the doped silicide layer.

[0010] In some embodiments, the thickness of the doped polysilicon layer is 30 nm to 200 nm.

[0011] In some embodiments, the thickness of the doped silicide layer is 10 nm to 80 nm.

[0012] In some embodiments, the doping concentration of the doping element in the doped polysilicon layer is 6E19cm -3 ~7E20cm-3 .

[0013] In some embodiments, the doping concentration of the doping element in the doped silicide layer is 1E19 cm -3 ~7E20cm -3 .

[0014] In some embodiments, the thickness of the first silicon oxide layer is less than 3 nm.

[0015] In some embodiments, the thickness of the second silicon oxide layer is less than 3 nm.

[0016] In some embodiments, the silicide in the doped silicide layer includes one or more of silicon carbide, silicon oxide, and silicon nitride.

[0017] In a second aspect, the present application also provides a method for preparing a solar cell, comprising the following steps:

[0018] forming a passivation contact structure on the back side of the silicon wafer; the passivation contact structure comprises a first silicon oxide layer and a doped polysilicon layer disposed in a first region and sequentially stacked in a direction gradually away from the silicon wafer;

[0019] a second silicon oxide layer and a doped silicide layer disposed in a second region and sequentially stacked in a direction gradually away from the silicon wafer; wherein the first region is the region where the electrode pattern is located, and the second region includes at least the remaining region of the solar cell excluding the region where the electrode pattern is located;

[0020] The electrode pattern is formed in the first region of the passivation contact structure, and the electrode pattern forms an ohmic contact with the doped polysilicon layer.

[0021] In some embodiments, the second region includes the remaining region of the solar cell except the region where the electrode pattern is located, and the preparation of the passivation contact structure includes the following steps:

[0022] forming the first silicon oxide layer on the back side of the silicon wafer;

[0023] forming the doped polysilicon layer on a surface of the first silicon oxide layer away from the silicon wafer;

[0024] removing the first silicon oxide layer and the doped polysilicon layer from the remaining areas except the area where the electrode pattern is located;

[0025] In the remaining areas except the area where the electrode pattern is located, the second silicon oxide layer and the doped silicide layer are stacked in sequence along a direction gradually away from the silicon wafer.

[0026] In some embodiments, the second region also includes the region where the electrode pattern is located, and the preparation of the passivation contact structure further includes the following steps:

[0027] While the second silicon oxide layer and the doped silicide layer are stacked in sequence in the remaining areas except the area where the electrode pattern is located, the second silicon oxide layer and the doped silicide layer are also formed on the side of the doped polysilicon layer away from the silicon wafer, so that the second silicon oxide layer and the doped silicide layer extend to cover the area where the electrode pattern is located.

[0028] The present application provides a solar cell comprising a silicon wafer, a passivation contact structure disposed on the back side of the silicon wafer, and an electrode pattern. The passivation contact structure includes a doped polysilicon layer disposed in the region where the electrode pattern is located. The doped polysilicon layer helps reduce the contact resistance of the electrode, thereby improving the fill factor and energy conversion efficiency of the cell. Furthermore, a doped silicide layer is disposed in at least the region other than the region where the electrode pattern is located. The doped silicide layer helps reduce parasitic absorption of light, increases back reflectivity, and thereby further improves the photoelectric conversion efficiency of the cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 FIG. 4 is a schematic structural diagram of a solar cell in one embodiment.

[0030] 1: Solar cell; 10: Silicon wafer; 20: Passivation contact structure; 21: First silicon oxide layer; 22: Doped polysilicon layer; 23: Second silicon oxide layer; 24: Doped silicide layer; 30: Anti-reflection film layer; 40: Electrode pattern. DETAILED DESCRIPTION

[0031] To facilitate understanding of the present application, the present application will be described more fully below in conjunction with the embodiments and accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] In traditional technology, the passivation contact structure in solar cells usually contains a polysilicon layer to reduce the recombination of metal and non-metal regions. However, the polysilicon layer has severe parasitic absorption of light. If a thick polysilicon layer is grown on the entire surface of the silicon wafer, the cell's light utilization rate will be greatly reduced. To overcome the above problems, some studies have replaced the polysilicon layer in the passivation contact structure with a silicide film. Although the silicide film can reduce the parasitic absorption of light compared to the polysilicon layer, the contact resistance between the silicide film and the electrode is higher than that of the polysilicon layer, resulting in a low fill factor and energy conversion efficiency of the solar cell.

[0034] like Figure 1 As shown, in order to solve the above problems, the present application provides a solar cell 1, comprising a silicon wafer 10, a passivation contact structure 20 and an electrode pattern 40 provided on the back side of the silicon wafer 10;

[0035] The passivation contact structure 20 includes a first silicon oxide layer 21 and a doped polysilicon layer 22, which are disposed in a first region and sequentially stacked in a direction gradually away from the silicon wafer 10; a second silicon oxide layer 23 and a doped silicide layer 24, which are disposed in a second region and sequentially stacked in a direction gradually away from the silicon wafer 10;

[0036] The first region is where the electrode pattern 40 is located, and the second region at least includes the remaining regions of the solar cell 1 except where the electrode pattern 40 is located. The electrode pattern 40 forms an ohmic contact with the doped polysilicon layer 22 .

[0037] The present application provides a solar cell 1 comprising a silicon wafer 10, a passivation contact structure 20 disposed on the back side of the silicon wafer 10, and an electrode pattern 40. Within the passivation contact structure 20, a doped polysilicon layer 22 is disposed in the region where the electrode pattern 40 is located. The doped polysilicon layer 22 helps reduce recombination between metal and non-metal regions, lowering the contact resistance of the electrodes and improving the cell's fill factor and energy conversion efficiency. Furthermore, a doped silicide layer 24 is disposed in at least the remaining region excluding the region where the electrode pattern 40 is located. The doped silicide layer 24 helps reduce parasitic absorption of light and increases back reflectivity, thereby further improving the cell's photoelectric conversion efficiency.

[0038] The solar cell 1 provided in the present application is provided with a doped polysilicon layer 22 in the area where the electrode pattern 40 is located, so that there is a lower contact resistance between the electrode and the passivation contact structure 20, and a doped silicide layer 24 is provided in the remaining areas except the area where the electrode pattern 40 is located to replace the doped polysilicon layer 22, so as to avoid having a thick doped polysilicon layer 22 on the back of the entire silicon wafer 10, which is beneficial to reduce parasitic absorption of light and improve back reflectivity.

[0039] In some embodiments, the second region also includes: the region where the electrode pattern 40 is located;

[0040] The second silicon oxide layer 23 and the doped silicide layer 24 also extend to cover the side of the doped polysilicon layer 22 away from the silicon wafer 10 .

[0041] The side of the doped polysilicon layer 22 away from the silicon wafer 10 in the area where the electrode pattern 40 is located is also covered with a second silicon oxide layer 23 and a doped silicide layer 24, but this does not affect the ohmic contact formed between the electrode pattern 40 and the doped polysilicon layer 22, which can further improve the back reflectivity of the battery.

[0042] In some embodiments, the thickness of the doped polysilicon layer 22 is greater than the thickness of the doped silicide layer 24. Using a thicker doped polysilicon layer 22 is beneficial for reducing contact resistance and forming a good ohmic contact between the electrode pattern 40 and the doped polysilicon layer 22.

[0043] In some embodiments, the thickness of the doped polysilicon layer 22 is 30 nm to 200 nm. Within this thickness range, the doped polysilicon layer 22 can provide good electrical conductivity, which helps reduce the contact resistance of the electrode pattern 40. Furthermore, the parasitic absorption of light by the doped polysilicon layer 22 is controlled within an appropriate range. It is understood that the thickness of the doped polysilicon layer 22 can be, for example, but not limited to, 30 nm, 60 nm, 80 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, and the like.

[0044] In some embodiments, the thickness of the doped silicide layer 24 is 10 nm to 80 nm. Within this thickness range, the doped silicide layer 24 can effectively overcome the problem of parasitic light absorption by the doped polysilicon layer 22, thereby improving back reflectivity and increasing light utilization. At the same time, it also avoids the impact of excessive thickness of the doped silicide layer 24 on the contact resistance with the electrode, which is beneficial for improving the fill factor and conversion efficiency of the battery. It is understood that the thickness of the doped silicide layer 24 can be, for example, but not limited to, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, etc.

[0045] In some embodiments, the doping concentration of the doping element in the doped polysilicon layer 22 is 6E19 cm -3 ~7E20cm -3 The doping concentration of the doping element within the above-mentioned doping concentration range can ensure a low contact resistance, so that the electrode forms a good ohmic contact with the doped polysilicon layer 22. It can be understood that the doping concentration of the doping element in the doped polysilicon layer 22 can be, for example, but not limited to, 6E19cm -3 、7E19cm -3 、8E19cm-3 、9E19cm -3 、1E20cm -3 、2E20cm -3 、3E20cm -3 、4E20cm -3 、5E20cm -3 、6E20cm -3 、7E20cm -3 etc.

[0046] It can be understood that the doping element in the doped polysilicon layer 22 can be phosphorus doping or boron doping.

[0047] In some embodiments, the doping concentration of the doping element in the doped silicide layer 24 is 1E19 cm -3 ~7E20cm -3 The doping element can have a good effect of reducing the metal and non-metal composite within the above-mentioned doping concentration range, and is conducive to improving the back reflectivity. It can be understood that the doping concentration of the doping element in the doped silicide layer 24 can be, for example, but not limited to, 1E19cm -3 、2E19cm -3 、3E19cm -3 、4E19cm -3 、5E20cm -3 、6E19cm -3 、7E19cm -3 、8E19cm -3 、9E19cm -3 、1E20cm -3 、2E20cm -3 、3E20cm -3 、4E20cm -3 、5E20cm -3 、6E20cm -3 、7E20cm -3 etc.

[0048] It can be understood that the doping element in the doped silicide layer 24 can be phosphorus doping or boron doping.

[0049] In some embodiments, the thickness of the first silicon oxide layer 21 is less than 3 nm. The first silicon oxide layer 21 facilitates charge transfer and improves battery efficiency. It is understood that the thickness of the first silicon oxide layer 21 can be, but is not limited to, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, and the like.

[0050] In some embodiments, the thickness of the second silicon oxide layer 23 is less than 3 nm. The second silicon oxide layer 23 functions similarly to the first silicon oxide layer 21, both facilitating charge transfer and improving battery efficiency. It is understood that the thickness of the second silicon oxide layer 23 can be, but is not limited to, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, and the like.

[0051] In some embodiments, the silicide in the doped silicide layer 24 includes one or more of silicon carbide, silicon oxide, and silicon nitride. A suitable silicide can be selected according to actual needs.

[0052] In some embodiments, the solar cell 11 further includes an anti-reflection film 3030, which is disposed on a surface of the doped silicide layer 24 away from the back surface of the silicon wafer 10. The anti-reflection film 3030 helps further reduce the back reflectivity of light and improve light absorption and light utilization.

[0053] Furthermore, the anti-reflection film layer 30 may be, for example, a stack of aluminum oxide and silicon nitride, or may be only a stack of silicon nitride.

[0054] In some embodiments, the material of the electrode pattern 40 may be, but is not limited to, silver, silver-aluminum, etc.

[0055] In a second aspect, the present application further provides a method for preparing a solar cell 1 , comprising the following steps S100 and S300 .

[0056] Step S100: forming a passivation contact structure 20 on the back side of the silicon wafer 10; the passivation contact structure 20 includes a first silicon oxide layer 21 and a doped polysilicon layer 22, which are arranged in a first region and sequentially stacked in a direction gradually away from the silicon wafer 10; and a second silicon oxide layer 23 and a doped silicide layer 24, which are arranged in a second region and sequentially stacked in a direction gradually away from the silicon wafer 10; wherein the first region is the region where the electrode pattern 40 is located, and the second region includes at least the remaining region of the solar cell 1 except the region where the electrode pattern 40 is located.

[0057] Step S300 : forming an electrode pattern 40 in the first region of the passivation contact structure 20 , wherein the electrode pattern 40 forms an ohmic contact with the doped polysilicon layer 22 .

[0058] In some embodiments, the second region includes the remaining regions of the solar cell 1 except the region where the electrode pattern 40 is located, and the preparation of the passivation contact structure 20 includes the following steps S110 to S140.

[0059] Step S110 : forming a first silicon oxide layer 21 on the back side of the silicon wafer 10 .

[0060] Furthermore, the thickness of the first silicon oxide layer 21 is less than 3 nm.

[0061] Furthermore, the first silicon oxide layer 21 is formed by thermal oxidation.

[0062] Step S120 : forming a doped polysilicon layer 22 on a surface of the first silicon oxide layer 21 away from the silicon wafer 10 .

[0063] Furthermore, the thickness of the doped polysilicon layer 22 is 30 nm to 200 nm. It is understandable that the thickness of the doped polysilicon layer 22 can be, for example but not limited to, 30 nm, 60 nm, 80 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc.

[0064] Furthermore, the doping concentration of the doping element in the doped polysilicon layer 22 is 6E19cm -3 ~7E20cm -3 It is understood that the doping concentration of the doping element in the doped polysilicon layer 22 may be, for example but not limited to, 6E19cm -3 、7E19cm -3 、8E19cm -3 、9E19cm -3 、1E20cm -3 、2E20cm -3 、3E20cm -3 、4E20cm -3 、5E20cm -3 、6E20cm -3 、7E20cm -3 etc.

[0065] Furthermore, the doped polysilicon layer 22 is formed by low pressure chemical vapor deposition (LPCVD) or polyethylene chemistries vapor deposition (PECVD).

[0066] Step S130 : removing the first silicon oxide layer 21 and the doped polysilicon layer 22 in the remaining areas except the area where the electrode pattern 40 is located.

[0067] Furthermore, step 130 includes steps S131 and S132.

[0068] Step S131: After step S120, a mask is formed on the surface of the doped polysilicon layer 22 located in the region where the electrode pattern 40 is located, away from the silicon wafer 10. The mask may be, for example but not limited to, a PSG film, a silicon oxide film, etc.

[0069] Step S132: Locally etch the doped polysilicon layer 22 from the remaining areas except for the electrode pattern 40. After etching, HF solution is used to etch the remaining areas. The mask located in the area where the electrode pattern 40 is located is removed, while retaining the doped polysilicon layer 22 located in the area where the electrode pattern 40 is located. During this process, the first silicon oxide layer 21 in the remaining areas except for the area where the electrode pattern 40 is located is also etched away. Therefore, a new silicon oxide layer needs to be formed in this area later.

[0070] Step S140 : forming a stacked second silicon oxide layer 23 and a doped silicide layer 24 in sequence in the remaining area except the area where the electrode pattern 40 is located, in a direction gradually away from the silicon wafer 10 .

[0071] Furthermore, the thickness of the second silicon oxide layer 23 is less than 3 nm.

[0072] Furthermore, a second silicon oxide layer 23 is formed by PECVD.

[0073] Furthermore, the thickness of the doped polysilicon layer 22 is greater than the thickness of the doped silicide layer 24 .

[0074] Furthermore, the thickness of the doped silicide layer 24 is 10 nm to 80 nm. It is understandable that the thickness of the doped silicide layer 24 can be, for example but not limited to, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, etc.

[0075] Furthermore, the doping concentration of the doping element in the doped silicide layer 24 is 1E19 cm -3 ~7E20cm -3 It is understood that the doping concentration of the doping element in the doped silicide layer 24 may be, for example but not limited to, 1E19 cm -3 、2E19cm -3 、3E19cm -3 、4E19cm -3 、5E20cm -3 、6E19cm -3 、7E19cm -3 、8E19cm -3 、9E19cm -3 、1E20cm -3 、2E20cm -3 、3E20cm -3 、4E20cm -3 、5E20cm -3 、6E20cm -3 、7E20cm -3 etc.

[0076] Furthermore, the silicide in the doped silicide layer 24 includes one or more of silicon carbide, silicon oxide, and silicon nitride.

[0077] Furthermore, a doped silicide layer 24 is formed by PECVD.

[0078] Furthermore, the silicide includes silicon carbide, the doped silicide layer 24 is n-type doped, and the reaction gas includes silane, phosphine, hydrogen, and methane.

[0079] Furthermore, the silicide includes silicon carbide, the doped silicide layer 24 is p-type doped, and the reaction gas includes silane, borane, hydrogen, and methane.

[0080] Furthermore, the silicide includes silicon oxide, the doped silicide layer 24 is n-type doped, and the reaction gas includes silane, phosphine, and hydrogen, and also includes carbon dioxide or nitrous oxide.

[0081] Furthermore, the silicide includes silicon oxide, the doped silicide layer 24 is p-type doped, and the reaction gas includes silane, borane, and hydrogen, and also includes carbon dioxide or nitrous oxide.

[0082] Furthermore, the silicide includes silicon nitride, the doped silicide layer 24 is n-type doped, and the reaction gas includes silane, phosphine, hydrogen, and ammonia.

[0083] Furthermore, the silicide includes silicon nitride, the doped silicide layer 24 is p-type doped, and the reaction gas includes silane, borane, hydrogen, and ammonia.

[0084] In some embodiments, the second region also includes the region where the electrode pattern 40 is located, and the step S140 of preparing the passivation contact structure 20 further includes the following step S141 .

[0085] Step S141: While a stacked second silicon oxide layer 23 and a doped silicide layer 24 are sequentially formed in the remaining areas except the area where the electrode pattern 40 is located, a second silicon oxide layer 23 and a doped silicide layer 24 are also formed on the side of the doped polysilicon layer 22 away from the silicon wafer 10, so that the second silicon oxide layer 23 and the doped silicide layer 24 extend to cover the area where the electrode pattern 40 is located.

[0086] In some embodiments, the method for preparing the solar cell 1 further includes step S200 .

[0087] Step S200 : forming an anti-reflection film layer 30 on a surface of the doped silicide layer 24 away from the back surface of the silicon wafer 10 .

[0088] Furthermore, the anti-reflection film layer 30 may be, for example, a stack of aluminum oxide and silicon nitride, or may be only a stack of silicon nitride.

[0089] Furthermore, the anti-reflection film layer 30 is formed by using a PECVD method or an ALD method.

[0090] In some embodiments, step S300 includes step S310.

[0091] Step S310: Printing an electrode paste on a region corresponding to the electrode pattern 40 on the surface of the anti-reflection film layer 30 away from the back surface of the silicon wafer 10. After sintering, the electrode paste burns through the anti-reflection film layer 30, the doped silicide layer 24, and the second silicon oxide layer 23, forming the electrode pattern 40 in ohmic contact with the doped polysilicon layer 22.

[0092] Furthermore, the electrode paste is printed using screen printing technology.

[0093] Furthermore, the electrode paste may be, for example but not limited to, silver, silver aluminum, etc.

[0094] The solar cell 1 provided by the preparation method of the present application utilizes a doped polysilicon layer 22 in the region where the electrode pattern 40 is located, which helps reduce contact resistance. At least in the remaining region other than the region where the electrode pattern 40 is located, a doped silicide layer 24 is provided, which can reduce parasitic absorption of light and increase back reflectivity. The combination of these two factors can improve the cell's fill factor and photoelectric conversion efficiency. Furthermore, the solar cell 1 provided by the present application can improve conversion efficiency by 0.2%.

[0095] The following are specific examples.

[0096] Example 1

[0097] A method for preparing a solar cell 1 comprises the following steps:

[0098] (1) Cleaning the n-type silicon wafer 10.

[0099] (2) A first silicon oxide layer 21 is prepared on the back side of the silicon wafer 10 by thermal oxidation. The thickness of the first silicon oxide layer 21 is 1.5 nm.

[0100] (3) A doped polysilicon layer 22 is prepared on the surface of the first silicon oxide layer 21 away from the silicon wafer 10 by using a chemical vapor deposition method (PECVD). The doping element of the doped polysilicon layer 22 is phosphorus doping and the thickness is 150 nm.

[0101] (4) A PSG film is formed as a mask on the surface of the doped polysilicon layer 2222 in the area where the electrode pattern 40 is located, away from the silicon wafer 1010.

[0102] (5) The doped polysilicon layer 22 in the area other than the area where the electrode pattern 40 is located is removed by local etching. After the etching is completed, HF solution is used for etching to remove the mask located in the area where the electrode pattern 40 is located, while retaining the doped polysilicon layer 22 in the area where the electrode pattern 40 is located. During the processing, the first silicon oxide layer 21 in the area other than the area where the electrode pattern 40 is located is also etched away.

[0103] (6) A second silicon oxide layer 23 having a thickness of 1.5 nm is formed on the surface of the doped polysilicon layer 22 away from the silicon wafer 10 in the area other than the area where the electrode pattern 40 is located, using nitrous oxide as a reaction gas by chemical vapor deposition (PECVD).

[0104] (7) A doped silicide layer 24 is deposited on the surface of the second silicon oxide layer 23 away from the silicon wafer 10 by using silane, borane, hydrogen and methane as reaction gases through a chemical vapor deposition method (PECVD). The silicide is silicon carbide and the doping element is phosphorus. The thickness of the formed doped silicide layer 24 is 20 nm.

[0105] (8) A silicon nitride stack is deposited on the surface of the doped silicide layer 24 away from the back side of the silicon wafer 10 by chemical vapor deposition (PECVD) to form an anti-reflection film layer 30. The thickness of the anti-reflection film layer 30 is 80 nm.

[0106] (10) Silver paste is printed on the area where the electrode pattern 40 is located on the surface of the anti-reflection film layer away from the back of the silicon wafer 10 by screen printing technology. After sintering, the silver paste burns through the anti-reflection film layer 30, the doped silicide layer 24 and the second silicon oxide layer 23, forming the electrode pattern 40 in ohmic contact with the doped polysilicon layer 22.

[0107] Comparative Example 1

[0108] A method for preparing a solar cell comprises the following steps:

[0109] (1) Clean the n-type silicon wafer.

[0110] (2) A first silicon oxide layer is prepared on the back of the silicon wafer by thermal oxidation. The thickness of the first silicon oxide layer is 1.5 nm.

[0111] (3) A doped polysilicon layer is prepared on the surface of the first silicon oxide layer away from the silicon wafer by chemical vapor deposition (PECVD). The doping element of the doped polysilicon layer is phosphorus doping and the thickness is 150 nm.

[0112] (4) A silicon nitride stack is deposited on the surface of the doped polysilicon layer away from the back side of the silicon wafer using chemical vapor deposition (PECVD) to form an anti-reflection film layer. The thickness of the anti-reflection film layer is 80 nm.

[0113] (5) Silver paste is printed on the area where the electrode pattern is located on the surface of the anti-reflection film layer away from the back of the silicon wafer using screen printing technology. After sintering, the silver paste burns through the anti-reflection film layer to form an electrode pattern that is in ohmic contact with the doped polysilicon layer.

[0114] Comparative Example 2

[0115] A method for preparing a solar cell comprises the following steps:

[0116] (1) Clean the n-type silicon wafer.

[0117] (2) A first silicon oxide layer is prepared on the back of the silicon wafer by thermal oxidation. The thickness of the first silicon oxide layer is 1.5 nm.

[0118] (3) A doped silicide layer is deposited on the surface of the first silicon oxide layer away from the silicon wafer by using silane, borane, hydrogen and methane as reaction gases through chemical vapor deposition (PECVD). The silicide is silicon carbide and the doping element is phosphorus. The thickness of the doped silicide layer is 150 nm.

[0119] (4) A silicon nitride stack is deposited on the surface of the doped silicide layer away from the back side of the silicon wafer using chemical vapor deposition (PECVD) to form an anti-reflection film layer. The thickness of the anti-reflection film layer is 80 nm.

[0120] (5) Silver paste is printed on the electrode pattern area on the side of the anti-reflection film layer away from the back of the silicon wafer using screen printing technology. After sintering, the silver paste burns through the anti-reflection film layer and comes into direct contact with the doped silicide layer.

[0121] The electrical performance of the solar cells prepared in Example 1 and Comparative Examples 1 and 2 was tested, and the test results are shown in the following table.

[0122] Table 1 Performance test results of solar cells

[0123]

[0124] As can be seen from Table 1, compared with Comparative Examples 1 and 2, the solar cell of Example 1 has higher open circuit voltage (Voc), short circuit current (Isc), fill factor (FF) and conversion efficiency (Eta).

[0125] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A solar cell, characterized in that: including silicon wafer and electrode pattern; A first silicon oxide layer and a doped polysilicon layer are provided in a first area on the back side of the silicon wafer and are sequentially stacked in a direction gradually away from the silicon wafer; a doped silicide layer disposed in a second region on the back side of the silicon wafer; The first region is provided with the electrode pattern, and the electrode pattern forms an ohmic contact with the doped polysilicon layer.

2. The solar cell according to claim 1, wherein The doped silicide layer does not cover the doped polysilicon layer.

3. The solar cell according to claim 2, wherein It also includes a first anti-reflection film layer arranged on the surface of the doped silicide layer away from the back side of the silicon wafer.

4. The solar cell according to claim 3, characterized in that The first anti-reflection film layer includes a silicon nitride layer or a stacked aluminum oxide layer and a silicon nitride layer.

5. The solar cell according to claim 1, wherein The doped silicide layer covers the doped polysilicon layer to a side away from the silicon wafer.

6. The solar cell according to claim 5, characterized in that The doped silicide layer covers the doped polysilicon layer.

7. The solar cell according to claim 5 or 6, characterized in that It also includes a second anti-reflection film layer arranged on the surface of the doped silicide layer away from the back side of the silicon wafer, and the doped silicide layer includes a doped silicide layer arranged at one or two locations that does not cover the doped polysilicon layer and covers the doped polysilicon layer.

8. The solar cell according to claim 7, characterized in that The second anti-reflection film layer includes a silicon nitride layer or a stacked aluminum oxide layer and a silicon nitride layer.

9. The solar cell according to any one of claims 1 to 6, characterized in that It also includes a second silicon oxide layer disposed in the second region, and the second silicon oxide layer and the doped silicide layer are sequentially stacked in a direction gradually away from the silicon wafer.

10. The solar cell according to claim 9, characterized in that The thickness of the second silicon oxide layer is less than 3 nm.

11. The solar cell according to claim 1, wherein The thickness of the doped polysilicon layer is greater than the thickness of the doped silicide layer.

12. The solar cell according to claim 1, wherein The thickness of the doped polysilicon layer is 30 nm to 200 nm.

13. The solar cell according to claim 1, wherein The thickness of the doped silicide layer is 10 nm to 80 nm.

14. The solar cell according to any one of claims 1 to 6 and 10 to 13, wherein: The doping concentration of the doping element in the doped polysilicon layer is 6E19cm -3 ~7E20cm -3 .

15. The solar cell according to any one of claims 1 to 6 and 10 to 13, characterized in that: The doping concentration of the doping element in the doped silicide layer is 1E19cm -3 ~7E20cm -3 .

16. The solar cell according to any one of claims 1 to 6 and 10 to 13, characterized in that: The thickness of the first silicon oxide layer is less than 3 nm.

17. The solar cell according to any one of claims 1 to 6 and 10 to 13, characterized in that: The silicide in the doped silicide layer includes one or more of silicon carbide, silicon oxide and silicon nitride.

18. A method for preparing a solar cell, characterized in that: The steps include: forming a first silicon oxide layer and a doped polysilicon layer sequentially stacked in a direction gradually away from the silicon wafer in a first region on the back side of the silicon wafer; forming a doped silicide layer in a second region on the back side of the silicon wafer; The first region is provided with an electrode pattern; the electrode pattern forms an ohmic contact with the doped polysilicon layer.

19. The method for preparing a solar cell according to claim 18, wherein: The steps include: forming the first silicon oxide layer on the back side of the silicon wafer; forming the doped polysilicon layer on a surface of the first silicon oxide layer away from the silicon wafer; Parts of the first silicon oxide layer and the doped polysilicon layer are removed to form the doped silicide layer that does not cover the doped polysilicon layer.

20. The method for preparing a solar cell according to claim 18, wherein: The following steps are also included: forming the first silicon oxide layer on the back side of the silicon wafer; forming the doped polysilicon layer on a surface of the first silicon oxide layer away from the silicon wafer; removing a portion of the first silicon oxide layer and the doped polysilicon layer, The doped silicide layer is formed on the back side of the silicon wafer and on a side of the doped polysilicon layer away from the silicon wafer, so that the doped silicide layer covers the doped polysilicon.

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