Packaging structure and terminal

Abstract

The invention provides a packaging structure and a terminal. The packaging structure comprises a wafer, a first packaging layer arranged on the wafer and a solder ball arranged on the first packaging layer. The plurality of solder balls are arranged at intervals, and first connecting parts are arranged at the bottoms of the solder balls; a circuit is arranged in the wafer; a redistribution layer and a first capacitor structure are arranged in the first packaging layer; the redistribution layer is electrically connected with the circuit and is spaced from the first connecting part; the first capacitor structure is connected in series between the redistribution layer and the first connecting part, the first capacitor structure is located in the vacant area, and the first capacitor structure and the wafer are arranged at an interval; the vacant area comprises at least one of a first area and a second area, the first area is the area except the area where the first connecting part and the redistribution layer are located in the first packaging layer, and the second area is the area between the solder balls. According to the packaging structure and the terminal provided by the invention, the capacitance value of the capacitor structure can be relatively large so as to meet use requirements.

Description

Technical Field

[0001] The present application relates to the field of electronic devices, and in particular to a packaging structure and a terminal. Background Art

[0002] Chips are key components in terminals. Chips typically contain integrated circuits, and to ensure the stability of the integrated circuit's operation, capacitors are installed in the circuit. However, current capacitors are generally installed within the chip's wafer. As the size of the wafer (also known as the die) in the chip becomes smaller and smaller, the processing area left for the capacitor is getting smaller and smaller, which results in the capacitor size becoming smaller and smaller, making it difficult to meet the capacitance value requirements. Summary of the Invention

[0003] The present application provides a packaging structure and a terminal, which solves the problem that the processable area of ​​existing capacitors is getting smaller and smaller, and the capacitance value is difficult to meet the use requirements.

[0004] To achieve the above objectives, this application adopts the following technical solutions:

[0005] In a first aspect, a packaging structure is provided, comprising a wafer, a first packaging layer arranged on the wafer, and solder balls arranged on the first packaging layer. A plurality of solder balls are provided, the plurality of solder balls are spaced apart, and a first connecting portion is provided at the bottom of the solder balls. A circuit is provided in the wafer. A redistribution layer and a first capacitor structure are provided in the first packaging layer. The redistribution layer is electrically connected to the circuit and is spaced apart from the first connecting portion. The first capacitor structure is connected in series between the redistribution layer and the first connecting portion, the first capacitor structure is located in a vacant area, and the first capacitor structure is spaced apart from the wafer. The vacant area includes at least one of a first area and a second area, the first area being the area in the first packaging layer excluding the area where the first connecting portion and the redistribution layer are located, and the second area being the area between the solder balls.

[0006] The packaging structure provided by the embodiments of the present application breaks through the traditional idea that capacitor structures can only be located within the wafer. The first capacitor structure is moved from the wafer to the first packaging layer. Unlike the wafer, the first packaging layer is not provided with many circuits. The first packaging layer has fewer circuits and generally only has a redistribution layer and a first connection portion. The first capacitor structure is provided in the first packaging layer, which has at least the following advantages:

[0007] First, the first capacitor structure is processed in the first packaging layer. The size of the first capacitor structure can be made into micrometer level, while the size of the capacitor structure in the wafer is generally at nanometer level. In this way, the plate area of ​​the first capacitor structure can be increased from nanometer level to micrometer level, thereby increasing the capacitance value to meet the use requirements.

[0008] Secondly, the increase in the size of the first capacitor structure can reduce the difficulty of wafer processing and testing to a certain extent, making the processing of the wafer and the first capacitor structure simpler;

[0009] Thirdly, placing the first capacitor structure in the first packaging layer can reduce the space originally reserved for the capacitor structure in the wafer, allowing the size of the wafer to be further reduced, which is in line with current development trends.

[0010] Fourthly, the interconnection layers in the wafer are generally small in size and narrow in spacing. The capacitor structure is disposed in the wafer, and the stress generated during the preparation of the capacitor structure will have a significant impact on the reliability of the interconnection layers in the wafer. However, the interconnection layers in the first packaging layer are larger in size and wider in spacing. The first capacitor structure is disposed in the first packaging layer and spaced apart from the wafer. This can reduce the stress generated by the preparation of the first capacitor structure on the circuits on the wafer surface and the interconnection layers in the first packaging layer, thereby improving the reliability of the resulting packaging structure to a certain extent.

[0011] Fifthly, the utilization rate of the inner space and / or the upper space of the first packaging layer can be improved;

[0012] In a sixth aspect, the first capacitor structure is spaced apart from the wafer, so that the preparation of the first capacitor structure will not be affected by the circuit setting on the wafer surface, and more positions can be selected for preparation, making it easier to prepare.

[0013] The packaging structure provided in the embodiment of the present application can be used in various types of chips, which can reduce the difficulty of wafer processing and testing to a certain extent, and can further reduce the size of the chip.

[0014] In some embodiments, at least a portion of the first capacitor structure is located in the second region, and the second region is further provided with a second packaging layer, which is formed on the side of the first packaging layer facing away from the wafer and covers the portion of the first capacitor structure protruding from the first packaging layer. Using the solution provided by this embodiment, on the one hand, at least a portion of the first capacitor structure is located in the second region, which can make the first capacitor structure occupy a smaller space in the first packaging layer, and can make the volume of the first packaging layer unchanged or changed slightly, thereby facilitating the design requirement of miniaturization of the packaging structure; on the other hand, the portion of the first capacitor structure protruding from the first packaging layer is covered by the second packaging layer, which can make the first capacitor structure, while occupying part of the second region, also covered by the packaging material and not exposed to the air, thereby reducing the risk of damage, corrosion, etc. to the first capacitor structure.

[0015] In some embodiments, the thickness of the second packaging layer is less than the height of the solder balls protruding from the first packaging layer. This ensures that the solder balls are not affected by the second packaging layer and / or the first capacitor structure when connected to the circuit board, and also reduces the risk of damage to the second packaging layer and / or the first capacitor structure when the packaging structure is connected to the circuit board.

[0016] In some embodiments, the entire first capacitor structure is located within the second packaging layer. Since the second packaging layer is located between two adjacent solder balls, and no structures are generally disposed in this area, the entire first capacitor structure is disposed in this area, so that the configuration of the first capacitor structure does not affect the configuration of the redistribution layer or other structures in the first packaging layer.

[0017] In some embodiments, the first packaging layer includes multiple stacked layers, with the first capacitor structure located within one of the layers, or between two adjacent layers. This can reduce the space occupied by the first capacitor structure and mitigate the adverse effects of the first capacitor structure on other structures within the first packaging layer without increasing the volume of the packaging structure.

[0018] In some embodiments, the first capacitor structure includes a first division and a second division connected to the first division. At least a portion of the first division is located in the first region. At least a portion of the second division is located in the second region. The second region is also provided with a second packaging layer. The second packaging layer is formed on the side of the first packaging layer facing away from the wafer, and covers the portion of the second division located in the second region. By adopting the solution provided in this embodiment, a portion of the first capacitor structure (including at least a portion of the first division) is arranged in the first region, and another portion of the first capacitor structure (including at least a portion of the second division) is arranged in the second region. Compared with the solutions provided in the first and second embodiments, the area spanned by the first capacitor structure can be made larger, thereby making the size of the first capacitor structure larger and the capacitance value higher.

[0019] In some embodiments, the first capacitor structure includes a second connecting portion and at least two straight portions, wherein the at least two straight portions are spaced apart and connected by the second connecting portion. This allows the shape of the first capacitor structure to be flexibly adjusted based on the shape of the first region or the second region, resulting in a larger size and a higher capacitance value for the first capacitor structure.

[0020] In some embodiments, at least two straight portions are arranged opposite to each other and in parallel, which can make the first capacitor structure compact.

[0021] In some embodiments, at least two straight portions are staggered in a first direction, which is perpendicular to the thickness direction of the first encapsulation layer. This can reduce the thickness of the first capacitor structure and facilitate fabrication.

[0022] In some embodiments, the first packaging layer includes a first layer and a second layer. The first layer is formed on a wafer, and the second layer is formed on the first layer. The first layer is provided with a through hole that penetrates the first layer in the thickness direction. The first part of the redistribution layer is located between the first layer and the second layer, the second part of the redistribution layer is formed on the inner wall of the through hole, and the second part forms a recessed structure. At least part of the first capacitor structure is located in the recessed structure. This can make the size of the redistribution layer larger, and when the packaging structure is a power chip, the electrical energy stored in the power chip can be larger. Under normal circumstances, there is no circuit in this recessed structure, which will cause a waste of space in the first packaging layer. In this embodiment, at least part of the first capacitor structure is formed in the recessed structure. On the first hand, the space utilization rate of the first packaging layer can be improved, and on the second hand, the size of the first capacitor structure can be larger, so that the capacitance value of the first capacitor structure is higher, which can meet the needs of use.

[0023] In some embodiments, the shape of the portion of the first capacitor structure located within the recessed structure matches the shape of the recessed structure, so that the space of the first region can be fully utilized, resulting in a larger size of the first capacitor structure and a larger capacitance value.

[0024] In some embodiments, the package structure further includes a second capacitor structure disposed between the solder balls and the redistribution layer, with the second capacitor structure and the first capacitor structure corresponding to different solder balls. This embodiment provides a solution that stabilizes the performance of multiple circuits within the package structure, and allows for the selection of capacitor structures of different shapes based on the characteristics of different circuits.

[0025] In some embodiments, the first connection portion includes an underbump metallization (UBM) layer formed on the interface between the solder ball and the first packaging layer. The UBM layer includes a stacked electrode plate, a dielectric layer, and an electrode plate, and the UBM layer forms a second capacitor structure. This embodiment converts the UBM layer from a metal layer to a capacitor structure, which can reduce the size of the first packaging layer and achieve filtering functionality, achieving multiple goals at once.

[0026] In some embodiments, the first connection portion includes an underbump metallization (UBM) layer formed on the interface between the solder ball and the first packaging layer. The UBM layer is connected to the second capacitor structure, and at least a portion of the second capacitor structure is shaped to match the shape of the UBM layer. This allows the second capacitor structure to have a curved structure and be larger in size. Furthermore, the space in the corner area of ​​the UBM layer structure can be utilized, effectively utilizing the space in the first packaging layer.

[0027] In some embodiments, a third capacitor structure is further provided in the first packaging layer, and the third capacitor structure is connected in series or in parallel with the first capacitor structure to form a capacitor group. The structure and shape of the third capacitor structure may be the same as or different from the structure and shape of the first capacitor structure, and may be determined specifically according to the needs of use. The third capacitor structure and the first capacitor structure are connected in series or in parallel, so that the capacitance value of the capacitor group formed by the two is larger than that of only one capacitor structure, and the two capacitor structures can adopt different shapes and be set in different positions, so that the setting method of the capacitor structure is more diverse, and different first packaging layer structures can be applied, making the design of the capacitor structure easier.

[0028] In some embodiments, at least a portion of the thickness direction of the third capacitor structure is arranged at an angle to the thickness direction of the first capacitor structure. Using the solution provided by this embodiment can further improve the space utilization of the first packaging layer, making the packaging structure more compact and having a larger capacitance value.

[0029] In some embodiments, the first capacitor structure is a MIM capacitor. Compared to other capacitor structures, such as a polysilicon-insulator-polysilicon structure or a metal-oxide layer-silicon substrate structure, the first, second, and third capacitor structures employ MIM capacitors, which can reduce parasitic capacitance and contact resistance between the capacitor electrodes, thereby helping to improve the performance of the packaging structure.

[0030] In a second aspect, a terminal is provided, comprising multiple chips, at least one of which has a packaging structure employing the packaging structure described in the aforementioned embodiments. The chips in the terminal employing the aforementioned packaging structure can achieve a larger capacitance value for the capacitor structure within the chip, thereby stabilizing chip performance and, consequently, terminal performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the cross-sectional structure of the packaging structure in the related art;

[0032] Figure 2 A schematic cross-sectional view of a packaging structure provided in one embodiment of the present application;

[0033] Figure 3 A schematic cross-sectional view of a packaging structure provided in another embodiment of the present application;

[0034] Figure 4 A schematic cross-sectional view of a packaging structure provided in another embodiment of the present application;

[0035] Figure 5 A schematic cross-sectional view of a packaging structure provided in another embodiment of the present application;

[0036] Figure 6A schematic cross-sectional view of a packaging structure provided in another embodiment of the present application;

[0037] Figure 7 A schematic cross-sectional view of a first capacitor structure in a packaging structure provided in an embodiment of the present application;

[0038] Figure 8 A schematic cross-sectional view of a first capacitor structure in a packaging structure provided in another embodiment of the present application;

[0039] Figure 9 A schematic cross-sectional view of a first capacitor structure in a packaging structure provided in another embodiment of the present application;

[0040] Figure 10 A schematic cross-sectional view of a packaging structure provided in another embodiment of the present application;

[0041] Figure 11 for Figure 10 A schematic structural diagram of the first capacitor structure and the third capacitor structure;

[0042] Figures 12 to 35 Schematic diagrams of cross-sectional structures corresponding to steps 1 to 24 in the method for preparing a packaging structure provided in one embodiment of the present application.

[0043] Description of reference numerals:

[0044] 10', wafer; 11', active layer; 12', circuit; 13', capacitor; 14', pad; 20', first packaging layer; 21', passivation layer; 22', PI layer; 30', first seed layer; 40', redistribution layer; 50', solder ball; 60', conductive layer; 70', second seed layer;

[0045] 100, wafer; 110, circuit; 120, pad; 200, first packaging layer; 210, redistribution layer; 211, first portion; 212, second portion; 213, first seed layer; 220, first capacitor structure; 221, first subsection; 222, second subsection; 223, straight portion; 224, second connecting portion; 225, lower plate; 226, dielectric layer; 227, upper plate; 230, first layer; 231, first through hole; 232, first auxiliary layer; 23 3. First groove; 240. Second layer; 241. First PI layer; 242. Second through-hole; 243. Second seed layer; 244. Second copper layer; 245. Second PI layer; 246. Second groove; 247. Third PI layer; 248. Third through-hole; 249. Second auxiliary layer; 250. Second packaging layer; 251. Fourth through-hole; 260. Second capacitor structure; 270. Third capacitor structure; 300. Solder ball; 310. First connection portion; 320. Third seed layer;

[0046] X, first direction; Y, thickness direction of the first capacitor structure; Z, thickness direction of the third capacitor structure. DETAILED DESCRIPTION

[0047] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0048] In the description of this application, it should be understood that the terms "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this application.

[0049] To facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the first limiting portion and the second limiting portion are merely used to distinguish between different limiting portions and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean that they are different.

[0050] It should be noted that, in this application, words such as "in one embodiment" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described in this application as "in one embodiment" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "in one embodiment" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] In this application, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, indirect connection through an intermediate medium, internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0052] In order to make the purpose, technical solutions and advantages of this application more clear, this application is further described in detail below with reference to the accompanying drawings and embodiments.

[0053] With the development of society, terminals such as smart watches, mobile phones, and laptops are increasingly used in various aspects of modern life, work communication, etc. Chips are key components of terminals. The chips in the terminal include but are not limited to application processors, baseband chips, radio frequency chips, power management chips, memory chips, etc. These chips generally have integrated circuits, and in order to ensure the stability of the operation of the integrated circuit, capacitors are set in the circuit. Capacitors are a common component in circuits. Their main function is to store charge or electrical energy, and can act as filters, block DC, etc. in the circuit. In chip circuits, capacitors are mainly used to provide power supply filtering, resistor noise, power supply noise, and other forms of noise filtering.

[0054] Chip preparation involves at least the following steps: integrated circuit design, wafer manufacturing, wafer processing, and packaging and testing. Packaging and testing refers to packaging and testing, the purpose of which is to package and protect the products obtained after wafer processing to prevent them from damage or corrosion. Wafer processing is generally divided into the front end of the line (FEOL) and the back end of the line (BEOL). The front end is mainly the manufacture of metal-oxide-semiconductor field effect transistors (MOS tubes for short), and the back end is the construction of interconnection circuits. The above-mentioned capacitors are generally made in the back end process to play the role of filtering and decoupling to meet the requirements of signal integrity and power integrity.

[0055] In related technologies, the chip packaging structure mostly adopts the "Fan-Out Wafer-Level Packaging" (FOWLP) structure. Figure 1As shown, the wafer 10' is provided with an active layer 11' and a circuit 12' electrically connected to the active layer 11'. The circuit 12' is connected in series with a capacitor 13'. A pad 14' is provided on the top of the wafer 10', and the pad 14' is electrically connected to the circuit 12'. At the same time, a first packaging layer 20' is formed on the top of the wafer 10'. The first packaging layer 20' has at least two layers. A passivation layer 21' is formed on the surface of the wafer 10'. A polyimide (PI) layer is formed on the surface of the passivation layer 21'. A redistribution layer 40' is provided between the passivation layer 21' and the PI layer 22'. The passivation layer 21' is provided with a through hole. The redistribution layer 40' is electrically connected to the pad 14' through the through hole. In addition, a solder ball 50' is provided on the side of the PI layer 22' away from the passivation layer 21'. The solder ball 50' is connected to the redistribution layer 40' through a conductive layer 60'. Among them, the redistribution layer (RDL) is a metal layer added to the integrated circuit to redistribute the electrical connections. The conductive layer 60' and the redistribution layer 40' are generally made of copper layers, but other metal layers that can achieve conductivity can also be used. At the same time, in order to facilitate the preparation of the copper layer, a seed layer is generally set on the corresponding layer first, such as Figure 1 The first seed layer 30' is located below the redistribution layer 40' and the second seed layer 70' is located below the conductive layer 60'. The capacitor 13' is generally a Metal Insulator Metal (MIM) capacitor.

[0056] The above packaging structure results in at least the following problems when preparing capacitors: the size of the wafer (also known as die) in the chip is getting smaller and smaller, and the processable area left for the capacitor is getting smaller and smaller, which leads to the capacitor size becoming smaller and smaller, making it difficult to meet the capacitance value requirements.

[0057] In order to improve or at least partially improve the above problems, an embodiment of the present application provides a packaging structure. This packaging structure breaks through the inherent idea that the traditional capacitor structure can only be located inside the wafer, and moves the setting position of the first capacitor structure from inside the wafer to the first packaging layer, so that the first capacitor structure is located in the vacant area, and the first capacitor structure is spaced apart from the wafer. The above-mentioned vacant area includes at least one of the first area and the second area. The first area is the area in the first packaging layer excluding the area where the first connection portion and the redistribution layer are located, and the second area is the area between the solder balls. Since the first packaging layer is not provided with as many circuits as the wafer, there are fewer lines in the first packaging layer, and generally only a redistribution layer and a first connecting part are provided. The first capacitor structure is provided in the first packaging layer. The size of the first capacitor structure can be made into micron level, while the size of the capacitor structure in the wafer is generally at nanometer level. In this way, the plate area of ​​the first capacitor structure can be increased from nanometer level to micrometer level, thereby increasing the capacitance value to meet the needs of use, and to a certain extent reducing the difficulty of wafer processing and testing, making the processing of the wafer and the first capacitor structure simple, and also reducing the space originally reserved for the capacitor structure in the wafer, so that the size of the wafer can be further reduced, which is in line with the current development trend.

[0058] The packaging structure provided in the embodiments of the present application can be used in chips with capacitor structures and terminals using such chips. The terminals can be smart watches, mobile phones, laptops, etc. The chips can be power chips, such as linear power chips, voltage reference chips, switching power chips, voltage detection chips, battery charge management chips, gate drivers, load switches, wide bandgap switches, etc.; they can also be non-power chips, such as memory chips.

[0059] like Figure 2 As shown, an embodiment of the present application provides a packaging structure. The packaging structure includes a wafer 100, a first packaging layer 200 disposed on the wafer 100, and solder balls 300 disposed on the first packaging layer 200. A plurality of solder balls 300 are provided. The plurality of solder balls 300 are spaced apart. A first connecting portion 310 is provided at the bottom of the solder balls 300. The first connecting portion 310 can be a bump metallization layer or other structures. When the first connecting portion 310 is a bump metallization layer, the performance of the PN junction in the semiconductor can be better stimulated.

[0060] The wafer 100 includes a circuit 110. The circuit 110 can be designed according to the function of the chip, and is not limited here.

[0061] The first packaging layer 200 is provided with a redistribution layer 210 and a first capacitor structure 220. The redistribution layer 210 can be provided in a variety of ways according to the needs of use. For example, when the chip is a power chip, a through hole can be provided on the layer body close to the wafer 100 in the first packaging layer 200, and then the redistribution layer 210 can be prepared on the surface of the layer body, and the redistribution layer 210 can cover the inner wall of the through hole to form a Figure 2 When the chip is a non-power chip, it can be laid flat on the surface of the wafer 100.

[0062] The redistribution layer 210 is used to connect the circuit 110 and the solder ball 300. To facilitate the connection, the surface of the wafer 100 is generally provided with a solder pad 120 connected to the circuit 110, and the solder ball 300 is provided with a first connecting portion 310. Therefore, the redistribution layer 210 generally connects the solder pad 120 and the first connecting portion 310 to achieve an electrical connection between the solder pad 120 and the solder ball 300.

[0063] The first capacitor structure 220 is generally used for filtering and can be connected in series between the redistribution layer 210 and the first connection portion 310. It is understood that the first capacitor structure 220 can be directly connected to the redistribution layer 210 and the first connection portion 310, respectively, or can be connected through wires, lines, or other electrical connectors.

[0064] The first capacitor structure 220 is located in the vacant area, and the first capacitor structure 220 is spaced apart from the wafer 100. The vacant area includes at least one of a first area and a second area. The first area is the area of ​​the first packaging layer 200 excluding the first connection portion 310 and the redistribution layer 210. The second area is the area between the solder balls 300.

[0065] The first capacitor structure 220 is located in the vacant area, which includes at least the following situations: first, the entire first capacitor structure 220 is located in the first area; second, a portion of the first capacitor structure 220 is located in the above-mentioned first area, and the other portion is located in the second area between the solder balls 300; third, the entire first capacitor structure 220 is located in the above-mentioned second area.

[0066] It should be noted that in the second and third cases mentioned above, at least part of the first capacitor structure 220 can be located outside the first packaging layer 200, or the first packaging layer 200 can form a second packaging layer 250 in the second area, and at least part of the first capacitor structure 220 is located in the above-mentioned second packaging layer 250.

[0067] The capacitance setting principle of the packaging structure provided in the embodiment of the present application is as follows:

[0068] Unlike the wafer 100, the first packaging layer 200 is not provided with more circuits 110. The first packaging layer 200 has fewer circuits and is generally provided with only a redistribution layer 210 and a first connection portion 310. Moreover, since the redistribution layer 210 and / or the first connection portion 310 may have some bending structures, the space utilization rate of the first packaging layer 200 is not high. Figure 2 As shown, it is specifically manifested in the following areas:

[0069] In the first area, a portion of the redistribution layer 210 covers the sidewalls of the through-hole, forming a recessed structure. Circuits are generally not arranged in the area enclosed by the recessed structure, resulting in a waste of space in the first packaging layer 200. In particular, in power chips, to ensure a certain current flow capacity, the through-holes provided in the first packaging layer 200 are often large in size. This results in a relatively large depth of the recessed structure, resulting in further space waste.

[0070] In the second area, if the first connection portion 310 adopts a bump metallization layer, it will also have a bent structure, with the middle portion protruding toward the inside of the first packaging layer 200, forming a corner structure between the middle portion and the edge portion. The area enclosed by the corner structure is generally not provided with cables, which will also cause a waste of space in the first packaging layer 200.

[0071] In the third area, since multiple circuits 110, multiple redistribution layers 210, and multiple solder balls 300 are generally provided in the same chip, there is generally a certain distance between two adjacent redistribution layers 210 and two adjacent first connection portions 310. Generally, no circuits are provided in this distance area.

[0072] The fourth area, the second surface of the first packaging layer 200 is generally a plane, and generally no structure is provided between two adjacent solder balls 300 . This area (ie, the second area) will cause waste of space above the first packaging layer 200 .

[0073] The first area mentioned above includes the first area, the second area and the third area mentioned above.

[0074] The first capacitor structure 220 is arranged in a vacant area, that is, the first capacitor structure 220 can be arranged in an area that was originally unused in the first packaging layer 200. Since the area of ​​this area is large, the area of ​​the plate of the first capacitor structure 220 can be made larger. The capacitance calculation formula is as follows: C = εS / 4πkd, where C is the capacitance, ε is an electrical constant, S is the area of ​​one surface of the capacitor plate, d is the distance between the capacitor plates, and k is the constant of the electrostatic force. According to the capacitance calculation formula, the size of the capacitance value C is related to the area of ​​the plate and the distance between the plates (which is also the thickness of the dielectric layer 226). The larger the plate area and the smaller the thickness of the dielectric layer 226, the greater the capacitance value.

[0075] The packaging structure provided by the embodiments of the present application breaks through the traditional idea that capacitor structures can only be located within the wafer 100. The first capacitor structure 220 is moved from the wafer 100 to the first packaging layer 200. Unlike the wafer 100, the first packaging layer 200 is not provided with a large number of circuits 110. The first packaging layer 200 has fewer circuits and generally only has a redistribution layer 210 and a first connecting portion 310. The first capacitor structure 220 is provided in the first packaging layer 200, which has at least the following advantages:

[0076] First, the first capacitor structure 220 is processed on the first packaging layer 200. The size of the first capacitor structure 220 can be made into micrometer level, while the size of the capacitor structure in the wafer 100 is generally at the nanometer level. In this way, the plate area of ​​the first capacitor structure 220 can be increased from the nanometer level to the micrometer level, thereby increasing the capacitance value to meet the use requirements.

[0077] Secondly, the increase in the size of the first capacitor structure 220 can reduce the difficulty of processing and testing the wafer 100 to a certain extent, making the processing of the wafer 100 and the first capacitor structure 220 simpler;

[0078] Thirdly, disposing the first capacitor structure 220 in the first packaging layer 200 can reduce the space originally reserved for the capacitor structure in the wafer 100, so that the size of the wafer 100 can be further reduced, which is in line with current development trends;

[0079] Fourthly, the interconnection layer in the wafer 100 is generally small in size and narrow in pitch. The capacitor structure is disposed in the wafer 100. The stress generated during the preparation of the capacitor structure will have a significant impact on the reliability of the interconnection layer in the wafer 100. However, the interconnection layer in the first packaging layer 200 is large in size and wide in pitch. The first capacitor structure 220 is disposed in the first packaging layer 200 and spaced apart from the wafer 100. This can reduce the stress generated by the preparation of the first capacitor structure 220 on the circuit 110 on the surface of the wafer 100 and the interconnection layer in the first packaging layer 200, thereby improving the reliability of the resulting packaging structure to a certain extent.

[0080] Fifthly, the utilization rate of the inner space and / or the upper space of the first encapsulation layer 200 can be improved;

[0081] Sixthly, the first capacitor structure 220 is spaced apart from the wafer 100 , so that the preparation of the first capacitor structure 220 will not be affected by the circuit setting on the surface of the wafer 100 , and there are more selectable positions for preparation, making it easier to prepare.

[0082] The packaging structure provided in the embodiment of the present application can be used in various types of chips, which can reduce the difficulty of processing and testing the wafer 100 to a certain extent, and can further reduce the size of the chip.

[0083] As mentioned above, the first capacitor structure 220 can be configured in a variety of ways. For ease of understanding, the following examples are provided:

[0084] First embodiment

[0085] like Figure 2 As shown, at least a portion of the first capacitor structure 220 is located in the second region. The second region is also provided with a second encapsulation layer 250. The second encapsulation layer 250 is formed on the side of the first encapsulation layer 200 facing away from the wafer 100 and covers the portion of the first capacitor structure 220 protruding from the first encapsulation layer 200. The material of the second encapsulation layer 250 in this embodiment can be the same as that of the first encapsulation layer 200, or it can be different from the material of the first encapsulation layer 200, depending on the specific application needs.

[0086] By adopting the solution provided in this embodiment, on the one hand, at least part of the first capacitor structure 220 is located in the second area, so that the first capacitor structure 220 occupies a smaller space in the first packaging layer 200, and the volume of the first packaging layer 200 does not change, or changes only slightly, which is conducive to the design requirement of miniaturization of the packaging structure; on the other hand, the part of the first capacitor structure 220 protruding from the first packaging layer 200 is covered by the second packaging layer 250, so that the first capacitor structure 220 can be covered by the packaging material while occupying part of the second area, and will not be exposed to the air, thereby reducing the risk of damage, corrosion, etc. to the first capacitor structure 220.

[0087] It can be understood that if the connection structure between the first capacitor structure 220 and the first connection part 310 or the redistribution layer 210 also protrudes from the first packaging layer 200, the protruding part of the above connection structure can also be covered by the second packaging layer 250, thereby reducing the risk of the second connection part 224 being corroded or damaged.

[0088] In this embodiment, the first capacitor structure 220 may be as follows Figure 2 The flat plate structure shown can also be Figure 3 The bending structure shown can also be a structure of other shapes, which can be determined according to the specific use requirements.

[0089] On the basis of the above embodiments, in order to reduce the adverse effects of the second packaging layer 250 and the first capacitor structure 220 on the installation of the packaging structure, in some embodiments, the thickness of the second packaging layer 250 is less than the height of the solder balls 300 protruding from the first packaging layer 200. This ensures that when the solder balls 300 are connected to the circuit board 110, they are not affected by the second packaging layer 250 and / or the first capacitor structure 220, and also reduces the risk of damage to the second packaging layer 250 and / or the first capacitor structure 220 when the packaging structure is connected to the circuit board 110.

[0090] In some embodiments, the entire first capacitor structure 220 is located within the second encapsulation layer 250 .

[0091] Since the second packaging layer 250 is located between two adjacent solder balls 300, no structure is generally set in this area, and the first capacitor structure 220 is entirely set in this area, so that the setting of the first capacitor structure 220 does not affect the setting of the redistribution layer 210 or other structures in the first packaging layer 200.

[0092] Second embodiment

[0093] like Figure 4 As shown, the first capacitor structure 220 is located in the first area. The first packaging layer 200 includes a plurality of layers arranged in a stacked manner. For example, the first packaging layer 200 may include two layers, one of which is a passivation layer and the other is a PI layer. In other embodiments, the first packaging layer 200 may also adopt other settings, such as setting three or four layers, which may be determined according to the circuits set in the first packaging layer 200 and the needs of use, and is not limited here. The first capacitor structure 220 is located in one of the layers, or between two adjacent layers. That is, the first capacitor structure 220 can be set in a variety of ways. In some embodiments, the first capacitor structure 220 is located in one of the layers of the first packaging layer 200; in other embodiments, the first capacitor structure 220 is located between two adjacent layers.

[0094] It should be noted that when the first capacitor structure 220 is located in one of the layers of the first packaging layer 200, the layer where the first capacitor structure 220 is located is generally a layer that is spaced apart from the wafer 100, that is, the layer where the first capacitor structure 220 is located is generally not in contact with the wafer 100. This can ensure that the preparation of the first capacitor structure 220 will not be affected by the arrangement of the circuits on the surface of the wafer 100, resulting in more selectable locations for preparation and easier preparation. At the same time, the preparation of the first capacitor structure 220 can also have less adverse effects on the circuits on the surface of the wafer 100, thereby stabilizing the performance of the packaging structure.

[0095] In addition, the first capacitor structure 220 is set in a layer body or between two adjacent layers, which can reduce the space occupied by the first capacitor structure 220, reduce the adverse effects of the setting of the first capacitor structure 220 on other structures in the first packaging layer 200, and will not increase the volume of the packaging structure.

[0096] In this embodiment, the first capacitor structure 220 can adopt various shapes, such as a flat plate structure, that is, the two plates of the first capacitor structure 220 are both flat plates; Figure 4 The structure with one end bent as shown; Figure 5 The structure shown in FIG. Figure 5 The structure shown utilizes the space formed by the redistribution layer 210. Of course, in other embodiments, the first capacitor structure 220 may also adopt other shapes, which may be determined according to specific application requirements.

[0097] When the first capacitor structure 220 is configured as Figure 4 、 Figure 5 When the structure shown is used, compared with the flat plate structure, the plate area is larger and the capacitance value is higher.

[0098] In such Figure 5 In the illustrated packaging structure, the first packaging layer 200 includes a first layer 230 and a second layer 240. The first layer 230 is formed on the wafer 100, and the second layer 240 is formed on the first layer 230. It is understood that the first layer 230 and the second layer 240 in this embodiment can be manufactured through a single process or multiple processes. That is, the first layer 230 and the second layer 240 can be a single integrally formed layer or a composite layer composed of multiple layers, and the specific process can be determined according to the production requirements.

[0099] The solder ball 300 is provided on the side of the second layer 240 facing away from the first layer 230. The first layer 230 is provided with a through hole that penetrates the first layer 230 in the thickness direction, and the redistribution layer 210 includes at least a first part 211 and a second part 212. The first part 211 of the redistribution layer 210 is located between the first layer 230 and the second layer 240. The second part 212 of the redistribution layer 210 is formed on the inner wall of the through hole, and the second part 212 forms a recessed structure, and at least part of the first capacitor structure 220 is located in the recessed structure. There can be one or more first parts 211, which can be determined according to the design requirements of the redistribution layer 210. When there are multiple first parts 211, the multiple first parts 211 can be arranged on both sides of the second part 212 and connected to the second part 212 respectively.

[0100] In this embodiment, the redistribution layer 210 can be surrounded by the above-mentioned recessed structure, so that the size of the redistribution layer 210 can be larger. When the packaging structure is a power chip, the power chip can store more electrical energy. Under normal circumstances, no circuit is set in this recessed structure, which will cause a waste of space in the first packaging layer 200. In this embodiment, at least part of the first capacitor structure 220 is formed in the recessed structure. On the first hand, it can improve the space utilization rate of the first packaging layer 200. On the second hand, it can make the size of the first capacitor structure 220 larger, so that the capacitance value of the first capacitor structure 220 is higher, which can meet the needs of use.

[0101] The shape of the portion of the first capacitor structure 220 located within the recessed structure may be the same as or similar to the shape of the recessed structure, or may be different from the shape of the recessed structure. For example, the cross-sectional shape of the recessed structure is generally a trapezoid, while the cross-sectional shape of the portion of the first capacitor structure 220 located within the recessed structure may be a strip, a V-shape, a rectangle, a trapezoid, etc., which may be determined based on specific usage requirements. When the shape of the portion of the first capacitor structure 220 located within the recessed structure matches the shape of the recessed structure, that is, when the shape of the portion of the first capacitor structure 220 located within the recessed structure can be the same as or similar to the shape of the recessed structure, full utilization of the space in the first region can be achieved, so that the first capacitor structure 220 is larger in size and has a larger capacitance value.

[0102] Third embodiment

[0103] like Figure 6 As shown, the first capacitor structure 220 includes a first subsection 221 and a second subsection 222 connected to the first subsection 221. At least a portion of the first subsection 221 is located in the first region. At least a portion of the second subsection 222 is located in the second region. A second encapsulation layer 250 is also provided in the second region. The second encapsulation layer 250 is formed on a side of the first encapsulation layer 200 facing away from the wafer 100 and covers the portion of the second subsection 222 located in the second region.

[0104] In this embodiment, the first subdivision 221 and the second subdivision 222 each include two plates and a dielectric layer 226 disposed between the two plates. The shape of the first subdivision 221 and the shape of the second subdivision 222 can be the same or different, depending on the specific needs of use. In this embodiment, the first subdivision 221 can be completely located in the first area, and the second subdivision 222 can be completely located in the second area; the first subdivision 221 can be completely located in the first area, and a portion of the second subdivision 222 can be located in the first area and another portion can be located in the second area; the first subdivision 221 can be partially located in the first area, another portion can be located in the second area, and the entire second subdivision 222 can be located in the second area; the first subdivision 221 can be partially located in the first area, another portion can be located in the second area, and the second subdivision 222 can be partially located in the first area and another portion can be located in the second area, and the second subdivision 222 can be partially located in the first area and another portion can be located in the second area.

[0105] By adopting the solution provided in this embodiment, a portion of the first capacitor structure 220 (including at least a portion of the first division 221) is set in the first area, and another portion of the first capacitor structure 220 (including at least a portion of the second division 222) is set in the second area. Compared with the solutions provided in the first and second embodiments, the area spanned by the first capacitor structure 220 can be made larger, thereby making the size of the first capacitor structure 220 larger and the capacitance value higher.

[0106] In the above embodiments, the first capacitor structure 220 can adopt a flat plate structure or a bent structure. Figures 7 to 9 As shown, in some embodiments, the first capacitor structure 220 includes a second connecting portion 224 and at least two straight portions 223, and the at least two straight portions 223 are spaced apart and connected by the second connecting portion 224. The plate of the straight portion 223 in this embodiment is a flat plate, which can be parallel to the surface of the wafer 100 or the metal layer in the redistribution layer 210, or can be perpendicular to the surface of the wafer 100 or the metal layer in the redistribution layer 210. Figure 7 and Figure 8 As shown, the plates of the straight portion 223 are all arranged horizontally, that is, parallel to the surface of the wafer 100; Figure 9 In the figure, the plates of the straight portion 223 are all arranged vertically, that is, perpendicular to the surface of the wafer 100.

[0107] By adopting the solution provided in this embodiment, the shape of the first capacitor structure 220 can be flexibly set according to the shape of the first region or the second region, and the size of the first capacitor structure 220 can be larger and the capacitance value can be higher.

[0108] like Figure 7 and Figure 9As shown, in some embodiments, at least two straight portions 223 are disposed opposite to and in parallel with each other, which can make the structure of the first capacitor structure 220 compact.

[0109] like Figure 8 As shown, in some embodiments, at least two straight portions 223 are staggered in a first direction X, which is perpendicular to the thickness direction of the encapsulation layer. This can reduce the thickness of the first capacitor structure 220 and facilitate fabrication.

[0110] The same package structure is often provided with multiple circuits 110 and multiple solder balls 300. In order to ensure that the performance of the multiple circuits 110 is stable, Figures 2 to 6 As shown, in some embodiments, the package structure also includes a second capacitor structure 260 arranged between the solder ball 300 and the redistribution layer 210. The second capacitor structure 260 and the first capacitor structure 220 correspond to different solder balls 300. For example, the first capacitor structure 220 can correspond to one of the solder balls 300, which can be recorded as solder ball 1, and the second capacitor structure 260 can correspond to another solder ball 300, which can be recorded as solder ball 2. The structure and shape of the second capacitor structure 260 can be the same as or different from the structure and shape of the first capacitor structure 220, and can be specifically determined according to the needs of use. By adopting the solution provided by this embodiment, the performance of multiple circuits in the package structure can be stabilized, and capacitor structures of different shapes can be selected according to the characteristics of different circuits.

[0111] like Figures 2 to 6 As shown, in some embodiments, the first connection portion 310 includes an under-bump metallization layer formed below the solder ball 300. The under-bump metallization layer includes a stacked electrode plate, a dielectric layer, and an electrode plate, and the under-bump metallization layer forms the second capacitor structure 260.

[0112] In this embodiment, the under-bump metallization layer is changed from a metal layer to a capacitor structure, which can reduce the size of the first packaging layer 200 and realize the filtering function, achieving multiple goals at one stroke.

[0113] In some embodiments, the first connection portion 310 includes an under-bump metallization layer formed under the solder ball 300 , the under-bump metallization layer is connected to the second capacitor structure 260 , and at least a portion of the second capacitor structure 260 has a shape that matches the shape of the under-bump metallization layer.

[0114] At least a portion of the shape of the second capacitor structure 260 is adapted to the shape of the UBM layer, meaning that at least a portion of the shape of the second capacitor structure 260 is identical or similar to the shape of the UBM layer. This allows the second capacitor structure 260 to have a curved structure and be larger in size. Furthermore, the space in the corner area of ​​the UBM layer can be utilized, effectively utilizing the space of the first packaging layer 200.

[0115] Sometimes, only one capacitor structure (ie, the first capacitor structure 220) is provided in the connection line between the solder ball 300 and the circuit 110, which cannot meet the use requirements. To solve this problem, Figure 10 and Figure 11 As shown, in some embodiments, a third capacitor structure 270 is further provided in the first packaging layer 200. The third capacitor structure 270 is connected in series or in parallel with the first capacitor structure 220 to form a capacitor group.

[0116] The structure and shape of the third capacitor structure 270 can be the same as or different from the structure and shape of the first capacitor structure 220, depending on the specific needs. The third capacitor structure 270 and the first capacitor structure 220 are connected in series or in parallel, which can make the capacitor group formed by the two have a larger capacitance value than that of only one capacitor structure. The two capacitor structures can adopt different shapes and be arranged in different positions, making the arrangement of the capacitor structure more diverse and applicable to different first packaging layer 200 structures, making the design of the capacitor structure easier.

[0117] It is understandable that, according to usage requirements, in some embodiments, the second capacitor structure 260 and the third capacitor structure 270 may exist simultaneously in the same packaging structure.

[0118] Since the first packaging layer 200 often has 2P2M and 3P3M structures, the vertical space can also be utilized to make more capacitor structures perpendicular to the redistribution layer 210 to increase the number of capacitors. In some embodiments, at least part of the thickness direction Z of the third capacitor structure 270 is arranged at an angle to the thickness direction Y of the first capacitor structure 220. Figure 10 and Figure 11 As shown, the thickness direction Z of the third capacitor structure 270 is perpendicular to the thickness direction Y of the first capacitor structure 220. In other embodiments, the thickness direction Z of the third capacitor structure 270 and the thickness direction Y of the first capacitor structure 220 may also form other angles, such as 30°, 45°, 60°, etc. By adopting the solution provided by this embodiment, the space utilization rate of the first packaging layer 200 can be further improved, making the packaging structure more compact and having a larger capacitance value.

[0119] In some embodiments, at least one of the first capacitor structure 220 , the second capacitor structure 260 , and the third capacitor structure 270 is a MIM capacitor.

[0120] The first capacitor structure 220, the second capacitor structure 260, and the third capacitor structure 270 use MIM capacitors, which can reduce parasitic capacitance and contact resistance between the two electrodes of the capacitor compared to other capacitor structures, such as polysilicon-insulator-polysilicon structure or metal-oxide layer-silicon substrate structure, thereby helping to improve the performance of the packaging structure.

[0121] It is understandable that, based on the above embodiments, the capacitance value can be increased by replacing the materials of the plates and the dielectric layer 226 of each capacitor structure.

[0122] Another embodiment of the present application provides a terminal, which includes multiple chips, and the packaging structure of at least one chip is the packaging structure provided by any of the above embodiments.

[0123] The chip in the terminal adopts the above packaging structure, which can make the capacitance value of the capacitor structure in the chip larger, make the chip performance stable, and thus make the terminal performance stable.

[0124] The package structure provided in any of the above embodiments can be manufactured using existing manufacturing processes. For ease of understanding, the manufacturing method of the package structure is described below by taking the manufacturing of the first capacitor structure 220 above the RDL structure as an example, wherein the first capacitor structure 220 is a MIM capacitor:

[0125] Step 1: Prepare the wafer 100 to be packaged, such as Figure 12 As shown, a first layer 230 is provided on the wafer 100 , and the first layer 230 is a passivation layer.

[0126] Step 2: If Figure 13 As shown, a first through hole 231 is prepared above the pad 120 in the wafer 100 by exposure and development methods. The first through hole 231 is a through hole position of the RDL structure.

[0127] Step 3: If Figure 14 As shown, a first seed layer 213 is deposited. The material of the first seed layer 213 can be any one of Ti, TiW, and Cu, in preparation for copper electroplating.

[0128] Step 4: If Figure 15 As shown, a first auxiliary layer 232 is spin-coated, and the first auxiliary layer 232 is a PR (Photoresist) layer or a PI layer.

[0129] Step 5: Figure 16 As shown, a portion of the first auxiliary layer 232 is removed by exposure and development to obtain a first groove 233 . The first groove 233 is a path for manufacturing a copper wiring layer in the RDL structure.

[0130] Step 6: Figure 17As shown, a first copper layer is electroplated in the first groove 233 . The first copper layer is the copper routing layer in the RDL structure and is also the redistribution layer 210 .

[0131] Step 7: Figure 18 As shown, the remaining first auxiliary layer 232 is removed, and the first seed layer 213 outside the RDL structure is etched away, that is, the portion of the first seed layer 213 originally covered by the remaining first auxiliary layer 232 is etched away.

[0132] Step 8: Figure 19 As shown, a first PI layer 241 is spin-coated, and the first PI layer 241 is a part of the second layer body 240 mentioned above.

[0133] Step 9: Figure 20 As shown, a second through hole 242 is made by exposure and development. The second through hole 242 is used to prepare an electrical connection structure, which is a structure for achieving electrical connection between the redistribution layer 210 and the plate of the first capacitor structure 220.

[0134] Step 10: Figure 21 As shown, a second seed layer 243 is deposited in the second through hole 242 . The material of the second seed layer 243 can be any one of Ti, TiW, and Cu, in preparation for copper electroplating.

[0135] Step 11: Figure 22 As shown, a second copper layer 244 is electroplated in the second through hole 242 .

[0136] Step 12: Figure 23 As shown, a second PI layer 245 is spin-coated, and the second PI layer 245 is a part of the second layer body 240 .

[0137] Step 13: Figure 24 As shown, a portion of the second PI layer 245 is removed by exposure and development to form a second groove 246 . The second groove 246 is where the first capacitor structure 220 is formed.

[0138] Step 14: Figure 25 As shown, the lower plate 225 of the first capacitor structure 220 is deposited by using PCD (Physical Vapor Deposition) or ALD (Atomic layer deposition) methods, and the plate material is not limited to TiN.

[0139] Step 15: Figure 26 As shown, the dielectric layer 226 of the MIM capacitor is deposited by PCD or ALD, and the material of the dielectric layer 226 is not limited to ZrO2 and HfO2.

[0140] Step 16: Figure 27 As shown, the upper plate 227 of the MIM capacitor is deposited by PCD or ALD, and the plate material is not limited to TiN.

[0141] Step 17: Figure 28 As shown, a third PI layer 247 is spin-coated, and the third PI layer 247 is a part of the second layer body 240.

[0142] Step 18: Figure 29 As shown, a third through hole 248 is formed by exposure and development. The third through hole 248 is a through hole for preparing UBM (under ball metal, depositing an under bump metal layer).

[0143] Step 19: Figure 30 As shown, a third seed layer 320 is deposited. The material of the third seed layer 320 can be any one of Ti, TiW, and Cu, in preparation for copper electroplating.

[0144] Step 20: Figure 31 As shown, a second auxiliary layer 249 is spin-coated, and the second auxiliary layer 249 may be a PI layer.

[0145] Step 21: Figure 32 As shown, a portion of the second auxiliary layer 249 is removed by exposure and development to form a fourth through hole 251 . The fourth through hole 251 is a structure for forming a UBM layer.

[0146] Step 22: Figure 33 As shown, Cu is electroplated in the fourth through hole 251 and a UBM is fabricated to form the first connecting portion 310 .

[0147] Step 23: Figure 34 As shown, the remaining second auxiliary layer 249 is removed.

[0148] Step 24: Figure 35 As shown, solder balls 300 are obtained by applying flux, planting balls, and reflowing.

[0149] The above solution only provides a processing method for a single capacitor. We can make multiple capacitors in parallel to increase the capacitance value, such as Figure 10 and Figure 11 shown.

[0150] Finally, it should be noted that the above are only specific embodiments of this application, but the scope of protection of this application is not limited to them. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A packaging structure, characterized in that: It includes a wafer, a first packaging layer arranged on the wafer, and solder balls arranged on the first packaging layer; there are multiple solder balls, the multiple solder balls are arranged at intervals, and a first connecting portion is provided at the bottom of the solder balls; a circuit is provided in the wafer; a redistribution layer and a first capacitor structure are provided in the first packaging layer; the redistribution layer is electrically connected to the circuit and is spaced apart from the first connecting portion; the first capacitor structure is connected in series between the redistribution layer and the first connecting portion, the first capacitor structure is located in a vacant area, and the first capacitor structure is spaced apart from the wafer; the vacant area includes at least one of a first area and a second area, the first area is the area in the first packaging layer excluding the area where the first connecting portion and the redistribution layer are located, and the second area is the area between the solder balls.

2. The packaging structure according to claim 1, wherein: At least part of the first capacitor structure is located in the second area. The second area is also provided with a second packaging layer. The second packaging layer is formed on the side of the first packaging layer away from the wafer and covers the part of the first capacitor structure protruding from the first packaging layer.

3. The packaging structure according to claim 2, wherein: The thickness of the second packaging layer is smaller than the height of the solder ball protruding from the first packaging layer.

4. The packaging structure according to claim 2 or 3, characterized in that: The entire first capacitor structure is located within the second packaging layer.

5. The packaging structure according to claim 1, wherein: The first packaging layer includes a plurality of stacked layers, and the first capacitor structure is located in one of the layers, or between two adjacent layers.

6. The packaging structure according to claim 1, wherein: The first capacitor structure includes a first branch and a second branch connected to the first branch, at least part of the first branch is located in the first area, at least part of the second branch is located in the second area, and the second area is also provided with a second packaging layer, which is formed on the side of the first packaging layer facing away from the wafer and covers the part of the second branch located in the second area.

7. The packaging structure according to any one of claims 1 to 6, wherein: The first capacitor structure includes a second connecting portion and at least two straight portions, and the at least two straight portions are spaced apart and connected by the second connecting portion.

8. The packaging structure according to claim 7, wherein: At least two of the straight portions are arranged opposite to each other and in parallel.

9. The packaging structure according to claim 7, wherein: At least two of the straight portions are staggered in a first direction, where the first direction is perpendicular to a thickness direction of the first encapsulation layer.

10. The packaging structure according to any one of claims 1 to 7, characterized in that: The first packaging layer includes a first layer body and a second layer body, the first layer body is formed on the wafer, the second layer body is formed on the first layer body, the first layer body is provided with a through hole penetrating itself along the thickness direction, the first part of the redistribution layer is located between the first layer body and the second layer body, the second part of the redistribution layer is formed on the inner wall of the through hole, the second part forms a recessed structure, and at least part of the first capacitor structure is located in the recessed structure.

11. The packaging structure according to claim 10, wherein: The shape of the portion of the first capacitor structure located in the recessed structure is adapted to the shape of the recessed structure.

12. The packaging structure according to any one of claims 1 to 11, characterized in that: The packaging structure further includes a second capacitor structure disposed between the solder ball and the redistribution layer, wherein the second capacitor structure and the first capacitor structure correspond to different solder balls.

13. The packaging structure according to claim 12, wherein: The first connection portion includes an under-bump metallization layer formed on the contact surface between the solder ball and the first packaging layer. The under-bump metallization layer includes a stacked electrode, a dielectric layer and an electrode. The under-bump metallization layer forms the second capacitor structure.

14. The packaging structure according to claim 12, wherein: The first connection portion includes an under-bump metallization layer formed on the contact surface between the solder ball and the first packaging layer. The under-bump metallization layer is connected to the second capacitor structure, and at least a portion of the shape of the second capacitor structure is adapted to the shape of the under-bump metallization layer.

15. The packaging structure according to any one of claims 1 to 14, characterized in that: A third capacitor structure is further provided in the first packaging layer, and the third capacitor structure is connected in series or in parallel with the first capacitor structure to form a capacitor group.

16. The packaging structure according to claim 15, wherein: A thickness direction of at least a portion of the third capacitor structure is arranged at an angle to a thickness direction of the first capacitor structure.

17. The packaging structure according to any one of claims 1 to 16, characterized in that: The first capacitor structure is a MIM capacitor.

18. A terminal, characterized in that: The terminal includes multiple chips, and the packaging structure of at least one of the chips is the packaging structure according to any one of claims 1 to 17.

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