Sample preparation for charged particle beam imaging

Abstract

A method of preparing a sample for charged particle beam inspection is provided. The method includes providing a semiconductor structure sample and identifying an electrically isolated region in a region of the sample to be inspected. The method further includes providing an electrical connection to the at least one electrically isolated region.

Description

Technical Field

[0001] Various embodiments of the present invention relate to sample preparation techniques for semiconductor structures for charged particle beam imaging, such as scanning electron microscopy (SEM) imaging, and inspection of semiconductor structures by charged particle beam imaging. Background Art

[0002] As microstructures, such as those in semiconductor components, continue to grow smaller and more complex, the need for developing and optimizing inspection systems for these small structures is increasing. The development and production of semiconductor components requires high-resolution metrology tools with high throughput. Furthermore, the production technology for these semiconductor components requires corresponding process monitoring.

[0003] One method used to inspect the semiconductor structures of such components is scanning electron microscopy (SEM), which uses an electron beam to scan the surface of a sample. To increase throughput, multibeam scanning electron microscopy (MSEM) has been used, which uses multiple electron beams for scanning. This type of MSEM is described, for example, in US Pat. No. 7,244,949 B2 and US Pat. No. 2019 / 0355544 A1. Charged particle beams other than electron beams (e.g., ion beams) may also be used.

[0004] Recently, 3D volumetric image generation has been introduced. 3D volumetric images are generated using a cross-sectional slicing technique, in which a charged particle beam system is used to slice and image an integrated semiconductor structure to determine a 3D volumetric image of a predetermined volume within the semiconductor structure. This cross-sectional imaging technique involves generating and storing a large number of 2D cross-sectional images and registering the 2D cross-sectional images within the volume to produce a highly accurate 3D volumetric image. The charged particle system can include a scanning electron microscope (SEM) for imaging and a focused ion beam (FIB) system for slicing, or an ion beam system for both slicing and imaging. One type of structure imaged in this manner is a three-dimensional structure (as opposed to a planar geometry), such as 3D NAND memory chips and other high-aspect-ratio structures (HARs). 3D imaging of NAND memory chips and other high-aspect-ratio structures is described in detail in WO 2022 / 223229 A1, the contents of which are incorporated herein by reference. During inspection, ion milling (slicing) can be used by the FIB system to prepare surfaces containing the area to be inspected. These surfaces can be tilted relative to the surface of the semiconductor structure in a wedge-like configuration. This method will also be referred to herein as wedge cutting. The area to be inspected is then examined using SEM (imaging). Slicing and imaging are repeated to obtain a 3D (volume) image. For example, multiple cross-sectional surfaces are then milled using focused ion beam milling, with the ion beam parallel to each newly formed cross-sectional surface. Multiple two-dimensional images are acquired by scanning electron beam imaging of each newly revealed cross-sectional surface. Each cross-sectional surface includes sections with vertical structures, such as high aspect ratio (HAR) structures of memory devices, and sections with numerous layers in a multilayer stack.

[0005] When scanning the surface of a semiconductor structure with a charged particle beam, the surface may become electrically charged. This charge can interfere with imaging. While this effect is desirable for certain analysis methods, such as verifying whether electrical connections in semiconductor structures are broken, in other cases it can lead to image degradation and, for example, inaccurate measurements of structure dimensions.

[0006] US 2020 / 402 813 A1 describes improved endpoint during delayering. Delayering with ion beam assisted etching perpendicular to the wafer surface is very sensitive, for example, charging can have a detrimental effect on the delayering and / or on measurements to ensure that the delayering is performed to the desired depth. Ensuring proper endpoint during the delayering process is very important for applications such as circuit editing. However, this is not an issue for ion beam sputtering in the wedge cutting configuration described above. Here, the ion beam is directed parallel to the profile surface to be produced, and the sputtering itself produces a smooth surface. Charging is not a major issue for ion beam sputtering.

[0007] Some applications use charged particle beams to image insulators. According to JP H08-138 617 A, an ion beam is used to form a conductive layer at the irradiated area of ​​the insulator. A conductive probe can contact the conductive layer and reduce the charging of the insulator.

[0008] During ion beam milling, such as in TEM lamellae preparation, particles sputtered by the ion beam may form a layer of debris around the milled area. Depositing protective coatings to protect sample surfaces is well known. For example, US 2008 / 073 587 A1 proposes the use of sputter coatings to form a protective or conductive coating on a surface. The sputtered-coated sample is then processed by ion beam milling.

[0009] During scanning electron beam inspection of a sample, such as a semiconductor mask or wafer, the sample may typically become electrically charged due to exposure to the electron beam. Therefore, the sample is typically electrically connected to a specific potential, such as ground. Grounding the mask or wafer sample may require forming a path to a conductive layer of the mask or wafer sample. Some examples of electrical connections for mask or wafer samples are shown in US 2023 / 005 698 A1.

[0010] Localized charging may occur on insulating materials, which can degrade the imaging of the insulator by the electron beam. Therefore, various methods have been proposed to remove surface charges formed on insulating materials such as photoresists. For example, US Pat. No. 5,512,746 proposes using a probe to remove electrons from the surface of an insulating material. US Pat. No. 4,991,661 proposes depositing a conductive film on only a portion of the sample surface to remove the charge. However, according to US Pat. No. 5,512,746, depositing a metal film on the measurement object can lead to contamination and is not suitable for in-line measurement of micropatterns.

[0011] The above approach does not provide a solution for a slice-and-image approach that uses a FIB for ion milling and another beam for inspection (such as an electron beam from an SEM), for example in a dual-beam setup for forming multiple cross-sectional images at oblique angles through a multi-layer stack within a semiconductor wafer as described above.

[0012] Surface charge on insulators is generally not a significant problem, as any surface charge generated on insulating materials is removed after each grinding step. However, alternating layers of a multilayer stack may contain structures formed from conductive materials, and insulating capacitance may form within some layers. Charge may slowly accumulate within these insulating conductive structures over a series of SEM image acquisitions, for example, over 100 image acquisitions, such as up to 1000 image acquisitions.

[0013] The deteriorating electric field is proportional to the accumulated charge, Q, divided by the capacitance, C, of ​​the insulating conductor (U = Q / C). Many small, distinct capacitors have different charges and, therefore, can create many different electric fields across a cross-section through a multilayer stack. In addition to the deteriorating effect of local fields on the secondary backscattered electron yield, the varying fields also introduce transverse field gradients, which can introduce significant distortion, particularly during imaging with low-momentum electron scanning charged-particle beams. Summary of the Invention

[0014] Therefore, there is a need to alleviate the above-mentioned adverse effects.

[0015] Certain techniques disclosed herein may help reduce charging effects during inspection of semiconductor samples, thereby, in some embodiments, improving image quality, improving measurement results, or both.

[0016] A method for inspecting a semiconductor structure sample is provided. The method includes providing a semiconductor structure sample, ion beam milling the semiconductor structure sample to form an inclined surface at an angle relative to a surface of the semiconductor structure sample, wherein the ion beam milling results in the formation of at least one electrically isolated region in a region of the semiconductor structure sample to be inspected, and providing an electrical connection to the at least one electrically isolated region. Providing the electrical connection allows charge accumulated in the at least one electrically isolated region to flow away from the region, thereby mitigating charging effects when inspecting the semiconductor structure sample using a charged particle inspection method, such as a scanning electron microscope. The method further includes performing charged particle beam inspection on the region to be inspected.

[0017] The angle between the surface of the semiconductor structure sample and the inclined surface may be, for example, between 10° and 30°, when measured as an acute angle between the planes in which the surface of the semiconductor structure sample and the inclined surface lie, respectively.

[0018] It should be noted that the electrical connections provided are not part of the semiconductor structure sample to be inspected itself, but are added specifically for inspection purposes.

[0019] It should be noted that the electrical connections may be provided before or after ion beam milling. In the former case (before ion beam milling), the formation of the electrical isolation regions described above should be understood to mean that such isolation regions would be formed in the absence of electrical connections.

[0020] The term "semiconductor structure sample" does not exclude the presence of materials other than semiconductors. For example, the semiconductor structure sample may include structured or unstructured metal layers, structured or unstructured dielectric layers, or other layers and materials commonly found in semiconductor devices.

[0021] In some examples, providing the electrical connection includes providing the electrical connection outside the area to be inspected, so that the inspection is not disturbed by the electrical connection and the entire area to be inspected can be inspected.

[0022] In some examples, providing the electrical connection may include depositing a conductive material, such as a metal such as platinum or tungsten, into a trench formed in the semiconductor structure sample. In this manner, the electrical connection may be formed using standard semiconductor techniques or, at least in part, using a semiconductor charged particle inspection apparatus. For example, in the apparatus described in the introduction, a focused ion beam (FIB) may be used to form the trench.

[0023] The method may include identifying the at least one electrically isolated region. Identifying the at least one electrically isolated region in the region to be inspected may be based on knowledge of the semiconductor structure sample. Typically, the semiconductor structure sample has a known nominal structure, i.e., is designed to have a specific structure, which is reflected in design data. Based on this design data, the at least one electrically isolated region may be identified.

[0024] While in some instances this identification may be performed by an operator reviewing the design of a sample semiconductor structure, in other instances this identification may be performed automatically or by an operator supported by automated analysis.

[0025] As described above, the nominal semiconductor structure sample is known from the design data. Furthermore, the electrical network formed by the semiconductor structure sample is also known, and the semiconductor structure is designed to have a certain electrical function, and commercial chip design tools provide a mapping between the two. Connectivity analysis, also provided by commercial semiconductor design software, can be used to locate electrically isolated regions. When removing material to prepare areas for ion beam milling inspection, corresponding portions of the electrical network can also be removed, and again, connectivity analysis can identify at least one electrically isolated region. The location of electrical connections can also be determined using the corresponding design software, for example by finding a cubic space connecting at least one electrically isolated region (which is filled with conductive material to form an electrical connection).

[0026] In some examples, at least one electrically isolated region may include multiple electrically isolated regions, and electrical connections connect the multiple electrically isolated regions to each other. In this way, the charge between the electrically isolated regions can be balanced. According to one aspect of the present invention, by forming at least one electrical connection, locally isolated capacitors are interconnected, and a larger capacitor is formed. In turn, local large regions with small capacitance are eliminated. By interconnecting many capacitors, at least one large capacitor is formed. Therefore, local field differences and lateral field gradients are also balanced and eliminated. According to one aspect of the present invention, the interconnection structure alone significantly increases the capacitance, further reducing the electric field generated by the increased capacitance (U~Q / C).

[0027] In other embodiments, the electrical connection may additionally or alternatively connect the at least one electrically isolated region to a reference potential (such as ground) and / or to the semiconductor substrate so that charge can flow away from the at least electrically isolated region.

[0028] As described above, the method involves preparing a region to be inspected by removing material from a wedge-shaped semiconductor structure sample using a focused ion beam, which can be used to provide 3D imaging of the semiconductor sample. In this case, electrical isolation of at least one electrically isolated region can result from the preparation (i.e., material removal) of the region to be inspected. In other words, by removing material to prepare the region to be inspected, a previously non-electrically isolated region can become electrically isolated. Furthermore, because the preparation of the region to be inspected can be pre-planned, identification can be performed based on prior knowledge. It should be noted that preparing the region to be inspected can be performed before or after providing electrical connections. The ion beam milling and inspection process can be repeated multiple times to obtain a 3D image. In some examples, at least one electrical connection provides electrical connectivity to additional isolated regions for multiple inclined surfaces formed by the repetitions.

[0029] In some examples, the semiconductor structure sample may include a 3D NAND memory structure. This structure includes slots that insulate groups of channels from each other. Depending on the preparation of the region to be inspected, such groups of channels may correspond to electrically isolated regions.

[0030] In some examples, a method is also provided, comprising preparing a semiconductor structure sample for charged particle beam inspection by any of the above methods, and inspecting the prepared sample using a charged particle beam.

[0031] A corresponding sample inspection apparatus is also provided, which is configured to provide electrical connection to at least one electrically isolated region in a region to be inspected of a semiconductor structure sample, comprising a focused ion beam device and a charged particle beam inspection device such as a scanning electron microscope. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 FIG. 1 is a flow chart illustrating a method according to an embodiment.

[0033] Figure 2 is a block diagram of a system according to one embodiment.

[0034] Figures 3A to 3C A 3D NAND semiconductor structure is shown.

[0035] Figure 4A and 4B Shows the effect of charging.

[0036] Figure 5 is a perspective view of a semiconductor structure sample according to one embodiment.

[0037] Figure 6A and Figure 6B FIG2 is a view of a semiconductor structure sample for illustrating the effects of the embodiment.

[0038] Figure 7Aand 7B A view showing the formation of electrical connections.

[0039] Figure 8 SEM measurement results are shown to illustrate the effects of some embodiments.

[0040] Figure 9 An inspection device according to some embodiments is shown.

[0041] Figure 10 is a diagrammatic illustration of sample preparation according to some embodiments.

[0042] Figure 11A and Figure 11B Shows charge accumulation.

[0043] Figure 12 The formation of electrical connections is shown.

[0044] 13A to 13C Processing of a semiconductor sample structure according to some embodiments is also illustrated. DETAILED DESCRIPTION

[0045] The following embodiments will be described in detail with reference to the accompanying drawings. It should be understood that the description of the following embodiments should not be considered as limiting. The scope of this application is not intended to be limited by the following embodiments or drawings, which are considered to be illustrative only.

[0046] The accompanying drawings should be considered schematic representations, and the elements shown in the drawings are not necessarily shown to scale. Instead, the various elements are represented as general functions that will become apparent to those skilled in the art. Any connection or coupling between the functional blocks, devices, components, or other entities or functional units shown in the accompanying drawings or described herein may also be implemented by indirect connection or coupling. The functional blocks can be implemented in hardware, firmware, software, or a combination thereof.

[0047] In some of the embodiments described below, a 3D NAND memory structure will be used as an example of a semiconductor structure sample to be inspected. This should not be construed as limiting, and the techniques disclosed herein are generally applicable to semiconductor structure samples to be inspected using charged particle beam techniques, either due to the sample's structure or due to the preparation of the region to be inspected, including electrically isolated regions. Therefore, the example of a 3D NAND memory structure is provided for illustration and better understanding only. Furthermore, in the following, a scanning electron microscope (SEM), such as an MSEM, will be used as an example of a charged particle beam inspection technique, but other techniques using, for example, charged ions instead of electrons as the beam may also be used.

[0048] Figure 1 A method according to some embodiments is shown. At step 10, the method includes providing a semiconductor structure sample to be inspected using a charged particle beam technique.

[0049] For example, Figures 3A to 3C illustrates the 3D NAND memory structure, which is Figure 1 Step 10 provides an example of a semiconductor structure sample. Figure 3A and 3C shows two different orientations of the 3D NAND structure, and Figure 3B Shows the formation Figure 3A An enlarged portion of the channel bank of strip 30.

[0050] In general, a 3D NAND memory structure includes a pillar or channel 31 having multiple layers as shown, coupled via word lines 32. Strips 30 are separated by slits 35. Slits 35 provide electrical isolation between adjacent strips, which can result in the formation of electrically isolated regions, depending on sample preparation. Numeral 34 designates a transition layer, and numeral 36 indicates a bit line. The transition layer in the illustrated example is due to the fact that two 3D NAND memory chips are stacked on top of each other to achieve a higher level of integration. The transition layer is necessary due to technical limitations in the controlled etch depth of the channel. More information on this type of structure can be found in the aforementioned WO 2022 / 223229A1.

[0051] In step 11, Figure 1 The method comprises identifying electrically isolated regions in a region of a semiconductor sample to be inspected. In step 12, the method comprises providing electrical connections to at least one electrically isolated region. In step 13, the method comprises preparing the region to be inspected, for example, by focused ion beam sectioning. The identification of at least one electrically isolated region may be performed with respect to the preparation of the region to be inspected, i.e., in some examples, the preparation may result in the formation of an electrically isolated region. The order of steps 11-13 need not necessarily be in accordance with Figure 1 The order shown is not the same, but for example, preparing the area to be inspected in step 13 may precede providing electrical connections in step 12. Examples of various actions of steps 11-13 will now be explained with reference to Figures 4 to 13 (including corresponding sub-figures A, B, C provided).

[0052] For the preparation in step 13 and the measurements described further below with respect to step 14, for example, to investigate a 3D inspection volume within a semiconductor wafer, a slicing and imaging method suitable for inspecting volumes within the wafer can be used. In one example, a 3D volume image is generated from the inspection volume within the wafer using a so-called "wedge-cut" method or wedge-cut geometry, without removing a sample slice from the wafer. The slicing and imaging method is suitable for inspection volumes measuring a few micrometers, for example, lateral extensions of 5 to 10 micrometers in a wafer with a diameter of 200 or 300 mm. Lateral extensions can also be larger, up to 30 or 50 micrometers. V-shaped grooves or edges are milled into the top surface of the integrated semiconductor wafer to enable cross-sections at an angle to the top surface. 3D volume images of the inspection volume are acquired at a limited number of inspection locations, such as representative locations of the die, such as at a process control monitor (PCM), or at locations identified by other inspection tools. The slicing and imaging method only locally destroys the wafer, allowing for the use of other die or further processing. Methods and inspection systems based on the generation of 3D volume images are described in WO 2021 / 180600 A1, the content of which is incorporated herein by reference in its entirety. Figure 9 1 shows an example of a wafer inspection system 1000 for 3D volume inspection. Wafer inspection system 1000 is configured to perform a slicing and imaging method using a dual-beam arrangement 91 in a wedge-cut geometry. Inspection locations, including inspection locations 96.1 and 96.2, are defined for wafer 98 in a location map or inspection list generated by an inspection tool or design information. These inspection locations define the locations of regions to be inspected within a semiconductor structure sample, such as wafer 98 having a structure formed thereon. Wafer 98 is placed on a wafer support table 915. Wafer support table 915 is mounted on a platform 9155 having actuators and position control. Actuators and devices for precise control of the wafer platform, such as laser interferometers, are known in the art. A control unit 916 is configured to control wafer platform 9155 and adjust inspection location 96.1 of wafer 98 at intersection 943 of dual-beam arrangement 91. The dual beam apparatus 91 includes a FIB column 950 having a FIB optical axis 948 and a charged particle beam (CPB) imaging system 940 having an optical axis 942. At the intersection 943 of the optical axes of the FIB and the CPB imaging system, the wafer surface 955 is configured to be tilted at an angle GF relative to the FIB axis 948. The FIB axis 948 and the CPB imaging system axis 942 include an angle GFE, and the CPB imaging system axis forms an angle GE with the normal to the wafer surface 955. Figure 9In the coordinate system of , the normal to the wafer surface 955 is given by the z-axis. A focused ion beam (FIB) 951 is generated by the FIB column 50 and impinges on the surface 55 of the wafer 98 at an angle GF. By ion beam milling, an oblique profile is milled into the wafer at the inspection site 96.1 at approximately the oblique angle GF. Figure 9 In the example of FIG, the tilt angle GF is about 30°. Due to the beam divergence of the focused ion beam (eg, gallium ion beam), the actual tilt angle of the tilted cross-sectional surface may deviate from the tilt angle GF by 1° to 4°.

[0053] In general, the FIB column 950 can be, for example, a gallium FIB, with or without a Wien filter or similar mechanism to allow alloy-based sources (e.g., silicon, gold, etc.), or a FIB with a gas field ion source (GFIS), a plasma source, or a dual plasma tube with other types of ion species, such as xenon, oxygen, or argon ions, or related technologies (e.g., a "cluster" or "cryogenic" ion source). In general, the FIB column 950 is used to generate a focused ion beam, selectively in different ion charge states.

[0054] An image of the polished surface is obtained using a charged particle beam imaging system 940 tilted at an angle GE relative to the wafer normal. Figure 9 In the example of FIG, the angle GE is about 15°. However, other configurations are possible, such as GE=GF, such that the CPB imaging system axis 942 is perpendicular to the FIB axis 948 (and GFE=90°), or GE=0°, such that the CPB imaging system axis 942 is perpendicular to the wafer surface 955.

[0055] During imaging, a beam 944 of charged particles is scanned by a scanning unit of a charged particle beam imaging system 940 along a scanning path on the cross-sectional surface of the wafer 98 at the inspection site 96.1, and secondary particles and scattered particles are generated. For example, a secondary electron particle detector 917.1 collects at least some of the secondary particles and scattered particles and communicates the particle count to a control unit 919. Detectors of other interaction products may also be present, such as an in-lens detector 917.2 for collecting backscattered electrons. The control unit 919 controls the charged particle beam imaging system 940 of the FIB column 950 and is connected to the stage control unit 916 to control the position of the wafer 98 mounted on the wafer support table 915 via the wafer stage 9155. The control unit 919 communicates with the operation control unit 2, which triggers, for example, placement and alignment of the inspection site 96.1 of the wafer 98 at the intersection 943 via wafer stage movement, and triggers repeated operations of FIB milling, image acquisition, and stage movement.

[0056] Each new intersection surface is milled by the FIB beam 951 and imaged by a charged particle imaging beam 944, which is, for example, a scanning electron beam.

[0057] The dual-beam system 91 further includes a gas injection system (GIS) 79 having a gas nozzle connected to at least one gas reservoir (not shown) via a valve (not shown). This system provides controlled amounts of precursor gas during milling or imaging, and can, for example, produce a metal coating. For example, alignment marks or fiducials can be created. For example, a tungsten metal coating can be produced by providing tungsten hexacarbonyl. The metal coating can be formed by ion beam milling, and alignment marks or fiducials can be formed near the inspection site. This enables precise registration and image alignment of multiple cross-sectional images. Using specialized precursor gases can enhance milling operations using the FIB 951. For example, milling uniformity can be improved across different material compositions and droop can be reduced. The material composition of the semiconductor wafer can include silicon, silicon dioxide, silicon nitride, copper, aluminum, or other materials.

[0058] Preferred precursor gases include at least one of the following: ammonia, ammonium hydroxide, ammonium carbamate, bromine, chlorine, hydrazine, hydrogen peroxide, hadacetidine, iodine, diiodoethane, isopropyl alcohol, methyl difluoroacetate, nitroethane, nitroethanol, nitrogen, nitrogen tetroxide, nitrogen trifluoride, nitromethane, nitropropane, nitrobutane, oxygen, ozone, PMCPS, tungsten hexacarbonyl, water, or xenon difluoride. However, other gases are also possible, such as methoxyacetyl chloride, methyl acetate, methyl nitroacetate, ethyl acetate, ethyl nitroacetate, propyl acetate, propyl nitroacetate, ethyl nitroacetate, methyl methoxyacetate, methoxyacetyl chloride, acetic acid or thiolacetic acid, hexafluoroacetylacetone, silazane, trifluoroacetamide, dicobalt octacarbonyl, molybdenum hexacarbonyl, and combinations thereof.

[0059] Furthermore, the dual-beam system 91 further comprises a stylus 981. The stylus 981 is connected to a manipulator (not shown) for precise movement of the stylus 981, for example during image acquisition, under the control of the charged particle imaging beam 944. This allows structures present on the wafer surface to be contacted and electrically connected to the control device 19.

[0060] Figure 10 Shown as a reference Figures 3A to 3C Wedge-cut geometry at an instance of a 3D memory stack as explained. Figure 10 This situation is illustrated when the surface 952 is the newly profiled surface that was last milled by the FIB beam 951. For example, the profiled surface 952 is scanned by the SEM beam 944. Figure 10In the example, SEM beam 944 is configured for normal incidence on wafer surface 955 and produces high-resolution cross-sectional image slices. FIB beam 951 is then used to mill cross-sectional surfaces 953.1…953.N at an angle GF of approximately 30° relative to wafer surface 955, although other angles GF, such as between GF = 20° and GF = 60°, are possible. The cross-sectional image slices include first cross-sectional image features formed by intersections with high-aspect-ratio (HAR) structures or vias (e.g., first cross-sectional image features of HAR structures 94.1, 94.2, and 94.3), and second cross-sectional image features formed by intersections with layers L.1…LM, which may include, for example, SiO2, SiN, or tungsten lines. Some lines are also referred to as "word lines." The maximum number of layers, M, is typically greater than 50, for example, greater than 100 or even greater than 200. The HAR structures and their layers extend through most of the wafer volume but may contain gaps. The HAR structures typically have a diameter below 100 nm, for example, approximately 80 nm, or, for example, 40 nm. Thus, the cross-sectional image slices contain first cross-sectional image features as intersections or cross-sections of the HAR structures at different depths (Z) at corresponding XY locations. In the case of cylindrical vertical memory HAR structures, the first cross-sectional image features obtained are circular or elliptical structures at different depths determined by the structures' positions on the oblique cross-sectional surface 952. The memory stack extends in the Z direction perpendicular to the wafer surface 955. The thickness d, or minimum distance d, between two adjacent cross-sectional image slices is adjusted to a value typically on the order of a few nm, for example, 30 nm, 20 nm, 10 nm, 5 nm, 4 nm, or even less. Once the material layer of the predetermined thickness d is removed using the FIB, the next cross-sectional surface 953.i…953.J is exposed and can be used for imaging using the charged particle imaging beam 944. During the repeated grinding and imaging process, multiple cross-sections are formed and multiple cross-sectional images are acquired, ensuring that inspection volume 9160, measuring LX x LY x LZ, is accurately sampled and, for example, a 3D volume image can be generated. This limits any damage to the wafer to the damage volume of inspection volume 9160 plus the y-direction length LYO. When the inspection depth LZ is approximately 10 μm, the additional extension of the damage volume in the y-direction is typically limited to less than 20 μm.

[0061] Figure 4A and 4B Shown as Figures 3A to 3C Example SEM measurement of a region of the explained 3D NAND semiconductor structure, as described above, a wedge is prepared as the region to be inspected, for example using Figure 9 To further illustrate, Figure 5 Another 3D NAND semiconductor structure sample 51 is schematically shown, with Figure 10Similar to that shown in , where the wedge is prepared by removing a portion 50 along the wedge edge 50A to provide the area to be inspected. Figure 4A In the case of Figure 4B In this case, the edge 50A extends perpendicular to the slit 35. Figure 4A In , the image is uniform, while in Figure 4B Strong brightness variations occur in the image. These variations are caused by the electron beam charging of the SEM used, such as Figure 4B In the case of Figure 5 The material shown in is removed and electrically isolated. Figure 4B In the case of Figure 1 At step 11, the region between the slits is identified as an electrically isolated region.

[0062] exist Figure 11A and 11B This charging is further illustrated in FIG. Figure 11A The results of the inspection using beam 944 are shown. Figure 10 The charge generated in the layers L.1…LM (indicated by “-”). When the imaging is repeated, the charge can be further accumulated, such as Figure 11B As shown, the image is further degraded.

[0063] According to one embodiment, Figure 4B Provides electrical connection of the connecting strips in cases with electrically isolated areas. Figure 6A and 6B Show the effect.

[0064] Figure 6A An SEM image is shown in which the area to be inspected 60 is formed as shown in FIG. Figure 4A The wedge in Figure 5 The edge 50A perpendicular to the slit 35 is shown here as arrow 61. Here, the charge can flow through the stripe, for example, through the word line, to the right and left sides of the area to be tested where the stripe is connected, so that the charge can flow away from the area to be tested 60. No additional electrical connection is required here.

[0065] On the contrary, Figure 6B The areas to be inspected are as follows Figure 4B Formed, that is, having Figure 5 The edge 50A is parallel to the slit 35. In this case, due to the electrical isolation provided by the slit 35, the charge cannot flow to the formed wedge sidewall, as shown by the crossed arrows 62. In addition, due to the material removal, the charge cannot flow along the Figure 6B The flow in the downward direction is also shown by the crossed arrows 62.

[0066] If there is no Figure 6B The top of the probe provides electrical connection, so the charge cannot flow away from the area to be tested, resulting in Figure 4B However, in Figure 6B In step 12 of the example, a ground trench 64 is formed to provide electrical connection. Figure 7A and 7B An exemplary formation is shown in FIG. 1 , wherein a trench 70 is formed and then at least partially formed by Figure 7B The conductive material 71 is filled in, for example, a metal such as platinum. For example, a highly doped semiconductor material can also be used instead of metal to form an electrical connection.

[0067] exist Figure 6B In the embodiment, the trenches 64 filled with conductive material provide the possibility for charges to flow from the region to be inspected 60 to the through trenches 64. Figure 6B In the example of , the trench 64 couples the strips to a reference potential (such as ground) and / or to the substrate, thus allowing charge to flow away. In other embodiments, the trench may simply connect the strips to each other to balance the charge.

[0068] Although a single trench filled with conductive material is described above, multiple electrical connections may be provided, for example using multiple trenches.

[0069] refer to Figure 12 13 further illustrate various examples for forming electrical connections. Figure 12 In the embodiment, electrical connections 971 are provided by depositing metal or other conductive material in trenches 99 on the otherwise slanted surface, thus interconnecting all or part of the layers L1 . . . LM with each other. 13A to 13C The formation of electrical connection 971 is shown: Figure 13A The formation of trench 99 by ion beam milling using a FIB 951 is shown, similar to the preparation of the inclined surface 956 for inspection.

[0070] Compared to Figure 13A Rotated 180° Figure 13B The deposition of electrical connections 971 is shown. The deposition can be performed using a particle beam 979 of a corresponding conductive material (e.g., a metal such as platinum). This material can then be structured using a FIB 951.

[0071] Please refer again Figure 1After step 13, an SEM measurement of the area to be inspected is performed in step 14. For 3D tomography, step 13 can then be repeated by removing material and performing further measurements. In some embodiments, step 12 may be performed only once to provide electrical connectivity to all electrically isolated areas, which can occur during the preparation of the area to be inspected. The measurement results can then be evaluated in step 15, for example, in the case of 3D NAND memory or other high-aspect-ratio structures (as described in the referenced WO 2022 / 223 229 A1).

[0072] For various beam currents and accelerating voltages, the effects of measuring electrical connections are provided. Figure 8 As shown, the voltage is 1 kV or 2 kV, and the beam current is 50 pA or 500 pA. Without the electrical connection (top row), the brightness variation of the SEM measurement is large, while the brightness variation is significantly reduced when the electrical connection is provided (bottom row).

[0073] Figure 2 A further device according to an embodiment is shown, which is configured to perform the aforementioned method. Figure 2 The system comprises one or more sample preparation devices 20, which specifically perform Figure 1 Steps 12 and 13 of the present invention are to provide electrical connections for at least one electrically isolated area and prepare the area to be inspected. Such a sample preparation device may include conventional semiconductor manufacturing and analysis equipment, such as an ion beam device for trench formation, a metal deposition chamber (for example, for depositing metal in the trench), a gas injection system (GIS) for precursor gases used in 3D pattern generation, a SEM or other imaging device for observing and monitoring the preparation process, a photolithography device, etc., which are controlled by one or more controllers to perform the aforementioned sample preparation. The sample thus prepared is then provided to the SEM 21 for SEM measurement. Although in Figure 9 In the embodiment of the present invention, the inspection and sample preparation are performed in a single device 1000, but Figure 2 An example of the two being separated is shown, illustrating that there are two possibilities.

[0074] Some embodiments are defined by the following examples:

[0075] Example 1. A method for preparing a sample for charged particle beam imaging, comprising:

[0076] Providing semiconductor structure samples;

[0077] identifying at least one electrically isolated region in the region to be inspected of the semiconductor structure sample; and

[0078] An electrical connection is provided to the at least one electrically isolated region.

[0079] Example 2. The method of Example 1, wherein the electrical connection is coupled to one of a reference potential or a substrate.

[0080] Example 3. The method of example 1 or 2, wherein the at least one electrically isolated region comprises a plurality of electrically isolated regions, and wherein the electrical connection electrically couples the plurality of electrically isolated regions to one another.

[0081] Example 4. The method of any of Examples 1-3, wherein providing the electrical connection comprises providing a trench and at least partially filling the trench with a conductive material.

[0082] Example 5. The method of any one of examples 1-4, wherein the electrical connection is provided outside the area to be inspected.

[0083] Example 6 The method of any one of Examples 1-5, further comprising preparing the region to be inspected, wherein preparing the region to be inspected results in forming at least one of the at least one electrically isolated region.

[0084] Example 7. The method of Example 6, wherein preparing the region to be inspected comprises removing material from the semiconductor structure sample.

[0085] Example 8. The method of any one of Examples 1-7, wherein the semiconductor structure sample comprises a NAND memory structure.

[0086] Example 9. The method of any one of Examples 1-8, wherein identifying the electrically isolated region is based on design data of the semiconductor structure sample.

[0087] Example 10. A method for inspecting a semiconductor structure sample, comprising:

[0088] preparing a sample based on the semiconductor structure sample according to the method of any one of Examples 1-9; and

[0089] Perform charged particle beam examination of the prepared samples.

[0090] Example 11. A sample preparation device configured to perform the method of any one of Examples 1-10.

[0091] Example 12. A system comprising:

[0092] The apparatus of example 11; and

[0093] Charged particle beam inspection device.

Claims

1. A method for inspecting a semiconductor structure sample, comprising: providing semiconductor structure samples (51, 98); Ion beam milling the semiconductor structure sample (51, 98) to form an inclined surface (952) at an angle (GF) relative to a surface (955) of the semiconductor structure sample (51, 98), wherein the ion beam milling results in the formation of at least one electrically isolated region in the region to be inspected (60, 96) of the semiconductor structure sample (51, 98), providing electrical connection (64) to the at least one electrically isolated region; and A charged particle beam inspection of the area to be inspected (60, 96) is performed.

2. The method of claim 1, wherein the electrical connection (64) is coupled to one of a reference potential or a substrate.

3. The method of claim 1 or 2, wherein the at least one electrically isolated region comprises a plurality of electrically isolated regions, and wherein the electrical connection (64) electrically couples the plurality of electrically isolated regions to one another.

4. The method of claim 3, wherein prior to providing the electrical connection (64), the plurality of electrically isolated regions result in the formation of a plurality of capacitors, wherein providing the electrical connection (64) combines the plurality of capacitors into a single capacitor.

5. The method of any one of claims 1 to 4, wherein providing the electrical connection (64, 971) comprises providing a trench (70, 99) and at least partially filling the trench (70, 99) with an electrically conductive material (71, 971).

6. The method according to any one of claims 1 to 5, wherein the electrical connection (64) is arranged outside the area to be inspected (60, 960).

7. The method of any one of claims 1 to 6, wherein the semiconductor structure sample (51, 98) comprises a NAND memory structure.

8. The method of any one of claims 1 to 7, further comprising identifying the electrically isolated region based on design data of the semiconductor structure sample (51, 98).

9. The method of any one of claims 1 to 8, further comprising repeating the ion beam milling to produce one or more additional inclined surfaces (952) having one or more additional regions to be inspected, and performing the charged particle beam inspection one or more times to inspect the one or more additional regions to be inspected.

10. The method of claim 9, wherein the electrical connection (64) is also a connection to one or more electrically isolated areas of the one or more further areas to be inspected.

11. The method according to any one of claims 1 to 10, wherein the semiconductor structure sample comprises a slit (35), wherein an edge (50A) formed between a surface (955) of the semiconductor structure sample (51, 98) and the inclined surface (952) is perpendicular to the slit (35), and wherein the at least one electrically isolated region is formed between adjacent slits (35).

12. A sample inspection device (1000), comprising: A focused ion beam device (50) configured to perform ion beam milling on a semiconductor structure sample (51, 98) to form an inclined surface (952) at an angle (GF) relative to a surface (955) of the semiconductor structure sample (51, 98); A deposition device configured to provide an electrical connection (64, 971) to at least one electrically isolated region formed in a region to be inspected (60, 96) of the semiconductor structure sample (51, 98) formed by forming the inclined surface (952), the at least one electrically isolated region being formed by electrically separating the electrically isolated region from a conductive portion of the semiconductor structure sample; as well as A charged particle beam inspection device is configured to inspect the area to be inspected (60, 96).

13. The apparatus (1000) of claim 12, configured to perform the method of any one of claims 1 to 11.

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