Fully controllable power semiconductor switch assembly, power semiconductor device, snubber-less power converter and method of manufacture

Abstract

The present disclosure relates to a fully controllable power semiconductor switch assembly (40) comprising: a first cell (51, 61, 71) comprising a latch-type power semiconductor switching device (41) controlled by a first gate terminal (44); a second unit (52, 62, 72) comprising an unlatched power semiconductor switching device (42) controlled by a second gate terminal (45); and a power semiconductor diode (43). The latch-type power semiconductor switching device (41) and the non-latch-type power semiconductor switching device (42) are connected in a parallel configuration with respect to the current switched by the switching assembly (40). The power semiconductor diodes (43) are connected in an anti-parallel configuration with respect to the current switched by the switching assembly (40). The present disclosure also provides a power semiconductor device (100), a snubber-free power converter, and a method for manufacturing a snubber-free power converter.

Description

Technical Field

[0001] The present disclosure relates to a fully controllable power semiconductor switch assembly, comprising a latching power semiconductor switch device, a non-latching power semiconductor switch device, and a power semiconductor diode. The present disclosure also relates to a power semiconductor device, comprising an insulating housing package, a non-latching power semiconductor switch device, and a power semiconductor diode. The present disclosure also relates to a snubberless power converter and a method for manufacturing the power converter. Background Art

[0002] In the field of power semiconductor devices, turn-off power semiconductor devices, such as gate turn-off (GTO) thyristors, in particular integrated gate-commutated thyristors (IGCTs), are known. Such power semiconductor devices are useful for various applications, in particular for power converters, such as inverters used, for example, in power transmission networks or electric vehicles.

[0003] Figure 1 A simplified circuit diagram of a first switching circuit 10 for switching high voltages and / or high currents is shown. Figure 1 The circuit 10 shown in FIG is based on two switching elements 11 , such as a pair of GTO thyristors, which are connected to a common central node 12 to form two halves of a switching bridge. Figure 1 The switching elements 11 of the GTO thyristors 11 become conductive when an appropriate turn-on (usually positive) gate control signal is applied. They remain conductive as long as sufficient current flows through them or an appropriate turn-off (usually negative) gate control signal is provided.

[0004] Figure 1 Turning off the switch circuit 10 shown in FIG requires providing one or more snubber circuits 13 to reduce the rate of voltage change dv / dt at the switch element 11, as shown. For example, a resistor-capacitor-diode (RCD) dv / dt snubber circuit may be used.

[0005] In addition, the switching circuit 10 includes a choke circuit 14 (or a di / dt snubber circuit) for limiting the current change di / dt during the turn-on period, and a clamping circuit 15 for clamping the induced overvoltage generated by the choke circuit 14. Its function is to clamp the induced overvoltage generated by the choke circuit 14 to a level that is safe for all components in the switching circuit 10. The choke circuit 14 may include, for example, an inductor 16. The clamping circuit 15 may include, for example, a diode 17, a resistor 18, and a capacitor 19 as shown. Attention is drawn to the fact that in typical switching circuits based on insulated gate bipolar transistors (IGBTs), a choke circuit, and therefore a clamping circuit, is unnecessary.

[0006] Figure 2An improved second switching circuit 20 for switching high voltage and / or high current is shown. Figure 1 In contrast to the circuit shown in Figure 2 The circuit shown in FIG is based on a pair of two IGCTs 21 that can be turned off without a buffer to reduce the voltage change dv / dt. Two freewheeling diodes 22 are connected in an anti-parallel configuration relative to the corresponding IGCT 21. When the current across the two IGCTs 21 is switched on, the voltage across the IGCTs 21 collapses in an uncontrolled manner. To prevent overstressing the two freewheeling diodes 22, a choke circuit 14 is used to limit the rate of rise di / dt of the anode current (whether the word is placed at the end), as described in relation to FIG. Figure 1 The first switching circuit 10 is described.

[0007] In each case, the inductors 16 provided in the choke circuits 14 are relatively large components which, in practice, determine the Figure 1 and 2 The total volume of the switching circuits 10 and 20 shown in FIG.

[0008] WO 2021 / 197774 A1 discloses a power semiconductor device comprising a thyristor and a bipolar junction transistor (BJT), thereby avoiding some of the disadvantages of known IGCTs and / or switching circuits. Specifically, the document provides a power semiconductor device with reduced system losses and a reduced need for protection circuits (such as the snubber circuit described above). Summary of the Invention

[0009] Among other things, it is an object of the present disclosure to provide components suitable for implementing an improved power semiconductor device, which components can be integrated with each other and packaged so as to provide a simple but effective fully controllable power semiconductor switch assembly.

[0010] According to aspects of the present disclosure, a fully controllable power semiconductor switch assembly is provided. The assembly includes: a first unit including a latching power semiconductor switch device controlled by a first gate terminal; a second unit including a non-latching power semiconductor switch device controlled by a second gate terminal; and a power semiconductor diode. The latching power semiconductor switch device and the non-latching power semiconductor switch device are connected in parallel with respect to a current switched by the switch assembly, and the power semiconductor diode is connected in anti-parallel with respect to the current switched by the switch assembly.

[0011] The disclosed assembly allows for controlling the switching on and off operation of a power semiconductor-based switching circuit, wherein the voltage change during the switching on period and the current change during the switching off period can be controlled by corresponding gate control signals. This enables, in particular, completely unbuffered operation of a fully controllable power semiconductor switching assembly. To avoid any integration issues, at least at the packaging level, the latching and non-latching power semiconductor switching devices are integrated into two separate units, each with its own gate terminal. As a result, standard packaging and integration technologies for semiconductor power devices with only a single control terminal can be employed.

[0012] Depending on the embodiment, the power semiconductor diode can be integrated into the first unit, the second unit, or an additional third unit. This freedom is based on the insight that the power semiconductor diode does not need to be controlled by a corresponding gate terminal. If, for example, the power semiconductor diode is integrated into one of the first or second units, no additional housing and / or control terminals are required in the overall assembly, which facilitates integration.

[0013] According to at least one embodiment, the diode structure of the semiconductor diode is integrated into a common housing, for example into a housing of a non-latching power semiconductor switching device.

[0014] According to at least one embodiment, the first unit and / or the second unit may further include a gate unit for a latching power semiconductor switch device and / or a non-latching power semiconductor switch device, respectively. For example, the power semiconductor switch devices and the corresponding gate units may be arranged on a common printed circuit board (PCB).

[0015] According to at least one embodiment, the dimensions of the first unit correspond to the dimensions of the second unit, and / or the latching power semiconductor switching device is integrated into the first housing, in particular into the housing of the first press-fit device, and the non-latching power semiconductor switching device is integrated into the second housing, in particular into the housing of the second press-fit device, and the dimensions of the first housing correspond to the dimensions of the second housing. The use of first and second units and / or power semiconductor devices of substantially identical dimensions enables the integration of different functional units into a larger switch assembly. In particular, when the semiconductor power diode is integrated into a common housing together with the non-latching power semiconductor switching device, the power density of the first and second units can be made comparable, thereby resulting in symmetric thermal loads on the two units and the power semiconductor devices included therein.

[0016] According to another aspect of the present disclosure, a power semiconductor device is provided, particularly a power semiconductor device for use in the switch assembly described above. The power semiconductor device includes: a sealed housing having a first power terminal, a second power terminal, and a gate terminal; a non-latching power semiconductor switch device disposed within the sealed housing and configured to selectively switch current from the first power terminal to the second power terminal based on a control signal provided via the gate terminal; and a power semiconductor diode disposed within the sealed housing and configured to conduct current from the second power terminal to the first power terminal.

[0017] This type of power semiconductor device, which integrates a non-latching power semiconductor switch device and a power semiconductor diode into a single sealed housing having a single gate terminal and two power terminals, is particularly useful for implementing the non-latching power semiconductor switch device of the second unit of the above assembly. However, it does not integrate the functionality of the latching power semiconductor switch device into the same housing, thereby alleviating the need for a second gate terminal in the same housing.

[0018] In at least one embodiment, the non-latching power semiconductor switch device and the power semiconductor diode are formed as semiconductor structures on or within a common semiconductor substrate. Such substrate or wafer-level integration of two functional semiconductor structures further facilitates device integration.

[0019] In at least one embodiment, a power semiconductor device is a press-pack device, and a sealed housing includes: a conductive first housing portion forming a first power terminal; a conductive second housing portion forming a second power terminal; an insulating sidewall separating the first metal housing portion from the second metal portion; and a sleeve disposed at or within the insulating sidewall and configured to provide a control signal to a gate terminal. Such a press-pack device with a sleeve configured to provide a single control signal to a single gate terminal can be easily integrated with existing power electronic components.

[0020] In various embodiments, a latching power semiconductor switching device may include at least one integrated gate-commutated thyristor (IGCT) structure. Such IGCT structures are particularly useful for switching and maintaining high currents and / or high voltages. Such structures can be used to control dv / dt voltage changes when turning off the latching power semiconductor switching device.

[0021] The non-latching power semiconductor switch device of the power semiconductor device may include at least one bipolar junction transistor (BJT) structure or a non-latching thyristor structure. Such a structure can be used to control di / dt current changes when the latching power semiconductor switch device is turned on.

[0022] According to a further aspect of the present disclosure, a snubberless power converter, in particular a power inverter, is provided, which includes the fully controllable power semiconductor switch assembly as detailed above.

[0023] The advantages of the provided power converter correspond to the advantages detailed above with respect to the switching components and power semiconductor devices, respectively. In particular, such a power converter does not require internal or external snubber circuits, thereby alleviating the need to provide relatively bulky additional circuit components (such as inductors or other throttling components).

[0024] In at least one embodiment, the power converter further includes a control circuit configured to provide at least one control signal for controlling the non-latching power semiconductor switch device and / or the latching power semiconductor switch device. By also providing corresponding control circuits, a fully integrated switch device and / or power converter can be achieved.

[0025] According to various embodiments, the control circuit may be directly or indirectly connected to the first unit and the second unit and configured to provide a first control signal to the first gate terminal and a second control signal to the second terminal. In particular, in the case of an indirect connection, a master control unit forming part of one of the two units may be used to indirectly provide a control signal to the corresponding other unit (e.g., to a slave control unit of the corresponding other unit).

[0026] In at least one embodiment, the controller can be specifically configured to apply a positive gate current between the gate and cathode terminals of the non-latching power semiconductor switching device when the switching component is turned on. Furthermore, after the voltage between the anode and gate terminals of the latching power semiconductor switching device has collapsed, the controller can trigger the gate of the latching power semiconductor switching device and reduce the positive gate current between the gate and cathode terminals of the non-latching power semiconductor switching device to zero. Furthermore, when the switching component is turned off, the controller can apply a negative gate current to the gate terminals of the latching power semiconductor switching device and, optionally, to the gate terminals of the non-latching power semiconductor switching device.

[0027] The above operations enforce safe activation or switching on and deactivation or switching off of the switching components and thus allow the power converter to operate without buffering. According to another aspect of the present disclosure, a method for manufacturing a power converter is provided. The manufacturing method comprises the following steps: - providing a first unit comprising a latch-type power semiconductor switching device controlled by a first gate terminal; - providing a second unit comprising a non-latching power semiconductor switching device controlled by a second gate terminal; - providing a power semiconductor diode within the first unit, the second unit or within a separate third unit; - connecting a latching type power semiconductor switching device and a non-latching type power semiconductor switching device in a parallel configuration with respect to a current switched by the power converter; and - The power semiconductor diodes are connected in an anti-parallel configuration with respect to the current switched by the power converter.

[0028] The above steps basically achieve the manufacture of the power converter as detailed above.

[0029] The present disclosure provides several aspects of a power semiconductor switch assembly. Every feature described with respect to one of these aspects is also disclosed herein with respect to another aspect, even if the corresponding feature is not explicitly mentioned in the context of a particular aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the disclosed devices, systems, and methods. In the drawings, elements of the same structure and / or function may be referenced by the same reference numerals. It will be understood that the embodiments shown in the drawings are pictorial representations and are not necessarily drawn to scale.

[0031] Figure 1 and Figure 2 Two different semiconductor switching circuits are shown, each semiconductor switching circuit including a snubber circuit.

[0032] Figure 3 A snubberless type semiconductor switching circuit is shown.

[0033] Figure 4 A switching assembly comprising three power semiconductor structures and corresponding devices is shown.

[0034] Figures 5 to 7 The following are respectively based on three semiconductor device functional units and two semiconductor device functional units. Figure 4 Different implementations of the switch assembly.

[0035] Figures 8 to 11 Various embodiments of an inverter circuit including an inverter controller and a power semiconductor switch assembly are shown.

[0036] Figure 12 A perspective view of a unit including a power semiconductor switching device and a corresponding gate unit is shown.

[0037] Figure 13 A cross section through a power semiconductor switching device is shown.

[0038] Figure 14 A comparison of substrate areas of two different power semiconductor switching devices is shown.

[0039] Figure 15 The steps of a method for manufacturing a power converter are shown. DETAILED DESCRIPTION

[0040] Figure 3 A third switching circuit 30 is shown, which can be safely switched on and off without providing a snubber circuit. This is achieved by using two modified power semiconductor switching elements 31, similar to insulated gate bipolar transistors (IGBTs), which can be switched on and off in a controlled manner. Power semiconductor switching elements 31 include a fully controllable integrated gate-controlled thyristor (FCGCT) 32 and a freewheeling diode 22. FCGCT 32 can be implemented by integrating two functional structures (such as an IGCT structure and a non-latching switching structure (such as a BJT structure)) on a common substrate, thereby forming a single power semiconductor device. Optionally, a diode structure for freewheeling diode 22 can also be formed on the common substrate.

[0041] During the turn-on period, the current change di / dt of the switching element 31 can be controlled by driving the gate of the BJT structure of the FCGCT 32. Similarly, during the turn-off period, the voltage change dv / dt of the switching element 31 can also be controlled by driving the gate of the IGCT structure of the FCGCT 32. Although such an FCGCT-based switching element 31 may be desirable for the reasons indicated above regarding its switching behavior, the provision of two separate gate terminals results in a relatively complex housing once the FCGCT 32 is installed in a larger assembly, such as a converter or similar power switching circuit.

[0042] According to various embodiments of the present disclosure, this and other problems are addressed by packaging at least some of the structures used to implement FCGCT 32 not into a single chip or device, but into two or three separate chips or devices, each with only a single control terminal.

[0043] Figure 4 A general switch assembly 40 according to the present disclosure is shown, which implements functions corresponding to those of the improved power semiconductor switch element 31. The switch assembly 40 includes an IGCT structure 46, a BJT structure 47, and a diode structure 48. Compared to the improved power semiconductor switch element 31 based on the integrated FCGCT 32, each of the IGCT structure 46, the BJT structure 47, and the diode structure 48 can be integrated into a separate power semiconductor device. Figure 4As shown in FIG, in the context of the present disclosure, these three devices are referred to as a "thyristor device" or latching type power semiconductor switching device 41, a "transistor device" or non-latching type power semiconductor switching device 42, and a power semiconductor diode 43. Each of the two switching devices 41 and 42 has its own gate terminal 44 and 45, respectively.

[0044] Generally speaking, such switch assemblies 40 may be integrated into two or three units, as described below with respect to Figures 5 to 7 Further details are provided. The term "unit" may refer to a physically separate unit, such as a complete integrated circuit chip or device, or several circuit chips or devices arranged on a common carrier substrate (such as a PCB) and / or integrated into a common housing. The term "device," particularly "semiconductor switching device," may refer to the unit itself or one of its components. For example, a first unit may refer to a first PCB, and a latching power semiconductor switching device may be a first press-fit device arranged on or permanently connected to the first PCB. Similarly, a second unit may refer to a second PCB, and a non-latching power semiconductor switching device may be a second press-fit device arranged on or permanently connected to the second PCB. In contrast, the terms "structure" (particularly the term "IGCT structure"), "thyristor structure," "BJT structure," "transistor structure," and "diode structure" generally refer to internal portions of a larger device or unit. For example, the IGCT structure and the diode structure may be integrally formed within or on top of the substrate of a first semiconductor power device (such as the first press-fit device). Similarly, the BJT structure and the diode structure may be integrally formed within or on top of a substrate of a second semiconductor power device (such as a second press-fit device).

[0045] exist Figure 5 In the configuration shown in FIG, a total of three units 51 to 53 are provided. The first unit 51 includes a latching power semiconductor switch device 41 and a corresponding first gate unit 54. The second unit 52 includes a non-latching power semiconductor switch device 42 and a corresponding second gate unit 55. The third unit 53 includes a power semiconductor diode 43.

[0046] like Figure 5 As can be seen in FIG5 , each of the power semiconductor devices 41 to 43 includes a first power supply terminal 56 and a second power supply terminal 57. In the depicted embodiment, the latch-type power semiconductor switching device 41 is implemented by an IGCT structure 46. In this case, the first power supply terminal 56 corresponds to the anode of the thyristor structure contained therein and the second power supply terminal 57 corresponds to the cathode.

[0047] The non-latching power semiconductor switch device 42 can be implemented in the form of a BJT structure 47 or a non-latching thyristor structure. For example, the non-latching power semiconductor switch device 42 may include a quenched or non-self-sustaining thyristor structure that automatically turns off when a reasonable gate current through its gate electrode is turned off. In other words, the non-latching thyristor structure may have such a low current gain product that it does not latch during normal operation. In particular, the thyristor structure is designed so that it is non-self-sustaining, for example, it automatically turns off when the gate current through the designated gate electrode is turned off.

[0048] In the case of the BJT structure 47, the first power supply terminal 56 corresponds to the collector of the BJT or the anode of the non-latching thyristor structure. The second power supply terminal 57 corresponds to the emitter of the BJT structure 47 or the cathode of the non-latching thyristor structure. That is, the first latching power semiconductor switching device 41 and the second non-latching power semiconductor switching device 42 are arranged in parallel with respect to the current switched by the switch assembly 40.

[0049] In contrast, the anode of the power semiconductor diode 43 or the diode structure 48 included therein is connected to the second power supply terminal 57 and the cathode thereof is connected to the first power supply terminal 56. That is, the power semiconductor diode 43 is configured in an anti-parallel configuration with respect to the power semiconductor switching devices 41 and 42. Therefore, in operation, the power semiconductor diode 43 acts as a freewheeling diode.

[0050] The first gate unit 54 and the second gate unit 55 are connected to the first gate terminal 44 of the latching type power semiconductor switching device 41 and the second gate terminal 45 of the non-latching type power semiconductor switching device 42. These gate units are provided to provide appropriate control signals to the corresponding gate terminals so as to safely cut off in the case of the first gate unit 54 of the switching component 40 and safely turn on in the case of the second gate unit 55.

[0051] In particular, the switch assembly 40 operates as described below. During turn-on, a gate current is applied between the second gate terminal 45 of the non-latching power semiconductor switching device 42 and the second power supply terminal 57. The current change di / dt (specifically, the anode current in the case of a thyristor structure used as the non-latching power semiconductor switching device 41) is controlled by the current change di / dt of the applied gate current. In the case of a BJT structure, the operation is largely the same. However, a higher gate current is used to drive the BJT structure. During this phase, the second gate terminal 44 of the latching switching device 41 remains in the off state.

[0052] As soon as the anode / cathode voltage across the latching power semiconductor switch device 41 collapses (e.g., typically to 25% of the DC link voltage switched by the switch assembly 40), the gate of the latching power semiconductor switch device 41 is triggered by a corresponding gate current supplied from the first gate unit 54 to the first gate terminal 44. The gate current of the non-latching power semiconductor switch device 42 is ramped down to zero again. Thus, the current flowing through the switch assembly 40 commutates from the non-latching power semiconductor switch device 42 to the latching power semiconductor switch device 41. Once current is flowing through the latching power semiconductor switch device 41, the gate current of the latching power semiconductor switch device 41 can also be disabled.

[0053] When the switch assembly 40 is to be turned off, a negative gate current is applied to the gate IGCT structure 46 of the latching power semiconductor switching device 41 via the first gate unit 54 and the first gate contact 44. Optionally, a negative gate current can also be applied to the non-latching semiconductor switching device 42 via the second control unit 55 and the second gate terminal 45.

[0054] Figure 6 An alternative embodiment of the switch assembly 40 according to an embodiment of the present disclosure is shown. Figure 5 In contrast to the configuration detailed in Figure 6 Only two cells 61 and 62 are provided in the configuration shown in . Each of the cells 61 and 62 includes a single power semiconductor switching device, namely a latching power semiconductor switching device 41 and a non-latching power semiconductor switching device 42. In addition, the first cell 61 also includes a diode 48 structure, which is directly integrated into the latching power semiconductor switching device 41. In other words, the semiconductor switching device 41 of the first cell 61 includes an IGCT structure 46 and a diode structure 48. The non-latching power semiconductor switching device 42 only includes a transistor structure, such as a BJT structure 47 or a quenched IGCT, as described in detail above with respect to the second cell 52. The various terminals and their interconnections correspond to Figure 5 The configuration shown in and is not described again for the sake of brevity.

[0055] Attention is drawn to the fact that, although the diode structure 48 is integrated into the first power semiconductor switch device 41, only a single gate terminal 44 needs to be provided with respect to the latch-type power semiconductor switch device 41. Therefore, each of the first power semiconductor switch device 41 and the second power semiconductor switch device 42 can be integrated into a conventional housing, such as a housing of a press-fit type device having a single control gate terminal.

[0056] Figure 7 An alternative configuration of the switch assembly 40 is shown, which is similar to Figure 6The configuration shown in is similar in that it also includes only two units, namely a first unit 71 and a second unit 72. Figure 6 In contrast to the illustrated configuration, the diode structure 48 is integrated into the non-latching power semiconductor switch device 42. In contrast, the non-latching power semiconductor switch device 41 includes only the IGCT structure 46. Figure 7 Other aspects of the switch assembly 40 correspond to Figure 5 and Figure 6 and are not described again for the sake of brevity.

[0057] As detailed above, the integration of the diode structure 48 into the non-latching power semiconductor switch device 42 does not require the provision of an additional gate terminal. Therefore, the non-latching power semiconductor switch device 42 also includes only a single gate terminal 45. Figure 14 As detailed, this particular configuration has the following advantages: it achieves thermal balancing of the two power semiconductor switching devices 41 and 42 .

[0058] Figures 8 to 11 Different embodiments of parts of the converter circuit 80, in particular a part of the inverter, are shown. Figures 8 to 11 In the embodiment shown in FIG, a switch assembly 40 is shown which includes three separate power semiconductor devices 41 to 43. However, with respect to FIG. Figures 8 to 11 The control signals described are also applicable to Figure 6 and Figure 7 One of two unit configurations of the switch assembly 40 is shown in FIG.

[0059] In particular, Figure 8 In the converter circuit 80 shown in FIG, the inverter control circuit 81 directly provides two different control signals to the first gate unit 54 and the second gate unit 55 respectively. Figure 9 In the configuration shown in , the inverter controller 81 provides only a single control signal directly to the first gate control unit 54. The gate unit 54 is configured as a master controller and generates a corresponding second control signal for the second gate unit 55, which is configured as a slave controller. Figure 10 A complementary configuration is shown, wherein the controller 81 provides control signals directly to the second gate unit 55. The second gate unit 55 is configured as a master controller and provides corresponding control signals to the first gate unit 54, which is configured as a slave controller.

[0060] exist Figure 11In the configuration, only a single combined gate unit 82 is provided, and this combined gate unit is directly controlled by the control circuit 81. The combined gate unit 82 provides a first control signal to the first gate terminal 44 of the latching power semiconductor switch device 41 and a second control signal to the second gate terminal 45 of the non-latching power semiconductor switch device 42. The combined gate unit 82 can be, for example, part of the first unit 51, 61, or 71 or the second unit 52, 62, or 72. Alternatively, the combined gate unit 82 can be part of a separate entity (e.g., a PCB with the inverter controller 81).

[0061] Figure 12 One switching unit 90 of the at least two units of the switching assembly 40 is shown. In particular, Figure 12 The switch unit 90 shown in FIG. 1 may correspond to Figure 7 The second unit 72 is shown in FIG.

[0062] like Figure 12 As shown in FIG, a switch unit 90 includes a printed circuit board (PCB) 91, a first housing 92 covering a portion of the PCB 91, and a press-pack device 94 placed on the PCB 91 and having a second housing 93. The first housing 92 may be, for example, an open metal housing, and the second housing 93 may be, for example, a sealed high-pressure-resistant housing, as described in further detail below.

[0063] In the embodiment described, the press-contact device 94 corresponds to the non-latching power semiconductor switching device 42 described above. The first power supply terminal 56 and the second power supply terminal 57 of the non-latching power semiconductor switching device 42 are formed on the upper and lower sides of the press-contact device 94. The gate terminal 45 and the auxiliary contact (at the bottom) connected to the second power supply terminal 57 of the non-latching power semiconductor switching device 42 Figure 12 The first housing 92 includes a first housing 92 and a second housing 92 (not shown in the figure). ...). The first housing 92 includes a first housing 92 and a second housing 92 (not shown). The first housing 92 includes a first housing 92 and a second housing 92 (not shown). The first housing 92 includes a first housing 92 and a second housing 92 (

[0064] Figure 13 A cross section is shown through the power semiconductor device 100 . In the depicted embodiment, the power semiconductor device 100 implements a non-latching power semiconductor switch device 42 with an integrated semiconductor power diode 43 . Figure 13 Specifically shown are press-fit devices such as Figure 12 The internal setting of the press-fit device 94).

[0065] As in Figure 13As can be seen from the cross section of the power semiconductor device 100, the housing includes a first ( Figure 13 The lower part) housing part 101, the second (in Figure 13 The first housing portion 101 and the second housing portion 102 are formed of a material having good conductive properties, such as copper or another suitable metal, and form the outer parts of the power terminals 56 and 57 of both the power semiconductor switching device 42 and the integrated semiconductor power diode 43. They are separated by the insulating side walls 103. For example, the insulating side walls 103 can take the form of a hollow cylinder made of ceramic or other insulating material. Figure 13 As also shown in FIG, the outer surface of the insulating sidewall 103 may have an integrated shed structure 104 to increase the creepage distance between the first housing portion 101 and the second housing portion 102. The insulating sidewall 103 also includes a sleeve 105 for passing a gate lead 106. Together, the housing portions 101 to 103 and 105 form a hermetically sealed cavity 107 for one or more electronic components of the press-fit device.

[0066] In the depicted embodiment, the electronic components take the form of semiconductor structures formed within a semiconductor substrate 110, such as a semiconductor wafer. The substrate 110 is held in place by a wafer edge insulating portion 111. The wafer edge insulating portion 111 may be made of, for example, silicon. Figure 13 As can be seen in the cross-section of FIG, semiconductor substrate 110 has different functional regions associated with the different semiconductor structures formed therein. Starting from the center and working outward, semiconductor substrate 110 includes a thyristor gate contact region 112, a conducting thyristor portion 113, and a diode portion 114. The lower major surfaces of conducting thyristor portion 113, which corresponds to the anode of the non-latching thyristor structure, and diode portion 114, which corresponds to the cathode of the diode structure, are in direct contact with a first inner portion 116 of the first power supply terminal 56, which may be formed of molybdenum. The upper surfaces of conducting thyristor portion 113, which corresponds to the cathode of the non-latching thyristor structure, and diode portion 114, which corresponds to the anode of the diode structure, are in direct contact with a second inner portion 117 of the second power supply terminal 57, which may be formed of molybdenum, for example. The thyristor gate contact region 112 is isolated from the two inner portions 116 and 117 and is connected to the gate lead 106.

[0067] Figure 14 The left side shows Figure 13Schematic top view of the semiconductor substrate 110. The thyristor gate contact region 112 and the conducting thyristor portion 113 of the semiconductor substrate 110 are used to implement the non-self-sustaining thyristor structure 118 of the non-latch type power semiconductor switch device 42. Figure 13 and Figure 14 The non-self-sustaining thyristor structure 118 is indicated in FIG, but may be as described above with respect to Figures 4 to 11 The corresponding BJT structure 47 is implemented as described in detail. The outer portion of the semiconductor substrate 110 is used to implement the diode structure 48 of the non-latching power semiconductor switch device 42.

[0068] Figure 14 The right side of FIG shows another semiconductor substrate 120 for implementing a latch-type power semiconductor switching device 41 including an IGCT structure 46. It includes a central thyristor gate contact region 121 and a holding thyristor portion 122 surrounding it. By comparison Figure 14 From the top view of the first and second semiconductor switching devices 41 and 42, it becomes clear that more surface area is available for implementing the self-sustaining IGCT structure 46 of the latching power semiconductor switching device 41, compared to the non-self-sustaining thyristor structure of the non-latching power semiconductor switching device 42. This is advantageous for thermal or load balancing because, on average, the IGCT structure 46 will carry a larger portion of the current switched by the corresponding semiconductor power switch assembly 30. Therefore, if the same housing type, or at least a housing type with similar dimensions, is used to encapsulate the first and second semiconductor switching devices 41 and 42, thermal balancing between the two devices 41 and 42 can be achieved.

[0069] Further details on suitable IGCT structures, BJT structures and diode structures and their manufacture and integration can be found in WO 2021 / 197774 A1, which is incorporated herein by reference. Further details on suitable self-sustaining thyristor structures, non-self-sustaining thyristor structures and diode structures and their manufacture and integration can also be found in European patent application 21212227.9, which is incorporated herein by reference.

[0070] Figure 15 Steps S1 to S5 for manufacturing a power converter, such as the converter circuit 80 , are shown in a schematic flow chart.

[0071] In step S1 , a first unit having a first gate terminal is provided. As described above with respect to various embodiments, the first unit comprises at least a latch-type power semiconductor switch device and may further comprise additional components such as a diode structure or device and / or a first gate unit.

[0072] In step S2, a second unit having a second gate terminal is provided. As described above in detail with respect to various embodiments, the second unit includes at least a non-latching power semiconductor switching device and may include additional components, such as a diode structure or device and / or a second gate unit. In particular, if the first unit does not include a diode structure or device, the second unit may include a diode structure or device.

[0073] In step S3, a power semiconductor diode is provided. As detailed above, this may be a diode structure or device forming part of the first unit or the second unit. Alternatively, a separate third unit may be provided in step S3, the third unit comprising a diode structure or device.

[0074] In step S4, the latching-type power semiconductor switching device included in the first unit and the non-latching-type power semiconductor switching device included in the second unit are connected in parallel with respect to the current switched by the power converter. This can be achieved, for example, by placing the corresponding conductive housing portions of the corresponding press-fit devices between a common busbar.

[0075] In step S5, a power semiconductor diode is connected in an anti-parallel configuration relative to the current switched by the power converter. If the power semiconductor diode is formed in a separate unit (such as the third unit), this can be achieved by positioning the third unit in an opposite direction relative to the first and second units. If the power semiconductor device is formed as an integrated part of either the first or second unit, this is typically achieved during the design phase by arranging the anode contact of the diode structure on the same semiconductor substrate surface as the cathode portion of the corresponding thyristor structure or the emitter of the corresponding transistor structure. Similarly, the cathode of the diode structure can be formed on the same surface as the anode portion of the thyristor structure or the collector of the corresponding transistor structure.

[0076] Figures 1 to 15 The embodiments shown in the accompanying drawings represent exemplary embodiments of improved power semiconductor switch arrangements, power semiconductor devices, converter circuits, and methods for manufacturing the same. Therefore, they do not constitute a complete list of all embodiments according to the improved devices, systems, and methods. For example, actual devices, arrangements, and methods may differ from the illustrated embodiments in terms of, for example, their relative arrangement, specific components, and the signals provided for controlling them.

[0077] Reference numerals 10 (First) Switching Circuit 11 Switching elements 12 Central Nodes 13 Buffer Circuit 14 Choke circuit 15 Clamp Circuit 16 Inductor 17 Diode 18 resistors 19 Capacitor 20 (Second) Switching Circuit 21 Integrated gate-commutated thyristor (IGCT) 22 Freewheeling diode 30 (Third) Switching Circuit 31 Power semiconductor switching elements 32 Fully Controllable Gate Commutated Thyristor (FCGCT) 40 switch assembly 41 (Latch type) power semiconductor switching device 42 (Non-latching) power semiconductor switching devices 43 Power semiconductor diodes 44 first gate terminal 45 Second gate terminal 46 IGCT structure 47 BJT structure 48 Diode Structure 51 Unit 1 52 Unit 2 53 Unit 3 54 first gate unit 55 Second gate unit 56 First power terminal 57 Second power terminal 61 Unit 1 62 Unit 2 71 Unit 1 72 Unit 2 80 Converter Circuit 81 Control Circuit 82 combined gate units 90 switch unit 91 Printed Circuit Board (PCB) 92 first shell 93 Second Shell 94 Press-fit devices 100 Power semiconductor devices 101 first shell part 102 Second shell part 103 Insulation sidewall 104 Shed Structure 105 casing 106 gate lead 107 Cavity 108 Auxiliary cathode contact 110 semiconductor substrate 111 Wafer edge insulation part 112 Thyristor gate contact area 113 Turn-on thyristor part 114 diode part 116 First inner portion (of the first power supply terminal) 117 Second inner portion (of the second power supply terminal) 118 Non-self-sustaining thyristor structure 120 (Another) semiconductor substrate 121 Thyristor gate contact area 122 Holding thyristor part

Claims

1. A fully controllable power semiconductor switch assembly (40), comprising: - a first unit (51, 61, 71) comprising a latch-type power semiconductor switching device (41) controlled by a first gate terminal (44); - a second unit (52, 62, 72) comprising a non-latching power semiconductor switching device (42) controlled by a second gate terminal (45); and - Power semiconductor diodes (43); - wherein the latching power semiconductor switching device (41) and the non-latching power semiconductor switching device (42) are connected in a parallel configuration with respect to the current switched by the switching component (40), and the power semiconductor diode (43) is connected in an anti-parallel configuration with respect to the current switched by the switching component (40).

2. The switch assembly (40) according to claim 1, wherein The semiconductor diode (43) is integrated into the second unit (72), and the semiconductor diode (43) is particularly integrated into the housing of the non-latching power semiconductor switching device (42) as a diode structure (48).

3. The switch assembly (40) according to claim 1, wherein - the semiconductor diode (43) is integrated into the first unit (61), the semiconductor diode (43) being integrated, in particular as a diode structure (48), into a housing for the latch-type power semiconductor switching device (41); or The switch assembly further comprises a third unit (53), which comprises the power semiconductor diode (43), which is integrated into a separate housing, in particular as a diode structure (48).

4. The switch assembly (40) according to any one of claims 1 to 3, wherein: - the first unit (51, 61, 71) further includes a combined gate unit (82) for the latching power semiconductor switch device (41) and the non-latching power semiconductor switch device (42); The second unit (52, 62, 72) further includes a combined gate unit (82) for the latching power semiconductor switch device (41) and the non-latching power semiconductor switch device (42); or The first unit (51, 61, 71) further comprises a first gate unit (54) for the latch-type power semiconductor switch device (41), and the second unit (52, 62, 72) further comprises a second gate unit (55) for the non-latching power semiconductor switch device (42).

5. The switch assembly (40) according to any one of claims 1 to 4, wherein: - the dimensions of the first unit (51, 61, 71) correspond to the dimensions of the second unit (52, 62, 72); and / or - The latching power semiconductor switching device (41) is integrated into a first housing, in particular into a housing of a first press-contact device, and the non-latching power semiconductor switching device (42) is integrated into a second housing (93), in particular into a housing (103) of a second press-contact device (94), and the size of the first housing corresponds to the size of the second housing (93).

6. The switch assembly (40) according to any one of claims 1 to 5, wherein: The latch-type power semiconductor switch device (41) includes at least one integrated gate commutated thyristor (IGCT) structure (46).

7. A power semiconductor device (100), in particular for use in a switch assembly (40) according to any one of claims 1 to 6, the power semiconductor device (100) comprising: - a sealed housing (93) having a first power terminal (56), a second power terminal (57) and a gate terminal (45); - a non-latching power semiconductor switching device (42) arranged in the sealed housing (93) and configured to selectively switch current from the first power terminal (56) to the second power terminal (57) based on a control signal provided via the gate terminal (45); as well as - a power semiconductor diode (43) arranged within the sealed housing (93) and configured to conduct current from the second power supply terminal (57) to the first power supply terminal (56).

8. The power semiconductor device (100) according to claim 7, wherein: The non-latching power semiconductor switch device (42) and the power semiconductor diode (43) are formed as semiconductor structures (47, 48, 118) on or within a common semiconductor substrate (110).

9. The power semiconductor device (100) according to claim 7 or 8, wherein: The power semiconductor device (100) is a press-fit device (94), and the sealed housing (93) comprises: - a conductive first housing part (101) forming at least a portion of the first power terminal (56); - a conductive second housing part (102) forming at least a portion of the second power terminal (57); - an insulating side wall (103) separating the first housing part (101) and the second housing part (102); and - a bushing (105) arranged at or within the insulating sidewall (103) and configured for providing the control signal to the gate terminal (45).

10. The switch assembly (40) according to any one of claims 1 to 6 or the power semiconductor device (100) according to any one of claims 7 to 9, wherein: - the non-latching power semiconductor switch device (42) comprises a bipolar transistor structure (47); or - The non-latching power semiconductor switching device (42) includes a non-self-sustaining thyristor structure (118).

11. A snubberless power converter, in particular a power inverter, comprising a fully controllable power semiconductor switch assembly (40) according to any one of claims 1 to 6.

12. The snubberless power converter of claim 11 , further comprising: - a control circuit (81) configured to provide at least one control signal for controlling the non-latching power semiconductor switching device (41) and / or the latching power semiconductor switching device (42).

13. The snubberless power converter according to claim 12, wherein: - the control circuit (81) is connected to both the first cell (51, 61, 71) and the second cell (52, 62, 72) and is configured to provide a first control signal to a first gate cell (54) associated with the first gate terminal (44) and a second control signal to a second gate cell (55) associated with the second gate terminal (45); - the control circuit (81) is connected to the first unit (51, 61, 71) and is configured to provide a first control signal to a main control unit associated with the first gate terminal (44), in particular to the combined gate unit (82) or the first gate unit (54) according to claim 4, wherein the main control unit is configured to provide a second control signal to the second unit (52, 62, 72); or The control circuit (81) is connected to the second unit (52, 62, 72) and is configured to provide a second control signal to a main control unit associated with the second gate terminal (45), in particular a combined gate unit (82) or a second gate unit (55) according to claim 4, wherein the main control unit is configured to provide a first control signal to the first unit (51, 61, 71).

14. The snubberless power converter according to claim 12 or 13, wherein: The controller (81) is specifically configured to: - when the switch assembly (40) is turned on, applying a positive gate current between the gate terminal (45) and the cathode terminal of the non-latching power semiconductor switching device (42); - after the voltage between the anode and the gate terminal (44) of the latching power semiconductor switching device (41) has collapsed, triggering the gate of the latching power semiconductor switching device (41) and reducing the positive gate current between the gate terminal (45) and the cathode terminal of the non-latching power semiconductor switching device (42) to zero; as well as - With the switching component (40) switched off, a negative gate current is applied to the gate terminal (44) of the latching power semiconductor switching device (41) and optionally to the gate terminal (45) of the non-latching power semiconductor switching device (42).

15. A method for manufacturing a power converter, in particular a snubberless power converter according to any one of claims 11 to 14, the method comprising: - providing a first unit (51, 61, 71) comprising a latch-type power semiconductor switching device (41) controlled by a first gate terminal (44); - providing a second unit (52, 62, 72) comprising a non-latching power semiconductor switching device (42) controlled by a second gate terminal (45); - providing a power semiconductor diode (43) within the first unit (61), the second unit (72) or within a separate third unit (53); - connecting the latching type power semiconductor switching device (41) and the non-latching type power semiconductor switching device (42) in a parallel configuration with respect to a current switched by the power converter; and - connecting the power semiconductor diode (43) in an anti-parallel configuration with respect to the current switched by the power converter.

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