Groove type MOSFET device integrated with junction control diode and method

Abstract

The invention relates to the technical field of power semiconductor devices, and discloses a trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device integrated with a junction control diode and a method. A P-type well region is arranged on the first N-type epitaxial layer, a source contact region is arranged on the P-type well region, and an N-type buffer region is arranged at the bottom of the P-type well region; the N-type buffer region penetrates through the source electrode contact region and the P-type well region and goes deep into the trench MOSFET region of the first N-type epitaxial layer. According to the invention, the junction-controlled freewheeling diode is integrated at the side of the shield grid, so that the conduction voltage drop of the diode during freewheeling is reduced, and the reverse recovery time is greatly shortened. A high-turn-on-voltage diode is additionally arranged at the bottom of the shielding grid, the turn-on voltage is bipolar conduction, self-turn-on conduction is achieved under extreme working conditions such as surge, and the reliability of the device is improved. And the shielding grid electrode can form an electric field shielding effect during reverse voltage withstanding, so that electric field clamping at the bottom of the true grid electrode is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a trench MOSFET device integrated with a junction-controlled diode and a method. BACKGROUND

[0002] Compared with silicon (Si) materials, wide-bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have physical properties such as large bandgap, high breakdown field strength, and fast electron saturation drift speed. The power devices such as diodes, transistors, and power modules prepared therefrom have more excellent electrical properties and can overcome the defects of silicon-based devices that cannot meet the application requirements of high power, high voltage, high frequency, and high temperature. Therefore, they are widely used in high-voltage, high-efficiency, and high-power applications such as photovoltaic, energy storage, charging piles, and electric vehicles.

[0003] However, in actual design and process manufacturing, there are still several problems with the trench MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) of wide-bandgap semiconductor materials: the high electric field of the material drift region causes a very high electric field on the gate dielectric layer, which is exacerbated at the trench corner, thereby inducing reliability problems at high drain voltages, and even directly causing gate dielectric breakdown. The poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in circuits. In addition, the parasitic body diode has a minority carrier storage effect, a long reverse recovery time, and increases the switching loss. In addition, minority carrier conduction can also cause diode bipolar degradation problems. Therefore, how to reduce the gate trench corner electric field of the wide-bandgap semiconductor trench MOSFET device while reducing the switching loss has become a problem to be solved.

[0004] As prior art 1: CN119545860A discloses a trench MOSFET device integrated with a junction-controlled diode, which is grounded through a P-type epitaxial layer and two types of P-type masking layers to achieve good electric field shielding effect during reverse voltage, thereby avoiding degradation of device switching characteristics. A junction-controlled freewheeling diode region is introduced between the two trench MOSFET regions to shield the conduction of the body diode, reduce the reverse recovery time, and reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device.

[0005] As prior art 2: CN114038908A discloses a trench gate silicon carbide MOSFET device integrated with diode and manufacturing method thereof, by introducing an N-type channel layer and a longitudinal inverted L-shaped N+ source region in the trench bottom deep Pwell region of the trench gate silicon carbide MOSFET device structure, a diode with low on-state voltage drop is integrated by using the low barrier existing at the interface between the N-type channel layer and the gate oxide layer, the third quadrant performance of the device is significantly improved, and the problem of bipolar degradation caused by the turn-on of the body diode is inhibited. SUMMARY

[0006] The present application aims at the problem that in the prior art, when the trench gate MOSFET withstands voltage, the high electric field of the material drift region causes a very high electric field on the gate dielectric layer, which is intensified at the trench corner, thereby inducing reliability problems under high drain voltage, and even directly causing gate dielectric breakdown, poor resistance to electrostatic effects in harsh environments, and poor resistance to high voltage spikes in circuits.

[0007] When the trench gate MOSFET is in freewheeling, the parasitic body diode has a minority carrier storage effect, the reverse recovery time is long, and the switching loss is increased, and the minority carrier conduction also causes the problem of bipolar degradation of the diode. Therefore, how to reduce the gate trench corner electric field of the wide bandgap semiconductor trench MOSFET device while reducing the switching loss has become a problem to be solved.

[0008] The trench gate MOSFET body diode has a high on-state voltage drop, which causes the problem of increased system loss, and a trench MOSFET device integrated with a junction-controlled diode and a method are provided.

[0009] A trench MOSFET device integrated with a junction-controlled diode, the MOSFET device is provided with a drain metal layer, an N-type substrate, an N-type buffer layer and a first N-type epitaxial layer from bottom to top in sequence; it further comprises a trench MOSFET region; A P-type well region is arranged on the first N-type epitaxial layer, a source contact region is arranged on the P-type well region, and an N-type buffer region is arranged at the bottom of the P-type well region; the N-type buffer region penetrates through the source contact region and the P-type well region, and extends into the trench MOSFET region of the first N-type epitaxial layer; The trench MOSFET region comprises a first gate, a second gate and a third gate; a first channel is formed between the first gate and the second gate, the side of the first channel close to the second gate is a conductive N-type channel, and the side of the first channel close to the first gate is a junction-controlled diode channel; a second channel is formed between the second gate and the third gate, the side of the second channel close to the second gate is a conductive N-type channel, and the side of the second channel close to the third gate is a junction-controlled diode channel; the conductive N-type channel is located on the P-type well region of the first N-type epitaxial layer; The second gate bottom is provided with a first P-type shielding area, and the first P-type shielding area covers the interlayer dielectric layer of the second gate and the inner conductive medium of the trench of the first gate. The first gate and the third gate are provided with a source contact area on the surface, and the bottom of the first gate and the third gate is provided with a second P-type shielding area; and the conductive medium inside the first gate and the third gate is connected with the second P-type shielding area.

[0010] Preferably, the source contact area comprises an N+ area source and a P+ area source, and the N+ area source and the P+ area source are provided with a source metal contact hole.

[0011] Preferably, at least one conductive N-type channel is arranged at the second gate trench MOSFET area, the conductive N-type channel is arranged on a P-type well area of the first N-type epitaxial layer, and a source contact area exists on the P-type well area; an N-type buffer area is arranged at the bottom of the P-type well area, and the second gate penetrates the source contact area and the P-type well area and extends into the epitaxial layer.

[0012] Preferably, the first P-type shielding area arranged at the second gate trench comprises continuous arrangement or interval arrangement.

[0013] Preferably, the second P-type shielding area arranged at the first gate and the third gate comprises continuous arrangement or interval arrangement.

[0014] Preferably, the N+ area source is close to the top, the P+ area source extends into the P-type well area and is arranged at the bottom of the N+ area source.

[0015] Preferably, the depth of the first gate trench and the third gate trench is greater than the depth of the second gate trench.

[0016] Preferably, the surface of the first gate trench and the third gate trench is provided with an N-type well area.

[0017] To solve the above technical problems, the application provides a method for manufacturing a trench type MOSFET device integrated with a junction control diode, which comprises the following steps: An N-type substrate is sequentially grown with an N-type buffer layer and an N-type epitaxial layer; An ion implantation is performed to form an N-type buffer area, a P-type well area, an N+ area source and a P+ area source; An etching is performed to form a shielding gate trench, i.e. a region where the shielding gate conductive medium and the gate dielectric layer are located; An ion implantation is performed to form a second P-type shielding area; An etching is performed to form a real gate trench, i.e. a region where the shielding gate conductive medium and the gate dielectric layer are located; An ion implantation is performed to form a first P-type shielding area; An oxidation or deposition is performed to form a gate dielectric layer; Etching shield gate bottom gate dielectric layer; Depositing true gate conductive dielectric and shield gate conductive dielectric, which can be formed simultaneously or in two steps, increasing the margin that can be regulated; Source contact hole, source metal, drain metal formation.

[0018] To solve the above technical problems, the present application is solved by the following technical solutions: The present application has the following technical effects: The present application increases the gate shielding structure, alleviates the gate oxide field concentration at the trench bottom and corner during voltage resistance, and improves the reliability of the device gate.

[0019] The present application integrates a junction control freewheeling diode on the side of the shield gate, which not only reduces the conduction voltage drop of the diode during freewheeling, but also eliminates the minority carrier storage effect, thereby greatly reducing the reverse recovery time.

[0020] The high turn-on voltage diode is added at the bottom of the shield gate, which is bipolar conduction, and is self-conducting under extreme conditions such as surge, thereby improving the reliability of the device.

[0021] The depth of the shield gate is higher than that of the true gate trench: the shield gate forms an electric field shielding effect during reverse voltage resistance, achieving electric field clamping at the bottom of the true gate.

[0022] The second P-type shielding region and the first P-type shielding region at the bottom of the shield gate and the true gate can be simultaneously ion implanted in actual process, reducing manufacturing process and manufacturing cost; The conductive medium in the shield gate needs to be adjusted according to actual application, such as polycrystalline silicon, Ti, etc., so as to adjust the turn-on voltage at the interface; the conductive medium in the shield gate and the true gate can be the same type or different types, and the insulating medium of the shield gate and the true gate is the same type; The N-type well region doping concentration at the surface of the shield gate trench needs to be finely adjusted, one is to ensure that it can be depleted by the P+ source and the P-type well region, and the other is to ensure that the conduction voltage Vth is not too high, which is normally about 1.5V. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a structure schematic diagram of the trench MOSFET device of the present application.

[0024] Figure 2 is a structure AA' cross-sectional schematic diagram of the trench MOSFET device of the present application.

[0025] Figure 3 is a structure BB' cross-sectional schematic diagram of the trench MOSFET device of the present application.

[0026] Figure 4 is a schematic diagram of the cross section of the trench MOSFET device structure CC' of the present application.

[0027] Figure 5 is a flow chart of the preparation method of the MOSFET device of the present application.

[0028] Figure 6-1 is a layout implementation mode one of the first P-type shielding region, the second P-type shielding region and the trench bottom of the present application.

[0029] Figure 6-2 is a layout implementation mode two of the first P-type shielding region, the second P-type shielding region and the trench bottom of the present application.

[0030] Figure 6-3 is a layout implementation mode three of the first P-type shielding region, the second P-type shielding region and the trench bottom of the present application.

[0031] Figure 7 is a schematic diagram of the surface structure in which the P+ type source can be arranged of the present application.

[0032] Figure 8 is a schematic diagram of the structure in which the first P-type shielding region and the second P-type shielding region are doped as the same step ion implantation of the present application.

[0033] In the figure, 100 is the first N-type epitaxial layer, 101 is the second P-type shielding region, 102 is the shielding gate, 103 is the P-type well region, 104 is the N+ region source, 105 is the source metal region, 106 is the first P-type shielding region, 107 is the real gate, 108 is the P+ region source, 109 is the N-type well region, 110 is the source metal contact hole, 111 is the N-type buffer layer, 112 is the drain metal layer, 113 is the gate insulating medium, and 114 is the N-type buffer region. DETAILED DESCRIPTION

[0034] The present application will be further described in detail below in combination with the drawings and examples.

[0035] Example 1 A trench MOSFET device integrated with a junction controlled diode, the MOSFET device is sequentially provided from the bottom to the top with a drain metal layer 112, an N-type substrate, an N-type buffer layer 111 and a first N-type epitaxial layer 100; it further comprises a trench MOSFET region; The first N-type epitaxial layer 100 is provided with a P-type well region 103, the P-type well region 103 is provided with a source metal region 105, and the bottom of the P-type well region 103 is provided with an N-type buffer region 114; the N-type buffer region 114 penetrates through the source metal region 105 and the P-type well region 103, and extends into the trench MOSFET region of the first N-type epitaxial layer 100; The trench MOSFET region comprises a first gate, a second gate and a third gate; a first channel is formed between the first gate and the second gate, the first channel is a conductive N-type channel on one side close to the second gate, and the first channel is a junction-controlled diode channel on one side close to the first gate; a second channel is formed between the second gate and the third gate, the second channel is a conductive N-type channel on one side close to the second gate, and the second channel is a junction-controlled diode channel on one side close to the third gate; the conductive N-type channel is located on a P-type well region 103 on the first N-type epitaxial layer 100; The second gate is provided with a first P-type shielding region 106 at the bottom, and the first P-type shielding region 106 covers the interlayer dielectric layer of the second gate and the conductive dielectric inside the trench of the first gate; The first gate and the third gate are provided with a source metal region 105 on the surface; the first gate and the third gate are provided with a second P-type shielding region 101 at the bottom; and the conductive dielectric inside the first gate and the third gate is in contact with the second P-type shielding region 101.

[0036] The source metal region 105 comprises an N+ region source 104 and a P+ region source 108; and the N+ region source 104 and the P+ region source 108 are provided with a source metal contact hole 110.

[0037] At least one conductive N-type channel is arranged in the second gate trench MOSFET region, the conductive N-type channel is located on the P-type well region 103 on the first N-type epitaxial layer 100, and the P-type well region 103 is provided with the source metal region 105; the P-type well region 103 is provided with an N-type buffer region 114 at the bottom, and the second gate penetrates through the source metal region 105 and the P-type well region 103 and extends into the epitaxial layer.

[0038] The first P-type shielding region 106 arranged at the second gate trench comprises continuous arrangement or interval arrangement; The second P-type shielding region 101 arranged at the first gate and the third gate comprises continuous arrangement or interval arrangement.

[0039] The N+ region source 104 is close to the top, the P+ region source 108 extends into the P-type well region 103 and is located at the bottom of the N+ region source 104.

[0040] The depth of the trench at the first gate and the third gate is greater than the depth of the trench at the second gate.

[0041] The surface of the trench at the first gate and the third gate is provided with an N-type well region.

[0042] Embodiment 2 The embodiment is a method for realizing a trench MOSFET device integrated with a junction-controlled diode, and the method comprises the following steps: An N-type substrate is sequentially grown with an N-type buffer layer 111 and an N-type epitaxial layer 100; Ion implantation to form N-type buffer region 114, P-type well region 103, N+ region source 104, P+ region source 107; Etching to form shield gate trench, i.e. the region where shield gate conductive medium 102 and gate dielectric layer 113 are located; Ion implantation to form second P-type shield region 101 Etching to form real gate trench; i.e. the region where shield gate conductive medium 107 and gate dielectric layer 113 are located; Ion implantation to form first P-type shield region 106; Oxidation or deposition to form gate dielectric layer 113; Etching shield gate bottom gate dielectric layer 113; Deposition of real gate conductive medium 107 and shield gate conductive medium 102, which can be formed simultaneously or in two steps, increasing the margin that can be controlled; Source contact hole 110, source metal 105, drain metal formation 112.

[0043] Example 3 On the basis of Example 1, the layout implementation of the first P-type shield region 106 and the second P-type shield region 101 at the bottom of the trench can achieve the same effect by setting different layout proportions. Figure 6-1 In this embodiment, the first P-type shield region 106 is located in the middle of the real gate 107; the second P-type shield region 101 is located at the upper and lower ends of the shield gate 102.

[0044] Example 4 On the basis of Example 1, the layout implementation of the first P-type shield region 106 and the second P-type shield region 101 at the bottom of the trench can achieve the same effect by setting different layout proportions. Figure 6-2 In this embodiment, the first P-type shield region 106 is located in the middle of the real gate 107; the second P-type shield region 101 covers the entire shield gate 102.

[0045] Example 5 On the basis of Example 1, the layout implementation of the first P-type shield region 106 and the second P-type shield region 101 at the bottom of the trench can achieve the same effect by setting different layout proportions. Figure 6-3 In this embodiment, the first P-type shield region 106 covers the entire real gate 107; the second P-type shield region 101 covers the entire shield gate 102.

[0046] Example 6 On the basis of the above examples, the source P+ type region of this embodiment can be set on the surface, and the same effect can be achieved by adjusting the concentration and depth of the P-type well region 103.

[0047] Embodiment 7 On the basis of the above-mentioned embodiments, this embodiment forms another form of the structure by doping the first P-type shielding region 106 and the second P-type shielding region 101 as the same ion implantation process.

[0048] Embodiment 8 On the basis of Embodiment 2, in this embodiment, the process steps for simultaneously forming the first P-type shielding region and the second P-type shielding region are as follows: the N-type substrate is sequentially grown with an N-type buffer layer 111 and an N-type epitaxial layer 100. This step is a general step.

[0049] Ion implantation forms an N-type buffer region 114, a P-type well region 103, an N+ region source 104, and a P+ region source 107. This step is a general step. Etching forms a shielding gate trench, i.e., the region where the shielding gate conductive medium 102 and the gate dielectric layer 113 are located. Etching forms a real gate trench, i.e., the region where the shielding gate conductive medium 107 and the gate dielectric layer 113 are located. Ion implantation forms the first P-type shielding region 106 and the second P-type shielding region 101. By using this method, the two P-type shielding regions are of the same type, which can reduce the process steps. Oxidation or deposition forms the gate dielectric layer 113. Etching the bottom gate dielectric layer 113 of the shielding gate. Depositing the real gate conductive medium 107 and the shielding gate conductive medium 102. This step can be formed simultaneously or in two steps, which increases the margin that can be controlled. Source contact hole 110, source metal 105, and drain metal 112 are formed.

Claims

1. A trench MOSFET device integrated with a junction controlled diode, the MOSFET device is provided with, from bottom to top, a drain metal layer, an N-type substrate, an N-type buffer layer and a first N-type epitaxial layer; characterized in that: The first N-type epitaxial layer is provided with a P-type well region, the P-type well region is provided with a source contact region, and the bottom of the P-type well region is provided with an N-type buffer region; the N-type buffer region penetrates the source contact region and the P-type well region and extends into a trench MOSFET region of the first N-type epitaxial layer; The trench MOSFET region is further included. The trench MOSFET region includes a first gate, a second gate and a third gate; a first channel is formed between the first gate and the second gate, the first channel is an N-type conductive channel on one side close to the second gate, and the first channel is a junction-controlled diode channel on one side close to the first gate; a second channel is formed between the second gate and the third gate, the second channel is an N-type conductive channel on one side close to the second gate, and the second channel is a junction-controlled diode channel on one side close to the third gate; the N-type conductive channel is located in the P-type well region on the first N-type epitaxial layer; The bottom of the second gate is provided with a first P-type shielding region, the first P-type shielding region covers the interlayer dielectric layer of the second gate and the inner conductive dielectric of the first gate; The surface of the first gate and the third gate is provided with a source contact region; the bottom of the first gate and the third gate is provided with a second P-type shielding region; the inner conductive dielectric of the first gate and the third gate is connected with the second P-type shielding region.

2. The trench MOSFET device integrated with junction controlled diode as claimed in claim 1, wherein: The source contact region includes an N+ region source and a P+ region source; The N+ region source and the P+ region source are provided with a source metal contact hole.

3. The trench MOSFET device integrated with junction controlled diode of claim 1, wherein: At least one N-type conductive channel is arranged in the second gate trench MOSFET region, the N-type conductive channel is located in the P-type well region on the first N-type epitaxial layer, and the P-type well region is provided with a source contact region; the bottom of the P-type well region is provided with an N-type buffer region, the N-type buffer region penetrates the source contact region and the P-type well region and extends into the second gate of the epitaxial layer.

4. The trench MOSFET device of claim 1, wherein: the JBS diode is integrated with the trench MOSFET device. The first P-type shielding region arranged in the second gate trench includes continuous arrangement or interval arrangement.

5. The trench MOSFET device of claim 1, wherein: the JBS diode is integrated with the trench MOSFET device. The second P-type shielding region arranged in the first gate and the third gate includes continuous arrangement or interval arrangement.

6. The trench MOSFET device of claim 1, wherein: the JBS diode is integrated with the trench MOSFET device. The N+ region source is close to the top, the P+ region source extends into the P-type well region and is located at the bottom of the N+ region source.

7. The trench MOSFET device of claim 1, wherein: the JBS diode is integrated with the trench MOSFET device. The depth of the first gate and the third gate trench is greater than the depth of the second gate trench.

8. The trench MOSFET device of claim 1, wherein: the JBS diode is integrated with the trench MOSFET device. The surface of the first gate and the third gate trench is provided with an N-type well region.

9. The trench MOSFET device of claim 1, wherein: the JBS diode is integrated with the trench MOSFET device. The first gate and the third gate are shielding gates, and the second gate is a true gate.

10. A method of fabricating a trench MOSFET device integrated with a junction controlled diode, characterized by, A method for implementing the integrated junction-controlled diode trench MOSFET device of any one of claims 1-9 includes: An N-type substrate is sequentially grown with an N-type buffer layer and an N-type epitaxial layer; Ion implantation forms an N-type buffer region, a P-type well region, an N+ region source and a P+ region source; Etching forms a shielding gate trench, that is, a region where shielding gate conductive dielectric and gate dielectric layer are located; Ion implantation forms a second P-type shielding region; Etching forms a true gate trench, that is, a region where shielding gate conductive dielectric and gate dielectric layer are located; Ion implantation forms a first P-type shielding region; Oxidation or deposition forms a gate dielectric layer; Etching the gate dielectric layer at the bottom of the shielding gate; Depositing true gate conductive dielectric and shielding gate conductive dielectric; Forming a source contact hole, a source metal and a drain metal.

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