Semiconductor device, display device, and electronic apparatus

Abstract

Provided is a semiconductor device that operates stably. The semiconductor device stably maintains the potential of a floating node using a transistor having a long channel length. The transistor includes first to third conductive layers, a semiconductor layer, and an insulating film. The first conductive layer and the second conductive layer each include a region in contact with the top surface of the first insulating layer. The semiconductor layer includes a region in contact with a side surface of an opening formed in the first insulating layer, a top surface of the second insulating layer at the bottom of the opening, a top surface of the first conductive layer, and a top surface of the second conductive layer. The insulating film includes a region in contact with a top surface of the semiconductor layer, a top surface of the first conductive layer, and a top surface of the second conductive layer. The third conductive layer includes a region overlapping at least a portion of the semiconductor layer and in contact with a top surface of the insulating film. In addition, a channel formation region of the transistor is included in the semiconductor layer. In addition, in a display device, the semiconductor device may be provided in a drive circuit having a function of transmitting a signal for displaying an image.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a working method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product, or a composition of matter. Therefore, more specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods can be cited. Background Art

[0003] In recent years, various improvements have been made to display devices used in electronic devices such as XR (Extended Reality or Cross Reality) devices, such as VR (Virtual Reality) and AR (Augmented Reality), mobile phones (e.g., smartphones), tablet computers, and notebook PCs. For example, display devices are being developed to increase screen resolution, improve color reproduction (NTSC ratio), reduce driver circuit size, and reduce power consumption.

[0004] For example, to improve the display quality of display devices, circuits that can reduce characteristic variations of drive transistors in pixels are being actively developed. In particular, Patent Document 1 describes an invention of a pixel circuit including a circuit that can correct the threshold voltage of a drive transistor.

[0005] Another example is a technology of applying a transistor using an oxide semiconductor for a semiconductor thin film as a switching element included in a pixel circuit in a display device.

[0006] Silicon-based semiconductor materials are known as semiconductor thin films that can be used for transistors. Furthermore, oxide semiconductors are attracting attention as materials other than silicon-based semiconductor materials. For example, oxide semiconductors are known to include oxides of single-element metals such as indium oxide and zinc oxide, as well as oxides of multi-element metals. Among multi-element metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly intense.

[0007] Transistors using IGZO in their active layers have been reported to have extremely low off-state current (see Non-Patent Document 1), as well as LSIs (Large Scale Integrations) and display devices that utilize this characteristic (see Non-Patent Documents 2 and 3). Furthermore, Patent Document 2 discloses an invention in which a transistor containing IGZO in its active layer is used in a pixel circuit of a display device. [Prior technical literature] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2017-10000 [Patent Document 2] Japanese Patent Application Publication No. 2010-156963 [Non-patent literature]

[0009] [Non-patent document 1] K. Kato et al., “Japanese Journal of Applied Physics,” 2012, volume 51, pp. 021201-1-021201-7 [Non-Patent Document 2] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers,” 2015, pp. T216-T217 [Non-Patent Document 3] S.Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629 Summary of the Invention Technical problem to be solved by the invention

[0010] A display device displays images through the operation of its driver circuit. This driver circuit is required to display images on the display device, and the quality of the image displayed sometimes depends on the performance of the driver circuit. For example, to display smooth images on the display device, it is necessary to increase the frame rate. To achieve this, the display device preferably has a driver circuit that can cope with this frame rate.

[0011] As one of the circuits included in the driving circuit, a shift register circuit can be cited. A shift register circuit is a circuit that connects multiple holding circuits (e.g., flip-flop circuits) in series, and has the function of transferring information held in a holding circuit to an adjacent holding circuit whenever a pulse signal is input. The frequency of the pulse signal input to the shift register circuit is determined by the frame frequency of the display device. Therefore, when displaying an image with a high frame frequency on the display device, a shift register circuit that can operate stably even when a high-frequency pulse signal is input is required.

[0012] As an example of a holding circuit included in a shift register circuit, consider a structure that holds a potential corresponding to information in a floating node. This holding circuit preferably has a structure that can stably hold the potential held by the floating node when the shift register circuit is operating. For example, when the leakage current (the current flowing between the source and drain when the transistor is in the off state, sometimes referred to as the off-state current) in the transistor used to hold the potential of the floating node is large, the charging of the charge to the floating node becomes slow, resulting in a delay in the operation of the shift register circuit. When the operation of the shift register circuit is delayed, the driving speed of the driving circuit also slows down, thereby reducing the frame frequency of the display device.

[0013] Furthermore, by increasing the channel length of the transistor, the amount of off-state current can be reduced, but the area occupied by the transistor increases, resulting in an increase in the area of ​​the holding circuit.

[0014] One object of one embodiment of the present invention is to provide a semiconductor device that operates stably. Another object of one embodiment of the present invention is to provide a semiconductor device with a high drive speed. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a display device including the above-mentioned semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device including the above-mentioned display device. Another object of one embodiment of the present invention is to provide a novel semiconductor device, novel display device, or novel electronic device.

[0015] Note that the purpose of one embodiment of the present invention is not limited to the purpose listed above. The purpose listed above does not preclude the existence of other purposes. In addition, other purposes may be purposes not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the purposes not mentioned above from the description of the specification or drawings. In addition, one embodiment of the present invention achieves at least one of the purposes listed above and other purposes, but does not necessarily achieve all of the above and other purposes. Means of solving technical problems

[0016] A semiconductor device according to one embodiment of the present invention is a holding circuit that can be provided in a shift register circuit and stably holds information. The holding circuit has a structure for holding the information in a floating node and includes a transistor for stably holding the information, the transistor having a long channel length and a small footprint.

[0017] The transistor includes a conductive layer, which is located on an insulating layer. In addition, the conductive layer and the insulating layer are provided with an opening and are separated into a pair of conductive layers. In addition, the semiconductor layer of the transistor is arranged along the top surfaces of both sides of the pair of conductive layers, the side surfaces of the opening provided in the insulating layer, and the bottom of the opening. As a result, the channel formation region of the transistor becomes U-shaped in the opening, so the channel length can be increased. Therefore, the off-state current of the transistor can be reduced. In addition, since the channel formation region of the transistor is arranged along the side surfaces of the opening provided in the insulating layer and the bottom of the opening, the area occupied by the transistor is smaller than that of a planar transistor.

[0018] The structure of a semiconductor device, a display device, or an electronic device according to one embodiment of the present invention will be described below. (1) One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor.

[0020] The first gate of the first transistor is electrically connected to the first gate of the second transistor. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor, the first gate of the fourth transistor, the first gate of the seventh transistor, and one of the pair of electrodes of the first capacitor. One of the source and drain of the first transistor is electrically connected to one of the source and drain of the fourth transistor and one of the source and drain of the fifth transistor. The other of the source and drain of the fifth transistor is electrically connected to one of the pair of electrodes of the second capacitor and the gate of the sixth transistor. One of the source and drain of the sixth transistor is electrically connected to the other of the pair of electrodes of the second capacitor and one of the source and drain of the seventh transistor.

[0021] The second transistor and the fourth transistor each include a first conductive layer serving as one of a source and a drain, a second conductive layer serving as the other of the source and the drain, a third conductive layer serving as a first gate, a semiconductor layer, and a gate insulating film.

[0022] The first conductive layer and the second conductive layer both include regions in contact with the top surface of the first insulating layer. The semiconductor layer includes regions in contact with the side surfaces of the opening formed in the first insulating layer, the top surface of the second insulating layer at the bottom of the opening, the top surface of the first conductive layer, and the top surface of the second conductive layer. The gate insulating film includes regions in contact with the top surface of the semiconductor layer, the top surface of the first conductive layer, and the top surface of the second conductive layer. The third conductive layer includes a region overlapping with at least a portion of the semiconductor layer and in contact with the top surface of the gate insulating film. Furthermore, each channel formation region of the second transistor and the fourth transistor is included in the semiconductor layer. (2) Furthermore, in (1) above, one embodiment of the present invention may employ a structure in which both the second transistor and the fourth transistor include a fourth conductive layer serving as a second gate. In particular, preferably, the fourth conductive layer includes a region that overlaps with at least a portion of the semiconductor layer and contacts the bottom surface of the second insulating layer. (3) In addition, in the above (2), one embodiment of the present invention may adopt a structure in which the semiconductor layer contains one or more selected from indium, zinc, and element M.

[0025] Note that the element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony. (4) Furthermore, in (3) above, one embodiment of the present invention may employ a structure including an eighth transistor. It is particularly preferred that the gate of the eighth transistor is electrically connected to one of the source and drain of the sixth transistor, the other of the pair of electrodes of the second capacitor, and one of the source and drain of the seventh transistor, and that one of the source and drain of the eighth transistor is electrically connected to one of the source and drain of the first transistor, one of the source and drain of the fourth transistor, and one of the source and drain of the fifth transistor. (5) Another embodiment of the present invention is a display device including a driver circuit and a display device. The driver circuit includes the semiconductor device described in any one of (1) to (4) above, and has a function of transmitting a signal for displaying an image to the display device. (6) In addition, in the above (5), one embodiment of the present invention may adopt a structure in which the display device includes a light-emitting device or a liquid crystal display device. (7) Furthermore, one embodiment of the present invention is an electronic device including the display device described in (6) above and a housing. Effects of the Invention

[0030] By adopting the above structure, the leakage current of the transistor can be reduced, so the potential of the floating node can be stably maintained. As a result, a semiconductor device capable of stably retaining information can be realized.

[0031] By providing this semiconductor device as a holding circuit in a shift register circuit, unintended potential fluctuations at the floating node can be suppressed, thereby reducing information transmission delays between the two holding circuits. This allows for a shift register circuit to be constructed without reducing driving speed.

[0032] According to one embodiment of the present invention, a semiconductor device that operates stably can be provided. According to one embodiment of the present invention, a semiconductor device with a high drive speed can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one embodiment of the present invention, a display device including the semiconductor device can be provided. Furthermore, according to one embodiment of the present invention, an electronic device including the display device can be provided. Furthermore, according to one embodiment of the present invention, a novel semiconductor device, a novel display device, or a novel electronic device can be provided.

[0033] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. In addition, other effects are effects not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description in the specification or drawings. In addition, one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, depending on the circumstances, one embodiment of the present invention may not have the effects listed above. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a circuit diagram showing an example of a semiconductor device. Figure 2A and Figure 2B is a circuit diagram showing an example of a circuit in a semiconductor device. Figure 3A is a schematic plan view showing a transistor in a semiconductor device, Figure 3B and Figure 3C is a schematic cross-sectional view illustrating a transistor in a semiconductor device. Figure 4A is a schematic plan view showing a transistor in a semiconductor device, Figure 4B and Figure 4C is a schematic cross-sectional view illustrating a transistor in a semiconductor device. Figure 5A is a schematic plan view showing a transistor in a semiconductor device, Figure 5B and Figure 5Cis a schematic cross-sectional view illustrating a transistor in a semiconductor device. Figure 6A is a schematic plan view showing a transistor in a semiconductor device, Figure 6B and Figure 6C is a schematic cross-sectional view illustrating a transistor in a semiconductor device. Figure 7A is a schematic plan view showing a transistor in a semiconductor device, Figure 7B and Figure 7C is a schematic cross-sectional view illustrating a transistor in a semiconductor device. Figures 8A to 8G is a circuit diagram showing an example of a circuit in a semiconductor device. Figure 9 is a circuit diagram showing an example of a semiconductor device. Figure 10 is a block diagram showing an example of a display device. Figure 11A and Figure 11B is a block diagram showing an example of a driving circuit. Figure 12 This is a circuit diagram showing an example of a semiconductor device in a driving circuit. Figure 13 This is a circuit diagram showing an example of a semiconductor device in a driving circuit. Figure 14 This is a circuit diagram showing an example of a semiconductor device in a driving circuit. Figure 15 This is a circuit diagram showing an example of a semiconductor device in a driving circuit. Figure 16 1 is a timing chart showing an operation example of a circuit in the driving circuit. Figure 17 Is a block diagram showing an example of a driving circuit. Figure 18 is a timing chart showing an example of the operation of the driving circuit. Figure 19 This is a circuit diagram showing an example of a semiconductor device in a driving circuit. Figure 20 This is a circuit diagram showing an example of a semiconductor device in a driving circuit. Figure 21 is a block diagram showing an example of a driving circuit. Figure 22 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 23 This is a circuit diagram showing an example of a semiconductor device in a driving circuit. Figure 24: is a circuit diagram showing an example of a circuit in a driving circuit. Figure 25 This is a circuit diagram showing an example of a circuit in a driving circuit. Figure 26 is a timing chart showing an example of the operation of the driving circuit. Figure 27 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 28 is a layout diagram showing an example of an amplifier circuit. 29A to 29D is a circuit diagram showing a structural example of a pixel circuit. Figure 30A and Figure 30B is a circuit diagram showing a structural example of a pixel circuit. Figure 31A and Figure 31B is a circuit diagram showing a structural example of a pixel circuit. Figure 32 is a circuit diagram showing a structural example of a pixel circuit. Figure 33 is a circuit diagram showing a structural example of a pixel circuit. Figure 34A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 34B to 34D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 35A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 35B to 35D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 36A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 36B to 36D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 37A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 37B to 37D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 38A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 38B to 38D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 39A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 39B to 39D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 40A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 40B to 40D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 41A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 41B and Figure 41C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 42A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 42B to 42D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 43A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 43B to 43D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 44A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 44B to 44D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 45A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 45B to 45D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 46A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figures 46B to 46D 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 47A and Figure 47B It is a perspective schematic diagram showing a structural example of a display device. Figure 48 is a block diagram showing a structural example of a display device. Figure 49 is a schematic cross-sectional view illustrating a structural example of a display device. Figures 50A to 50C is a schematic cross-sectional view illustrating a structural example of a display device. Figure 51 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 52 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 53 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 54 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 55 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 56 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 57 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 58 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 59 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 60A and Figure 60B is a diagram showing a structural example of a display module. Figures 61A to 61I It is a perspective view showing an example of an electronic device. Figure 62A is a perspective view illustrating an example of the structure of a storage device, Figure 62B This is a block diagram illustrating a structural example of a semiconductor device. Figure 63 A is a block diagram illustrating a structural example of a storage device. Figure 64A and Figure 64B is a circuit diagram showing a structural example of a memory cell in a memory device. Figure 65A and Figure 65B is a diagram showing an example of an electronic device, Figures 65C to 65E This is a diagram showing an example of a mainframe computer. Figure 66 This is a diagram showing an example of space equipment. Figure 67 FIG. 1 is a diagram illustrating an example of a storage system that can be used in a data center. Figure 68 This is a block diagram illustrating a configuration example of an imaging device. Figure 69 This is a circuit diagram showing a configuration example of an imaging pixel circuit in an imaging device. Modes for Carrying Out the Invention

[0035] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (for example, a transistor, a diode, a photodiode), and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. As an example of a semiconductor device, an integrated circuit can be cited. In addition, as an example of a semiconductor device, a chip having an integrated circuit can also be cited. In addition, as an example of a semiconductor device, an electronic component in which a chip is housed in a package can also be cited. In addition, for example, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device are sometimes themselves semiconductor devices, or sometimes include a semiconductor device.

[0036] In this specification, the phrase "X and Y are connected" indicates that the following are disclosed: X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, connections other than those shown in the drawings or text are not limited to those specified in the specification. Connections other than those shown in the drawings or text are also considered to be those described in the drawings or text. X and Y are each an object (e.g., a device, element, circuit, wiring, electrode, terminal, conductive film, or layer).

[0037] As an example of electrically connecting X and Y, one or more elements capable of electrically connecting X and Y (e.g., switches, transistors, capacitors, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) may be connected between X and Y. Furthermore, a switch has the function of controlling whether to turn it on or off. In other words, whether current flows is controlled by placing the switch in a conductive state (on) or a non-conductive state (off).

[0038] Furthermore, if both X and Y have components and power lines (e.g., VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or wiring that applies a desired potential) between them, then X and Y cannot be said to be electrically connected. Furthermore, if only a power line is provided between X and Y, and no other components are between them, then X and Y can be said to be directly connected. Therefore, even if only a power line is provided between X and Y, it can be said that "X and Y are electrically connected." However, if both X and Y have components and power lines between them, it can be said that X is electrically connected to the power line (through the components) and that Y is electrically connected to the power line, rather than that X and Y are electrically connected. Furthermore, if the gate and source of a transistor are between X and Y, then X and Y cannot be said to be electrically connected. Furthermore, if the gate and drain of a transistor are between X and Y, then X and Y cannot be said to be electrically connected. That is, with respect to a transistor, if the drain and source of the transistor are between X and Y, then X and Y can be said to be electrically connected. Furthermore, when a capacitor is placed between X and Y, it may be said that X and Y are electrically connected, but it may not be said that X and Y are electrically connected. For example, in the configuration of a digital circuit or a logic circuit, when a capacitor is placed between X and Y, it may not be said that X and Y are electrically connected. On the other hand, in the configuration of an analog circuit, for example, when a capacitor is placed between X and Y, it may be said that X and Y are electrically connected.

[0039] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (e.g., logic circuits (e.g., inverters, NAND circuits, NOR circuits), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as boost circuits and buck circuits, and level shift circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (e.g., circuits capable of increasing signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits), signal generation circuits, storage circuits, control circuits, etc.) may be connected between X and Y. Note that, for example, even if other circuits are interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0040] Alternatively, for example, it can be expressed as “X, Y, the source of the transistor (sometimes referred to as one of the first and second terminals), and the drain of the transistor (sometimes referred to as the other of the first and second terminals) are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence.” Alternatively, it can be expressed as “the source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence.” Alternatively, it can be expressed as “X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are connected to each other in sequence.” By specifying the connection order in the circuit structure using the same notation as these examples, the source and drain of the transistor can be distinguished, thereby determining the technical scope. Note that this notation is only an example and is not limited to the above-mentioned notation. Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0041] Furthermore, even when independent components are electrically connected on a circuit diagram, a single component may sometimes perform the functions of multiple components. For example, when a portion of a wiring serves as an electrode, a single conductive film may perform both wiring and electrode functions. Therefore, the term "electrically connected" in this specification also encompasses situations where a single conductive film performs the functions of multiple components.

[0042] In this specification, etc., a "resistor" may be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, etc., a "resistor" includes a wiring having a resistance value, a transistor, a diode, or a coil through which current flows between a source and a drain. Therefore, a "resistor" may sometimes be referred to as a "resistor," a "load," or a "region having a resistance value." In contrast, a "resistor," a "load," or a "region having a resistance value" may sometimes be referred to as a "resistor." As a resistance value, for example, it is preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0043] In this specification, etc., a "capacitor" may be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of wiring having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, "capacitor", "parasitic capacitance" or "gate capacitance" etc. may sometimes be referred to as "capacitor". In contrast, "capacitor" may sometimes be referred to as "capacitor", "parasitic capacitance" or "gate capacitance". In addition, a "capacitor" (including "capacitors" with three or more terminals) has a structure including an insulator and a pair of conductors sandwiching the insulator. Thus, the "pair of conductors" of the "capacitor" may be referred to as a "pair of electrodes", "a pair of conductive regions", "a pair of regions" or "a pair of terminals". In addition, "one of a pair of terminals" and "the other of a pair of terminals" are sometimes referred to as the first terminal and the second terminal, respectively. The electrostatic capacitance value may be, for example, greater than 0.05fF and less than 10pF. In addition, for example, it may also be greater than 1pF and less than 10μF.

[0044] In this specification, etc., a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (e.g., n-channel type, p-channel type) and the level of the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as the source and the other as the drain. Therefore, in this specification, etc., the source and drain can be interchanged. In this specification, etc., when describing the connection relationship of the transistor, the expressions "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. In addition, depending on the structure of the transistor, a back gate is sometimes included in addition to the above three terminals. In this case, in this specification, etc., one of the gate and back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and back gate of the transistor is sometimes referred to as the second gate. Moreover, in the same transistor, "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate may be referred to as a first gate, a second gate, a third gate, etc. in this specification and the like.

[0045] For example, in this specification, etc., a multi-gate structure transistor having two or more gate electrodes can be used as an example of a transistor. When a multi-gate structure is adopted, since the channel forming regions are connected in series, a structure in which multiple transistors are connected in series is formed. Therefore, by adopting a multi-gate structure, the off-state current can be reduced and the voltage resistance of the transistor can be improved (improving reliability). Alternatively, by utilizing a multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the change in the current between the drain and the source is not too large, so that a voltage-current characteristic with a flat tilt angle can be obtained. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with an extremely high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0046] Furthermore, a circuit diagram showing a circuit element sometimes includes a case where the circuit element includes a plurality of circuit elements. For example, a circuit diagram showing a resistor includes a case where two or more resistors are electrically connected in series. Furthermore, for example, a circuit diagram showing a capacitor includes a case where two or more capacitors are electrically connected in parallel. Furthermore, for example, a circuit diagram showing a transistor includes a case where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Similarly, for example, a circuit diagram showing a switch includes a case where the switch includes two or more transistors, the two or more transistors being electrically connected in series or in parallel and the gates of each transistor being electrically connected to each other.

[0047] In this specification, etc., a node may be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region depending on the circuit structure or device structure. In addition, terminals, wiring, etc. may also be referred to as nodes.

[0048] In this specification, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, when the reference potential is ground potential (e.g., ground potential), "voltage" may be referred to as "potential." Ground potential does not necessarily mean 0V. Furthermore, potential is relative; changes in the reference potential also cause changes in the potential applied to wiring, applied to circuits, and output from circuits.

[0049] In this specification and other documents, the terms "high-level potential" and "low-level potential" do not necessarily refer to specific potentials. For example, even if two wirings are described as "wirings for supplying a high-level potential," the high-level potentials applied to the two wirings may be different. Similarly, even if two wirings are described as "wirings for supplying a low-level potential," the low-level potentials applied to the two wirings may be different.

[0050] In addition, "current" refers to the phenomenon of charge movement (conduction). For example, the description of "conduction occurs in a positively charged body" can be replaced by the description of "conduction occurs in a negatively charged body in the opposite direction". Therefore, in this specification, etc., unless otherwise specified, "current" refers to the phenomenon of charge movement (conduction) when carriers move. Here, as carriers, for example, electrons, holes, anions, cations, complex ions, etc. can be cited. The carriers are different depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, and vacuum). In addition, the "direction of current" in wiring, etc. is the direction in which positively charged carriers move, and is recorded as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is recorded as a negative current amount. Therefore, in this specification, etc., unless otherwise specified, regarding the positive and negative signs of current (or the direction of current), the description of "current flows from element A to element B" can be replaced by the description of "current flows from element B to element A". In addition, the description of "current is input to element A" can be replaced by the description of "current is output from element A".

[0051] Furthermore, in this specification, etc., ordinal numbers such as "first," "second," and "third" are added to avoid confusion between components. Therefore, these ordinal numbers do not limit the number of components. Furthermore, these ordinal numbers do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification, etc., may be referred to as "second" in another embodiment or claim. Furthermore, for example, in this specification, etc., a component referred to as "first" in one embodiment may be omitted in another embodiment or claim.

[0052] In this specification, etc., for the sake of convenience, words and phrases such as "upper" and "lower" that represent configurations are sometimes used to describe the positional relationship of components with reference to the accompanying drawings. In addition, the positional relationship of the components is appropriately changed depending on the direction in which each structure is described. Therefore, the wording is not limited to the words and phrases described in the specification, etc., and words and phrases can be appropriately replaced according to the situation. For example, in the expression "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can also be referred to as "an insulator located below the conductor".

[0053] In addition, the words "above" or "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, if it is an expression "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B above insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B below insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A below insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included.

[0054] In addition, in this specification, etc., words such as "row" and "column" are sometimes used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships of the components vary depending on the direction in which each structure is described. Therefore, the terms are not limited to those described in the specification, etc., and may be replaced as appropriate depending on the situation. For example, when referring to the "row direction," the term "column direction" may sometimes be referred to as "row direction" by rotating the illustrated drawing 90 degrees.

[0055] In this specification, etc., the terms "film" and "layer" may be interchanged depending on the situation. For example, "conductive layer" may be interchanged with "conductive film." Also, "insulating film" may be interchanged with "insulating layer." Furthermore, depending on the situation or circumstances, other terms may be used in place of "film" and "layer." For example, "conductive layer" or "conductive film" may be interchanged with "conductive body." Also, for example, "insulating layer" or "insulating film" may be interchanged with "insulator."

[0056] Note that in this specification, etc., the words "electrode", "wiring" and "terminal" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, the words "electrode" or "wiring" also include the case where a plurality of "electrodes" or "wirings" are formed into one. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or "electrode", and vice versa. Furthermore, the words "terminal" also include the case where one or more selected from "electrode", "wiring" and "terminal" are formed into one. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", for example, a "terminal" can be a part of a "wiring" or "electrode". In addition, the words "electrode", "wiring" or "terminal" are sometimes replaced with words such as "region" depending on the circumstances.

[0057] In this specification, etc., depending on the situation or circumstances, the words "wiring", "signal line" or "power line" can be interchanged. For example, "wiring" can sometimes be replaced with "signal line". In addition, for example, "wiring" can sometimes be replaced with "power line". Vice versa, "signal line" or "power line" can sometimes be replaced with "wiring". In addition, "power line" can sometimes be replaced with "signal line". Vice versa, "signal line" can sometimes be replaced with "power line". In addition, depending on the situation or circumstances, "potential" applied to the wiring can sometimes be replaced with "signal". In addition, "signal" can sometimes be replaced with "potential".

[0058] In addition, in this specification, etc., the working method of the semiconductor device is sometimes described with reference to a timing diagram. In addition, the timing diagram used in this specification, etc. shows an ideal working example, and is not limited to the period shown in the timing diagram, the size of the signal (for example, potential or current), and the timing unless otherwise specified. In the timing diagram of this specification, etc., the size and timing of the signal (for example, potential or current) input to each wiring (including nodes) in the timing diagram can be changed according to the situation. For example, even if two periods of equal intervals are shown in the timing diagram, the lengths of the two periods are sometimes different. In addition, for example, even if one of the two periods is long and the other is short, the lengths of the two periods may sometimes be the same, or one of the two periods may sometimes be short and the other may be long. In addition, in order to clearly show the timing diagram, for example, two or more overlapping signals are sometimes intentionally staggered and illustrated.

[0059] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when the metal oxide can constitute the channel formation region of a transistor having at least one of an amplification effect, a rectification effect and a switching effect, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor). In addition, an OS transistor can be referred to as a transistor comprising a metal oxide or an oxide semiconductor.

[0060] In this specification and other documents, metal oxides containing nitrogen may also be referred to as metal oxides (metal oxides). In addition, metal oxides containing nitrogen may also be referred to as metal oxynitrides (metal oxynitrides).

[0061] In addition, in this specification, etc., impurities of a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are included, for example, one or more of the following may occur: an increase in the defect state density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, and in particular, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0062] In this specification, etc., a switch refers to an element that has a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element that has a function of selecting and switching a current path. Therefore, a switch sometimes includes two or more terminals through which current flows in addition to a control terminal. As an example of a switch, an electric switch or a mechanical switch can be used. In other words, a switch is not limited to a specific element as long as it can control current.

[0063] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM: Metal Insulator Metal) diodes, metal-insulator-semiconductor (MIS: Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these elements. When a transistor is used as a switch, the "on state" of the transistor refers to, for example, a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited or a state in which current can flow between the source electrode and the drain electrode. In addition, the "non-conducting state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When a transistor is used only as a switch, there is no particular restriction on the polarity (conductivity type) of the transistor.

[0064] An example of a mechanical switch is a switch using MEMS (Micro Electro Mechanical System) technology, which has a mechanically movable electrode and operates by controlling conduction and non-conduction by moving the electrode.

[0065] In this specification, devices manufactured using a metal mask or an FMM (Fine Metal Mask) are sometimes referred to as devices having an MM (Metal Mask) structure. In this specification, devices manufactured without using a metal mask or FMM are sometimes referred to as devices having an MML (Metal Mask Less) structure.

[0066] Note that in this specification and other documents, a structure in which light-emitting layers are formed or applied separately in light-emitting devices of each color (here, blue (B), green (G), and red (R)) is sometimes referred to as an SBS (Side-by-Side) structure. Furthermore, in this specification and other documents, a light-emitting device that can emit white light is sometimes referred to as a white light-emitting device. White light-emitting devices, when combined with coloring layers (e.g., color filters), can realize a display device capable of full-color display.

[0067] In addition, light-emitting devices can be roughly divided into single structures and series structures. A single-structure device preferably has the following structure: a light-emitting unit is included between a pair of electrodes, and the light-emitting unit includes one or more light-emitting layers. In the case of using two light-emitting layers to obtain white light, the light-emitting layers can be selected in such a way that the light-emitting colors of the two light-emitting layers are in a complementary color relationship. For example, by making the light-emitting colors of the first light-emitting layer and the light-emitting colors of the second light-emitting layer complementary colors, a structure in which the light-emitting device as a whole emits white light can be obtained. In addition, in the case of using three or more light-emitting layers to obtain white light, the light-emitting colors of the three or more light-emitting layers are combined to obtain a structure in which the light-emitting device as a whole emits white light.

[0068] Tandem devices preferably have a structure comprising two or more light-emitting units between a pair of electrodes, each unit comprising one or more light-emitting layers. To achieve white light, a structure can be employed in which the light emitted from the light-emitting layers of multiple light-emitting units is combined to produce white light. Note that the structure for achieving white light is the same as that for a single device. Furthermore, in tandem devices, an intermediate layer, such as a charge generation layer, is preferably provided between the multiple light-emitting units.

[0069] Furthermore, when comparing the aforementioned white light-emitting devices (single or tandem) with SBS-structured devices, the SBS-structured devices can be made to consume less power than the white light-emitting devices. For devices that require lower power consumption, SBS-structured devices are preferred. Furthermore, the manufacturing process for white light-emitting devices is simpler than that for SBS-structured devices, which can reduce manufacturing costs or increase manufacturing yields, making them preferable.

[0070] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0071] In this specification, the structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one mode of the present invention. In addition, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0072] In addition, the content (or part thereof) described in a certain embodiment may be applied / combined / replaced with other content (or part thereof) described in that embodiment and at least one of the content (or part thereof) described in one or more other embodiments.

[0073] Note that the contents described in the embodiments refer to the contents described in the various drawings in each embodiment or the contents described in the text described in the specification.

[0074] In addition, more figures can be formed by combining a figure (or part thereof) shown in a certain embodiment with other parts of the figure, other figures (or parts thereof) shown in the embodiment, and at least one figure (or part thereof) shown in one or more other embodiments.

[0075] The embodiments described in this specification are described with reference to the accompanying drawings. However, a person skilled in the art can easily understand the fact that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to represent the same parts or parts with the same functions, and repeated descriptions are omitted. In stereograms, etc., for the sake of clarity, the illustration of some constituent elements is sometimes omitted.

[0076] In this specification, etc., when the same reference numeral is used for multiple elements and it is necessary to distinguish them, the reference numeral may be appended with an identifying symbol such as "_1," "[n]," or "[m,n]." Furthermore, in the drawings, etc., when a reference numeral is appended with an identifying symbol such as "_1," "[n]," or "[m,n]," the identifying symbol may not be appended if it is not necessary to distinguish them in this specification, etc.

[0077] In the drawings of this specification, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate idealized examples and are not limited to the shapes or numerical values ​​shown.

[0078] (Implementation 1) In this embodiment, a holding circuit of a semiconductor device which is one embodiment of the present invention is described.

[0079] <Structural Example 1 of Holding Circuit> Figure 1 The illustrated circuit MDV is an example of a holding circuit of a semiconductor device according to one embodiment of the present invention, and includes a terminal IT, a terminal CLK1 , a terminal CLK2 , a terminal OT, a circuit LGC, and a circuit OPC.

[0080] The terminal IT, the terminal CLK1 , and the terminal CLK2 all function as input terminals in the circuit MDV, and the terminal OT functions as an output terminal in the circuit MDV.

[0081] The terminal IT functions as a terminal for receiving, for example, a 1-bit signal held in the circuit MDV from outside the circuit MDV. Therefore, the signal may be, for example, a high-level potential or a low-level potential.

[0082] The terminal CLK1 functions as a terminal for receiving a clock signal for operating the circuit MDV, for example.

[0083] Terminal CLK2 functions as a terminal for receiving a clock signal for operating circuit MDV, for example. Note that the clock signal input to terminal CLK2 is preferably different from the clock signal input to terminal CLK1. Note that, depending on the circumstances, the clock signals input to terminals CLK1 and CLK2 may be the same. Furthermore, in this case, terminals CLK1 and CLK2 may be combined into a single terminal.

[0084] The terminal OT functions as a terminal for outputting a 1-bit signal held in the circuit MDV.

[0085] Circuit MDV can be functionally divided into circuit LGC and circuit OPC. Circuit LGC, for example, functions as a logic circuit for processing signals input to terminal IT, while circuit OPC, for example, functions as a logic circuit for generating signals output to terminal OT. Furthermore, one or both of circuits LGC and OPC may be analog circuits rather than logic circuits.

[0086] In addition, if Figure 1 As shown, circuit LGC includes, for example, transistors MN1 to MN4 and capacitor C5. Circuit OPC includes, for example, transistor MN12 and circuit BSPR. Circuit BSPR includes circuit BB, transistor MN11, and capacitor C1. Furthermore, for example, circuit BSPR includes terminal Ti functioning as an input terminal and terminal To functioning as an output terminal. Furthermore, for example, circuit BB includes terminal Bi functioning as an input terminal and terminal Bo functioning as an output terminal.

[0087] also, Figure 1 The difference between the circuit LGC and the circuit OPC shown in the figure, which includes the transistors MN1 to MN4, the transistor MN11, the transistor MN12, the capacitor C1, and the capacitor C5, is only an example, and there is no particular limitation on the structures of the circuit LGC and the circuit OPC. Figure 1 In the embodiment, capacitor C5 in circuit LGC may also be included in circuit OPC.

[0088] Transistors MN1 to MN4, transistor MN11, and transistor MN12 preferably use OS transistors, for example. In particular, as the metal oxide contained in the channel formation region of the OS transistor, for example, an In-M-Zn oxide containing indium, element M, and zinc is preferably used (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony). In addition, transistors MN1 to MN4, transistor MN11, and transistor MN12 may also use transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors). In addition, as silicon, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon can be used. In addition, as transistors other than OS transistors and Si transistors, for example, transistors including germanium (Ge) in the channel formation region, transistors including compound semiconductors such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) or silicon germanium (SiGe) in the channel formation region, transistors including carbon nanotubes in the channel formation region, or transistors including organic semiconductors in the channel formation region can be used.

[0089] In addition, Figure 1 In the embodiment, the transistors MN1 to MN4, the transistor MN11, and the transistor MN12 are all n-channel transistors. However, depending on circumstances, at least one selected from the transistors MN1 to MN4, the transistor MN11, and the transistor MN12 may be a p-channel transistor.

[0090] Note that, except for the description of the transistor Figure 1 In addition, the same applies to transistors described in other parts of the specification or transistors shown in other drawings.

[0091] Terminal IT is electrically connected to the gate of transistor MN1 and the gate of transistor MN2. A first terminal of transistor MN1 is electrically connected to wiring VDE1, and a second terminal of transistor MN1 is electrically connected to a first terminal of transistor MN4 and terminal Ti of circuit BSPR. Terminal CLK2 is electrically connected to the gate of transistor MN3, a first terminal of transistor MN3 is electrically connected to wiring VDE2, and a second terminal of transistor MN3 is electrically connected to the gate of transistor MN4, the first terminal of transistor MN2, the gate of transistor MN12, and the first terminal of capacitor C5. A second terminal of capacitor C5 is electrically connected to wiring VSE1, a second terminal of transistor MN4 is electrically connected to wiring VSE2, and a second terminal of transistor MN2 is electrically connected to wiring VSE3.

[0092] Note that in Figure 1 , the portion where the second terminal of transistor MN1, the first terminal of transistor MN4, and the terminal Ti of circuit BSPR are electrically connected is recorded as node N1, and the portion where the second terminal of transistor MN3, the gate of transistor MN4, the first terminal of transistor MN2, the gate of transistor MN12, and the first terminal of capacitor C5 are electrically connected is recorded as node N2.

[0093] Terminal Ti of circuit BSPR is electrically connected to terminal Bi of circuit BB. Terminal Bo of circuit BB is electrically connected to the gate of transistor MN11 and the first terminal of capacitor C1. The first terminal of transistor MN11 is electrically connected to terminal CLK1. The second terminal of transistor MN11 is electrically connected to the second terminal of capacitor C1 and terminal To of circuit BSPR.

[0094] The terminal To of the circuit BSPR is electrically connected to the terminal OT and the first terminal of the transistor MN12. In addition, the second terminal of the transistor MN12 is electrically connected to the wiring VSE4.

[0095] Wiring VDE1 and wiring VDE2 both function as wiring for supplying a fixed potential. This fixed potential can be, for example, a high-level potential. Wiring VDE1 and wiring VDE2 can supply equal or unequal fixed potentials. Furthermore, for example, when wiring VDE1 and wiring VDE2 supply equal fixed potentials, wiring VDE1 and wiring VDE2 can be the same wiring.

[0096] In addition, one or both of the wiring VDE1 and the wiring VDE2 may be a wiring that supplies not a fixed potential but a variable potential (sometimes referred to as a pulse voltage, a pulse potential, a pulse signal, etc.).

[0097] Each of the wirings VSE1 to VSE4 functions as a wiring supplying a fixed potential. This fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. The wirings VSE1 to VSE4 can supply fixed potentials that are equal to each other, or they can supply fixed potentials that are unequal to each other. Furthermore, two or more wirings among the wirings VSE1 to VSE4 can supply fixed potentials that are equal to each other, and the remaining wirings can supply potentials that are different from the fixed potential. Furthermore, two or more wirings among the wirings VSE1 to VSE4 that supply fixed potentials that are equal to each other can be the same wiring. For example, when the wirings VSE1 and VSE2 supply fixed potentials that are equal to each other, the wirings VSE1 and VSE2 can be the same wiring.

[0098] In addition, one or more selected from the wirings VSE1 to VSE4 may have a function of a wiring that supplies a variable potential instead of a fixed potential.

[0099] Here, it is assumed that a high-level potential is input to the wirings VDE1 and VDE2 and a low-level potential is input to the wirings VSE1 to VSE3. Figure 1 The operation of the circuit LGC is described below.

[0100] exist Figure 1 In circuit LGC, for example, when a low-level potential is supplied to terminal IT and a high-level potential is supplied to terminal CLK2, transistor MN1 is turned off and transistor MN4 is turned on, resulting in the potential at node N1 being the low-level potential supplied by wiring VSE2. Furthermore, transistor MN2 is turned off and transistor MN3 is turned on, resulting in the potential at node N2 being the high-level potential supplied by wiring VDE2 minus the threshold voltage of transistor MN3. Furthermore, a potential obtained by subtracting the threshold voltage of transistor MN3 from the high-level potential supplied by wiring VDE2 is input to the gate of transistor MN4, resulting in the potential at node N1 being slightly higher than the low-level potential supplied by wiring VSE2.

[0101] Next, for example, when the high-level potential supplied to terminal CLK2 changes to a low-level potential, transistor MN3 turns off, node N2 becomes floating, and a potential obtained by subtracting the threshold voltage of transistor MN3 from the high-level potential supplied from wiring VDE2 is held in the first terminal of capacitor C5. Furthermore, transistor MN4 remains on, so the potential of node N1 remains unchanged from the low-level potential (or a potential slightly higher than the low-level potential) supplied from wiring VSE1.

[0102] When a high-level potential is supplied to terminal IT and a low-level potential is supplied to terminal CLK2, transistor MN2 is turned on and transistor MN3 is turned off, resulting in the potential at node N2 being a low-level potential supplied by wiring VSE3. Furthermore, transistor MN1 is turned on and transistor MN4 is turned off, resulting in the potential at node N1 being a potential obtained by subtracting the threshold voltage of transistor MN1 from the high-level potential supplied by wiring VDE1.

[0103] Next, for example, when the high-level potential supplied to terminal IT changes to a low-level potential, transistor MN1 turns off, causing node N1 to float. Ideally, the potential of node N1 remains unchanged at a potential equal to the high-level potential supplied from wiring VDE1 minus the threshold voltage of transistor MN1. Furthermore, transistor MN2 also turns off, causing node N2 to float, and the low-level potential supplied from wiring VSE3 is retained at the first terminal of capacitor C5.

[0104] In short, when a low-level potential is input to terminal CLK2 and a high-level potential is input to terminal IT, ideally, the potential of node N1 becomes a high-level potential, and the potential of node N2 becomes a low-level potential. Furthermore, when a high-level potential is input to terminal CLK2 and a low-level potential is input to terminal IT, ideally, the potential of node N1 becomes a low-level potential, and the potential of node N2 becomes a high-level potential. Furthermore, when a low-level potential is input to terminal IT and the potential of terminal CLK2 changes from a high-level potential to a low-level potential, the potentials of nodes N1 and N2 do not change before and after the potential change of terminal CLK2. Similarly, when a low-level potential is input to terminal CLK2 and the potential of terminal IT changes from a high-level potential to a low-level potential, the potentials of nodes N1 and N2 do not change before and after the potential change of terminal IT.

[0105] Next, assuming that a low level potential is input to the wiring VSE4, Figure 1 The circuit shown explains the operation of OPC.

[0106] Figure 1The circuit BSPR shown is an example of an amplifier circuit and includes a circuit BB, a transistor MN11, and a capacitor C1. As described above, the circuit BB includes, for example, a terminal Bi functioning as an input terminal and a terminal Bo functioning as an output terminal.

[0107] The transistor MN11 is a normally closed transistor, and the threshold voltage of the transistor MN11 is V th_MN11 In addition, the threshold voltage V th_MN11 To meet V High -V Low >V th_MN11 Note that V High is a high level potential, V Low It is a low level potential.

[0108] In this specification, etc., the term "normally off" refers to a state in which no current flows through the transistor when no potential is applied to the gate, when the gate is grounded, or when the gate-source potential is 0 V. Note that the term "normally off" for an OS transistor refers to a state in which the current flowing through the transistor per channel width of 1 μm is 1×10 -20 Below A, at 85℃, it is 1×10 -18 A or less, or 1×10 -16 A or less. On the other hand, normally-on refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate. Alternatively, normally-on refers to a state in which a channel exists and current flows through the transistor even when the gate-source voltage is 0V.

[0109] Note that in this embodiment, a portion where the terminal Bo of the circuit BB, the gate of the transistor MN11, and the first terminal of the capacitor C1 are electrically connected is referred to as a node N.

[0110] Circuit BB has, for example, a function of floating node N. Therefore, circuit BB may include, for example, a switching element. In addition, circuit BB has a function of outputting a potential corresponding to the potential input to terminal Bi to terminal Bo. For example, circuit BB may have a function of outputting a potential corresponding to the potential input to terminal Bi to terminal Bo when a high-level potential V is supplied to terminal Bi. High When the potential V is output to the terminal Bo Mid Note that V Mid Lower than the high level potential V High and higher than the low level potential V Low In addition, V Mid To meet V Mid -V Low >V th_MN11 voltage.

[0111] Here, assuming Figure 1 The potential of the node N of the BSPR circuit becomes lower than the high-level potential V High The potential V Mid . In addition, it is assumed that the node N is not in a floating state at this time. In addition, the potentials of the nodes N1 and N2 are low level potentials. Therefore, the transistor MN12 is turned off. In addition, it is assumed that the low level potential V is supplied from the terminal CLK1 to the first terminal of the transistor MN11. Low .

[0112] At this time, the gate-source voltage of the transistor MN11 (at this time, the gate-first terminal voltage) becomes V Mid -V Low In addition, the V Mid -V Low To meet V Mid -V Low >V th_MN11 Therefore, the transistor MN11 is turned on. Therefore, in the circuit MDV, the potential of the terminal OT becomes the low-level potential V input from the terminal CLK1 through the transistor MN11. Low .

[0113] Next, it is assumed that the low-level potential V is supplied from the terminal CLK1 to the first terminal of the transistor MN11. Low becomes a high level potential V High In addition, it is assumed that the node N is made to float using the circuit BB. At this time, the gate-source voltage of the transistor MN11 (at this time, the gate-second terminal voltage) is V Mid -V Low , whereby the transistor MN11 turns on. Therefore, current flows from the terminal CLK1 to the terminal OT through the transistor MN11, and the potential of the terminal OT changes from V Low In addition, the node N is in a floating state, so through the capacitive coupling of the capacitor Ca, the potential of the node N also increases from V to Mid As a result, the gate-source voltage of the transistor MN11 is maintained by the capacitor C1, and the potential of the terminal OT increases to V High In addition, ideally, the potential of the node N is V Mid +V High -V Low .

[0114] Thus, in the circuit BSPR, a voltage lower than the high level potential V is input to the node N. Mid The potential of the terminal CLK1 changes from the low level potential V Low becomes a high level potential V High When the potential of terminal OT becomes VHigh In this specification and other documents, the case where the gate potential is increased as the potential of the first terminal or the second terminal of the transistor increases by utilizing capacitive coupling as described above is referred to as bootstrapping.

[0115] exist Figure 1 In the circuit BSPR, the potential of the first terminal of the transistor MN11 is changed from the low level potential V LOW becomes a high level potential V High And the node N is supplied with a potential V mid When the potential of node N rises to V Mid +V High -V Low , the potential of the terminal To output to the circuit BSPR becomes V High .

[0116] also, Figure 1 The transistor MN11 shown may also include a back gate, for example. Specifically, for example, Figure 1 The transistor MN11 of the BSPR circuit may also be a transistor having a multi-gate structure including gates above and below the channel. Figure 2A The transistor MN11 shown, for example, adopts an n-channel transistor with a multi-gate structure including gates above and below the channel. The transistor MN11 includes a second gate in addition to the first gate. Note that in this specification, etc., for convenience, for example, the first gate is recorded as the gate (sometimes recorded as the front gate) and the second gate is recorded as the back gate to distinguish them. In addition, in this specification, etc., the first gate and the second gate can be interchanged, so the "gate" can be recorded as the "back gate". Similarly, the "back gate" can be recorded as the "gate". Specifically, the connection structure of "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be replaced with the connection structure of "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring".

[0117] Although Figure 2A The transistor MN11 shown in the figure has a back gate, but the connection structure of the back gate is not shown. Note that the electrical connection object of the back gate can be determined during the design. For example, in a transistor including a back gate, the gate and the back gate can be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and the back gate of the transistor MN11 can also be electrically connected. In addition, for example, in a transistor including a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring for electrically connecting the back gate of the transistor to an external circuit can be provided, and a potential can be supplied to the back gate of the transistor through the external circuit.

[0118] Note that while the transistor MN11 described above may also include a back gate, transistors described elsewhere in the specification or shown in other figures may also include back gates. For example, transistors MN1 to MN4 in circuit LGC and transistor MN12 in circuit OPC may also include back gates.

[0119] In addition, when the gate capacitance between the gate of the transistor MN11 and the channel formation region (which may include one or both of the first terminal and the second terminal depending on the situation) is large, as shown in FIG. Figure 2B As shown in FIG. 1 , the circuit BSPR may have a structure without the capacitor C1 . In this case, the circuit area of ​​the circuit BSPR can be reduced.

[0120] In addition, in order to lower the potential V of the terminal OT which is increased by the bootstrapping of the circuit BSPR High For example, if the potential of terminal Bi decreases due to some reason, the potential of terminal Bo may also decrease through circuit BB, and as a result, the potential of node N may also decrease.

[0121] One of the reasons for the potential drop at terminal Bi is leakage current flowing when the transistor in circuit LGC is in the off state. For example, in a transistor (e.g., transistor MN4 in circuit LGC) used to maintain the potential at terminal Bi (node ​​N1), when the off-state current flowing between the source and drain or the leakage current flowing between the gate and source or gate and drain increases, the potential at terminal Bi (node ​​N1) drops. This causes the potential of terminal Bi supplied to circuit BB to fluctuate, affecting the potential of node N. As a result, the potential of terminal OT, which has been raised by bootstrapping in circuit BSPR, may become unstable. In other words, the potential V of terminal OT, which has been raised by bootstrapping in circuit BSPR, is output by circuit MDV. High During the period, the potential of the terminal Bi (node ​​N1) preferably does not change.

[0122] Similarly, the potential V at the output terminal OT of the circuit MDV is High During the period of 100V, the potential of the gate (node ​​N2) of the transistor MN12 preferably does not change. If the potential of the gate (node ​​N2) of the transistor MN12 changes for some reason, the gate-source voltage of the transistor MN12 may also change, and the off-state current of the transistor MN12 may increase. As a result, the potential of the terminal OT output by the circuit MDV may change from V High decline.

[0123] In order to solve the above problems, it is preferable to use transistors MN2 and MN4. Figures 3A to 3C transistor shown.

[0124] <<Transistor Structure Example 1>> Figures 3A to 3C The transistor ML shown is a transistor called a VLFET (Vertical Lateral Field Effect Transistor), which has a structure in which current flows in both the vertical and lateral directions. Specifically, the semiconductor layer contacts each of the side surfaces of the opening provided in the first insulating layer and the top surface of the second insulating layer corresponding to the bottom of the opening, and the channel formation region of the transistor ML is included in the semiconductor layer. In other words, since the channel length of the transistor ML has a component along the side surfaces of the opening and a component along the bottom of the opening, it is easy to increase compared to the channel length of the existing transistor structure. Note that the channel length here can refer to the length between the source and the drain of the channel formation region.

[0125] In addition, Figure 3B 1 shows a channel length CHL of a channel formation region in the semiconductor layer SC1 in the transistor ML.

[0126] By increasing the channel length, the off-state current (leakage current) of the transistor can be reduced. Figures 3A to 3C The transistor ML shown is used for Figure 1 The transistor MN2 and the transistor MN4 can maintain the potential of the node N1 or the node N2 in a floating state for a long time. In other words, the potential of the node N1 or the node N2 can be prevented from fluctuating.

[0127] Figure 3A FIG. 1 shows a schematic plan view of transistor ML. Figure 3B corresponds to Figure 3A The schematic cross-sectional view of the portion along the dashed line A1 - A2 is also a schematic cross-sectional view of the transistor ML. Figure 3C corresponds to Figure 3A The schematic cross-sectional view of the portion along the dashed line A3 - A4 is also a schematic cross-sectional view of the transistor ML.

[0128] exist Figures 3A to 3C In FIG, the direction of the dotted line A1-A2 is regarded as the X direction, and the direction of the dotted line A3-A4 is regarded as the Y direction. In addition, the direction perpendicular to the X direction and the Y direction is the Z direction. The X direction and the Y direction may be perpendicular to each other. In addition, the definitions of the X direction, the Y direction, and the Z direction may be the same or different in the following drawings. In addition, Figure 3A In the description of the planar schematic diagrams, etc., the right side is sometimes referred to as the +X direction, the left side is sometimes referred to as the -X direction, the upper side is sometimes referred to as the +Y direction, and the lower side is sometimes referred to as the -Y direction. Figure 3BIn the description of the cross-sectional schematic diagrams, etc., the right side is sometimes referred to as the +X direction, the left side is sometimes referred to as the -X direction, the upper side is sometimes referred to as the +Z direction, and the lower side is sometimes referred to as the -Z direction. Figure 3C In the description of the cross-sectional schematic diagrams of FIG. 1 , the right side may be referred to as the −Y direction, the left side may be referred to as the +Y direction, the upper side may be referred to as the +Z direction, and the lower side may be referred to as the −Z direction.

[0129] Figures 3A to 3C The transistor ML includes, for example, insulating layers IS1 to IS3 , insulating layers IB1 to IB4 , an insulating layer GI1 , conductive layers ME2 a , ME2 b , ME3 , and a semiconductor layer SC1 .

[0130] The insulating layer IS1 functions as, for example, a base film for providing the transistor ML thereover.

[0131] The insulating layers IB1 and IB2 function as barrier films that suppress diffusion of impurities from below the insulating layers IB1 and IB2 to the conductive layer or semiconductor layer SC1 above the insulating layers IB1 and IB2 , for example.

[0132] For example, impurities in the conductive layer include oxygen that reduces conductivity due to oxidation. In addition, for example, impurities in the semiconductor layer include elements, atoms, molecules, ions, etc. that increase the number of carriers in the semiconductor layer. In particular, Figures 3A to 3C In the transistor ML, the insulating layer IB1 and the insulating layer IB2 are preferably used as a barrier film for suppressing diffusion of impurities into the semiconductor layer SC1.

[0133] In addition, the insulating layer IB2, the insulating layer IS2, and the insulating layer IB3 have the function of forming an insulating layer of the semiconductor layer SC1, for example. Figures 3A to 3C As shown, the insulating layers IB2, IS2, and IB3 include an opening KK1, and the transistor ML has a structure in which a portion of the semiconductor layer SC1 is included in the opening KK1. Specifically, the insulating layers IB2, IS2, and IB3 are provided with the opening KK1 so that the semiconductor layer SC1 has a region in contact with the side walls of the insulating layers IB2, IS2, and IB3 corresponding to the side surfaces of the opening KK1 and the top surface of the insulating layer IB1 corresponding to the bottom of the opening KK1. In addition, the transistor ML has a structure in which the semiconductor layer SC1 provided inside the opening KK1 includes a channel formation region of the transistor ML. Note that in Figure 3B and Figure 3C In FIG, the insulating layer IB2, the insulating layer IS2, and the insulating layer IB3 are collectively referred to as the insulating layer ISP.

[0134] Note that in Figure 3AIn the top view of FIG, the shape of the opening KK1 is, for example, a perfect circle, but one embodiment of the present invention is not limited thereto. The shape of the opening KK1 can be, for example, a figure with a single closed curve as an edge (including an ellipse) or a polygon with rounded corners.

[0135] Furthermore, the side surfaces of the opening KK1 in the insulating layer IS2 and the insulating layer IB3 of the semiconductor layer SC1 in which the transistor ML is provided are preferably substantially perpendicular to the XY plane (with a taper angle of 70° to 110°). In particular, the closer the taper angle is to 90°, the smaller the opening area of ​​the opening KK1 can be, thereby reducing the area required to form the transistor ML.

[0136] In addition, the insulating layer IB3 also has a barrier function of, for example, suppressing the diffusion of impurities from the insulating layer IS2 below the insulating layer IB3 to the conductive layer ME2a and the conductive layer ME2b above the insulating layer IB3. Figures 3A to 3C In transistor ML, insulating layer IB3 preferably functions as a barrier film to inhibit oxygen diffusion into conductive layer ME2a and conductive layer ME2b. By using insulating layer IB3 as a barrier film to inhibit oxygen diffusion, oxidation of conductive layer ME2a and conductive layer ME2b can be prevented, thereby preventing a decrease in the conductivity of conductive layer ME2a and conductive layer ME2b.

[0137] Conductive layer ME2a, for example, functions as one of the source and drain of transistor ML. Furthermore, conductive layer ME2b, for example, functions as the other of the source and drain of transistor ML. Note that all or part of conductive layer ME2a and conductive layer ME2b may sometimes be referred to as electrodes, terminals, wiring, or the like.

[0138] The conductive layer ME2a and the conductive layer ME2b are both located above the insulating layer IB3. Figure 3A A top view of Figure 3B In the cross-sectional view of FIG, the conductive layer ME2a and the conductive layer ME2b are separated into a pair of conductive layers by the opening KK1. Figures 3A to 3C In the transistor ML, Figure 3A In the top view of FIG, the width of the conductive layer ME2a and the conductive layer ME2b in the Y direction is preferably smaller than the width of the opening KK1 in the Y direction. Figure 3A In the top view of , the opening KK1 is, for example, a perfect circle, and the width of the opening KK1 in the Y direction is equivalent to the diameter of the perfect circle.

[0139] In addition, Figures 3A to 3C In FIG. 2 , the conductor ME2a extends in the −X direction as a wiring, for example. The conductor ME2b extends in the +X direction as a wiring, for example.

[0140] As described above, semiconductor layer SC1 includes regions that contact the sidewalls of insulating layer IS2 and insulating layer IB3, which correspond to the side surfaces of opening KK1, and the top surface of insulating layer IB1, which corresponds to the bottom surface of opening KK1. Furthermore, semiconductor layer SC1 includes regions that contact the top surfaces of conductive layer ME2a and conductive layer ME2b. As described above, semiconductor layer SC1 includes the channel formation region of transistor ML. The channel length CHL of the channel formation region of transistor ML is determined by the area of ​​the bottom surface of opening KK1 and the depth of opening KK1 (the length of the side surfaces of opening KK1 or the thickness of insulating layer ISP).

[0141] The insulating layer GI1 functions as a gate insulating layer (sometimes referred to as a gate insulating film) of the transistor ML. The insulating layer GI1 has regions in contact with the top surfaces of the semiconductor layer SC1, the conductor ME2a, and the conductor ME2b.

[0142] In particular, the thickness of the insulating layer GI1 significantly affects the electrical characteristics of the transistor ML. For example, when the insulating layer GI1 is thicker (the gate insulating layer of the transistor ML is thicker), the voltage gradient between the gate of the transistor ML (conductor ME3) and the channel formation region of the semiconductor layer SC1 can be smoothed, thereby improving the resistance to gate potential. On the other hand, when the gate insulating film thickness of the transistor is smaller, the change in the electric field applied from the gate to the channel formation region of the semiconductor layer when the gate potential changes becomes faster, thereby increasing the driving frequency of the transistor.

[0143] Therefore, for example, among multiple transistors ML, by determining the thickness of the insulating layer GI1 serving as the gate insulating layer for each transistor ML, a transistor with high resistance to gate-source voltage (or gate-drain voltage) and a transistor with high driving frequency can be easily formed respectively.

[0144] The conductor ME3 functions as, for example, a gate of the transistor ML. The conductor ME3 includes a region that overlaps with at least a portion of the semiconductor layer SC1 and is in contact with the top surface of the insulating layer GI1.

[0145] In addition, Figures 3A to 3C In FIG, the conductor ME3 extends in the +Y direction and the −Y direction as wiring, for example.

[0146] In addition, the insulating layer IB4 has a function of a barrier film for suppressing diffusion of impurities from the insulating layer IS3 above the insulating layer IB4 to the conductive layer ME3 below the insulating layer IB4. Figures 3A to 3CIn the transistor ML, the insulating layer IB4 is preferably used as a barrier film to suppress oxygen diffusion into the conductive layer ME3. By using the insulating layer IB4 as a barrier film to suppress oxygen diffusion, oxidation of the conductive layer ME3 can be prevented, and a decrease in the conductivity of the conductive layer ME3 can be prevented.

[0147] Insulating layer IS3 also functions as a planarization film, for example, to fill in the unevenness resulting from the formation of transistor ML. Using insulating layer IS3 as a planarization film facilitates placement of other circuit elements above transistor ML. In other words, a stacked structure can be formed with transistor ML and other circuit elements interposed via insulating layer IS3.

[0148] Notice, Figures 3A to 3C The transistor ML has a structure including an opening KK1 and an insulating layer IB4 and an insulating layer IS3, but one embodiment of the present invention is not limited thereto. Figures 4A to 4C As shown, the transistor ML may also have a structure in which the opening KK1 is filled with the conductor ME3. Figures 4A to 4C The structure shown is equivalent to Figures 3A to 3C A modified example of the structure shown.

[0149] In addition, Figures 3A to 3C A conductive layer having a back gate function may be additionally provided in the transistor ML. Figures 5A to 5C The transistor ML shown has a Figures 3A to 3C The conductive layer ME0 serving as a back gate is provided in the transistor ML. Note that Figures 5A to 5C The structure shown is equivalent to Figures 3A to 3C A modified example of the structure shown.

[0150] exist Figures 5A to 5C In the embodiment, insulating layer IS1 is located above insulating layer IS0. Furthermore, insulating layer IS1 includes an opening, in which conductive layer ME0 is embedded. Note that insulating layer IS1 includes this opening, for example, in a region that overlaps with at least a portion of semiconductor layer SC1. In other words, conductive layer ME0 includes a region that overlaps with at least a portion of semiconductor layer SC1.

[0151] In addition, Figures 5A to 5C In the embodiment, the conductive layer ME0 has the function of a back gate, so the insulating layer IB1 also has the function of a gate insulating layer. Figures 5A to 5C The transistor ML includes two gates, so the insulating layer GI1 is sometimes referred to as a first gate insulating layer, and the insulating layer IB1 is sometimes referred to as a second gate insulating layer (back gate insulating layer).

[0152] Note that in Figures 5A to 5C In FIG, the conductor ME0 extends in the +Y direction as a wiring, for example.

[0153] Note that the above instructions will Figures 3A to 3C Although the transistor ML is used as an example for the transistor MN2 and the transistor MN4, transistors of other structures may be used for the transistor MN2 and the transistor MN4 depending on circumstances.

[0154] <<Transistor Structure Example 2>> In wanting to improve Figure 1 When the driving speed of circuit MDV is increased, it is preferable to use transistors with large on-state current or capable of high frequency driving as transistors in circuit MDV. Specifically, for example, it is preferable to use transistors with large on-state current or capable of high frequency driving as transistors MN1, MN3, MN11, and MN12.

[0155] Figures 6A to 6C An example of a transistor having a large on-state current or capable of being driven at a high frequency is shown. Figures 6A to 6C In the transistor MV shown, the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor MV can also be called a VFET (Vertical Field Effect Transistor: vertical field effect transistor), a vertical transistor, a vertical channel transistor, a vertical channel type transistor, etc. In other words, since the channel length of the transistor MV has a component along the side of the opening, it is easy to shorten compared to the channel length of the existing transistor structure.

[0156] Note that in Figure 6B and Figure 6C The transistor MV shows the channel length CHV of the channel formation region in the semiconductor layer SC1. The channel length CHV can be said to be the shortest distance between the portion of the semiconductor layer SC1 that contacts the conductive layer ME1 and the portion that contacts the conductive layer ME2 when viewed in cross section.

[0157] By reducing the channel length, the on-state current of the transistor can be increased, thereby Figures 6A to 6C The transistor MV shown is used Figure 1 The on-state currents of the transistors MN1, MN3, MN11, and MN12 are increased, thereby shortening the charging time. In other words, the driving speed of the circuit MDV can be increased.

[0158] Figure 6A is a schematic plan view of transistor MV. In addition, Figure 6B corresponds to Figure 6AThe cross-sectional view of the portion along the dot-dash line B1-B2 is also a cross-sectional view of the transistor MV. Figure 6C corresponds to Figure 6A The schematic cross-sectional view of the portion taken along the dashed line B3 - B4 is also a schematic cross-sectional view of the transistor ML.

[0159] exist Figures 6A to 6C In FIG, the direction of the dot-dash line B1-B2 is regarded as the X direction, and the direction of the dot-dash line B3-B4 is regarded as the Y direction. In addition, the direction perpendicular to the X direction and the Y direction is the Z direction. The X direction and the Y direction may be perpendicular to each other. In addition, the definitions of the X direction, the Y direction, and the Z direction may be the same or different in the following drawings. In addition, Figure 6A In the description of the planar schematic diagrams, etc., the right side is sometimes referred to as the +X direction, the left side is sometimes referred to as the -X direction, the upper side is sometimes referred to as the +Y direction, and the lower side is sometimes referred to as the -Y direction. Figure 6B In the description of the cross-sectional schematic diagrams, etc., the right side is sometimes referred to as the +X direction, the left side is sometimes referred to as the -X direction, the upper side is sometimes referred to as the +Z direction, and the lower side is sometimes referred to as the -Z direction. Figure 6C In the description of the cross-sectional schematic diagrams of FIG. 1 , the right side may be referred to as the −Y direction, the left side may be referred to as the +Y direction, the upper side may be referred to as the +Z direction, and the lower side may be referred to as the −Z direction.

[0160] Figures 6A to 6C The transistor MV includes, for example, insulating layers IS1 to IS3 , insulating layers IB1 to IB4 , an insulating layer GI1 , conductive layers ME1 , ME2 , ME3 , and a semiconductor layer SC1 .

[0161] The insulating layer IS1 functions as, for example, a base film for providing the transistor MV thereover.

[0162] The insulating layer IB1 has, for example, a function as a barrier film that suppresses diffusion of impurities from below the insulating layer IB1 to the conductive layer ME1 or the semiconductor layer SC1 located above the insulating layer IB1 .

[0163] For example, impurities in the conductive layer ME1 include oxygen that reduces conductivity due to oxidation. By using the insulating layer IB1 as a barrier film to suppress diffusion of oxygen, oxidation of the conductive layer ME1 can be prevented, thereby preventing a decrease in conductivity of the conductive layer ME1.

[0164] Furthermore, as impurities in the semiconductor layer, for example, there can be mentioned elements, atoms, molecules, ions, etc. that increase the number of carriers in the semiconductor layer. Figures 6A to 6C In the transistor MV, the insulating layer IB1 is preferably used as a barrier film for suppressing diffusion of impurities into the semiconductor layer SC1.

[0165] The conductive layer ME1 has the function of, for example, one of the source and drain of the transistor MV. In addition, the conductive layer ME1 is located above the insulating layer IB1. Note that Figures 6A to 6C In FIG, the conductor ME1 extends in the +Y direction and the −Y direction as wiring, for example.

[0166] The insulating layer IB2, for example, functions as a barrier film that inhibits oxygen from diffusing from above the insulating layer IB2 into the conductive layer ME1 located below the insulating layer IB2. By using the insulating layer IB2 as a barrier film to inhibit oxygen diffusion, the conductive layer ME1 can be prevented from being oxidized, and a decrease in the conductivity of the conductive layer ME1 can be prevented, similarly to the insulating layer IB1.

[0167] The insulating layer IS2 and the insulating layer IB3 function as insulating layers for forming the semiconductor layer SC1, for example, and also function as interlayer films that separate the source and drain of the transistor MV.

[0168] In addition, if Figures 6A to 6C As shown, the insulating layer IS2, the insulating layer IB3, and the conductive layer ME2 include an opening KK2, and the transistor MV has a structure in which a portion of the semiconductor layer SC1 is included in the opening KK2. Specifically, the insulating layer IS2, the insulating layer IB3, and the conductive layer ME2 are provided with the opening KK2 so that the semiconductor layer SC1 includes a region that contacts the sidewalls of the insulating layer IS2, the insulating layer IB3, and the conductive layer ME2, which correspond to the side surfaces of the opening KK2, and the top surface of the conductive layer ME1, which corresponds to the bottom of the opening KK1. Furthermore, the transistor MV has a structure in which the semiconductor layer SC1, which is provided within the opening KK2, includes a channel formation region for the transistor MV.

[0169] Note, about Figure 6A The shape of the opening KK2 shown in the top view of FIG. 1 can refer to the description of the opening KK1. In addition, the taper angle of the opening KK2 can also refer to the description of the opening KK1.

[0170] In addition, the insulating layer IB3 also has a function of a barrier film for suppressing diffusion of impurities from the insulating layer IS2 below the insulating layer IB3 to the conductive layer ME2 above the insulating layer 3. In particular, Figures 6A to 6C In the transistor MV, the insulating layer IB3 is preferably used as a barrier film to suppress oxygen diffusion into the conductive layer ME2. By using the insulating layer IB3 as a barrier film to suppress oxygen diffusion, oxidation of the conductive layer ME2 can be prevented, and a decrease in the conductivity of the conductive layer ME2 can be prevented.

[0171] Conductive layer ME2 has, for example, the function of the other of the source and the drain of transistor MV. Note that the entirety or a portion of the conductive layer ME2 may be referred to as an electrode, a terminal, a wiring, or the like.

[0172] The conductive layer ME2 is located on the top surface of the insulating layer IB3. Figure 6A A top view of Figure 6B In the cross-sectional view of FIG, the insulating layer IB3 is also located above the edge of the opening KK2. Figures 6A to 6C In the transistor MV, Figure 6A In the top view of FIG, the width of the conductive layer ME2 in the Y direction is preferably greater than the width of the opening KK2 in the Y direction. Figure 6A In the top view of , the opening KK2 is, for example, a perfect circle, and the width of the opening KK2 in the Y direction is equivalent to the diameter of the perfect circle.

[0173] Note that in Figures 6A to 6C In FIG, the conductor ME2 extends in the +X direction and the −X direction as wiring, for example.

[0174] Furthermore, as described above, semiconductor layer SC1 includes a region that contacts the sidewalls of insulating layer IS2, insulating layer IB3, and conductive layer ME2, which correspond to the side surfaces of opening KK2, and the top surface of conductive layer ME1, which corresponds to the bottom of opening KK2. Furthermore, semiconductor layer SC1 includes a region that contacts the top surface of conductive layer ME2. Furthermore, as described above, semiconductor layer SC1 includes a channel formation region for transistor MV. Note that the channel length CHV of the channel formation region of transistor MV is determined by the depth of opening KK2 (the length of the side surfaces of opening KK2 and the thickness of insulating layer ISP).

[0175] The insulating layer GI1 functions as, for example, a gate insulating layer (sometimes referred to as a gate insulating film) of the transistor MV. The insulating layer GI1 includes a region in contact with the top surface of the semiconductor layer SC1 and the top surface of the conductor ME2.

[0176] In particular, the thickness of the insulating layer GI1 has a significant influence on the electrical characteristics of the transistor MV. Figures 3A to 3C Similarly to the description of transistor ML, by increasing the thickness of insulating layer GI1 of transistor MV, the resistance to gate-source voltage (or gate-drain voltage) can be improved. On the other hand, by reducing the thickness of insulating layer GI1 of transistor MV, transistor MV can be driven at a high frequency. Therefore, by determining the thickness of insulating layer GI1, which serves as the gate insulating layer for each transistor ML, it is possible to easily form a transistor with high resistance to gate-source voltage (or gate-drain voltage) and a transistor with high driving frequency.

[0177] The conductor ME3 functions as, for example, a gate of the transistor MV. The conductor ME3 includes a region that overlaps with at least a portion of the semiconductor layer SC1 and is in contact with the top surface of the insulating layer GI1.

[0178] Note that in Figures 6A to 6C In FIG, the conductor ME3 extends in the +Y direction and the −Y direction as wiring, for example.

[0179] In addition, for example, Figures 3A to 3C Similarly to the description of the transistor ML, the insulating layer IB4 has a function as a barrier film that suppresses diffusion of impurities from the insulating layer IS3 above the insulating layer IB4 to the conductive layer ME3 below the insulating layer IB4.

[0180] In addition, for example, Figures 3A to 3C Similar to the description of the transistor ML, the insulating layer IS3 has a function as a planarizing film that fills the unevenness generated by the formation of the transistor MV.

[0181] Notice, Figures 6A to 6C The transistor MV has a structure including the insulating layer IB4 and the insulating layer IS3 in the opening KK2, but one embodiment of the present invention is not limited thereto. 7A to 7C As shown, the transistor MV may also have a structure in which the opening KK2 is filled with the conductor ME3. 7A to 7C The structure shown is equivalent to Figures 3A to 3C Example of a deformation of the structure.

[0182] like Figures 6A to 6C As shown, by arranging the channel formation region of the transistor along the side of the opening of the insulator serving as the interlayer film, the formation area of ​​the transistor can be reduced compared to the case where the channel formation region of the transistor is arranged along the XY plane. In the transistor MV, the source electrode, semiconductor layer, and drain electrode can be arranged in an overlapping manner, so the occupied area can be greatly reduced compared to the so-called planar transistor in which the semiconductor layer is arranged in a planar shape. Therefore, by forming a circuit using one or both of the transistors MV, the area of ​​the circuit can be reduced. In addition, as a result, the semiconductor device or display device including the circuit can be miniaturized.

[0183] The channel length CHV of the transistor MV is equivalent to the length in the height direction of the opening KK2 of the insulating layer IS2 when viewed from a cross section. That is, the channel length CHV is determined by the thickness of the insulating layer IS2. In addition, when the opening KK2 is conical, the channel length CHV is also determined by the angle formed by the opening KK2 and the XY plane (or the formation surface of the conductive layer ME1). Therefore, for example, the channel length CHV can be set to a value smaller than the limiting resolution of the exposure device, so that a transistor of a fine size can be realized. Specifically, a transistor with an extremely small channel length that cannot be realized in the exposure device used in the mass production of conventional flat panel displays (for example, a minimum line width of about 2μm or 1.5μm) can be realized. In addition, a transistor with a channel length of less than 10nm can be realized without using the very expensive exposure device used in the most advanced LSI technology.

[0184] The channel length CHV may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length CHV may be set to 100 nm or more and 1 μm or less.

[0185] By reducing the channel length CHV, the on-state current of the transistor MV can be increased. Therefore, for example, by using the transistor MV in the driver circuit of a large display device or a high-definition display device, the power consumption of these driver circuits can be reduced. In addition, when the transistor MV is used in a large display device or a high-definition display device, even if the number of wiring lines increases, the signal delay in each wiring line can be reduced, and display unevenness can be suppressed. In addition, since the circuit area can be reduced, the frame of the display device can be reduced.

[0186] Figures 6A to 6C The VFET transistor MV shown is with Figures 3A to 3C The transistor ML shown in the figure differs from the VLFET in that the bottom of the opening KK2 in the insulating layer IS2 is formed by the conductive layer ME1. Furthermore, the transistor MV differs from the transistor ML in that, in the schematic top view of the transistor MV, the Y-direction width of the conductor ME2 is longer than the Y-direction width of the opening KK2, while in the schematic top view of the transistor ML, the Y-direction widths of the conductors ME2a and ME2b are shorter than the Y-direction width of the opening KK1. This makes it easier to form the transistor ML as a VLFET and the transistor MV as a VFET separately. Note that the method for simultaneously manufacturing the VLFET and the VFET is described in detail in Embodiment 4.

[0187] Note that the above instructions will Figures 6A to 6C Although the transistor MV is used as an example for the transistor MN1 , the transistor MN3 , the transistor MN11 , and the transistor MN12 , transistors of other structures may be used for the transistor MN2 and the transistor MN4 depending on circumstances.

[0188] <<Configuration Example 1 of Circuit BB>> Next, explain Figure 1 、 Figure 2A and Figure 2B Configuration examples of circuit BB in each circuit configuration.

[0189] Notice, Figures 8A to 8G A configuration example of circuit BB is shown. Figures 8A to 8G The transistor MNb shown is equivalent to Figure 1 、 Figure 2A and Figure 2B The transistor MN11 in Figures 8A to 8G The capacitor Ca shown is equivalent to Figure 1 and Figure 2A In addition, Figures 8A to 8G The wiring VAL1 is shown with Figure 1 、 Figure 2A and Figure 2B The wiring is electrically connected to the terminal CLK1.

[0190] exist Figure 8A In the circuit BSPR shown in FIG. 1 , the circuit BB includes a transistor MNa. As the transistor MNa, for example, a transistor that can be used for the transistor MNb (transistor MN11 ) can be used.

[0191] A first terminal of the transistor MNa is electrically connected to the terminal Bi, and a second terminal of the transistor MNa is electrically connected to the terminal Bo. In addition, a gate of the transistor MNa is electrically connected to the wiring VAL2.

[0192] Wiring VAL2, like wiring VAL1, is used as a wiring for supplying a fixed potential or a variable potential. Examples of the fixed potential include a high-level potential, a low-level potential, a ground potential, or a negative potential. Examples of the variable potential include a pulse signal or a clock signal.

[0193] Furthermore, the wiring VAL2 may be electrically connected to the wiring VAL1. In other words, the wiring VAL2 may be the same wiring as the wiring VAL1.

[0194] Here, it is explained Figure 8A For example, suppose that a high-level potential V is input to the terminal Ti of the circuit BSPR. High In other words, becoming V in =VHigh In addition, it is assumed that a high-level potential V is supplied from the wiring VAL2 to the gate of the transistor MNa. High In addition, the potential of the node N is a low level potential V Low .

[0195] In addition, the transistor MNa is a normally closed transistor, and the threshold voltage of the transistor MNa is recorded as V th_MNa In addition, the threshold voltage V th_MNa To meet V High -V Low >V th_MNa voltage.

[0196] The gate-source voltage of the transistor MNa (at this time, the gate-second terminal voltage) becomes V High -V Low , so the transistor MNa turns on. Therefore, charge accumulates between the source and drain of the transistor MNa from the terminal Ti at the node N, and the potential of the node N rises until the transistor MNa turns off. Specifically, the gate-source voltage of the transistor MNa drops to V th_MNa When the transistor MNa is turned off, the potential of the node N (the second terminal of the transistor MNa) becomes V High -V th_MNa . Note that V High -V th_MNa Equivalent to Figure 2A The V Mid .

[0197] In addition, with Figure 2A Similar to the transistor MN11 shown, the transistor MNa may also be a multi-gate structure transistor including gates above and below the channel. Figure 8B The transistor MNa shown is, for example, an n-channel transistor of a multi-gate structure including gates above and below a channel. The transistor MNa includes a second gate in addition to a first gate.

[0198] to the general Figure 8A The circuit BB is used for Figure 1 A structural example of circuit BB in circuit MDV will be described. Figure 9 This structural example is shown. Figure 9 The circuit MDV1 has the Figure 8A The circuit BSPR is used Figure 1 In this case, the transistor MN10 in the circuit BB is preferably used. Figures 6A to 6C The transistor MV or 7A to 7C In addition, depending on the situation, transistor MN10 can also be used Figures 3A to 3Ctransistor ML, Figures 4A to 4C transistor ML, Figures 5A to 5C The transistor is an ML or other structured transistor.

[0199] <<Configuration Example 2 of Circuit BB>> Figure 8C The circuit BSPR in the circuit BB shown is Figure 8A This is a modified example of the circuit BB in the circuit BSPR of FIG. 1 , and is different from the circuit BB in that the gate of the transistor MNa is not electrically connected to the wiring VAL2 but is electrically connected to the first terminal of the transistor MNa. Figure 8A The circuit BSPR is different from the circuit BB.

[0200] exist Figure 8C In FIG, the first terminal of the transistor MNa is electrically connected to the gate of the transistor MNa, so the transistor MNa can be said to be diode-connected. Therefore, for example, when a high-level potential V is input to the terminal Ti of the circuit BSPR, High When the potentials of the first terminal and the gate of the transistor MNa are both at a high level potential V High , so the potential of node N (the second terminal of transistor MNa) becomes V High -V th_MNa .

[0201] Note that when you want to lower the potential V of the node N (the second terminal of the transistor MNa), High -V th_MNa , that is, when you want to release the charge accumulated at node N, you need to further change Figure 8C Circuit BSPR of circuit BB.

[0202] Figure 8D The BSPR of the circuit shown in circuit BB is Figure 8C The circuit BSPR is a modified example of the circuit BB and is different from the circuit BSPR in that the charge accumulated at the node N can be released. Figure 8C Circuit BSPR is different from circuit BB in circuit BSPR.

[0203] exist Figure 8D In the circuit BSPR, the circuit BB includes a transistor MNd in addition to the transistor MNa.

[0204] As the transistor MNd, for example, a transistor that can be used for the transistor MNa or the transistor MNb can be used.

[0205] A first terminal of the transistor MNd is electrically connected to the second terminal of the transistor MNa and the terminal Bo, a second terminal of the transistor MNd is electrically connected to the wiring VAL3 , and a gate of the transistor MNd is electrically connected to the wiring RST.

[0206] Wiring VAL3, for example, is used as a wiring for supplying a fixed potential, similar to wiring VAL1 or wiring VAL2. Furthermore, a low-level potential can be used as a fixed potential, for example. Other fixed potentials include ground potential or a negative potential. Wiring VAL3 can also be used as a wiring for supplying a variable potential, depending on circumstances.

[0207] The wiring RST is used as, for example, a wiring for transmitting a signal for selecting whether to discharge the charge accumulated in the node N. Specifically, for example, when the charge of the node N is not discharged, a low-level potential V may be supplied to the wiring RST. Low As a signal, the transistor MNd is turned off. For example, when the charge of the node N is released, a high-level potential V may be supplied to the wiring RST. High The transistor MNd is turned on as a signal.

[0208] When you want to increase the potential of node N (you want to set the potential of node N to V High -V th_MNa ), for example, a low-level potential V is supplied to the wiring RST. Low The transistor MNd is turned off, and a high-level potential V is supplied to the terminal Ti. High , then. In addition, if you want to lower the potential of node N (you want to set the potential of node N to V Low ), for example, a low-level potential V is supplied to the terminal Ti. Low The transistor MNa is turned off, and a high-level potential V is supplied to the wiring RST. High Here, the potential supplied by the wiring VAL3 is set to the low level potential V Low When the charge at the node N flows to the wiring VAL3, the potential of the node N becomes V Low .

[0209] <<Configuration Example 3 of Circuit BB>> Figure 8E The BSPR of the circuit shown in circuit BB is Figure 8A In the modified example of the circuit BB in the circuit BSPR, the gate of the transistor MNa is not electrically connected to the wiring VAL2 but to the terminal Bi, and the first terminal of the transistor MNa is not electrically connected to the terminal Bi but to the wiring VAL2. Figure 8A Circuit BSPR is different from circuit BB in circuit BSPR.

[0210] illustrate Figure 8E For example, suppose that a high-level potential V is input to the terminal Ti of the circuit BSPR. HighIn addition, it is assumed that a high-level potential V is supplied from the wiring VAL2 to the first terminal of the transistor MNa. High In addition, the potential of the node N is a low level potential V Low .

[0211] The gate-source voltage of the transistor MNa (at this time, the gate-second terminal voltage) becomes V High -V Low , so the transistor MNa turns on. Therefore, a current flows from the wiring VAL2 through the transistor MNa in the node N, and charge accumulates. The potential of the node N rises until the transistor MNa turns off. Specifically, the gate-source voltage of the transistor MNa drops to V th_MNa When the transistor MNa is turned off, the potential of the node N (the second terminal of the transistor MNa) becomes V High -V th_MNa . Note that V High -V th_MNa Equivalent to Figure 2A The V Mid .

[0212] Note that when you want to lower the potential V of the node N (the second terminal of the transistor MNa), High -V th_MNa , that is, when you want to release the charge accumulated at node N, you need to further change Figure 8E Circuit BSPR of circuit BB.

[0213] Figure 8F The circuit BSPR in the circuit BB shown is Figure 8E This is a modified example of the circuit BB in the circuit BSPR and is different from the circuit BB in that the charge accumulated in the node N can be released. Figure 8E Circuit BSPR is different from circuit BB in circuit BSPR.

[0214] exist Figure 8F In the circuit BSPR, the circuit BB includes a transistor MNd in addition to the transistor MNa.

[0215] A first terminal of the transistor MNd is electrically connected to the second terminal of the transistor MNa and the terminal Bo, a second terminal of the transistor MNd is electrically connected to the wiring VAL3 , and a gate of the transistor MNd is electrically connected to the wiring RST.

[0216] The transistor MNd, the wiring VAL3, and the wiring RST can be referred to as Figure 8D Description of the transistor MNd, wiring VAL3, and wiring RST in the circuit BSPR.

[0217] When you want to increase the potential of node N (you want to set the potential of node N to VHigh -V th_MNa ), for example, a low-level potential V is supplied to the wiring RST. Low The transistor MNd is turned off, and a high-level potential V is supplied to the terminal Ti. High , then. In addition, if you want to lower the potential of node N (you want to set the potential of node N to V Low ), for example, a low-level potential V is supplied to the terminal Ti. Low The transistor MNa is turned off, and a high-level potential V is supplied to the wiring RST. High Here, the potential supplied by the wiring VAL3 is set to the low level potential V Low When the charge at the node N flows to the wiring VAL3, the potential of the node N becomes V Low .

[0218] <<Configuration Example 4 of Circuit BB>> exist Figure 8G In the circuit BSPR shown, the circuit BB includes an inverter circuit. Specifically, the circuit BB includes a transistor MNe and a transistor MNf, and the transistors MNe and MNf constitute the inverter circuit.

[0219] As the transistor MNe and the transistor MNf, for example, transistors that can be used for the transistor MNb can be used.

[0220] A first terminal of transistor MNe is electrically connected to its gate and wiring VAL2 , a second terminal of transistor MNe is electrically connected to terminal Bo and a first terminal of transistor MNf, a second terminal of transistor MNf is electrically connected to wiring VAL3 , and a gate of transistor MNf is electrically connected to terminal Bi.

[0221] For wiring VAL2, please refer to Figure 8A The wiring VAL2 in the circuit BSPR is described below. Figure 8D Description of the wiring VAL3 in the BSPR circuit.

[0222] Note that in Figure 8G In the example, the potential output from terminal To is denoted as V outb Instead of V out .

[0223] Here, it is explained Figure 8G For example, it is assumed that a high-level potential V is supplied from wiring VAL2 to the first terminal and gate of transistor MNe. High In addition, it is assumed that a low-level potential V is supplied from the wiring VAL3 to the second terminal of the transistor MNf.Low In addition, the potential of the node N is a low level potential V Low .

[0224] In addition, the transistor MNe and the transistor MNf are normally off transistors. In particular, the threshold voltage of the transistor MNe is V th_MNe , V th_MNe To meet V High -V Low >V th_MNe voltage.

[0225] First, consider that a low-level potential V is input to the terminal Ti. Low At this time, the gate of transistor MNf is input with V Low , so the transistor MNf becomes off. In addition, the gate-source voltage of the transistor MNe (at this time, the gate-second terminal voltage) becomes V High -V Low , so the transistor MNe turns on. As a result, a current flows from the wiring VAL2 through the transistor MNe in the node N, and charge accumulates. The potential of the node N rises until the transistor MNe turns off. Specifically, the gate-source voltage of the transistor MNe drops to V th_MNe When the transistor is turned off, the potential of the node N (the second terminal of the transistor MNe) becomes V High -V th_MNe . Note that V High -V th_MNe Equivalent to Figure 2A The V Mid .

[0226] Next, consider that a high-level potential V is input to the terminal Ti. High At this time, the gate of transistor MNf is input with V High , so the transistor MNf is turned on. In addition, since the transistor MNf is turned on, current flows from the node N through the transistor MNf to the wiring VAL3, and the charge is released. Ideally, the potential of the node N becomes the low-level potential V supplied by the wiring VAL3. Low In fact, when the potential of the second terminal (node ​​N) of the transistor MNe decreases, the transistor MNe becomes on, so the potential of the node N becomes a low-level potential V Low Above and high level potential V High the following.

[0227] <Application Example for Display Device> Next, a driving circuit including a holding circuit and a display device including the driving circuit according to one embodiment of the present invention will be described.

[0228] First, the display device will be described. Figure 10 A structural example of a display device including a driving circuit including the above-described holding circuit is shown. Figure 10 The display device DSP shown includes, for example, a driving circuit GD, a driving circuit SD, and a pixel array PA.

[0229] Notice, Figure 10 The abstract shows the driving circuit GD, the driving circuit SD, the pixel array PA, the wiring GLS[1], the wiring GLS[m], the wiring SLS[1], the wiring SLS[n], the pixel circuit PX[1,1], the pixel circuit PX[m,1], the pixel circuit PX[1,n] and the pixel circuit PX[m,n] (m is an integer greater than 1, and n is an integer greater than 1).

[0230] For example, the pixel array PA includes a plurality of pixel circuits PX. The pixel circuits PX are arranged in a matrix of m rows and n columns in the pixel array PA.

[0231] Figure 10 The symbols of the pixel circuits PX shown in the figure represent the addresses of the pixel circuits. For example, the symbol of pixel circuit PX[1,1] represents the pixel circuit PX configured at the position of row 1 and column 1 in the pixel array PA. Also, for example, the symbol of pixel circuit PX[m,1] represents the pixel circuit PX configured at the position of row m and column 1 in the pixel array PA. Also, for example, the symbol of pixel circuit PX[1,n] represents the pixel circuit PX configured at the position of row 1 and column n in the pixel array PA. Also, for example, the symbol of pixel circuit PX[m,n] represents the pixel circuit PX configured at the position of row m and column n in the pixel array PA.

[0232] Furthermore, a pixel circuit PX arranged in row i and column j (i is an integer from 1 to m, and j is an integer from 1 to n) in the pixel array PA is referred to as a pixel circuit PX[i, j] (not shown). Pixel circuit PX[i, j] is electrically connected to, for example, wiring GLS[i] (not shown). Furthermore, pixel circuit PX[i, j] is electrically connected to, for example, wiring SLS[j] (not shown).

[0233] For example, the drive circuit GD is electrically connected to the wiring GLS[1] to the wiring GLS[m]. In addition, for example, the drive circuit SD is electrically connected to the wiring SLS[1] to the wiring SLS[n].

[0234] For example, wiring GLS[1] to wiring GLS[m] can all be wiring extending in the row direction in the pixel array PA. Furthermore, the "x" appended to a wiring GLS indicates the row number to which the wiring extends. For example, the symbol for wiring GLS[1] indicates a wiring extending in the first row in the pixel array PA. Furthermore, for example, the symbol for wiring GLS[m] indicates a wiring extending in the mth row in the pixel array PA.

[0235] For example, wiring SLS[1] to wiring SLS[n] can all be wiring extending in the column direction in the pixel array PA. Furthermore, the "y" appended to a wiring SLS indicates the column number to which the wiring extends. For example, the symbol for wiring SLS[1] indicates a wiring extending in the first column in the pixel array PA. Furthermore, for example, the symbol for wiring SLS[n] indicates a wiring extending in the nth column in the pixel array PA.

[0236] Note that the wiring GLS[i] can be a single wiring or a wiring group consisting of a plurality of wirings. Similarly, the wiring SLS[j] can be a single wiring or a wiring group consisting of a plurality of wirings.

[0237] The pixel circuit PX may be, for example, a pixel circuit using one or more of a liquid crystal display device, a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting diode (for example, a micro-LED (Light Emitting Diode)). Note that in this embodiment, a case where a light-emitting device including an organic EL material is used in the pixel circuit PX of the pixel array PA is described. In particular, the brightness of light emitted from a light-emitting device capable of emitting light at high brightness may be, for example, 500 cd / m 2 Above, preferably 1000 cd / m 2 Above and 10000cd / m 2 Below, more preferably 2000 cd / m 2 Above and 5000cd / m 2 the following.

[0238] For example, in the pixel array PA of the display device DSP, the driver circuit GD has a function of selecting the pixel circuit PX to which image data is to be transmitted. Therefore, the driver circuit GD can be called a gate driver circuit or the like.

[0239] Thus, the wiring GLS electrically connecting the drive circuit GD and the pixel circuit PX is used as, for example, a wiring for transmitting a selection signal. The wiring GLS may be used as, for example, a wiring for supplying a fixed potential instead of being used as a wiring for transmitting a selection signal.

[0240] The drive circuit SD has a function of transmitting image data to the pixel circuits PX in the pixel array PA of the display device DSP, for example. Therefore, the drive circuit SD can be called a source driver circuit or the like.

[0241] Thus, the wiring SLS electrically connecting the drive circuit SD and the pixel circuit PX is used as, for example, a wiring for transmitting image data as a signal. The wiring SLS may also be used as a wiring for supplying a fixed potential instead of being used as a wiring for transmitting image data.

[0242] In addition, Figure 10 In the display device DSP shown, wiring other than wiring GLS[1] to wiring GLS[m] and wiring SLS[1] to wiring SLS[n] may be extended. For example, in the display device DSP, wiring for supplying a fixed potential to the pixel circuit PX may be extended.

[0243] <<Configuration Example of Drive Circuit GD>> Figure 11A Shown available for Figure 10 FIG. 1 is a configuration example of a drive circuit GD according to one embodiment of the present invention for a display device DSP. Figure 11A The driving circuit GD shown includes, for example, circuits 100A[ 1 ] to 100A[m].

[0244] For example, each of the circuits 100A[ 1 ] to 100A[m] includes a terminal IT, a terminal OT, a terminal CLK1 , a terminal CLK2 , a terminal PWC, and a terminal GT.

[0245] For example, in each of the circuits 100A[ 1 ] to 100A[m], the terminal CLK1 is electrically connected to the wiring CL1 , the terminal CLK2 is electrically connected to the wiring CL2 , and the terminal PWC is electrically connected to the wiring PL.

[0246] Each of wiring CL1, wiring CL2, and wiring PL is used, for example, as a wiring for supplying a variable potential (sometimes referred to as a pulse voltage in this specification) such as a clock signal. However, one or more of wiring CL1, wiring CL2, and wiring PL may be a wiring for supplying a fixed potential rather than a variable potential.

[0247] For example, the terminal OT of the circuit 100A[k] (k is an integer greater than or equal to 1 and less than or equal to m−1) is electrically connected to the terminal IT of the circuit 100A[k+1].

[0248] The terminal GT of the circuit 100A[i] is electrically connected to the wiring GL[i]. The wiring GL[i] is equivalent to Figure 10 The wiring of the wiring GLS[i] is shown.

[0249] Each of the circuits 100A[ 1 ] to 100A[m] has, for example, a function of holding information input to the terminal IT and a function of outputting the held information to one or both of the terminal OT and the terminal GT.

[0250] For example, circuit 100A[i] has a function of outputting information held in circuit 100A[i] to terminal OT when a high-level potential is input to terminal CLK1. Furthermore, for example, circuit 100A[i] has a function of outputting information held in circuit 100A[i] to terminal GT when a high-level potential is input to terminal PWC. Furthermore, for example, circuit 100A[i] has a function of resetting information held in circuit 100A[i] when a high-level potential is input to terminal CLK2. Furthermore, circuit 100A[i] preferably has a configuration in which new information is input to terminal IT of circuit 100A[i] after resetting the information held in circuit 100A[i], thereby causing circuit 100A[i] to hold new information.

[0251] As described above, in circuits 100A[1] to 100A[m], by inputting information to terminal IT of circuit 100A[1] and then inputting variable potentials to terminals CLK1 and CLK2 at appropriate timing, the information can be sequentially transmitted to circuits from circuit 100A[2] onward. Furthermore, by inputting information to terminal IT of circuit 100A[1] and then inputting variable potentials to terminal PWC at appropriate timing, the information held by each of circuits 100A[1] to 100A[m] can be output from each terminal GT of circuits 100A[1] to 100A[m]. Therefore, in this specification and other documents, the structure of circuits 100A[1] to 100A[m] can be referred to as a shift register circuit.

[0252] In addition, the above information may be, for example, a selection signal for selecting a pixel circuit PX to write image data in the pixel array PA. Figure 11A In the example, the selection signal is recorded as signal SS.

[0253] exist Figure 11A In the driving circuit GD shown, the terminal OT is shown in the circuit 100A[m]. However, since the circuits 100A[1] to 100A[m] adopt the structure of a shift register circuit, the circuit 100A[m] may not be provided with the terminal OT.

[0254] In addition, it can be used Figure 10 The structure of the driving circuit GD of the display device DSP is not limited to Figure 11A For example, as can be used Figure 10 The structure of the driving circuit GD of the display device DSP can also be adopted Figure 11BThe driving circuit GD shown. Figure 11B The driving circuit GD is the same as that of the circuit BF[1] to the circuit BF[m]. Figure 11A The driving circuit GD is different.

[0255] exist Figure 11B In the driving circuit GD, each input terminal of the circuit BF[1] to the circuit BF[m] is electrically connected one-to-one to each terminal GT of the circuit 100A[1] to the circuit 100A[m], and each output terminal of the circuit BF[1] to the circuit BF[m] is electrically connected one-to-one to each of the wirings GL[1] to the wirings GL[m].

[0256] Each of circuits BF[1] to BF[m] may be configured to include an amplifier circuit such as a buffer circuit, an inverter circuit, or a latch circuit. Specifically, each of circuits BF[1] to BF[m] may have a function of outputting a potential obtained by amplifying the potential of terminal GT to wiring GL with reference to the potential of terminal GT.

[0257] In addition, Figure 11A and Figure 11B In the driving circuit GD shown, wirings other than the wirings CL1, CL2, and PL may be extended. For example, wirings for supplying a fixed potential for driving each of the circuits 100A[1] to 100A[m] may be extended.

[0258] Figure 12 The circuit 100A1 has the capability to be used for Figure 11A and Figure 11B The circuit configuration of each of the circuits 100A[1] to 100A[m] in the driving circuit GD is shown.

[0259] Figure 12 The circuit 100A1 is Figure 1 Circuit 100A1 is a modified example of circuit MDV and differs from circuit MDV in that circuit OPC includes circuit BSPRa, circuit BSPRb, transistor MN12, and transistor MN16. Circuit 100A1 also differs from circuit MDV in that it includes terminal PWC and terminal GT.

[0260] Figure 12 The circuit BSPRa shown has Figure 1 The circuit BSPR has the same circuit structure as shown. Figure 12 The circuit BBa in the circuit BSPRa can also have the same Figure 1 The circuit structure of circuit BSPR is the same as that of circuit BB.

[0261] Alternatively, the circuit BSPRb may have Figure 1The circuit structure is the same as the BSPR circuit shown in the figure. Figure 12 In FIG. 1 , circuit BSPRb includes circuit BBb, transistor MN15, and capacitor C2. Note that circuit BBb may also have Figure 1 The circuit structure of circuit BSPR is the same as that of circuit BB.

[0262] As the transistor MN15 and the transistor MN16, for example, the transistors MN15 and MN16 can be used. Figure 1 The transistor MN11 is shown as a transistor.

[0263] In addition, the transistor MN2 and the transistor MN4 can be, for example, Figures 3A to 3C 、 Figures 4A to 4C or Figures 5A to 5C The transistor ML (VLFET) of FIG. 1 is a transistor ML1. The transistor MN3, the transistor MN11, the transistor MN12, the transistor MN15 and the transistor MN16 can be, for example, the above-mentioned transistors MN1 and MN16. Figures 6A to 6C or 7A to 7C transistor MV (VFET).

[0264] The following describes the circuit structure of the circuit 100A1. Figure 1 Description of the common contents of the MDV circuit.

[0265] Terminal Bi of circuit BBb is electrically connected to terminal Bi of circuit BBa, the second terminal of transistor MN1, and the first terminal of transistor MN4. Furthermore, terminal Bo of circuit BBb is electrically connected to the gate of transistor MN15 and the first terminal of capacitor C2. The first terminal of transistor MN15 is electrically connected to terminal PWC, and the second terminal of transistor MN15 is electrically connected to the second terminal of capacitor C2, the first terminal of transistor MN16, and terminal GT. Furthermore, the gate of transistor MN16 is electrically connected to the gate of transistor MN12, the first terminal of transistor MN2, the second terminal of transistor MN3, the gate of transistor MN4, and the first terminal of capacitor C5. Furthermore, the second terminal of transistor MN16 is electrically connected to wiring VSE5.

[0266] The wiring VSE5 functions as a wiring for supplying a fixed potential, for example. The fixed potential may be, for example, a low-level potential, a ground potential, or a negative potential. Alternatively, the wiring VSE5 may function as a wiring for supplying a variable potential instead of a fixed potential.

[0267] Wirings VSE1 through VSE5 may supply fixed potentials that are equal to each other, or they may supply fixed potentials that are unequal to each other. Furthermore, two or more wirings among wirings VSE1 through VSE5 may supply fixed potentials that are equal to each other, and the remaining wirings may supply potentials that are different from the fixed potentials. Furthermore, two or more wirings among wirings VSE1 through VSE5 that supply fixed potentials that are equal to each other may be the same wiring. For example, if wirings VSE4 and VSE5 supply fixed potentials that are equal to each other, wirings VSE4 and VSE5 may be the same wiring.

[0268] Figure 13 Another specific example of the circuit 100A1 is shown. Figure 13 The circuit 100A2 shown has the Figure 8A The circuit BSPR is used Figure 12 In this case, the transistors MN10 and MN14 included in the circuits BBa and BBb are preferably used. Figures 6A to 6C The transistor MV or 7A to 7C In addition, depending on the situation, transistor MN10 and transistor MN14 can also be used. Figures 3A to 3C transistor ML, Figures 4A to 4C transistor ML, Figures 5A to 5C The transistor is an ML or other structured transistor.

[0269] In addition, a semiconductor device as one embodiment of the present invention Figure 13 The circuit 100A2 is a unipolar circuit including n-channel transistors, but it can also be Figure 13 The structure of the circuit 100A2 is changed to a unipolar circuit including p-channel transistors.

[0270] Figure 14 A specific structural example is shown. Figure 14 The circuit 100AP2 shown is Figure 13 In a modified example of circuit 100A2, transistors MN1 to MN4, MN10 to MN12, and MN14 to MN16 are replaced with transistors MP1 to MP4, MP10 to MP12, and MP14 to MP16, respectively; wiring VDE1 to VDE4 is replaced with wiring VSE21 to VSE24; and wiring VSE1 to VSE5 is replaced with wiring VDE15 to VDE19. As described above, transistors MP1 to MP4, MP10 to MP12, and MP14 to MP16 are all p-channel transistors.

[0271] Terminal IT is electrically connected to the gates of transistors MP1 and MP2. A first terminal of transistor MP1 is electrically connected to wiring VSE21, and a second terminal of transistor MP1 is electrically connected to the first terminal of transistors MP4, MP10, and MP14. Terminal CLK2 is electrically connected to the gate of transistor MP3, whose first terminal is electrically connected to wiring VSE22. A second terminal of transistor MP3 is electrically connected to the gate of transistor MP4, the first terminal of transistor MP2, the gate of transistor MP12, the gate of transistor MP16, and the first terminal of capacitor C5. A second terminal of capacitor C5 is electrically connected to wiring VDE15, a second terminal of transistor MP4 is electrically connected to wiring VDE16, and a second terminal of transistor MP2 is electrically connected to wiring VDE17.

[0272] Furthermore, the second terminal of transistor MP10 is electrically connected to the gate of transistor MP11 and the first terminal of capacitor C1. The first terminal of transistor MP11 is electrically connected to terminal CLK1. The second terminal of transistor MP11 is electrically connected to the second terminal of capacitor C1, the first terminal of transistor MP12, and terminal OT. Furthermore, the second terminal of transistor MP12 is electrically connected to wiring VDE18.

[0273] Furthermore, the second terminal of transistor MP14 is electrically connected to the gate of transistor MP15 and the first terminal of capacitor C2. The first terminal of transistor MP15 is electrically connected to terminal PWC. The second terminal of transistor MP15 is electrically connected to the second terminal of capacitor C2, the first terminal of transistor MP16, and terminal GT. The second terminal of transistor MP16 is electrically connected to wiring VDE19.

[0274] Wiring VDE15 to wiring VDE19 are all used, for example, as wiring for supplying a fixed potential. This fixed potential can be, for example, a high-level potential. Wiring VDE15 to wiring VDE19 can supply fixed potentials that are equal to each other, or they can supply fixed potentials that are unequal to each other. Furthermore, among wiring VDE15 to wiring VDE19, two or more wirings can supply fixed potentials that are equal to each other, and the remaining wirings can supply potentials that are different from the fixed potential. Furthermore, two or more wirings among wiring VDE15 to wiring VDE19 that supply fixed potentials that are equal to each other can be the same wiring. For example, when wiring VDE15 and wiring VDE16 supply fixed potentials that are equal to each other, wiring VDE15 and wiring VDE16 can be the same wiring.

[0275] One or more of the wirings VDE15 to VDE19 may be wirings that supply a variable potential instead of a fixed potential.

[0276] Wiring VSE21 through wiring VSE24, for example, all serve as wiring for supplying a fixed potential. This fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. Furthermore, each of wiring VSE21 through wiring VSE24 can supply a fixed potential that is equal to or different from each other. Furthermore, two or more wirings within wiring VSE21 through wiring VSE24 can supply a fixed potential that is equal to each other, while the remaining wirings can supply a potential different from the fixed potential. Furthermore, two or more wirings within wiring VSE21 through wiring VSE24 that supply a fixed potential that is equal to each other can be the same wiring. For example, when wiring VSE21 and wiring VSE22 supply a fixed potential that is equal to each other, wiring VSE21 and wiring VSE22 can be the same wiring.

[0277] One or more of the wirings VSE21 to VSE24 may be wirings that supply a variable potential instead of a fixed potential.

[0278] Regarding the operation of circuit 100AP2, please refer to the description of the operation example of circuit 100A1 described later. It should be noted that since circuit 100AP2 is a unipolar circuit including p-channel transistors, the logic of signals, potentials, etc. processed in circuit 100AP2 is the same as that of a unipolar circuit including n-channel transistors. Figure 12 The logic of the signal, potential, etc. processed in the circuit 100A1 is inverted.

[0279] Note that the semiconductor device of one embodiment of the present invention is not limited to Figure 12 The circuit 100A1 and Figure 13 The circuit 100A2 shown. For example, in Figure 13 In the circuit 100A2, at least one of the transistors MN1 to MN4, the transistors MN10 to MN12, and the transistors MN14 to MN16 may also be a transistor including a back gate.

[0280] Figure 15 A specific structural example is shown. Figure 15 The circuit 100A3 shown is Figure 13 This is a modified example of the circuit 100A2 and differs from the circuit 100A2 in that the transistors MN1 to MN4, the transistors MN10 to MN12, and the transistors MN14 to MN16 all include back gates.

[0281] In addition, Figure 15 In the circuit 100A3 shown, the connection destinations of the back gates of the transistors MN1 to MN4 , the transistors MN10 to MN12 , and the transistors MN14 to MN16 are clearly defined.

[0282] The gate of each of transistors MN1, MN3, MN10, and MN14 is electrically connected to the second gate. Furthermore, the back gate of transistor MN2 is electrically connected to wiring BG2. Furthermore, the back gate of transistor MN4 is electrically connected to wiring BG1. Furthermore, the back gates of transistors MN12 and MN16 are electrically connected to wiring BG3.

[0283] For example, wirings BG1 to BG3 are all used as wirings that supply a fixed potential. This fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. Furthermore, each of wirings BG1 to BG3 can supply a fixed potential that is equal to or unequal to each other. Furthermore, when two or more selected from wirings BG1 to BG3 supply a fixed potential that is equal to each other, the selected two or more wirings can be the same wiring. Furthermore, one or more selected from wirings BG1 to BG3 can be a wiring that supplies a variable potential instead of a fixed potential.

[0284] When wirings BG1 to BG3 are different from one another, different fixed potentials can be supplied to the back gates of transistors MN2, MN4, MN12, and MN16. In other words, the threshold voltages of transistors MN2, MN4, MN12, and MN16 can be independently controlled.

[0285] Therefore, for example, by supplying a negative potential to the back gate of the transistor MN2 and supplying a ground potential or a low-level potential (a potential higher than the negative potential) to the back gates of the transistors MN12 and MN16, the off-state currents of the transistors MN12 and MN16 can be made larger than the off-state current of the transistor MN2. Figure 11A or Figure 11B The circuits 100A[1] to 100A[m] of the driving circuit GD all adopt Figure 15 The circuit 100A3 can further improve the driving speed of the driving circuit GD.

[0286] <<Operation Example of Circuit 100A1>> Figure 16 is a timing chart showing an example of the operation of the circuit 100A1. For example, Figure 16 The timing chart shown in FIG. 1 shows the potential changes of the terminal IT, the terminal PWC, the terminal CLK1, the terminal CLK2, the node N1, the node N2, the terminal GT, and the terminal OT. Figure 16 In the example, the high level potential is recorded as V High , the low level potential is recorded as V Low.

[0287] Note that for simplicity of explanation of the operation of circuit 100A1, Figure 16 The length of the signal input period, the length of the output period, etc. shown in the timing diagram may differ from the actual circuit operation.

[0288] In this working example, the fixed potentials supplied by the wiring VDE1 and the wiring VDE2 are equal to each other in terms of the high-level potential V High In addition, the fixed potentials supplied by the wirings VSE1 to VSE5 are the same low-level potentials V Low .

[0289] Note that the high level potential V High and low level potential V Low Preferably, the high level potential V High and low level potential V Low The difference is higher than Figure 12 The threshold voltage potential of each transistor is shown.

[0290] [Time T1 to Time T2] During the period from time T1 to time T2, the terminal IT is supplied with a low-level potential V Low , the terminal PWC is supplied with a low level potential V Low , terminal CLK1 is supplied with V Low , the terminal CLK2 is supplied with a low level potential V Low In addition, the node N1 and the node N2 maintain a low level potential V Low .

[0291] A low-level potential V is supplied to the terminal CLK2. Low When the gate potential of transistor MN3 becomes a low level potential V Low In addition, it is assumed that the threshold voltage of the transistor MN3 is within an appropriate range. Therefore, the transistor MN3 is turned off.

[0292] The potential of the gate of the transistor MN4 (node ​​N2) is a low level potential V Low The second terminal of the transistor MN4 is supplied with the low-level potential V from the wiring VSE1. Low , so the transistor MN4 becomes off.

[0293] In addition, a low-level potential V is supplied to the terminal IT. Low When the first gate potential of the transistor MN1 becomes a low level potential V Low In addition, it is assumed that the threshold voltage of the transistor MN1 is within an appropriate range. Therefore, the transistor MN1 is turned off.

[0294] The potential of the gate of the transistor MN12 (node ​​N2) is a low-level potential V Low The second terminal of the transistor MN12 is supplied with the low-level potential V from the wiring VSE4. Low , so the transistor MN12 becomes off.

[0295] The potential of the gate of the transistor MN16 (node ​​N2) is a low level potential V Low The second terminal of the transistor MN16 is supplied with the low-level potential V from the wiring VSE5. Low , so the transistor MN16 becomes off.

[0296] The potential of the gate (terminal IT) of the transistor MN2 is a low-level potential V Low The second terminal of the transistor MN2 is supplied with the low-level potential V from the wiring VSE3. Low , so the transistor MN2 becomes off.

[0297] Note that in Figure 16 During the period from time T1 to time T2 of the timing chart, the potentials of the terminals OT and GT are each at a low level potential V Low During the period from time T1 to time T2, the potentials of the terminal OT and the terminal GT may be at the high level potential V High .

[0298] [Time T2 to Time T3] During the period from time T2 to time T3, the terminal CLK2 is supplied with a high-level potential V High .

[0299] A high-level potential V is supplied to the terminal CLK2. High When the gate potential of the transistor MN3 becomes a high level potential V High .

[0300] Here, the transistor MN3 is a normally-off transistor, and the threshold voltage of the transistor MN3 is V th_MN3 In addition, the threshold voltage V th_MN3 To meet V High -V Low >V th_MN3 voltage.

[0301] When the potential of the second terminal (node ​​N2) of the transistor MN3 is the low level potential V Low When the transistor MN3 is turned on, the charge from the wiring VDE2 is accumulated in the second terminal (node ​​N2) of the transistor MN3. High -Vth_MN3 When the charge is accumulated in the node N2, the transistor MN3 is turned off. As a result, the node N2 maintains the potential V High -V th_MN3 .

[0302] Note that when the potential of the second terminal (node ​​N2) of the transistor MN3 is higher than the high-level potential V High When the first terminal of the transistor MN3 is used as a source, the charge is released from the wiring VDE1 to the node N2. In addition, the potential of the second terminal (node ​​N2) of the transistor MN3 becomes V High -V th_MN3 When , the transistor MN3 becomes off. Thus, as described above, the node N2 maintains the potential V High -V th_MN3 .

[0303] In addition, during the period from time T2 to time T3, the terminal CLK2 is supplied with the high-level potential V High Then, a low level potential V Low Therefore, it is assumed that the first gate potential of the transistor MN3 becomes the low level potential V Low .

[0304] Through the above operation, the high-level potential V is supplied to the terminal CLK2 in the circuit 100A1. High The potential of the node N2 can be refreshed to a high level potential V High .

[0305] In addition, since the potential of node N2 is V High -V th_MN3 , so the potential of the first gate (node ​​N2) of transistor MN12 becomes V High -V th_MN3 , and the second terminal of the transistor MN12 is supplied with the low-level potential V from the wiring VSE4. Low , whereby the transistor MN12 is turned on. Therefore, the terminal OT and the wiring VSE4 are turned on, and the potential of the terminal OT becomes a low-level potential V Low .

[0306] In addition, since the potential of node N2 is V High -V th_MN3 , so the potential of the first gate (node ​​N2) of transistor MN16 becomes V High -V th_MN3 , and the second terminal of the transistor MN16 is supplied with the low-level potential V from the wiring VSE5 Low, whereby the transistor MN16 is turned on. Therefore, the terminal GT and the wiring VSE5 are turned on, and the potential of the terminal GT becomes a low-level potential V Low .

[0307] [Time T3 to Time T4] During the period from time T3 to time T4, the terminal IT is supplied with the low-level potential V Low , the terminal PWC is supplied with a low level potential V Low , terminal CLK1 is supplied with V Low , the terminal CLK2 is supplied with a low level potential V Low The potentials input to the terminal IT, the terminal PWC, the terminal CLK1, and the terminal CLK2 during the period from time T3 to time T4 are respectively equal to the potentials input to the terminal IT, the terminal PWC, the terminal CLK1, and the terminal CLK2 during the period from time T1 to time T2. Therefore, the operation example of the circuit 100A1 during the period from time T3 to time T4 can refer to the description of the operation example during the period from time T1 to time T2.

[0308] [Time T4 to Time T5] During the period from time T4 to time T5, the terminal IT is supplied with a high-level potential V High .

[0309] The first gate of the transistor MN2 is supplied with a high-level potential V from the terminal IT. High The second terminal of the transistor MN2 is supplied with V from the wiring VSE3. Low , so the transistor MN2 becomes on. As a result, the node N2 and the wiring VSE3 become conductive, so the potential of the node N2 changes from the high level potential V High becomes a low level potential V Low .

[0310] As a result, the potential of the first gate (node ​​N2) of the transistor MN4 is at a low level potential V Low The second terminal of the transistor MN4 is supplied with the low-level potential V from the wiring VSE1. Low , so the transistor MN4 becomes off.

[0311] In addition, the potential of the first gate (node ​​N2) of the transistor MN12 is a low-level potential V Low The second terminal of the transistor MN12 is supplied with the low-level potential V from the wiring VSE4. Low , so the transistor MN12 becomes off.

[0312] In addition, the potential of the first gate (node ​​N2) of the transistor MN16 is a low-level potential V LowThe second terminal of the transistor MN16 is supplied with the low-level potential V from the wiring VSE5. Low , so the transistor MN16 becomes off.

[0313] In addition, a high-level potential V is supplied through the terminal IT. High , the potential of the gate of transistor MN1 becomes a high level potential V High In addition, since the potential of the second terminal (node ​​N1) of the transistor MN1 is the low level potential V Low , so the transistor MN1 is turned on. Therefore, the charge from the wiring VDE1 is accumulated in the second terminal (node ​​N1) of the transistor MN1.

[0314] Here, transistor MN1 is a normally off transistor, and the threshold voltage of transistor MN1 is V th_MN1 In addition, the threshold voltage V th_MN1 To meet V High -V Low >V th_MN1 voltage.

[0315] Thus, until the gate-source voltage of the transistor MN1 (at this timing, the gate-second terminal voltage) reaches V High -V th_MN1 When the charge is accumulated in the node N1, the transistor MN1 is turned off. As a result, the node N1 maintains the potential V High -V th_MN1 .

[0316] In addition, during the period from time T4 to time T5, the terminal IT is supplied with the high-level potential V High Then, a low level potential V Low As a result, the potential of the gate of the transistor MN1 becomes a low-level potential V Low .

[0317] The gate of the transistor MN2 is supplied with a low-level potential V from the terminal IT. Low The second terminal of the transistor MN2 is supplied with the low-level potential V from the wiring VSE3. Low , so the transistor MN2 becomes off. As a result, the node N2 maintains the low level potential V Low .

[0318] [Time T5 to Time T6] During the period from time T5 to time T6, the terminal CLK1 is supplied with a high-level potential V High .

[0319] During the period from time T4 to time T5, the potential of the node N1 is at a high level potential V High -Vth_MN1 At this time, according to Figure 2A In the BSPR circuit, the terminal CLK1 is supplied with a high-level potential V High When the potential of the second terminal (terminal OT) of the transistor MN11 becomes a high-level potential V High .

[0320] [Time T6 to Time T7] During the period from time T6 to time T7, the terminal PWC is supplied with the high-level potential V High .

[0321] In addition, during the period from time T4 to time T6, the potential of the node N1 is V High -V th_MN1 At this time, according to Figure 2A In the BSPR circuit, the terminal PWC is supplied with a high-level potential V High When the potential of the second terminal (terminal GT) of the transistor MN15 also becomes the high level potential V High .

[0322] In addition, during the period from time T6 to time T7, the terminal PWC is supplied with the high-level potential V High Then, a low level potential V Low As a result, the potential of the second terminal (terminal GT) of the transistor MN15 becomes the low-level potential V Low .

[0323] [Time T8 to Time T9] During the period from time T8 to time T9, the terminal CLK1 is supplied with the low-level potential V Low .

[0324] As a result, the potential of the second terminal (terminal OT) of the transistor MN11 becomes the low-level potential V Low .

[0325] [Time T9 to Time T10] During the period from time T9 to time T10, the terminal CLK2 is supplied with a high-level potential V High At this time, the operation of the circuit 100A1 from time T9 to time T10 is the same as the operation from time T2 to time T3.

[0326] For example, a high-level potential V is supplied to the terminal CLK2. High When the potential of the second terminal (node ​​N2) of the transistor MN3 becomes a high level potential V High -V th_MN3As a result, the transistors MN4, MN12, and MN16 are turned on, and the potentials of the node N1, the terminal OT, and the terminal GT all become V Low .

[0327] [After time T10] For example, after time T10, a low-level potential V is input to the terminal CLK2. Low The variable potential of node N1 is V Low And the potential of node N2 is set to V High -V th_MN3 , then do not input V to terminal IT High The terminal CLK1 or the terminal PWC is supplied with V High The following describes a specific working example.

[0328] [Time T11 to Time T12] During the period from time T11 to time T12, the terminal CLK1 is supplied with V High .

[0329] The gate potential of transistor MN11 is V Low The first terminal of the transistor MN11 is supplied with V from the terminal CLK1. High , the potential of the second terminal of transistor MN11 is V Low At this time, the potential of the second terminal of the transistor MN11 is lower than the potential of the first terminal, so the second terminal of the transistor MN11 functions as a source and the transistor MN11 is turned off. As a result, the terminal CLK1 and the terminal OT are in a non-conductive state.

[0330] In addition, the gate potential of transistor MN12 is V High -V th_MN3 The second terminal of the transistor MN12 is supplied with V from the wiring VSE4. Low , so the transistor MN12 is turned on. Therefore, the terminal OT and the wiring VSE4 are turned on, and the potential of the terminal OT becomes V Low .

[0331] In addition, during the period from time T11 to time T12, the terminal CLK1 is supplied with V High Afterwards, V Low The potential of the first gate of transistor MN11 is V Low , the first terminal of the transistor MN11 is supplied with V from the terminal CLK1 Low , the potential of the second terminal of the transistor MN11 becomes V Low , whereby the transistor MN11 is turned off when the threshold voltage of the transistor MN11 is within an appropriate range.

[0332] As described above, even when V is input to terminal CLK2 Low The variable potential of the node N1 becomes V Low And the potential of node N2 becomes V High -V th_MN3 After that, do not input V to terminal IT High The terminal CLK1 is supplied with V High , the transistor MN11 also remains in the off state. In addition, even if V is supplied to the terminal CLK1 thereafter Low , the transistor MN11 also remains in the off state.

[0333] [Time T12 to Time T13] During the period from time T12 to time T13, the terminal PWC is supplied with V High .

[0334] The potential of the first gate of transistor MN15 is V Low The first terminal of the transistor MN15 is supplied with V from the terminal PWC. High , the potential of the second terminal of transistor MN15 is V Low At this time, the potential of the second terminal of the transistor MN15 is lower than the potential of the first terminal, so the second terminal of the transistor MN15 functions as a source and the transistor MN15 is turned off. As a result, the terminal PWC and the terminal GT are in a non-conductive state.

[0335] In addition, the potential of the first gate of the transistor MN16 is V High -V th_MN3 The second terminal of the transistor MN16 is supplied with V from the wiring VSE5. Low , so the transistor MN16 is turned on. Therefore, the terminal GT and the wiring VSE5 are turned on, and the potential of the terminal GT becomes V Low .

[0336] In addition, during the period from time T12 to time T13, the terminal PWC is supplied with V High Afterwards, V Low The potential of the first gate of transistor MN15 is V Low , the first terminal of the transistor MN15 is supplied with V from the terminal PWC Low , the potential of the second terminal of the transistor MN15 becomes V Low , whereby the transistor MN15 becomes off.

[0337] As described above, even when V is input to terminal CLK2 Low The variable potential of the node N1 becomes VLow And the potential of node N2 is set to V High -V th_MN3 After that, do not input V to terminal IT High While supplying V to terminal PWC High , the transistor MN15 also remains in the off state. In addition, even if V is supplied to the terminal PWC thereafter Low , transistor MN15 also remains in the off state.

[0338] The above describes an example of the operation of the circuit 100A1, but the operation method of the semiconductor device according to one embodiment of the present invention is not limited to this. For example, the operation method of the circuit 100A1 ( Figure 16 The timing diagram) can also be changed according to the situation.

[0339] <<Configuration Example of Drive Circuit SD>> Next, a configuration example of the drive circuit SD will be described.

[0340] Figure 17 Shown available for Figure 10 An example of a structure of a drive circuit SD of a display device DSP according to one embodiment of the present invention is shown. For example, Figure 17 The driving circuit SD shown includes a circuit SR, a circuit LAT, and a circuit DAC. In particular, the circuit SR includes, for example, circuits 100B[1] to 100B[n+2]. In addition, the circuit 100B[n+1] is a circuit for transmitting data from the terminal OT of the circuit 100B[n+1] to the terminal RT of the circuit 100B[n-1], and the circuit 100B[n+2] is a circuit for transmitting data from the terminal OT of the circuit 100B[n+2] to the terminal RT of the circuit 100B[n]. In addition, Figure 17 In FIG, circuits 100B[1] to 100B[6] are summarized.

[0341] For example, each of the circuits 100B[ 1 ] to 100B[n] includes a terminal IT, a terminal ST, a terminal CLK1 , a terminal CLK2 , a terminal CLK3 , a terminal OT, a terminal PWC, and a terminal RT.

[0342] Furthermore, in circuit SR, the wiring CLKLA to the wiring CLKLD and the wiring PWCLA to the wiring PWCLD are extended.

[0343] In circuit 100B[4k-3] (where k is an integer greater than or equal to 1 and satisfies 1≤4k-3≤n), terminal CLK1 is electrically connected to wiring CLKLA, terminal CLK2 is electrically connected to wiring CLKLB, terminal CLK3 is electrically connected to wiring CLKLC, and terminal PWC is electrically connected to wiring PWCLA. Furthermore, in circuit 100B[4k-2] (where k is an integer greater than or equal to 1 and satisfies 2≤4k-2≤n), terminal CLK1 is electrically connected to wiring CLKLB, terminal CLK2 is electrically connected to wiring CLKLC, terminal CLK3 is electrically connected to wiring CLKLD, and terminal PWC is electrically connected to wiring PWCLB. Furthermore, in circuit 100B[4k-1] (where k is an integer greater than or equal to 1 satisfying 3≤4k-1≤n), terminal CLK1 is electrically connected to wiring CLKLC, terminal CLK2 is electrically connected to wiring CLKLD, terminal CLK3 is electrically connected to wiring CLKLA, and terminal PWC is electrically connected to wiring PWCLC. Furthermore, in circuit 100B[4k] (where k is an integer greater than or equal to 1 satisfying 4≤4k≤n), terminal CLK1 is electrically connected to wiring CLKLD, terminal CLK2 is electrically connected to wiring CLKLA, terminal CLK3 is electrically connected to wiring CLKLB, and terminal PWC is electrically connected to wiring PWCLD.

[0344] The terminal OT of the circuit 100B[j] (where j is an integer from 1 to n) is electrically connected to the terminal IT of the circuit 100B[j+1]. In addition, the terminal RT of the circuit 100B[j] is electrically connected to the terminal OT of the circuit 100B[j+2].

[0345] Each terminal ST of circuit 100B[1] to circuit 100B[n] is electrically connected to each input terminal of circuit LAT. In addition, each output terminal of circuit LAT is electrically connected to each input terminal of circuit DAC. In addition, circuit LAT is electrically connected to wiring VDL. In addition, circuit LAT is electrically connected to wiring SPR. In addition, each output terminal of circuit DAC is electrically connected to wiring SL[1] to wiring SL[n]. Wiring SL[1] to wiring SL[n] is equivalent to Figure 10 The wiring SLS[1] to the wiring SLS[n] shown in FIG. Figure 17 Schematically showing the wirings SL[1] to SL[6].

[0346] Each of the circuits 100B[ 1 ] to 100B[n] has, for example, the following functions: a function of holding information input to the terminal IT; and a function of outputting the held information to one or both of the terminal ST and the terminal OT.

[0347] For example, circuit 100B[j] has a function of outputting information held in circuit 100B[j] to terminal OT when a high-level potential is input to terminal CLK1. Furthermore, circuit 100B[j] has a function of outputting information held in circuit 100B[j] to terminal ST when a high-level potential is input to terminal PWC. Furthermore, circuit 100B[j] has a function of resetting information held in circuit 100B[j] when a high-level potential is input to one or both of terminal CLK2, terminal CLK3, and terminal RT. Furthermore, circuit 100B[j] preferably has a configuration in which new information is input to terminal IT of circuit 100B[j] after resetting the information held in circuit 100B[j], thereby causing circuit 100B[j] to hold new information.

[0348] In other words, with Figure 11A and Figure 11B The driving circuit GD is similar, Figure 17 The circuit SR shown is used as a shift register circuit.

[0349] The wiring VDL is used as, for example, a wiring for transmitting a video signal displayed on the pixel circuit PX in the pixel array PA. Figure 17 In FIG, the wiring VDL is described as a wiring for transmitting digital data.

[0350] For example, circuit LAT includes holding circuits for n columns. Furthermore, circuit LAT has the function of holding the video signals input to wiring VDL in the holding circuits based on signals from terminals ST of circuits 100B[1] to 100B[n]. Specifically, for example, when the potential of terminal ST of circuit 100B[j] is high, circuit LAT holds the video signals input to wiring VDL in the holding circuits for the jth column. Furthermore, for example, when a high potential is input to wiring SPR, circuit LAT has the function of simultaneously outputting each video signal held in the holding circuits for the nth column to each output terminal of circuit LAT.

[0351] For example, the circuit DAC has a function of converting a video signal of digital data output from each output terminal of the circuit LAT into analog data (analog potential). Note that this analog data (analog potential) is sent to the wiring SL on the column.

[0352] In addition, Figure 17 In the driving circuit SD shown in the figure, wirings other than the wiring CLKLA to the wiring CLKLD and the wiring PWCLA to the wiring PWCLD may be extended. Figure 17 The structure of the driving circuit SD shown is an example, and the number of wirings, the electrical connection structure, etc. may be changed as appropriate.

[0353] Figure 18 : is a timing chart showing an example of the operation of the drive circuit SD. Figure 18 The potential changes of each of the wiring CLKLA to wiring CLKLD, wiring PWCLA to wiring PWCLD, terminal IT, terminal ST[1], terminal ST[2], terminal ST[3], terminal ST[n], and wiring SPR from time T21 to time T36 and in the vicinity thereof are shown. Terminal ST[j] is the terminal ST of circuit 100B[j]. In addition, Figure 18 The video signal V DT [1] to V DT [n] An example of sequential input to the wiring VDL.

[0354] During the period from time T21 to time T22, the wiring CLKLA and the wiring PWCLA are supplied with the high-level potential V High In addition, during the period from time T22 to time T23, the wiring CLKLB and the wiring PWCLB are supplied with the high-level potential V High In addition, during the period from time T23 to time T24, the wiring CLKLC and the wiring PWCLC are supplied with the high-level potential V High In addition, during the period from time T24 to time T25, the wiring CLKLD and the wiring PWCLD are supplied with the high-level potential V High After time T25, the high-level potential V is supplied to the wirings CLKLA to CLKLD and the wirings PWCLA to PWCLD at the same timing as during the period from time T21 to time T25. High .

[0355] By supplying the high-level potential V to each of the wirings CLKLA to CLKLD and the wirings PWCLA to PWCLD at the above timing, High Before time T21, the terminal IT is supplied with a high-level potential V High When the high level potential V is outputted from each terminal ST[1] to terminal ST[n] at a predetermined timing, High For example, during the period from time T21 to time T22, a high-level potential V is output from the terminal ST[1]. High , a high level potential V is output from the terminal ST[2] during the period from time T22 to time T23. High , a high level potential V is output from the terminal ST[3] during the period from time T23 to time T24. High For example, during the period from time T31 to time T32, a high-level potential V is output from the terminal ST[n-2]. High , a high-level potential V is output from the terminal ST[n-1] during the period from time T32 to time T33. High, a high-level potential V is output from the terminal ST[n] during the period from time T33 to time T34. High .

[0356] Note that in Figure 18 The timing diagram shows the case where n is a multiple of 4. In the drive circuit SD, when n is not a multiple of 4, the potentials supplied to the wirings CLKLA to CLKLD and the wirings PWCLA to PWCLD during the period from time T30 to time T34 may be appropriately changed.

[0357] In addition, the circuit LAT outputs a high-level potential V from the terminal ST[1]. High The timing of the video signal V input to the wiring VDL DT [1] is held in the holding circuit of the first column. In addition, a high level potential V is output from the terminal ST[2]. High The timing of the video signal V input to the wiring VDL DT [2] The holding circuit in the second column outputs a high-level potential V from the terminal ST[3]. High The timing of the video signal V input to the wiring VDL DT [3] is held in the holding circuit of the third column. The same operation is performed sequentially, and a high level potential V is output from the terminal ST[n]. High The timing of the video signal V input to the wiring VDL DT [n] is held in the holding circuit for column n.

[0358] In addition, during the period from time T34 to time T35, the potential of the wiring SPR is changed to the high-level potential V High The circuit LAT stores the video signal V held by the holding circuits of the n columns in the circuit LAT. DT [1] to V DT [n] is output to the circuit DAC through each output terminal of the circuit LAT.

[0359] The drive circuit SD performs the above Figure 18 The working example of the timing diagram can send a video signal to each pixel circuit of the pixel array PA.

[0360] Figure 19 The circuit structure of the circuit 100B1 can be used for each of the circuits 100B[1] to 100B[n] in the driving circuit SD.

[0361] For example, circuit 100B1 includes circuit BSPRi, transistors MN21, MN24, MN25, MN28, MN31, MN34, MN40, MN41, and capacitor C26. Furthermore, circuit 100B1 includes, for example, terminal IT, terminal PWC, terminal CLK1, terminal CLK2, terminal CLK3, terminal RT, terminal OT, and terminal ST.

[0362] For example, transistors that can be used for transistors MN1, MN3, MN11, and MN12 can be used for transistors MN21, MN25, MN28, MN31, MN36, MN37, MN40, and MN41. Specifically, for example, transistors MN21, MN25, MN28, MN31, MN36, MN37, MN40, and MN41 can be used for transistors MN1, MN3, MN11, and MN12. Figures 6A to 6C or 7A to 7C In addition, as the above transistors, you can use Figures 3A to 3C 、 Figures 4A to 4C or Figures 5A to 5C The transistor ML may be a transistor of other structures.

[0363] As the transistor MN24 and the transistor MN34, for example, the transistors that can be used for the transistor MN2 and the transistor MN4 can be used. Specifically, for example, as the transistor MN24 and the transistor MN34, the transistors that can be used for the transistor MN2 and the transistor MN4 can be used. Figures 3A to 3C transistor ML, Figures 4A to 4C transistor or Figures 5A to 5C In addition, depending on the situation, as each of the above transistors, you can use Figures 6A to 6C The transistor MV or 7A to 7C The transistor MV can also use transistors of other structures.

[0364] In addition, Figure 19 In the circuit 100B1, the circuit BSPRi adopts the change Figure 2A Specifically, the circuit BSPRi adopts a circuit structure of Figure 2A The circuit shown has a BSPR circuit structure with one additional transistor.

[0365] The circuit BSPRi includes the equivalent of Figure 2A The circuit BSPR of the circuit BB of the circuit BBi is equivalent to Figure 2A The transistor MNb of the circuit BSPR is equivalent to the transistor MN37. Figure 2AThe capacitor Ca of the circuit BSPR is the capacitor C25 and the transistor MN36.

[0366] The first gate of transistor MN21 is electrically connected to the first gate of transistor MN34 and terminal IT, and the first terminal of transistor MN21 is electrically connected to wiring VDE21. In addition, the second terminal of transistor MN21 is electrically connected to the first terminal of transistor MN24 and terminal Bi of circuit BBi.

[0367] The gate of the transistor MN25 is electrically connected to the terminal CLK3, and the first terminal of the transistor MN25 is electrically connected to the wiring VDE22. In addition, the second terminal of the transistor MN25 is electrically connected to the first terminal of the transistor MN28. In addition, the gate of the transistor MN28 is electrically connected to the terminal CLK2.

[0368] A first gate of transistor MN31 is electrically connected to terminal RT, and a first terminal of transistor MN31 is electrically connected to wiring VDE23. Furthermore, a second terminal of transistor MN31 is electrically connected to the second terminal of transistor MN28, the gate of transistor MN24, the first terminal of capacitor C26, the first terminal of transistor MN34, the gate of transistor MN40, and the gate of transistor MN41.

[0369] The gate of transistor MN36 is electrically connected to terminal Bo of circuit BBi, the first terminal of capacitor C25, and the gate of transistor MN37. The first terminal of transistor MN36 is electrically connected to terminal CLK1. The second terminal of transistor MN36 is electrically connected to the first terminal of transistor MN40 and terminal OT. The first terminal of transistor MN37 is electrically connected to terminal PWC. The second terminal of transistor MN37 is electrically connected to the second terminal of capacitor C25, the first terminal of transistor MN41, and terminal ST.

[0370] The second terminal of transistor MN24 is electrically connected to wiring VSE11. Furthermore, the second terminal of capacitor C26 is electrically connected to wiring VSE12. Furthermore, the second terminal of transistor MN34 is electrically connected to wiring VSE13. Furthermore, the second terminal of transistor MN40 is electrically connected to wiring VSE14. Furthermore, the second terminal of transistor MN41 is electrically connected to wiring VSE15.

[0371] For example, the wirings VDE21 to VDE23 can refer to the description of the wirings VDE1 to VDE4 , respectively.

[0372] For the wirings VSE11 to VSE15 , for example, the description of the wirings VSE1 to VSE5 can be referred to, respectively.

[0373] Figure 20 Another specific example of the circuit 100B1 is shown. Figure 20 The circuit 100B2 shown has the Figure 8A The circuit BSPR is used for Figure 19 In this case, the transistor MN35 in the circuit BBi is preferably used. Figures 6A to 6C The transistor MV or 7A to 7C Alternatively, transistor MN35 may be used depending on the situation. Figures 3A to 3C transistor ML, Figures 4A to 4C transistor ML, Figures 5A to 5C The transistor is an ML or other structured transistor.

[0374] exist Figure 20 In FIG, a gate of the transistor MN35 is electrically connected to the wiring VDE35, a first terminal of the transistor MN35 is electrically connected to the terminal Bi, and a second terminal of the transistor MN35 is electrically connected to the terminal Bo.

[0375] As an example, the wiring VDE35 has the function of supplying a fixed potential. The fixed potential may be, for example, a high-level potential. Alternatively, the wiring VDE35 may be a wiring that supplies a variable potential instead of a fixed potential.

[0376] Furthermore, at least one of the wirings VDE21 to VDE23 and the wiring VDE35 may be supplied with fixed potentials equal to or unequal to each other. Furthermore, when at least one of the wirings VDE21 to VDE23 and the wiring VDE35 are supplied with fixed potentials equal to each other, at least one of the wirings VDE21 to VDE23 and the wiring VDE35 may be the same wiring.

[0377] Furthermore, the structure of the driver circuit SD of the semiconductor device according to one embodiment of the present invention is not limited to Figure 17 For example, Figure 17 The drive circuit SD can also be changed to Figure 21 The circuit structure shown.

[0378] Figure 21 The driving circuit SD shown is not provided with the circuit LAT and the circuit DAC and includes switches SSW[1] to SSW[n] (in Figure 21 In the figure, switches SSW[1] to SSW[6] are shown in summary form, which is similar to Figure 17 The structure of the driving circuit SD is different.

[0379] Each of switches SSW[1] to SSW[n] can be, for example, an analog switch or an electrical switch such as a transistor. When a transistor is used as each of switches SSW[1] to SSW[n], the transistor can have the same structure as transistor MN1 or transistor MN2. Furthermore, a mechanical switch can also be used in addition to an electrical switch.

[0380] Furthermore, switches SSW[1] through SSW[n] all include a control terminal. This control terminal functions as a terminal for receiving a signal for controlling switch SSW[j]. In this specification, inputting a high-level potential to the control terminal of switch SSW[j] turns switch SSW[j] on, and inputting a low-level potential to the control terminal of switch SSW[j] turns switch SSW[j] off.

[0381] exist Figure 21 In the embodiment of the present invention, terminal ST of circuit 100B[j] (where j is an integer greater than or equal to 1 and less than or equal to n) is electrically connected to the control terminal of switch SSW[j]. Furthermore, a first terminal of switch SSW[j] is electrically connected to wiring VDL, and a second terminal of switch SSW[j] is electrically connected to wiring SL[j].

[0382] in addition, Figure 21 The wiring VDL in is used as a wiring for sending a video signal as analog data to each first terminal of the switch SSW[1] to the switch SSW[n].

[0383] In addition, although Figure 21 Although not shown, the wiring VDL is electrically connected to the video signal generation circuit. As an example, the video signal generation circuit includes a digital-to-analog conversion circuit and a buffer circuit. The video signal generation circuit, for example, has the following functions: the digital-to-analog conversion circuit converts the video signal, which is digital data, into analog data, and the buffer circuit outputs the converted analog video signal to the wiring VDL.

[0384] exist Figure 21 In the driving circuit SD, by inputting a start pulse signal to the terminal IT and then periodically inputting a clock signal, a high-level potential can be output successively from each terminal ST of the circuit 100B[1] to the circuit 100B[n]. As a result, the switches SSW[1] to SSW[n] can be turned on one by one from the first column. In addition, by sending a video signal from the video signal generating circuit to the wiring VDL according to the timing when the switch SSW[j] turns on, the video signal can be written to the pixel circuit PX located in the j-th column of the pixel array PA. That is, by using Figure 21 The driving circuit SD can perform line sequential driving.

[0385] exist Figure 17 In the driving circuit SD, the scale of the circuit LAT and the circuit DAC becomes larger according to the number of columns, but Figure 21 In the driving circuit SD, the video signal generating circuit can be connected only to the wiring VDL. Figure 21 The circuit area of ​​the driving circuit SD is smaller than Figure 17 The circuit area of ​​the driving circuit SD.

[0386] Note that the operation of the above-mentioned switch SSW[j] is only an example. The switch SSW[j] can also be turned on by inputting a low-level potential to the control terminal of the switch SSW[j], and the switch SSW[j] can be turned off by inputting a high-level potential to the control terminal of the switch SSW[j].

[0387] <Structure Example 2 of Holding Circuit> The circuit 100A1 and the circuit 100B1 can include Figure 11A and Figure 11B The shift register circuit shown, Figure 17 The following describes a structural example of a holding circuit in circuit SR, etc.

[0388] Figure 22 The circuit 100C1 shown includes a terminal ITA, a terminal ITB, a terminal CLK3, and a terminal CLK4 serving as input terminals. In addition, the circuit 100C1 includes a terminal OTA, a terminal OTB, and a terminal NT serving as output terminals.

[0389] Furthermore, when considering the shift register circuit, the terminal OTA of the preceding circuit 100C1 is electrically connected to the terminal ITA of the succeeding circuit 100C1 , and the terminal OTB of the preceding circuit 100C1 is electrically connected to the terminal ITB of the succeeding circuit 100C1 .

[0390] Furthermore, circuit 100C1 includes terminals CLK4 and CLK5. Terminals CLK4 and CLK5 are, for example, equivalent to terminals CLK1 to CLK3 in circuit 100B1. Therefore, pulse potentials are input to terminals CLK4 and CLK5 of circuit 100C1. The pulse potentials input to terminals CLK4 and CLK5 can be equal or unequal. Note that equal pulse potentials refer to pulse potentials with the same timing and pulse width.

[0391] Furthermore, the circuit 100C1 includes a terminal NT. The terminal NT is a terminal equivalent to the terminal GT in the circuit 100A1 or the terminal ST in the circuit 100B1.

[0392] The circuit 100C1 includes, for example, transistors MN51 to MN54, transistor MN56, transistor MN57, transistor MN59, capacitor C6, capacitor C8, and circuit BSPRj. Figure 22 As shown, the circuit 100C1 is a unipolar circuit including no p-channel transistors and n-channel transistors.

[0393] in addition, Figure 22 The circuit BSPRj shown has the same Figure 1 The circuit BSPRj has the same circuit structure as the circuit BSPR shown in FIG. Therefore, the circuit BSPRj includes, for example, a transistor MN58, a capacitor C7, and a circuit BBj. Note that Figure 22 The circuit BBj in the circuit BSPRj can also have the same Figure 1 The circuit structure of circuit BSPR is the same as that of circuit BB.

[0394] In addition, Figure 22 In the circuit 100C1, the transistors MN51 to MN57 and the transistor MN59 have a single-gate structure, but transistors having a multi-gate structure including gates above and below a channel may also be used.

[0395] A first terminal of capacitor C6 is electrically connected to the first terminal of transistor MN52 and terminal CLK5. A second terminal of capacitor C6 is electrically connected to the first terminal of transistor MN51, the gate of transistor MN52, and the first terminal of transistor MN53. A second terminal of transistor MN51 is electrically connected to wiring VSE6, and the gate of transistor MN51 is electrically connected to terminal ITB. A second terminal of transistor MN53 is electrically connected to wiring VSE7, and the gate of transistor MN53 is electrically connected to terminal CLK4. A second terminal of transistor MN52 is electrically connected to the gate of transistor MN56, the first terminal of transistor MN57, the gate of transistor MN59, and the first terminal of capacitor C8. A second terminal of transistor MN57 is electrically connected to wiring VSE9. A second terminal of capacitor C8 is electrically connected to wiring VSE10.

[0396] A first terminal of transistor MN54 is electrically connected to wiring VDE6. A second terminal of transistor MN54 is electrically connected to terminal Bi of circuit BBj, the gate of transistor MN57, a first terminal of transistor MN56, and terminal OTB. A second terminal of transistor MN56 is electrically connected to wiring VSE8. Terminal Bo of circuit BBj is electrically connected to the gate of transistor MN58 and the first terminal of capacitor C7. A first terminal of transistor MN58 is electrically connected to terminal CLK5. A second terminal of transistor MN58 is electrically connected to the second terminal of capacitor C7, the first terminal of transistor MN59, terminal OTA, and terminal NT. A second terminal of transistor MN59 is electrically connected to wiring VSE11.

[0397] The wiring VDE6 has a function of supplying a fixed potential, for example, which may be a high-level potential.

[0398] As an example, wirings VSE6 through VSE11 all function as wirings supplying a fixed potential. This fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. Furthermore, each of wirings VSE6 through VSE11 can supply a fixed potential that is equal to or different from each other. Furthermore, two or more wirings from wirings VSE6 through VSE11 can supply a fixed potential that is equal to each other, while the remaining wirings can supply a potential that is different from the fixed potential. Furthermore, two or more wirings from wirings VSE6 through VSE11 that supply a fixed potential that is equal to each other can be the same wiring. For example, if wirings VSE6 and VSE7 supply a fixed potential that is equal to each other, wirings VSE6 and VSE7 can be the same wiring.

[0399] One or more of the wirings VSE6 to VSE11 may have a function of supplying a variable potential instead of a fixed potential.

[0400] When stabilizing the operation of the circuit 100C1, similarly to the circuits 100A1 and 100B1, it is preferable that the potential of the terminal Bi of the circuit BBj (equivalent to the node N1 in the circuit 100A1) and the potential of the gate of the transistor MN59 (equivalent to the node N2 in the circuit 100A1) do not fluctuate due to unintended factors such as leakage current. Therefore, for example, it is preferable to use transistors MN56 and MN57. Figures 3A to 3C transistor ML, Figures 4A to 4C The transistor ML or Figures 5A to 5C As described above, the transistor ML can have a very low off-state current, so by using the transistor ML for the transistor MN56 and the transistor MN57, the potentials of the terminal Bi of the circuit BBj and the gate of the transistor MN59 can be prevented from fluctuating due to leakage current. In addition, depending on the situation, the transistor MN56 and the transistor MN57 can be used Figures 6A to 6C The transistor MV, 7A to 7C The transistor is MV or a transistor of other structures.

[0401] In addition, transistors MN51 to MN55, transistor MN57 and transistor MN59 are preferably used. Figures 6A to 6C The transistor MV or 7A to 7C In addition, as the above transistors, you can use Figures 3A to 3C transistor ML, Figures 4A to 4Ctransistor ML, Figures 5A to 5C The transistor is an ML or other structured transistor.

[0402] Figure 23 Another specific example of the circuit 100C1 is shown. Figure 23 The circuit 100C2 shown has the Figure 8A The circuit BSPR is used for Figure 22 In this case, the transistor MN55 in the circuit BBj is preferably used. Figures 6A to 6C The transistor MV or 7A to 7C Alternatively, transistor MN55 may be used depending on the situation. Figures 3A to 3C transistor ML, Figures 4A to 4C transistor ML, Figures 5A to 5C The transistor is an ML or other structured transistor.

[0403] exist Figure 23 In FIG, a gate of the transistor MN55 is electrically connected to the wiring VDE7, a first terminal of the transistor MN55 is electrically connected to the terminal Bi, and a second terminal of the transistor MN55 is electrically connected to the terminal Bo.

[0404] As an example, the wiring VDE7 functions as a wiring for supplying a fixed potential. This fixed potential may be, for example, a high-level potential.

[0405] Wiring VDE6 and wiring VDE7 may supply equal or unequal fixed potentials. Furthermore, when wiring VDE6 and wiring VDE7 supply equal fixed potentials, wiring VDE6 and wiring VDE7 may be the same wiring. Alternatively, one or both of wiring VDE6 and wiring VDE7 may be a wiring that supplies a variable potential instead of a fixed potential.

[0406] Note that this embodiment mode can be combined with the same or other embodiment modes described in this specification as appropriate. For example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in this embodiment mode as appropriate. Furthermore, for example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in other embodiment modes as appropriate.

[0407] (Implementation Method 2) In this embodiment, another configuration example of the holding circuit described in Embodiment 1 will be described.

[0408] <Structure Example 3 of Holding Circuit> Figure 24 The circuit 100A4 shown is Figure 12The variation of the circuit 100A1 shown is different from the circuit 100A1 in that the circuit OPC in the circuit 100A4 includes the circuit FBa and the circuit FBb.

[0409] As an example, each of the circuit FBa and the circuit FBb includes a terminal Fi functioning as an input terminal and a terminal Fo functioning as an output terminal.

[0410] Terminal Fi of circuit FBa is electrically connected to terminal OT, the second terminal of capacitor C1, the second terminal of transistor MN11, and the first terminal of transistor MN12. Terminal Fo of circuit FBa is electrically connected to terminal Bi of circuit BBa, terminal Bi of circuit BBb, the second terminal of transistor MN1, the first terminal of transistor MN4, and terminal Fo of circuit FBb. Terminal Fi of circuit FBb is electrically connected to terminal GT, the second terminal of capacitor C2, the second terminal of transistor MN15, and the first terminal of transistor MN16.

[0411] Circuit FBa (circuit FBb), for example, has a function of obtaining the potential output from terminal To of circuit BSPRa (circuit BSPRb) and supplying a fixed potential to terminal Ti of circuit BSPRa (circuit BSPRb). In other words, circuit FBa (circuit FBb) is a circuit that provides feedback to circuit BSPRa (circuit BSPRb) based on the potential output from terminal To of circuit BSPRa (circuit BSPRb). Specifically, for example, circuit FBa (circuit FBb) may also have a function of receiving a high-level potential V at terminal Fi. High When a fixed potential (e.g., a high level potential V High ) structure.

[0412] By making the circuit FBa (circuit FBb) have the above-mentioned structure, for example, when the high-level potential V is output from the terminal To of the circuit BSPRa (circuit BSPRb), HighWhen a voltage is applied to terminal Ti of circuit BSPRa (circuit BSPRb), a fixed potential output from terminal Fo of circuit FBa (circuit FBb) is supplied to terminal Ti of circuit BSPRa (circuit BSPRb). Therefore, for example, even if the off-state current flowing between the source and drain or the leakage current flowing between the gate and source or gate and drain of the transistor used to maintain the potential of terminal Ti of circuit BSPRa (circuit BSPRb) increases, the potential of terminal Ti remains at the fixed potential supplied by circuit FBa (circuit FBb). Furthermore, even when a noise signal is input to terminal Ti, the potential of terminal Ti remains at the fixed potential supplied by circuit FBa (circuit FBb). Therefore, the potential of terminal To of circuit BSPRa (circuit BSPRb) does not change due to the aforementioned factors, and the potential of node N is not easily affected. Consequently, the potential output from terminal To of circuit BSPRa (circuit BSPRb) is stable.

[0413] Figure 25 Show Figure 24 A specific example of circuit 100A4 is circuit FBa. Figure 25 The circuit 100A5 shown is specifically shown Figure 24 The circuit 100A4 is a circuit FBa of the circuit 100A4. In addition, the circuit BSPRa of the circuit 100A5 is used. Figure 8A circuit BSPR. Note that Figure 25 In the configuration example of the circuit 100A5, the circuit FBb is not provided.

[0414] In the circuit 100A5, the circuit FBa includes a transistor MN17. The gate of the transistor MN17 is electrically connected to the terminal Fi, the first terminal of the transistor MN17 is electrically connected to the terminal Fo, and the second terminal of the transistor MN17 is electrically connected to the wiring VDE5.

[0415] Note that transistor MN17 is preferably used Figures 6A to 6C The transistor MV or 7A to 7C In addition, depending on the situation, transistor MN17 can also be used Figures 3A to 3C transistor ML, Figures 4A to 4C transistor ML, Figures 5A to 5C The transistor is an ML or other structured transistor.

[0416] As an example, wiring VDE5 functions as a wiring for supplying a fixed potential. This fixed potential can be, for example, a high-level potential. Alternatively, it can be a low-level potential, ground potential, or a negative potential, depending on the situation. Alternatively, wiring VDE5 can function as a wiring for supplying a variable potential.

[0417] Here, it is explained Figure 25For example, it is assumed that a high-level potential V is supplied from the wiring VDE5 to the second terminal of the transistor MN17. High .

[0418] <Operation Example of Circuit 100A4> As an example of the operation of the circuit 100A4, please refer to Figure 16 Therefore, the operation example of the circuit 100A4 which is different from the timing chart of the circuit 100A1 will be mainly described.

[0419] Figure 26 A timing chart showing an operation example of the circuit 100A4 is shown. Figure 26 The operation from time T5 to time T10 in the timing diagram is Figure 16 The timing diagram is different.

[0420] In addition, it is assumed that a high-level potential V is supplied from the wiring VDE5 to the second terminal of the transistor MN17. High .

[0421] During the period from time T4 to time T5, a high-level potential V is input through the terminal IT. High , the potential of node N1 becomes V High -V th_MN1 , the terminal Ti of the circuit BSPRa is input with V High -V th_MN1 At this time, the circuit BBa outputs the potential V to the terminal Bo. Mid As a result, the gate of the transistor MN11 (the first terminal of the capacitor C1) is supplied with V Mid .

[0422] In addition, a low-level potential V is supplied from the terminal CLK1 to the first terminal of the transistor MN11. Low At this time, the gate-source voltage of the transistor MN11 (at this time, the gate-first terminal voltage) becomes V Mid -V Low , so the transistor MN11 is turned on. Therefore, the terminal CLK1 outputs a low-level potential V to the terminal To of the circuit BSPRa through the transistor MN11. Low That is, the potential of terminal OT becomes V Low .

[0423] Therefore, the terminal Fi of the circuit FBa is input with the same potential as the terminal To. Low As a result, the gate of the transistor MN17 is supplied with a low-level potential V Low .

[0424] In addition, the transistor MN17 is a normally closed transistor, and the threshold voltage of the transistor MN17 is recorded as V th_MN17 In addition, the threshold voltage V th_MN17 To meet V High -V Low >V th_MN17 voltage.

[0425] Here, the gate-source voltage (here, the gate-first terminal voltage) of the transistor MN17 is V Low -V High <V th_MN17 , so the transistor MN17 becomes off.

[0426] During the period from time T5 to time T6, the potential supplied from the terminal CLK1 to the first terminal of the transistor MN11 changes from the low-level potential V Low becomes a high level potential V High In addition, the node N is made to float using the circuit BBa. At this time, the gate-source voltage of the transistor MN11 (at this time, the gate-second terminal voltage) becomes V Mid -V Low , so the transistor MN11 becomes on. Therefore, current flows from the terminal CLK1 through the transistor MN11 to the terminal To of the circuit BSPR, and the potential of the terminal To increases from V Low In addition, the node N is in a floating state, so through the capacitive coupling of the capacitor C1, the potential of the node N also increases from V Mid As a result, the gate-source voltage of the transistor MN11 is maintained by the capacitor C1, and the potential of the terminal To increases to V High In addition, ideally, the potential of the node N is V Mid +V High -V Low .

[0427] At this time, the terminal Fi of the circuit FBa is input with the same potential as the terminal To (terminal OT). High As a result, the gate of the transistor MN17 is supplied with a high-level potential V High .

[0428] Here, the gate-source voltage (here, the gate-first terminal voltage) of the transistor MN17 is, for example, V High -(V High -V th_MN1 )=V th_MN1 . In V th_MN1 Higher than V th_MN17 When the transistor MN17 is turned on, the potential of the node N1 becomes V High-V th_MN17 When the potential of node N1 reaches V High -V th_MN17 When V th_MN1 Lower than V th_MN17 In the case of , since the transistor MN17 is normally off, the transistor MN17 is in the off state. In addition, as the potential of the node N1 at this time, since the transistor MN17 is normally off, the transistor MN17 is in the off state. Note that Figure 26 Shown V th_MN1 Higher than V th_MN17 situation.

[0429] In this state, when the potential of the terminal Ti of the circuit BSPRa (the first terminal of the transistor MN17) is lower than V High -V th_MN17 When the voltage between the gate and the first terminal of the transistor MN17 exceeds the threshold voltage, the transistor MN17 turns on. At this time, the charge from the wiring VDE5 is accumulated in the terminal Ti of the circuit BSPRa, and the potential of the terminal Ti of the circuit BSPRa rises. Specifically, the voltage between the gate and the source of the transistor MN17 becomes V th_MN17 , so the potential of the terminal Ti (the first terminal of the transistor MN17) of the circuit BSPRa returns to V High -V th_MN17 .

[0430] As described above, in the circuit FBa, when the high-level potential V is output from the terminal To of the circuit BSPRa, High When the potential of the terminal Ti of the circuit BSPRa drops, the circuit FBa can supply the potential V to the terminal Ti. High -V th_MN17 Therefore, the potential of terminal Ti is kept roughly V High -V th_MN17 , so the potential output from the terminal To of the circuit BSPRa is stable.

[0431] Note that the semiconductor device of one embodiment of the present invention is not limited to Figure 24 The circuit 100A4 and Figure 25 The circuit 100A5 shown. For example, in Figure 25 In the circuit 100A5, at least one of the transistors MN1 to MN4, the transistors MN10 to MN12, and the transistors MN14 to MN17 may also be a transistor including a back gate.

[0432] Figure 27 A specific structural example is shown. Figure 27The circuit 100A6 shown is Figure 25 This is a modified example of the circuit 100A5 and differs from the circuit 100A5 in that the transistors MN1 to MN4, the transistors MN10 to MN12, and the transistors MN14 to MN17 all include back gates.

[0433] In addition, Figure 27 In the circuit 100A6 shown, the connection destinations of the back gates of the transistors MN1 to MN4 , the transistors MN10 to MN12 , and the transistors MN14 to MN17 are clearly defined.

[0434] Note that the back gates of transistors MN1 to MN4, transistors MN10 to MN12, and transistors MN14 to MN16 are connected to the same Figure 15 The structure of circuit 100A3 is the same.

[0435] The back gate of the transistor MN17 is electrically connected to the gate of the transistor MN17 , thereby increasing the amount of on-state current of the transistor MN17 .

[0436] By adopting the above-described structure, the driving speed of the circuit 100A6 can be increased compared to the circuits 100A4 and 100A5 .

[0437] <Layout Example of Holding Circuit> Next, an example of a layout diagram (plan view) of the holding circuit will be described.

[0438] Figure 28 yes Figure 13 The layout diagram of the circuit 100A2 is shown in FIG. Figure 28 The back gates of transistors MN1 to MN4, transistors MN10 to MN12, and transistors MN14 to MN16 are not shown in the layout diagram of FIG. Figure 28 The back gate is set in the layout diagram.

[0439] In addition, Figure 28 In the embodiment, the circuit 100A2 includes, for example, a conductive layer GEM, a conductive layer SDMB, a conductive layer SDMT, and a semiconductor layer SMC. Figure 28 The insulating layer in the circuit 100A2 is not shown.

[0440] The semiconductor layer SMC is located below the conductive layer GEM, for example. In addition, the conductive layer SDMT is located below the semiconductor layer SMC, for example. In addition, the conductive layer SDMB is located below the conductive layer SDMT, for example. That is, Figure 28In the circuit 100A2, a conductive layer SDMB, a conductive layer SDMT, a semiconductor layer SMC, and a conductive layer GEM are sequentially formed from the bottom.

[0441] A portion of the conductive layer GEM is used as, for example, a gate (sometimes referred to as a first gate) of each of the transistors MN1 to MN4 , the transistors MN10 to MN12 , and the transistors MN14 to MN16 .

[0442] A portion of the conductive layer SDMT is used as a source or a drain in the transistor MN2 and the transistor MN4 , for example.

[0443] Furthermore, a portion of each of the conductive layer SDMB and the conductive layer SDMT is used as a source or a drain of each of the transistors MN1 , MN3 , MN10 to MN12 , and MN14 to MN16 .

[0444] The conductive layer SDMB, the conductive layer SDMT, the semiconductor layer SMC, and the conductive layer GEM can all be formed using, for example, photolithography. Specifically, when forming the conductive layer GEM, the conductive material that will become the conductive layer GEM is formed using one or more methods selected from sputtering, CVD (Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition), and then the desired pattern is formed using photolithography. Furthermore, the conductive layer SDMB, the conductive layer SDMT, and the semiconductor layer SMC can also be formed using the same method as described above.

[0445] Furthermore, insulating layers may be provided between the semiconductor layer SMC and the conductive layer GEM, between the conductive layer GEM and the conductive layer SDMT, and between the conductive layer SDMB and the conductive layer SDMT. In particular, the insulator provided between the semiconductor layer SMC and the conductive layer GEM is sometimes used as a gate insulating film (sometimes referred to as a first gate insulating film, a front gate insulating film, etc.).

[0446] Furthermore, in region CR5 where a portion of conductive layer SDMT overlaps a portion of conductive layer GEM, conductive layer SDMT and conductive layer GEM are partially conductive. Specifically, conductive layer SDMT in transistor MN3 is conductively connected to the gates of transistors MN4, MN12, and MN16.

[0447] Furthermore, in the region CR1 where a portion of the conductive layer SDMB overlaps a portion of the conductive layer GEM, a portion of the conductive layer SDMB is electrically connected to a portion of the conductive layer GEM, that is, thereby electrically connecting the conductive layer SDMB in the transistor MN10 to the gate of the transistor MN11.

[0448] Furthermore, in the region CR2 where a portion of the conductive layer SDMB overlaps a portion of the conductive layer GEM, a portion of the conductive layer SDMB is electrically connected to a portion of the conductive layer GEM, that is, thereby electrically connecting the conductive layer SDMB in the transistor MN14 to the gate of the transistor MN15.

[0449] in addition, Figure 28 The illustrated capacitors C1, C2, and C5 all include portions of the conductive layer SDMB and the conductive layer GEM, respectively. Specifically, for example, capacitor C1 includes a region where a portion of the conductive layer SDMB overlaps with a portion of the conductive layer GEM. In other words, in capacitor C1, a portion of the conductive layer SDMB serves as one of a pair of electrodes, while a portion of the conductive layer GEM serves as the other. Similarly to capacitor C1, in each of capacitors C2 and C5, a portion of the conductive layer SDMB serves as one of a pair of electrodes, while a portion of the conductive layer GEM serves as the other.

[0450] Note that the layout diagram of the display device according to one embodiment of the present invention is not limited to Figure 28 The layout diagram of the display device according to one embodiment of the present invention may be appropriately changed. Figure 28 The resulting layout diagram.

[0451] Note that this embodiment mode can be combined with the same or other embodiment modes described in this specification as appropriate. For example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in this embodiment mode as appropriate. Furthermore, for example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in other embodiment modes as appropriate.

[0452] (Implementation 3) In this embodiment, a circuit configuration that can be used in the pixel circuit PX described in Embodiment 1 will be described.

[0453] <Pixel Circuit Configuration Example 1> Figure 29A This is a diagram showing the method that can be used in the first embodiment. Figure 10 A circuit diagram showing an example of the circuit configuration of a pixel circuit PX of a display device DSP.

[0454] As an example, Figure 29A The pixel circuit PX1 shown includes a transistor Tr1 , a transistor Tr2 , a capacitor Cs1 , a capacitor Cs2 , and a light emitting device ED.

[0455] As the light-emitting device ED, for example, a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting diode (for example, a Micro LED (Light Emitting Diode)) can be cited. In addition, the pixel circuit PX1 can be a pixel circuit using one or more of the light-emitting devices ED selected from the above. Note that in this embodiment, a case where a light-emitting device including an organic EL material is used in the pixel circuit PX of the pixel array PA is described. In particular, the brightness of light emitted from a light-emitting device capable of emitting light at high brightness can be, for example, 500 cd / m 2 Above, preferably 1000 cd / m 2 Above and 10000cd / m 2 Below, more preferably 2000 cd / m 2 Above and 5000cd / m 2 the following.

[0456] The first terminal of transistor Tr1 is electrically connected to wiring SL, the second terminal of transistor Tr1 is electrically connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is electrically connected to wiring GL. The first terminal of transistor Tr2 is electrically connected to wiring IL, and the second terminal of transistor Tr2 is electrically connected to the second terminal of capacitor Cs1, the first terminal of capacitor Cs2, and the anode of light-emitting device ED. Furthermore, the second terminal of capacitor Cs2 is electrically connected to wiring VCOM. Furthermore, the cathode of light-emitting device ED is electrically connected to wiring VCAT.

[0457] Wiring SL is equivalent to Figure 10 The wiring SLS[1] to the wiring SLS[n] shown, Figure 17 The wiring SL[1] to the wiring SL[6] shown are used as wiring for transmitting image signals from the drive circuit SD to the pixel circuit PX1.

[0458] Wiring GL is equivalent to Figure 10 The wiring GLS[1] to the wiring GLS[m] shown, Figure 11A and Figure 11B The wirings GL[1] to GL[m] are shown and are used as wirings for transmitting a selection signal from the driver circuit GD to the pixel circuit PX1.

[0459] The wiring IL is used as a wiring for supplying current to the anode of the light emitting device ED. Therefore, the wiring IL is sometimes called a current supply line.

[0460] Wiring VCOM is used to supply a fixed potential to the second terminal of capacitor Cs2. In particular, this fixed potential is sometimes referred to as a common potential. As an example, the common potential can be a low-level potential, a ground potential, or a negative potential. Furthermore, wiring VCOM can also be used to supply a common potential to the second terminals of capacitors Cs2 included in other pixel circuits PX1 in the same pixel array PA.

[0461] The wiring VCAT is used to supply a fixed potential to the cathode of the light-emitting device ED. In particular, this fixed potential is sometimes referred to as a cathode potential. For example, the cathode potential can be a low-level potential, a ground potential, or a negative potential. Furthermore, the wiring VCAT can also supply a cathode potential to the cathodes of the light-emitting devices ED included in other pixel circuits PX1 in the same pixel array PA.

[0462] The common potential supplied by the wiring VCOM and the cathode potential supplied by the wiring VCAT may be equal to each other. In this case, the wiring VCOM and the wiring VCAT may be the same wiring (not shown).

[0463] Transistor Tr1 is used as a write transistor for image signals in pixel circuit PX. Therefore, when it is desired to retain image signals for a long time, it is preferable to use a transistor with a long channel length as transistor Tr1. Specifically, transistor ML described in the above embodiment is preferably used as transistor Tr1. Note that when a transistor capable of high-frequency driving is used as transistor Tr1, for example, transistor MV described in the above embodiment can also be used.

[0464] Furthermore, transistor Tr2 is used as a drive transistor to control the amount of current flowing between the anode and cathode of the light-emitting device ED in the pixel circuit PX. Therefore, when the potential corresponding to the image signal is high, a transistor with high voltage resistance is preferably used as transistor Tr2. For example, a transistor with a thicker gate insulating film is preferably used as transistor Tr2. Therefore, for example, transistor ML or transistor MV with a thicker gate insulating film is preferably used as transistor Tr2. Alternatively, transistor ML or transistor MV with a thinner gate insulating film may also be used as transistor Tr2, depending on the situation.

[0465] <Pixel Circuit Configuration Example 2> Figure 29B The pixel circuit PX that can be used in the display device DSP described in the first embodiment is shown. Figure 29A Circuit diagram of a pixel circuit with different circuit configuration examples.

[0466] As an example, Figure 29BThe pixel circuit PX2 shown includes a transistor Tr1 , a transistor Tr2 , a transistor Tr3 , a transistor Tr4 , a capacitor Cs1 , a capacitor Cs3 , and a light emitting device ED.

[0467] Regarding the transistor Tr1 , the transistor Tr2 , the capacitor Cs1 , and the light emitting device ED, reference may be made to the description of the transistor Tr1 , the transistor Tr2 , the capacitor Cs1 , and the light emitting device ED included in the above-mentioned pixel circuit PX1 .

[0468] The pixel circuit PX2 has a function of not only emitting light having a light emission intensity corresponding to an input image signal but also correcting a threshold voltage of the transistor Tr2 as a driving transistor.

[0469] The first terminal of transistor Tr1 is electrically connected to wiring SL. The second terminal of transistor Tr1 is electrically connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1. The gate of transistor Tr1 is electrically connected to wiring GL1. The first terminal of transistor Tr2 is electrically connected to the first terminal of transistor Tr3. The second terminal of transistor Tr2 is electrically connected to the second terminal of capacitor Cs1, the first terminal of capacitor Cs3, the first terminal of transistor Tr4, and the anode of light-emitting device ED. The second terminal of transistor Tr3 is electrically connected to wiring VEL. The gate of transistor Tr3 is electrically connected to wiring GL2. The second terminal of capacitor Cs3 is electrically connected to wiring VEL. The second terminal of transistor Tr4 is electrically connected to wiring INIL. The gate of transistor Tr4 is electrically connected to wiring GL3. The cathode of light-emitting device ED is electrically connected to wiring VCAT.

[0470] For wiring SL and wiring VCAT, please refer to Figure 29A Description of the wiring SL and the wiring VCAT to which the pixel circuit PX1 is electrically connected.

[0471] The wiring GL1, wiring GL2 and wiring GL3 are equivalent to Figure 10 The wiring GLS[1] to the wiring GLS[m] are shown and are used as wiring for transmitting a selection signal from the driver circuit GD to the pixel circuit PX.

[0472] The wiring VEL is used as a wiring for supplying a potential to the anode of the light emitting device ED.

[0473] The wiring INIL is used as a wiring for supplying a potential to the anode of the light emitting device ED. In particular, this potential may be, for example, an initialization potential for resetting the anode potential of the light emitting device ED.

[0474] Transistors Tr3 and Tr4 are preferably transistors with high resistance to gate voltage (the voltage between the gate and the source or drain). For example, transistors with thicker gate insulating films are preferably used as transistors Tr3 and Tr4. Specifically, for example, transistors ML or MV with thicker gate insulating films are preferably used as transistors Tr3 and Tr4. In addition, when a transistor with low leakage current is used as transistor Tr3 or transistor Tr4, for example, transistor ML described in the above embodiment can also be used. In addition, when a transistor with high drive frequency is used as transistor Tr3 or transistor Tr4, for example, transistor MV described in the above embodiment can also be used.

[0475] In addition, in the pixel circuit PX2, the transistor Tr1 and the transistor Tr2 may also be transistors including back gates. Figure 30A As shown, the pixel circuit PX2 may also have a structure in which the back gate of transistor Tr1 is electrically connected to the gate of transistor Tr1, and the back gate of transistor Tr2 is electrically connected to the second terminal of transistor Tr2. In this case, for example, the transistor ML including the back gate electrode described in the above embodiment is preferably used as the transistor Tr1. Also, for example, the transistor ML including the back gate electrode described in the above embodiment is preferably used as the transistor Tr2.

[0476] <Pixel Circuit Configuration Example 3> Figure 29C The pixel circuit PX that can be used in the display device DSP described in the first embodiment is shown. Figure 29A and Figure 29B Circuit diagram of a pixel circuit with different circuit configuration examples.

[0477] As an example, Figure 29C The pixel circuit PX3 shown includes a transistor Tr1 , a transistor Tr2 , a transistor Tr4 , a transistor Tr5 , a capacitor Cs1 , and a light emitting device ED.

[0478] Regarding the transistor Tr1 , the transistor Tr2 , the transistor Tr4 , the capacitor Cs1 , and the light emitting device ED, reference may be made to the description of the transistor Tr1 , the transistor Tr2 , the transistor Tr4 , the capacitor Cs1 , and the light emitting device ED included in the above-mentioned pixel circuit PX2 .

[0479] Similar to the pixel circuit PX2 , the pixel circuit PX3 has a function of not only emitting light having a light emission intensity corresponding to an input image signal but also correcting the threshold voltage of the transistor Tr2 serving as a drive transistor.

[0480] The first terminal of transistor Tr1 is electrically connected to wiring SL. The second terminal of transistor Tr1 is electrically connected to the gate of transistor Tr2, the first terminal of transistor Tr5, and the first terminal of capacitor Cs1. The gate of transistor Tr1 is electrically connected to wiring GL1. The first terminal of transistor Tr2 is electrically connected to wiring VEL. The second terminal of transistor Tr2 is electrically connected to the second terminal of capacitor Cs1, the first terminal of transistor Tr4, and the anode of light-emitting device ED. The second terminal of transistor Tr5 is electrically connected to wiring VBL. The gate of transistor Tr5 is electrically connected to wiring GL4. The second terminal of transistor Tr4 is electrically connected to wiring INIL. The gate of transistor Tr4 is electrically connected to wiring GL3. The cathode of light-emitting device ED is electrically connected to wiring VCAT.

[0481] For wiring SL, wiring VCAT, wiring VEL, and wiring INIL, please refer to Figure 29B Description of the wiring SL, wiring VCAT, wiring VEL, and wiring INIL electrically connected to the pixel circuit PX2.

[0482] The wiring GL1, wiring GL3 and wiring GL4 are equivalent to Figure 10 The wiring GLS[1] to the wiring GLS[m] are shown and are used as wiring for transmitting a selection signal from the driver circuit GD to the pixel circuit PX.

[0483] The wiring VBL is used as a wiring for supplying a fixed potential to the first terminal of the capacitor Cs1. This fixed potential is preferably a potential input to the gate of the transistor Tr2 when correcting the threshold voltage of the transistor Tr2 and is substantially equal to the potential supplied by the wiring VEL.

[0484] Transistor Tr5 is preferably a transistor with high voltage resistance. For example, a transistor with a thick gate insulating film is preferably used as transistor Tr5. Specifically, for example, transistors ML and MV with thick gate insulating films are preferably used as transistor Tr5. Note that when a transistor with a high drive frequency is used as transistor Tr5, for example, transistor MV described in the above embodiment can also be used. Also, when a transistor with low leakage current is used as transistor Tr5, for example, transistor ML described in the above embodiment can also be used.

[0485] <Pixel Circuit Configuration Example 4> Figure 29D The pixel circuit PX that can be used in the display device DSP described in the first embodiment is shown. Figures 29A to 29C Circuit diagram of a pixel circuit with different circuit configuration examples.

[0486] As an example, Figure 29DThe pixel circuit PX4 shown includes a transistor Tr1 , a transistor Tr2 , a transistor Tr4 , a capacitor Cs1 , and a light emitting device ED.

[0487] Regarding the transistor Tr1 , the transistor Tr2 , the transistor Tr4 , the capacitor Cs1 , and the light emitting device ED, reference may be made to the description of the transistor Tr1 , the transistor Tr2 , the transistor Tr4 , the capacitor Cs1 , and the light emitting device ED included in the above-mentioned pixel circuit PX3 .

[0488] The pixel circuit PX4 has a function of emitting light having a light emission intensity corresponding to an input image signal, similarly to the pixel circuit PX1 .

[0489] The first terminal of transistor Tr1 is electrically connected to wiring SL, the second terminal of transistor Tr1 is electrically connected to the gate of transistor Tr2 and the first terminal of capacitor Cs1, and the gate of transistor Tr1 is electrically connected to wiring GL1. The first terminal of transistor Tr2 is electrically connected to wiring VEL, the second terminal of transistor Tr2 is electrically connected to the second terminal of capacitor Cs1, the first terminal of transistor Tr4, and the anode of light-emitting device ED. The second terminal of transistor Tr4 is electrically connected to wiring INIL, and the gate of transistor Tr4 is electrically connected to wiring GL3. The cathode of light-emitting device ED is electrically connected to wiring VCAT.

[0490] For the wiring SL, wiring VCAT, wiring INIL, wiring GL1 and wiring GL3, please refer to Figure 29C Description of the wiring SL and wiring VCAT to which the pixel circuit PX3 is electrically connected.

[0491] In the pixel circuit PX4, the transistor Tr2 may also be a transistor including a back gate. Figure 30B As shown, the pixel circuit PX4 may have a structure in which the back gate of the transistor Tr2 is electrically connected to the second terminal of the transistor Tr2. In this case, for example, the transistor ML including the back gate electrode described in the above embodiment is preferably used as the transistor Tr2.

[0492] <Pixel Circuit Configuration Example 5> Figure 31A The pixel circuit PX that can be used in the display device DSP described in the first embodiment is shown. 29A to 29D Circuit diagram of a pixel circuit with different circuit configuration examples.

[0493] As an example, Figure 31A The pixel circuit PX5 shown includes transistors Tr1 to Tr4 , a transistor Tr6 , a transistor Tr7 , a capacitor Cs1 , and a light emitting device ED.

[0494] Regarding the transistors Tr1 to Tr4 , the capacitor Cs1 , and the light emitting device ED, reference may be made to the description of the transistors Tr1 to Tr4 , the capacitor Cs1 , and the light emitting device ED included in the above-mentioned pixel circuit PX2 .

[0495] Like the pixel circuits PX2 and PX3 , the pixel circuit PX5 not only emits light having a light emission intensity corresponding to an input image signal but also corrects the threshold voltage of the transistor Tr2 serving as a drive transistor.

[0496] The first terminal of transistor Tr1 is electrically connected to wiring SL. The second terminal of transistor Tr1 is electrically connected to the first terminal of transistor Tr2 and the first terminal of transistor Tr7. The gate of transistor Tr1 is electrically connected to wiring GL1. The second terminal of transistor Tr2 is electrically connected to the first terminal of transistor Tr3 and the first terminal of transistor Tr6. The gate of transistor Tr2 is electrically connected to the second terminal of transistor Tr6 and the first terminal of capacitor Cs1. The second terminal of transistor Tr3 is electrically connected to wiring VEL, and the gate of transistor Tr3 is electrically connected to wiring GL2. The gate of transistor Tr6 is electrically connected to the gate of transistor Tr4 and wiring GL3. The second terminal of transistor Tr7 is electrically connected to the first terminal of transistor Tr4, the second terminal of capacitor Cs1, and the anode of light-emitting device ED. The second terminal of transistor Tr4 is electrically connected to wiring INIL. The cathode of light-emitting device ED is electrically connected to wiring VCAT.

[0497] For wiring SL, wiring VCAT, wiring VEL, and wiring INIL, please refer to Figure 29B Description of the wiring SL, wiring VCAT, wiring VEL, and wiring INIL electrically connected to the pixel circuit PX2.

[0498] The wiring GL1, wiring GL2, wiring GL3 and wiring GL5 are equivalent to Figure 10 The wiring GLS[1] to the wiring GLS[m] are shown and are used as wiring for transmitting a selection signal from the driver circuit GD to the pixel circuit PX.

[0499] Transistors Tr6 and Tr7 are preferably transistors with high voltage resistance. For example, transistors with thick gate insulating films are preferably used as transistors Tr6 and Tr7. Specifically, for example, transistors ML and MV with thick gate insulating films are preferably used as transistors Tr6 and Tr7. Furthermore, when transistors with high drive frequencies are used as transistors Tr6 and Tr7, for example, the transistor MV described in the above embodiment can also be used. Furthermore, when transistors with low leakage current are used as transistors Tr6 and Tr7, for example, the transistor ML described in the above embodiment can also be used.

[0500] The pixel circuit of the semiconductor device according to one embodiment of the present invention is not limited to Figure 31A The structure of the pixel circuit PX5 shown in the figure may be used by appropriately changing the circuit structure of the pixel circuit PX5.

[0501] For example, Figure 31B As shown in the pixel circuit PX5A, it is also possible to use Figure 31A A capacitor Cs4 is provided in the pixel circuit PX5. A first terminal of the capacitor Cs4 is electrically connected to the gate of the transistor Tr1 and the wiring GL1, and a second terminal of the capacitor Cs4 is electrically connected to the first terminal of the transistor Tr4, the second terminal of the transistor Tr7, the second terminal of the capacitor Cs1, and the anode of the light-emitting device ED.

[0502] In the pixel circuit PX5A, the transistor Tr1, the transistor Tr2, and the transistor Tr6 may also be transistors including back gates. Figure 32 As shown, pixel circuit PX5A may also have the following structure: the back gate of transistor Tr1 is electrically connected to the gate of transistor Tr1, the back gate of transistor Tr2 is electrically connected to the second terminal of transistor Tr2, and the back gate of transistor Tr6 is electrically connected to the gate of transistor Tr6. In this case, for example, the transistor ML including the back gate electrode described in the above embodiment is preferably used as transistor Tr1. Also, for example, the transistor ML including the back gate electrode described in the above embodiment is preferably used as transistor Tr2 and transistor Tr6.

[0503] <Pixel Circuit Configuration Example 6> In the above pixel circuit structure examples 1 to 5, the structure examples of the pixel circuit PX including the light-emitting device ED are described. However, the pixel circuit PX included in the display device DSP described in the above embodiment 1 may also include a liquid crystal display device, for example.

[0504] Figure 33 The pixel circuit PX6 shown is a pixel circuit that can be used as the pixel circuit PX described in the first embodiment, and is different from the pixel circuits PX1 to PX5 and PX5A in that it includes a liquid crystal display element LCR.

[0505] As an example, the pixel circuit PX6 includes a transistor Tr8, a capacitor Cs5, and a liquid crystal display device LCR.

[0506] A first terminal of transistor Tr8 is electrically connected to a first terminal of capacitor Cs5 and a first terminal of liquid crystal display device LCR. A second terminal of transistor Tr8 is electrically connected to wiring SL, and a gate of transistor Tr8 is electrically connected to wiring GL6. Furthermore, a second terminal of capacitor Cs5 is electrically connected to wiring CSL. Furthermore, a second terminal of liquid crystal display device LCR is electrically connected to wiring COM.

[0507] Wiring SL is equivalent to Figure 10 The wiring SLS[1] to the wiring SLS[n] shown, Figure 17 The wiring SL[1] to the wiring SL[6] shown are used as wiring for transmitting image signals from the drive circuit SD to the pixel circuit PX6.

[0508] Wiring GL6 is equivalent to Figure 10 The wiring GLS[1] to the wiring GLS[m] shown and Figure 11A and Figure 11B The wirings GL[1] to GL[m] shown are used as wirings for transmitting a selection signal from the driver circuit GD to the pixel circuit PX6.

[0509] The wiring CSL is used as a wiring for supplying a fixed potential to the second terminal of the capacitor Cs5. As an example, the fixed potential can be a low-level potential, a ground potential, or a negative potential. Furthermore, the wiring CSL can also be used to supply a common potential to the second terminal of the capacitor Cs2 included in other pixel circuits PX1 in the same pixel array PA.

[0510] The wiring COM is used as a wiring for supplying a fixed potential to the second terminal of the liquid crystal display device LCR. In particular, this fixed potential is sometimes referred to as a common potential. As an example, the common potential can be a low-level potential, a ground potential, or a negative potential. In addition, the wiring COM can also be a wiring for supplying a common potential to the second terminals of the liquid crystal display devices LCR included in other pixel circuits PX6 in the same pixel array PA.

[0511] In addition, the fixed potential supplied by the wiring CSL and the common potential supplied by the wiring COM may be equal to each other. In this case, the wiring CSL and the wiring COM may be the same wiring (not shown).

[0512] Transistor Tr8 is used as a write transistor for image signals in pixel circuit PX6. Therefore, when it is desired to retain image signals for a long time, it is preferable to use a transistor with a long channel length as transistor Tr8. Specifically, transistor ML described in the above embodiment is preferably used as transistor Tr8. Note that when a transistor with a high drive frequency is used as transistor Tr1, for example, transistor MV described in the above embodiment can also be used.

[0513] Note that this embodiment mode can be combined with the same or other embodiment modes described in this specification, as appropriate. For example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in the same embodiment mode, as appropriate. For example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in other embodiment modes, as appropriate.

[0514] (Implementation 4) In this embodiment, the above-described embodiment is simultaneously manufactured. Figures 3A to 3C The transistor ML and 7A to 7C The transistor MV method.

[0515] <Manufacturing Method Example> exist Figures 3A to 3C The transistor ML and 7A to 7C In the description of an example of a method for manufacturing a transistor MV, the Figures 34A to 46D .

[0516] exist 34A to 40D as well as Figures 42A to 46D In each figure, A is a plan view. In addition, B in each figure is a cross-sectional view taken along the dot-dash line C1-C2 shown in each figure A, and is also a cross-sectional view taken in the X direction. In addition, C in each figure is a cross-sectional view taken along the dot-dash line C3-C4 shown in each figure A, and is also a cross-sectional view taken in the Y direction. In addition, D in each figure is a cross-sectional view taken along the dot-dash line C5-C6 shown in each figure A, and is also a cross-sectional view taken in the Y direction. In addition, Figure 41A Shown is a plan view, Figure 41B and Figure 41C It is along Figure 41A Note that in the plan view of A in each drawing, some components are omitted for clarity.

[0517] Next, an insulating material for forming an insulating layer, a conductive material for forming a conductive layer, or a semiconductor material for forming a semiconductor can be deposited by appropriately using a deposition method such as sputtering, CVD, MBE (Molecular Beam Epitaxy), PLD, or ALD.

[0518] First, a substrate (not shown) is prepared, and an insulating layer IS1, an insulating layer IB1, and a conductive film ME1A are sequentially formed on the substrate (see FIG. Figures 35A to 35D ).

[0519] As the substrate, for example, a single crystal substrate (for example, a semiconductor substrate made of silicon or germanium) can be used. In addition to single crystal substrates, as substrates, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates containing stainless steel foil, tungsten substrates, substrates containing tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base films can be used. As an example of a glass substrate, barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass can be cited. As flexible substrates, laminated films, and base films, the following examples can be cited. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Alternatively, as an example, synthetic resins such as acrylic resins can be cited. In addition, as an example, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be cited. Examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, and paper. Note that when the manufacturing process of the display device DSP in Embodiment 1 includes heat treatment, a substrate with high heat resistance is preferably selected as the substrate. Alternatively, a substrate having components disposed thereon may be used. Examples of components disposed on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0520] As an example, an insulator IS1 is used as an interlayer film. The insulating layer IS1 used as an interlayer film can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, as the insulating layer IS1, for example, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with pores are preferred because they easily form regions containing oxygen that is released by heating. Alternatively, the insulating layer IS1 can be made of, for example, a resin. In addition, as the material for the insulating layer IS1, the above-mentioned insulating materials can also be appropriately combined. In addition, the insulating layer IS1 can have either a single-layer structure or a stacked-layer structure obtained by sequentially depositing two or more layers of insulating materials.

[0521] The insulating layer IS1 is preferably made of an insulating material with a low relative dielectric constant. Using an insulating material with a low relative dielectric constant for the interlayer film can reduce parasitic capacitance generated between wirings. Specifically, for example, the relative dielectric constant of the insulating layer IS1 is preferably less than 4, and more preferably less than 3. Examples of insulating materials with a low relative dielectric constant include silicon oxide, silicon oxynitride, and silicon nitride oxide.

[0522] As an example, the insulating layer IB1 is preferably used as a barrier insulating film for preventing impurities such as water, hydrogen, nitrogen, and oxygen contained in the insulating layer IS1 from entering the conductive layer ME1 and the semiconductor layer SC1 to be formed later.

[0523] Therefore, it is preferable to use an insulating material for the insulating layer IB1 that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N2O, NO, or NO2), and copper atoms (making these impurities less likely to pass through). Alternatively, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules) (making these oxygen less likely to pass through).

[0524] As an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, a single layer or a stack of insulators containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be mentioned. In addition, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, an oxide containing aluminum and hafnium (hafnium aluminate) can be mentioned. In addition, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, and silicon nitride can be mentioned.

[0525] In particular, aluminum oxide or silicon nitride is preferably used for the insulating layer IB1 , thereby suppressing, for example, the diffusion of impurities such as water and hydrogen from below the insulator IB1 into the transistors ML and MV.

[0526] The insulating layer IB1 may have a single-layer structure or a stacked-layer structure obtained by sequentially depositing two or more layers of insulating materials.

[0527] As a deposition method of the insulating layer IB1 , for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method can be used.

[0528] The conductive film ME1A is a film that becomes the conductive layer ME1 in a later step. In addition, a portion of the conductive layer ME1 is also used as one of the source electrode and the drain electrode of the transistor MV. Therefore, it is preferable to use a highly conductive material for the conductive film ME1A.

[0529] For example, the conductive film ME1A preferably uses a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing two or more of these metal elements; or an alloy combining two or more of these metal elements. Alternatively, for example, the conductive film ME1A preferably uses tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, and are therefore preferred. Alternatively, as the conductor, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element (such as phosphorus or arsenic), or a silicide (such as nickel silicide) may be used.

[0530] Furthermore, a plurality of conductive films formed from the above materials may be stacked. For example, a stacked structure may be formed by combining a material containing the above metal element and a conductive material containing oxygen. Alternatively, a stacked structure may be formed by combining a material containing the above metal element and a conductive material containing nitrogen. Alternatively, a stacked structure may be formed by combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0531] For example, the conductive layer ME1 may include a first conductive body and a second conductive body (not shown) surrounded by the first conductive body. The first conductive body may be made of titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, which are conductive materials that inhibit oxygen diffusion. The second conductive body may be made of a conductive material primarily composed of highly conductive tungsten, copper, or aluminum. Surrounding the second conductive body with the first conductive body prevents a decrease in conductivity caused by oxidation of the first conductive body.

[0532] Next, the conductive film ME1A is processed into a strip shape by photolithography to form a conductive layer ME1 (see Figures 36A to 36D In particular, the conductive layer ME1 is formed to extend in directions parallel to the dot-dash line C5-C6 (the +Y direction and the -Y direction). The above-mentioned processing can be performed by dry etching or wet etching. The processing using dry etching is particularly suitable for micro-processing.

[0533] Note that in photolithography, first, a resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using a KrF excimer laser, an ArF excimer laser, or EUV (Extreme Ultraviolet) light. In addition, an immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above-mentioned light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0534] Furthermore, a hard mask made of an insulator or conductor can also be used under the resist mask. When using a hard mask, an insulating film or a conductive film serving as the hard mask material can be formed on the conductive film ME1A, a resist mask formed thereon, and then the hard mask material can be etched to form a hard mask of the desired shape. Etching of the conductive film ME1A and the like can be performed either after removing the resist mask or without removing the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask can be removed by etching after etching the conductive film ME1A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0535] Next, an insulating film IB2A, an insulating film IS2A, an insulating film IB3A, and a conductive film ME2A are sequentially deposited on the conductive layer ME1 (see Figures 37A to 37D ). When depositing the insulating film IB2A, the insulating film IS2A, the insulating film IB3A, and the conductive film ME2A, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used.

[0536] In addition, after the insulating film IS2A is deposited (before the insulating film IB3A is deposited), the insulating film IS2A may be subjected to a planarization process such as chemical mechanical polishing (CMP) to planarize the top surface of the insulating film IS2A (see Figures 38A to 38D ).

[0537] Insulating film IB2A is a film that becomes insulating layer IB2 in a later step. Similarly to insulating layer IB1, insulating layer IB2 is preferably used, for example, as a barrier insulating film to prevent impurities such as water, hydrogen, nitrogen, and oxygen contained in insulating layer IS2 (to be formed later) from infiltrating into conductive layer ME1. Therefore, insulating layer IB2 can use the same materials and structures as those used for insulating layer IB1.

[0538] Insulating film IS2A is a film that becomes insulating layer IS2 in a later step. Insulating layer IS2 is used, for example, as an interlayer film. Therefore, insulating layer IS2 preferably comprises an insulating material with a low relative dielectric constant. Using an insulating material with a low relative dielectric constant for the interlayer film can reduce parasitic capacitance between wiring lines.

[0539] The insulating film IS2A may have a single-layer structure or a stacked-layer structure in which two or more insulating material layers are sequentially deposited.

[0540] The insulating film IS2A can be made of, for example, a material that can be used for the insulating layer IS1. In particular, when the semiconductor layer SC1 formed in a subsequent step is a metal oxide used as an oxide semiconductor, the insulating film IS2A is preferably made of, for example, silicon oxide, silicon oxynitride, or silicon oxide with vacancies. These materials can easily form regions containing oxygen that is released by heating, and this released oxygen can be supplied to the metal oxide. As a result, the carrier concentration of the metal oxide is reduced at and near the interface of the semiconductor layer SC1 in contact with the insulating layer IS2, and the interface of the semiconductor layer SC1 and the vicinity of the interface become i-type or substantially i-type. Therefore, the interface of the semiconductor layer SC1 and the vicinity of the interface serve as a channel formation region in the transistor ML or the transistor MV.

[0541] Insulating film IB3A is a film that becomes insulating layer IB3 in a later step. Similar to insulating layers IB1 and IB2, insulating layer IB3 is preferably used as a barrier insulating film to prevent impurities such as water, hydrogen, nitrogen, and oxygen contained in insulating layer IS2 (to be formed later) from infiltrating into conductive layer ME2 (to be formed later). Therefore, insulating layer IB3 can use the same materials or structures as those used for insulating layer IB1 or insulating layer IB2.

[0542] The conductive film ME2A is a film that becomes the conductive layer ME2 in a later step. Furthermore, a portion of the conductive layer ME2 also serves as the other of the source and drain electrodes of the transistor MV. Furthermore, another portion of the conductive layer ME2 also serves as the source electrode of the transistor ML. Furthermore, yet another portion of the conductive layer ME2 also serves as the drain electrode of the transistor ML. Therefore, a highly conductive material is preferably used for the conductive film ME2A.

[0543] The conductive film ME2A may use, for example, a material or structure that can be used for the conductive layer ME1.

[0544] Next, the conductive film ME2A is processed into a strip shape by photolithography to form a conductive film ME2B (see FIG. Figures 39A to 39D ). In particular, here, the conductive film ME2B is formed so as to extend in a direction parallel to the dot-dash line C1-C2 (+X direction and -X direction) and to have a region overlapping with a portion of the conductive layer ME1. Figures 36A to 36D Photolithography as described.

[0545] Next, the insulating film IB2A, the insulating film IS2A, the insulating film IB3A, and the conductive film ME2B are processed by photolithography to form the insulating layer IB2, the insulating layer IS2, the insulating layer IB3, and the conductive layer ME2 (see FIG. Figures 40A to 40D The insulating layers IB2, IS2, IB3, and ME2 all include openings KK1 and KK2 formed by this photolithography process. The above-described processing can utilize either dry etching or wet etching, with dry etching being particularly suitable for micromachining. Furthermore, the insulating films IB2A, IS2A, IB3A, and ME2B can also be processed under different conditions.

[0546] In particular, Figure 40B and Figure 40C As shown, the opening KK1 is preferably formed so that the top surface of the insulating layer IB1 becomes the bottom of the opening KK1. Alternatively, the opening KK1 may be formed so that the bottom of the opening KK1 becomes the top surface of the insulating layer IB2 or the top surface of the insulating layer IS1.

[0547] like Figure 40B and Figure 40D As shown, the opening KK2 is preferably formed in such a manner that the top surface of the conductive layer ME1 becomes the bottom of the opening KK2. In addition, depending on the situation, the opening KK2 may be formed in such a manner that not only the conductive layer ME1 but also the insulating layer IB1 or the insulating layer IS1 is exposed at the bottom of the opening KK2. Specifically, for example, Figure 41A and Figure 41B As shown in FIG. 1 , the opening KK2 may be formed in such a manner that not only the conductive layer ME1 but also the insulating layer IB1 is exposed at the bottom of the opening KK2. Figure 41A and Figure 41C As shown, the opening KK2 may be formed so as to expose not only the conductive layer ME1 but also the insulating layer IS1 at the bottom of the opening KK2 . Figure 41A is shown with Figure 40A Schematic diagram of different openings KK2, Figure 41B and Figure 41C It is along Figure 41A A schematic cross-sectional view of the position of the dot-dash line C7-C8 is shown.

[0548] In addition, Figures 40A to 40D As an example, the opening KK1 or the opening KK2 has a tapered shape with a taper angle substantially perpendicular to the XY plane (70° or more and 110° or less). Alternatively, as an example, the opening KK1 or the opening KK2 may have a tapered shape with a taper angle of 30° or more and less than 70°, or a taper angle of more than 0° and less than 30°, relative to the XY plane.

[0549] In this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a component is inclined relative to the substrate surface. Furthermore, the angle formed by the inclined side surface and the substrate surface is referred to as the taper angle. In particular, in this specification, etc., a tapered shape having a taper angle greater than 0° and less than 90° is referred to as a positive taper shape, and a tapered shape having a taper angle greater than 90° and less than 180° is referred to as a negative taper shape.

[0550] In addition, Figure 40A In the figure, the shapes of the openings KK1 and KK2 when viewed from a plane are illustrated as circles, but the shapes may also be shapes including curves (e.g., ellipses, triangles with rounded corners, quadrilaterals, pentagons, and other polygons, etc.) or shapes with corners (e.g., triangles, quadrilaterals, pentagons, and other polygons, etc.).

[0551] Furthermore, byproducts generated during the etching process described above may form in layers on the side surfaces of the openings KK1 and KK2 (side surfaces of the insulating layers IB2, IS2, IB3, and conductive layer ME2). In this case, these layered byproducts are formed between the insulating layers IB2, IS2, IB3, and conductive layer ME2, and the semiconductor film SC1A described later. Therefore, it is preferable to remove these layered byproducts that are formed so as to contact the insulating layers IB2, IS2, IB3, and conductive layer ME2.

[0552] Next, a semiconductor film SC1A is deposited on the conductive layer ME1, the insulating layer IB3, and the conductive layer ME2 (see Figures 42A to 42D). Specifically, inside each of the openings KK1 and the openings KK2, the semiconductor film SC1A is deposited on the top surface of the conductive layer ME1, the side surfaces of the insulating layer IB2, the side surfaces of the insulating layer IS2, the side surfaces of the insulating layer IB3, and the side surfaces of the conductor ME2. In addition, outside the openings KK1 and the openings KK2, the semiconductor film SC1A is deposited on the top surface of the conductive layer ME2 and the top surface of the insulating layer IB3. In other words, the semiconductor film SC1A is deposited on the bottom surface and inner side surfaces of the opening KK1, the bottom surface and inner side surfaces of the opening KK2, on the conductive layer ME2, and on the insulating layer IB3. The semiconductor film SC1A can be deposited using a deposition method such as sputtering, CVD, MBE, PLD, or ALD. The semiconductor film SC1A is preferably deposited using the ALD method. As described above, the semiconductor film SC1A is preferably deposited thinly, and thickness unevenness needs to be minimized. In contrast, the ALD method is a deposition method that alternately introduces precursors and reactants (e.g., oxidants). Since the thickness can be adjusted by repeating the cycle several times, the thickness can be precisely adjusted. Figure 42B and Figure 42D As shown, the semiconductor film SC1A needs to be deposited with high coverage on the bottom surface and inner side surfaces of the opening KK1, as well as the bottom surface and inner side surfaces of the opening KK2. In particular, in each of the openings KK1 and KK2, the semiconductor film SC1A is preferably deposited with high coverage on the top surface of the conductive layer ME1 and the side surfaces of the conductive layer ME2. By utilizing the ALD method, atomic layers can be deposited on the bottom surfaces and inner side surfaces of each of the openings KK1 and KK2, thereby allowing the semiconductor film SC1A to be deposited with high coverage in the respective openings.

[0553] Note that when the side surface of the opening KK1 or the opening KK2 has a tapered shape, deposition of the semiconductor film SC1A is not limited to the ALD method, and sputtering may be used, for example.

[0554] Semiconductor film SC1A is a film that becomes semiconductor layer SC1 in a later step. A portion of semiconductor layer SC1 is used as a channel formation region for transistors ML and MV, each formed in a later step. Another portion of semiconductor layer SC1 may also be used as one of a pair of electrodes for capacitor C1, also formed in a later step.

[0555] The semiconductor film SC1A may be, for example, a metal oxide used as an oxide semiconductor. In this case, the transistor ML and the transistor MV are OS transistors. The metal oxide preferably contains at least indium or zinc, for example. In particular, it preferably contains indium and zinc. In addition, it preferably contains element M. As element M, one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony can be used. In particular, element M is preferably one or more of aluminum, gallium, yttrium, and tin. In addition, element M more preferably contains one or both of gallium and tin.

[0556] As an example, the semiconductor film SC1A preferably uses an In-Ga-Zn oxide. In particular, a metal oxide with an atomic ratio of In:Ga:Zn = 1:1:1 or a composition close thereto, a composition close thereto of 4:2:3 or a composition close thereto of 3:1:2 is more preferably used as the In-Ga-Zn oxide. Furthermore, as another example, the semiconductor film SC1A preferably uses an In-Zn oxide. In particular, a metal oxide with an atomic ratio of In:Zn = 4:1 or a composition close thereto is more preferably used as the In-Zn oxide.

[0557] In particular, the semiconductor film SC1A preferably uses an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 When the carrier concentration of the oxide semiconductor film is to be reduced, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state with a low impurity concentration and a low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0558] Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes also have a low trap state density. Furthermore, charges trapped in the trap states of the oxide semiconductor take a long time to disappear, sometimes acting like fixed charges. Consequently, transistors with channel formation regions formed in oxide semiconductors with a high trap state density sometimes experience unstable electrical characteristics.

[0559] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components of the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0560] In a transistor including an oxide semiconductor (OS transistor), impurities or oxygen vacancies (hereinafter sometimes referred to as V O ), the electrical characteristics are easily changed, and reliability is sometimes reduced. In addition, in the OS transistor, hydrogen is introduced into the V O Defects (hereinafter sometimes referred to as V O H), sometimes electrons that become carriers are generated. In addition, when V O When the V is H, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become non-uniform. Therefore, the channel formation region in the oxide semiconductor contains V O When the gate-source voltage is 0V, the transistor is likely to be in a normally-on state (a state in which a channel exists and current flows through the transistor even when the gate-source voltage is 0V). Therefore, it is preferable to minimize impurities, oxygen vacancies, and V O H.

[0561] The semiconductor film SC1A preferably has, for example, a stacked structure of multiple oxide layers having different atomic ratios of metal atoms. For example, the metal oxides include a first metal oxide and a second metal oxide formed on the first metal oxide. When each metal oxide contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the first metal oxide relative to the number of atoms of all elements constituting the first metal oxide is preferably higher than the ratio of the number of atoms of the element M contained in the second metal oxide relative to the number of atoms of all elements constituting the second metal oxide. Furthermore, the ratio of the number of atoms of the element M contained in the first metal oxide relative to In is preferably greater than the ratio of the number of atoms of the element M contained in the second metal oxide relative to In.

[0562] The energy of the conduction band bottom of the first metal oxide is preferably higher than the energy of the conduction band bottom of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably lower than the electron affinity of the second metal oxide.

[0563] Here, the energy level of the conduction band bottom changes smoothly at the junction of the first metal oxide and the second metal oxide. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of the first metal oxide and the second metal oxide continuously changing or continuously joining. To this end, it is preferable to reduce the defect state density of the mixed layer formed at the interface between the first metal oxide and the second metal oxide.

[0564] Specifically, by making the first metal oxide and the second metal oxide contain the same element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the second metal oxide is In-Ga-Zn oxide (indium-gallium-zinc oxide), In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide can be used as the first metal oxide.

[0565] Specifically, the first metal oxide may have a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or a composition close thereto, a composition close thereto of 1:3:2 [atomic ratio] or a composition close thereto of 1:1:0.5 [atomic ratio] or a composition close thereto. Furthermore, the second metal oxide may have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition close thereto of 4:2:3 [atomic ratio] or a composition close thereto of 3:1:2 [atomic ratio] or a composition close thereto. The composition close thereto may fall within a range of ±30% of the desired atomic ratio.

[0566] In this case, the primary carrier path is through the second metal oxide. By providing the first metal oxide with this structure, the defect state density at the interface between the first and second metal oxides can be reduced. Consequently, the effect of interface scattering on carrier conduction is reduced, enabling the transistor to achieve high on-state current and high frequency characteristics.

[0567] Alternatively, the metal oxide may have a stacked structure comprising the second metal oxide and the first metal oxide formed on the second metal oxide. This structure can suppress increases in contact resistance between the conductor ME1 or the conductor ME2 and the metal oxide. Furthermore, deposition damage to the insulator GI1 (described in detail later) caused by the second metal oxide can be reduced.

[0568] Furthermore, a metal oxide is used as the semiconductor film SC1A and a conductor is provided in contact with the semiconductor layer SC1 (in the Figures 42A to 42DIn the case of a semiconductor layer SC1 (equal to conductive layers ME1 and ME2), the oxygen concentration near the conductor may decrease. Furthermore, a metal compound layer containing the metal in the conductor and components of the semiconductor layer SC1 may form near the conductor in the semiconductor layer SC1. In this case, the carrier concentration in the region near the conductor in the semiconductor layer SC1 increases, resulting in a low-resistance region.

[0569] In addition to metal oxides, semiconductor layer SC1 may also be made of a material containing silicon. Examples of silicon include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon (including low-temperature polycrystalline silicon (LTPS)), or single crystal silicon. Furthermore, during the formation of semiconductor film SC1A in openings KK1 and KK2, the interface with conductive layer ME1 and conductive layer ME2 in the semiconductor region forming semiconductor film SC1A and its vicinity are preferably converted into a low-resistance region. Thus, a low-resistance region and a semiconductor region are formed in semiconductor layer SC1, so transistors ML and MV can be Si transistors.

[0570] Note that in this embodiment, a case where the semiconductor film SC1A includes a metal oxide serving as an oxide semiconductor is described.

[0571] Next, the semiconductor film SC1A is processed by photolithography to form the semiconductor layer SC1 so as to expose a portion of the insulating layer IB1, a portion of the insulating layer IB2, a portion of the insulating layer IS2, a portion of the insulating layer IB3, and a portion of the conductive layer ME2. In particular, a portion of the semiconductor layer SC1 is processed so as to overlap with the insulating layer IB2 and the conductive layer ME2, and another portion of the semiconductor layer SC1 is processed so as to overlap with the conductive layer ME1 and the conductive layer ME2 (see FIG. Figures 43A to 43D ). In addition, regarding the photolithography method, please refer to Figures 36A to 36D Photolithography as described.

[0572] Next, an insulating layer GI1 is deposited on the insulating layer IB1, the insulating layer IB2, the insulating layer IS2, the insulating layer IB3, the conductive layer ME2, and the semiconductor layer SC1 (see FIG. Figures 44A to 44D When depositing the insulating layer GI1, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used.

[0573] The insulating layer GI1 is used as a gate insulating film of each of the transistor ML and the transistor MV.

[0574] As the insulating layer GI1, for example, an insulator composed of a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST) is preferably used in a single layer or a stacked layer. Alternatively, the insulating layer GI1 may be made of an insulator having a high relative dielectric constant, such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

[0575] As transistors become increasingly miniaturized and highly integrated, problems such as leakage current may occur due to thinning of gate insulators. Using high-k materials as gate insulators can reduce the gate potential during transistor operation while maintaining the physical thickness.

[0576] Alternatively, the insulating layer GI1 may be a laminate of the high-k material and silicon oxide or silicon oxynitride, thereby allowing a thermally stable insulating layer with a high relative dielectric constant to be used as the gate insulating film of each of the transistors ML and MV.

[0577] The insulating layer GI1 may have a single-layer structure or a stacked-layer structure obtained by sequentially depositing two or more layers of insulating materials.

[0578] Note that when the semiconductor layer SC1 contains a metal oxide used as an oxide semiconductor, it is preferable to perform microwave treatment in an atmosphere containing oxygen after forming the insulating layer GI1 (at the latest before depositing the conductive film ME3A described later). Here, microwave treatment refers to, for example, treatment using an apparatus including a power supply that generates high-density plasma using microwaves. In addition, in this specification, etc., microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Note that in the case where the insulating layer GI1 has a stacked structure, microwave treatment can also be performed at the stage of depositing the insulating layer GI1 midway. For example, in the case where the insulating layer GI1 includes a silicon oxide film or a silicon oxynitride film, the microwave treatment can also be performed at the stage of depositing the silicon oxide film or the silicon oxynitride film.

[0579] In addition, microwave treatment can use high frequencies such as microwaves or RF, oxygen plasma, oxygen free radicals, etc. In addition, when performing microwave treatment, it is preferable to use a microwave processing device that includes a power supply that generates high-density plasma with microwaves. Here, the frequency of the microwave processing device is set to be greater than 300 MHz and less than 300 GHz, preferably greater than 2.4 GHz and less than 2.5 GHz, for example, 2.45 GHz. By using high-density plasma, high-density oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves of the microwave processing device is greater than 1000 W and less than 10000 W, preferably greater than 2000 W and less than 5000 W. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the semiconductor SC1 as a metal oxide. Through the action of plasma, microwaves, etc., the V contained in the region of the semiconductor layer SC1 can be reduced. O H is separated to remove hydrogen from the region. In other words, the V contained in the region can be reduced. O H. Thus, the oxygen vacancies and V O H and thus reduce the carrier concentration. In addition, by supplying oxygen radicals generated in the above-mentioned oxygen plasma to the oxygen vacancies formed in the region, the oxygen vacancies in the region can be further reduced, thereby reducing the carrier concentration.

[0580] Next, a conductive film ME3A is deposited on the insulating layer GI1 (see Figures 45A to 45D ). In particular, Figures 45A to 45D The conductive film ME3A is deposited in such a manner as to fill the opening KK2. When depositing the conductive film ME3A, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used.

[0581] The conductive film ME3A will become the conductive layer ME3 in a later step. Furthermore, a portion of the conductive layer ME3 also serves as the gate electrode of the transistor ML. Furthermore, another portion of the conductive layer ME3 also serves as the gate electrode of the transistor MV. Therefore, a highly conductive material is preferably used for the conductive film ME3A.

[0582] The conductive film ME3A can use, for example, a material or structure that can be used for the electrical conductor ME1.

[0583] Next, the conductive film ME3A is processed into a strip shape by photolithography, thereby forming a conductive layer ME3 (see Figures 46A to 46D). In particular, here, a portion of the conductive layer ME3 is formed so as to extend in a direction parallel to the dot-dash line C3-C4 (+Y direction and -Y direction) and overlap with the semiconductor layer SC1 in the opening KK1. In addition, another portion of the conductive layer ME3 is formed so as to extend in a direction parallel to the dot-dash line C5-C6 (+Y direction and -Y direction) and overlap with other conductive layers ME1 and the semiconductor layer SC1 in the opening KK2. In addition, regarding the photolithography method, reference can be made to Figures 36A to 36D Photolithography as described.

[0584] Next, an insulating layer IB4 and an insulating layer IS3 are sequentially deposited on the insulating layer GI1 and the conductive layer ME3 (see Figures 34A to 34D ).

[0585] Similar to insulating layers IB1 to IB3, insulator IB4 is preferably used as a barrier insulating film to prevent impurities such as water, hydrogen, nitrogen, and oxygen contained in insulating layer IS3 from entering conductive layer ME3. Therefore, insulating layer IB3 can use the same material or structure as insulating layer IB1.

[0586] The insulating layer IS3 is a film used as an interlayer film, for example. Therefore, the insulating layer IS3 preferably includes an insulating material with a low relative dielectric constant. By using an insulating material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0587] By the above manufacturing method, it is possible to simultaneously manufacture Figures 3A to 3C The transistor ML (VLFET) and 7A to 7C The transistor MV (VFET) is shown.

[0588] The method for manufacturing a semiconductor device according to one embodiment of the present invention is not limited to the method described above. In manufacturing a semiconductor device according to one embodiment of the present invention, the manufacturing method may be modified as appropriate. Furthermore, even if the structure of the semiconductor device changes due to a modification of the manufacturing method, the semiconductor device may still be considered as one embodiment of the present invention.

[0589] Note that this embodiment mode can be combined with the same or other embodiment modes described in this specification as appropriate. For example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in this embodiment mode as appropriate. Furthermore, for example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in other embodiment modes as appropriate.

[0590] (Implementation 5) In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. The OS transistor is briefly described in comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor).

[0591] [OS transistor] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 When the carrier concentration of the oxide semiconductor film is to be reduced, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state with a low impurity concentration and a low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0592] Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes also have a low trap state density. Furthermore, charges trapped in the trap states of the oxide semiconductor take a long time to disappear, sometimes acting like fixed charges. Consequently, transistors with channel formation regions formed in oxide semiconductors with a high trap state density sometimes experience unstable electrical characteristics.

[0593] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components of the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0594] In an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed, which may reduce reliability. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V OH), electrons that become carriers may be generated. In addition, when V O When the voltage is V, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor tends to be normally on (a state in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H.

[0595] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called off-state leakage current or Ioff) of the transistor can be reduced.

[0596] In addition, in Si transistors, as the miniaturization of transistors progresses, the short channel effect (SCE) occurs. Therefore, the miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that silicon has a small band gap. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with a large band gap, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0597] The short-channel effect refers to the degradation of electrical properties that occurs with transistor miniaturization (reduction in channel length). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in the subthreshold swing value (sometimes referred to as the S value), and an increase in leakage current. The S value refers to the change in gate voltage in the subthreshold region that causes a single-digit change in drain current at a fixed drain voltage.

[0598] Characteristic length is widely used as an indicator of resistance to short channel effects. Characteristic length refers to the curvature of the potential in the channel formation region. The smaller the characteristic length, the more steeply the potential rises, and therefore it can be said that the resistance to short channel effects is high.

[0599] OS transistors are accumulation-mode transistors, while Si transistors are inversion-mode transistors. Therefore, the characteristic lengths between the source region and the channel formation region, and the characteristic lengths between the drain region and the channel formation region, are smaller in OS transistors than in Si transistors. Consequently, OS transistors are more resistant to short-channel effects than Si transistors. In other words, when manufacturing transistors with short channel lengths, OS transistors are more suitable than Si transistors.

[0600] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor. Therefore, the energy difference in the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to 0.1 eV or more and 0.2 eV or less. Therefore, the OS transistor can be regarded as having n + / n - / n + The accumulation type junction-less transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel forming region is n - Type region, source region and drain region are n + Type area.

[0601] When the above structure is adopted as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and greater than 1nm, greater than 3nm or greater than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of a short channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is also the width of the bottom surface of the gate electrode when the transistor is viewed from a plane.

[0602] Furthermore, miniaturizing the OS transistor can improve the transistor's high-frequency characteristics. Specifically, the transistor's cutoff frequency can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the transistor's cutoff frequency can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0603] As described above, OS transistors have advantages superior to Si transistors, such as small off-state current and the ability to manufacture transistors with small channel lengths.

[0604] Note that this embodiment mode can be combined with the same or other embodiment modes described in this specification as appropriate. For example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in this embodiment mode as appropriate. Furthermore, for example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in other embodiment modes as appropriate.

[0605] (Implementation 6) In this embodiment, a configuration example of a display device according to one embodiment of the present invention is described.

[0606] <Configuration Example of Display Device> Figure 47A This is a perspective schematic diagram illustrating a display device according to one embodiment of the present invention. For example, the display device DSP1 includes a display area DIS, a drive circuit area DRV, and a terminal area TMR. Furthermore, the display device DSP1 includes a substrate BS, on which the display area DIS, the drive circuit area DRV, and the terminal area TMR are located.

[0607] In addition, for example, the driving circuit region DRV includes a driving circuit GDR1 , a driving circuit GDR2 , and a driving circuit SDR.

[0608] As the substrate BS, for example, a semiconductor substrate (for example, a single crystal substrate made of silicon or germanium) can be used. In addition, as the substrate BS, in addition to the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate including a stainless steel foil, a tungsten substrate, a substrate including a tungsten foil, a flexible substrate, a laminated film, a paper including a fibrous material, or a base film can be used. As an example of a glass substrate, for example, barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass can be cited. As an example of a flexible substrate, a laminated film, a base film, etc., plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. In addition, as another example, a synthetic resin such as an acrylic resin can be cited. In addition, as another example, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be cited. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper. When the manufacturing process of the display device DSP1 includes heat treatment, a highly heat-resistant material is preferably used as the substrate BS.

[0609] In particular, when a semiconductor substrate made of silicon is used as the substrate BS, Si transistors can be used as transistors in the display region DIS and the driver circuit region DRV, and these can be formed on the substrate BS.

[0610] Furthermore, for example, when the transistors included in the display region DIS and the driver circuit region DRV are OS transistors, there is no particular limitation on the substrate on which the OS transistors are formed, and as described above, a substrate that can be used for the substrate BS may be used.

[0611] Furthermore, one or more of the driver circuits GDR1 , GDR2 , and SDR selected from the driver circuit region DRV may be mounted as an IC (Integrated Circuit) on the substrate BS using COG (Chip On Glass) technology.

[0612] For example, the drive circuit GDR1 and the drive circuit GDR2 are both used as drive circuits for displaying an image on the display area DIS. Specifically, for example, the drive circuit GDR1 and the drive circuit GDR2 are both used as gate driver circuits for the display area DIS. Also, for example, the drive circuit SDR is used as a source driver circuit for the display area DIS.

[0613] Therefore, as each of the drive circuit GDR1 and the drive circuit GDR2, for example, the drive circuit GDR1 and the drive circuit GDR2 described in the above embodiment can be used. Figure 10 In addition, as the driving circuit SDR, for example, the one described in the above embodiment can be used. Figure 10 The driving circuit SD.

[0614] The terminal region TMR includes terminals for supplying image signals and power supply voltage from outside the display device DSP1 to the inside of the display device DSP1. Alternatively, a flexible printed circuit (FPC) may be electrically connected to the terminal region TMR. Furthermore, an integrated circuit (IC) chip may be mounted on the FPC using COF (chip-on-film) technology. This IC may include, for example, a driver circuit for displaying images on the display region DIS.

[0615] The display area DIS includes, for example, a plurality of pixels. In addition, the plurality of pixels may be arranged in a matrix in the display area DIS.

[0616] In addition, each of the multiple pixels can represent one color or multiple colors. In particular, the multiple colors can be, for example, three colors: red, green, and blue. In addition, the multiple colors can also be, for example, two or more selected from red, green, blue, cyan, magenta, yellow, and white. When each pixel representing a different color is referred to as a sub-pixel and white is represented by the multiple sub-pixels of different colors, the multiple sub-pixels are sometimes collectively referred to as pixels. In this specification, for convenience, sub-pixels are referred to as pixels for explanation.

[0617] Furthermore, the display device of one embodiment of the present invention is not limited to Figure 47A For example, a display device according to one embodiment of the present invention may also be configured as a display device DSP1. Figure 47B The structure of the display device DSP2 is shown.

[0618] For example, Figure 47B The display device DSP2 shown includes a display area DIS, a circuit area SIC, and a terminal area TMR. Similarly to the display device DSP1, the display device DSP2 includes a substrate BS. The display device DSP2 differs from the display device DSP1 in that the circuit area SIC and the terminal area TMR are provided on the substrate BS, and the display area DIS is provided on the circuit area SIC.

[0619] For example, the circuit region SIC includes the aforementioned driver circuit region DRV. Furthermore, the circuit region SIC may also include various functional circuits other than the driver circuit region DRV. In this embodiment, these functional circuits are included in the functional circuit region MFNC.

[0620] For example, the functional circuit region MFNC may include a GPU (Graphics Processing Unit). Furthermore, when the display device DSP2 includes a touch panel, the functional circuit region MFNC may include a sensor controller that controls a touch sensor included in the touch panel.

[0621] Furthermore, when a light-emitting device using an organic EL material is used as the display element of the display device DSP2, the functional circuit region MFNC may also include an EL correction circuit. The EL correction circuit, for example, functions to appropriately adjust the current input to the light-emitting device containing the organic EL material. The brightness of a light-emitting device containing the organic EL material is proportional to the current. Therefore, if the characteristics of the drive transistor electrically connected to the light-emitting device are poor, the brightness of the light emitted by the light-emitting device may be lower than the desired brightness. For example, the EL correction circuit can monitor the current flowing through the light-emitting device and, if the current is lower than the desired level, increase the current flowing through the device to improve the brightness of the light emitted by the device. Conversely, if the current is higher than the desired level, the current flowing through the light-emitting device can be adjusted to a lower level.

[0622] Furthermore, when a liquid crystal element is used as a display element of the display device DSP2, the functional circuit region MFNC may include a gamma correction circuit.

[0623] Figure 48 It shows Figure 47B FIG. 1 is a block diagram showing an example of the structure of the display device DSP2. Figure 48 The display device DSP2 shown includes a display area DIS and a circuit area SIC. Figure 48 The sensor PDA is shown, and the sensor PDA can be configured inside or outside the display device DSP2.

[0624] in addition, Figure 47A The display device DSP1 can also be electrically connected to the functional circuit area MFNC located outside the display device DSP1 through the terminal area TMR. In this case, the structure of the display device DSP1 can be regarded as the same as that of the display device DSP1. Figure 48 The display device DSP2 shown has the same structure.

[0625] exist Figure 48 , thick solid lines represent multiple wires or buses.

[0626] In addition, Figure 48 For example, in the display area DIS, a plurality of pixel circuits PX are arranged in a matrix. The pixel circuits PX may be, for example, pixel circuits using one or more light-emitting devices selected from a liquid crystal display device, a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting diode such as a micro-LED. Note that this embodiment describes a case where a light-emitting device including an organic EL material is used in the pixel circuits PX of the display area DIS.

[0627] In addition, as mentioned above, Figure 48The middle circuit region SIC includes a driving circuit region DRV and a functional circuit region MFNC.

[0628] The driving circuit region DRV is used as a peripheral circuit for driving the display region DIS. Specifically, the driving circuit region DRV includes, for example, a driving circuit SDR, a digital-to-analog conversion circuit DAD, a driving circuit GDR, and a level converter circuit LVS. The driving circuit SDR is equivalent to Figure 10 The drive circuit SD and the drive circuit GDR are equivalent to Figure 10 The driving circuit GD in.

[0629] In addition, for example, the functional circuit area MFNC may be provided with: a storage device for storing image data displayed on the display area DIS; a decoder for decoding coded image data; a GPU, a power supply circuit, a correction circuit or a CPU for processing image data. Figure 48 For example, the functional circuit region MFNC includes a memory device MEM, a GPU 22 , an EL correction circuit ECR, a timing controller TMC, a CPU (NoffCPU (registered trademark)) 21 , a sensor controller SCC, and a power supp...

Claims

1. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; Seventh transistor; a first capacitor; as well as The second capacitor, wherein the first gate of the first transistor is electrically connected to the first gate of the second transistor, One of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor, the first gate of the fourth transistor, the first gate of the seventh transistor, and one of the pair of electrodes of the first capacitor. One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fourth transistor and one of the source and the drain of the fifth transistor, The other of the source and the drain of the fifth transistor is electrically connected to one of the pair of electrodes of the second capacitor and the gate of the sixth transistor. One of the source and the drain of the sixth transistor is electrically connected to the other of the pair of electrodes of the second capacitor and one of the source and the drain of the seventh transistor, The second transistor and the fourth transistor each include a first conductive layer serving as one of a source and a drain, a second conductive layer serving as the other of the source and the drain, a third conductive layer serving as a first gate, a semiconductor layer, and a gate insulating film. The first conductive layer and the second conductive layer both include a region in contact with the top surface of the first insulating layer, The semiconductor layer includes a region in contact with a side surface of an opening formed in the first insulating layer, a top surface of the second insulating layer at the bottom of the opening, a top surface of the first conductive layer, and a top surface of the second conductive layer. The gate insulating film includes a region in contact with a top surface of the semiconductor layer, a top surface of the first conductive layer, and a top surface of the second conductive layer. The third conductive layer includes a region overlapping with at least a portion of the semiconductor layer and in contact with a top surface of the gate insulating film. Furthermore, each channel formation region of the second transistor and the fourth transistor is included in the semiconductor layer.

2. The semiconductor device according to claim 1, wherein the second transistor and the fourth transistor both include a fourth conductive layer serving as a second gate, The fourth conductive layer includes a region overlapping with at least a portion of the semiconductor layer and in contact with a bottom surface of the second insulating layer.

3. The semiconductor device according to claim 2, wherein the semiconductor layer comprises one or more selected from indium, zinc and element M, The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony.

4. The semiconductor device according to claim 3, further comprising: The eighth transistor, wherein the gate of the eighth transistor is electrically connected to one of the source and drain of the sixth transistor, the other of the pair of electrodes of the second capacitor, and one of the source and drain of the seventh transistor, And one of the source and the drain of the eighth transistor is electrically connected to one of the source and the drain of the first transistor, one of the source and the drain of the fourth transistor, and one of the source and the drain of the fifth transistor.

5. A display device comprising: Drive circuit; as well as Display devices, wherein the driving circuit comprises the semiconductor device according to any one of claims 1 to 4, And the driving circuit has a function of sending a signal for displaying an image to the display device.

6. The display device according to claim 5, The display device includes a light emitting device or a liquid crystal display device.

7. An electronic device comprising: The display device according to claim 6; as well as shell.

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