Transmitting module and method for transmitting differential signal in serial bus system

Abstract

A transmission module (121; 121 ') for transmitting a differential signal in a serial bus system (1) is provided. 1210, 1210; 1211, 1211; 1212) and methods. The transmitting module (121; 1210, 1210; 1211, 1211; 1212) has: a first transmission stage (121A; 121A1) for generating a transmission current (I1 to In) for a first signal (CANH) to be transmitted onto a bus (40) of the bus system (1); the second transmitting stage (121B; 121B1) for generating a transmission current (I1 to In) for a second signal (CANL) to be transmitted onto the bus (40) as a differential signal of the first signal (CANH); the third transmitting stage (121C; 121C1) for generating a transmission current (I1 to In) for the first signal (CANH); the fourth transmitting stage (121D; 121D1) for generating a transmission current (I1 to In) for the second signal (CANL); and an adjustment circuit (15; 15A; 15B; 15B) for equalizing the first to fourth transmission stages (121A to 121D; 121A1 to 121D1), and a common mode voltage (VCM) of the first voltage (121A1 to 121D1); wherein the first to fourth transmitting stages (121A to 121D; 121A1 to 121D1) are connected in a full bridge, wherein the first and fourth transmitting stages (121A, 121D; 121A1, 121D1) are connected in series, and the third and second transmitting stages (121C, 121B; 121C1, 121B1) are connected in series, wherein the regulating circuit (15; 15A; 15B; 15B) has a transmission module (121; 1210, 1210; 1211, 1211; 1212), a replica of the output stage (152; 153, 154; 153A), and wherein the replica (152; 153, 154; 153A) is connected to the transmitting module (121; 1210, 1210; 1211, 1211; 1212) of the output stage.

Description

Technical Field

[0001] The present invention relates to a transmission module and a method for transmitting differential signals in a serial bus system, which can be used in particular for CANXL while adhering to emission limit values ​​(EMC). Background Art

[0002] Serial bus systems are used for the transmission of messages or data in technical installations. For example, they enable communication between sensors and control devices in vehicles or technical production facilities.

[0003] In a CAN bus system, messages are transmitted using the CAN and / or CAN FD protocols, as described in the standard ISO 11898-1:2015 as the CAN protocol specification under the name CAN FD. In CAN FD, transmission on the bus switches back and forth between a slow mode in the first communication phase (arbitration phase) and a fast mode in the second communication phase (data phase). In a CAN FD bus system, data transmission rates exceeding 1 megabit per second (1 Mbps) can be achieved in the second communication phase. CAN FD is used in vehicles by most manufacturers with an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s in the first stage.

[0004] To achieve even higher data rates in the second communication phase, there are successor bus systems to CAN FD, such as CAN-SIC and CAN XL. With CAN-SIC, which is based on the CiA601-4 standard of the CAN in Automation (CiA) organization, data rates of approximately 5 to 8 Mbit / s can be achieved in the second communication phase. With CAN XL, data rates of >10 Mbit / s are required in the second communication phase. Currently, the CiA610-3 standard is defined for CAN XL.

[0005] To send and receive bus signals, a CAN bus system typically uses a transmit / receive device for each communication participant. These are also called CAN transceivers or CAN FD transceivers, for example. The transmit function of a CAN transceiver is implemented in a module called a transmitter. The transmitter converts the digital states of the digital transmit signal (HI = high or LW = low) into a differential bus signal between bus terminals CANH and CANL.

[0006] In all the CAN-based bus systems described above, for the transmit signal TxD, the bus signal CAN_H is driven onto the bus alone, and ideally, the bus signal CAN_L with a predetermined bus level or bus voltage V_CAN_H, V_CAN_L is also driven onto the bus simultaneously. In this case, at least in the first communication phase, one bus state is actively driven in the bus signals CAN_H and CAN_L. The other bus state is not driven and is adjusted based on the terminal resistance of the bus lines or bus cores of the bus. The resulting voltage on the bus is the differential voltage VDIFF = CAN_H - CAN_L, more precisely, the differential voltage is equal to the voltage U of the signal CAN_H minus the voltage U of the signal CAN_L.

[0007] The differential voltage VDIFF varies depending on the state to be transmitted on the bus. For the dominant state, VDIFF_dom = 2V. For the recessive state, VDIFF_rec = 0V. For the Level 0 state, VDIFF_L0 = 1V. For the Level 1 state, VDIFF_L1 = -1V. However, for all the above states, the two bus levels or voltage amplitudes VCAN_H and VCAN_L of the signals CAN_H and CAN_L should be kept at the common mode voltage V CM = VCAN_H + VCAN_L = 5V. This is important because the common mode voltage V CM The change in VCC causes interference emission from the CAN transceiver. The value of 5V corresponds to the value of the voltage Vcc, which is also called the CAN power supply (Supply). In order to comply with the CAN specifications (ISO 11898-2:2016, CiA601-4, CiA610-3) and EMC standards (IEC 62228-3), the common-mode voltage V CM The same applies during the switching process between different bus states.

[0008] CAN or CAN FD transceivers must not exceed the limit values ​​for conducted emissions or emissions for operation in vehicles. Compared to CAN FD and CAN SIC, CAN XL transceivers must also adhere to the stricter limit values ​​specified in standard IEC 62228-3. This is necessary to operate the bus system at the required higher bit rates. Due to the available semiconductor technology, adhering to these strict limit values ​​is a significant challenge. Summary of the Invention

[0009] Therefore, the object of the present invention is to provide a transmission module and a method for transmitting differential signals in a serial bus system, which solve the aforementioned problems. In particular, the transmission module and the method for transmitting differential signals in a serial bus system should be able to compensate for interference variables that influence the transmission behavior of the transmission module.

[0010] This object is achieved by a transmission module for transmitting a differential signal in a serial bus system, having the features of claim 1. The transmission module comprises a first transmission stage for generating a transmission current for a first signal to be transmitted on a bus of the bus system; a second transmission stage for generating a transmission current for a second signal to be transmitted on the bus as a differential signal of the first signal; a third transmission stage for generating a transmission current for the first signal; a fourth transmission stage for generating a transmission current for the second signal; and a control circuit for equalizing the common mode voltages of the first to fourth transmission stages, wherein the first to fourth transmission stages are connected in the form of a full bridge, wherein the first and fourth transmission stages are connected in series, and the third and second transmission stages are connected in series, wherein the control circuit comprises a copy of an output stage of the transmission module, and wherein the copy is connected to the output stage of the transmission module.

[0011] The transmitting module is designed to always keep the common mode voltage at exactly the same voltage, regardless of the bus signal VDIFF. This also applies during switching operations between the different bus states dom, sic and rec or L0 and L1.

[0012] In particular, the transmitter module ensures that the common-mode voltage remains constant even if it is affected by the temperature and process dependencies of the transmitter module's diodes and cascodes (device parameters and leakage currents). This also applies to transmitter modules whose resistor bridges (also known as current-controlled H-bridges) still have an additional dependency on the equalization (matching or mismatching) of the bias currents. Furthermore, this also applies to transmitter modules whose resistor bridges (also known as resistive H-bridges) have an additional temperature and process dependency on the channel resistance of the current-limiting transistors.

[0013] The transmit module thus enables the required limit values ​​for transmission of a CAN XL transmit / receive device to be achieved. In particular, the transmit module complies with the IEC 62228-3 standard, which specifies the limit values ​​to be observed for bus states dom, sic, and rec on the CAN XL bus and for presettings. These limit values ​​are generated based on the transmit states dom, sic, and rec of the transmit module.

[0014] As a result, the transmitting module is prevented from transmitting and thus allows operation at a higher bit rate in the bus system.

[0015] Further advantageous embodiments of the transmission module are described in the dependent claims.

[0016] The common mode point of the replica can be at the common mode voltage of the output of the transmission stage. According to one embodiment, the regulation circuit further comprises a differential amplifier whose input is connected to the common mode point of the replica, and a regulation transistor for regulating the common mode voltage to a predetermined value, wherein the common mode voltage is applied to the common mode point of the replica.

[0017] It is conceivable that the replica includes a series circuit consisting of a transistor, a diode, a transistor, a diode, a transistor, and a transistor in the stated order, wherein the size of the components in the series circuit is a predetermined multiple smaller than the size of the output devices of the first and fourth transmission stages. In this case, the transistor and the transistor can each be configured as a cascode structure.

[0018] In the aforementioned transmitting module, the output of the full bridge can be provided for connection to a terminating resistor of a bus, wherein the replica in the series circuit has a bus load that is a replica of the terminating resistor of the bus.

[0019] According to one embodiment, the bus load has two resistors, both connected to the common mode point of the replicas.

[0020] According to another embodiment, the replica has a switching unit for switching the bus load on or off.

[0021] Each transmitting stage can be designed to adjust the value of the current output by the transmitting stage during operation of the transmitting module using a current mirror at the input of the transmitter.

[0022] The current mirror at the input end of each transmitting stage may have two CMOS transistors, wherein the CMOS transistor of the current mirror at the input end of the first transmitting stage is a PMOS transistor, wherein the CMOS transistor of the current mirror at the input end of the second transmitting stage is an NMOS transistor, wherein the CMOS transistor of the current mirror at the input end of the third transmitting stage is a PMOS transistor, and wherein the CMOS transistor of the current mirror at the input end of the fourth transmitting stage is an NMOS transistor.

[0023] Each transmission stage may have at least two current stages connected in parallel. In this case, the at least two current stages may have at least one current sink. The number n of the at least two current stages may be the same for each of the first to fourth transmission stages, where n is a natural number greater than 1.

[0024] The transmission module may also have a first resistor having one end connected to the first transmission stage and the other end connected to the third transmission stage; and a second resistor having one end connected to the second transmission stage and the other end connected to the fourth transmission stage.

[0025] The transmission module may further include a control circuit for controlling the switchable components of the first to fourth transmission stages in accordance with the digital transmission signal and the operating mode set for the transmission module. The control circuit may be configured to switch the resistance values ​​of at least two current stages in a time-staggered and controlled manner.

[0026] The aforementioned transmitting module may be part of a transmitting / receiving device of a subscriber station of a serial bus system, the transmitting / receiving device also having a receiving module for receiving signals from the bus.

[0027] The transmitting / receiving device can be part of a subscriber station of a serial bus system, which also has a communication control device for controlling the communication in the bus system and generating digital transmit signals for actuating the first to fourth transmitting stages.

[0028] Possibly, the subscriber station is designed to communicate in a bus system in which exclusive, conflict-free access to a bus of the bus system is guaranteed to the subscriber station at least temporarily.

[0029] The above object is also achieved by a method for transmitting differential signals in a serial bus system having the features of claim 20. The method is implemented using a transmitting module having first to fourth transmitting stages and a control circuit, wherein the method comprises the following steps: generating a transmit current for a first signal to be transmitted on a bus of the bus system using the first transmitting stage; generating a transmit current for a second signal to be transmitted on the bus as a differential signal of the first signal using the second transmitting stage; generating a transmit current for the first signal using the third transmitting stage; generating a transmit current for the second signal using the fourth transmitting stage; and equalizing the common mode voltage of the first to fourth transmitting stages using the control circuit, wherein the first to fourth transmitting stages are connected in full bridge form, wherein the first and fourth transmitting stages are connected in series, and the third and second transmitting stages are connected in series, wherein the control circuit comprises a copy of an output stage of the transmitting module, and wherein the copy is connected to the output stage of the transmitting module.

[0030] This method provides the same advantages as the aforementioned sending module.

[0031] Other possible implementations of the present invention also include combinations not explicitly mentioned of features or embodiments described above or below with respect to the embodiments. Here, professionals can also add various aspects as improvements or supplements to the corresponding basic forms of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention will be described in more detail below with reference to the accompanying drawings and according to embodiments, wherein:

[0033] Figure 1 shows a simplified block diagram of a bus system according to a first embodiment;

[0034] Figure 2 A diagram illustrating the structure of a message that can be sent by a user station of a bus system according to a first exemplary embodiment is shown;

[0035] Figure 3 Show Figure 1 Example of ideal time curves of bus signals CAN_H and CAN_L in a bus system;

[0036] Figure 4 Shown due to Figure 3 The time variation curve of the differential voltage VDIFF generated on the bus of the bus system due to the bus signal;

[0037] Figure 5 An example of the time profile of a digital transmission signal, which is to be converted into a signal in the arbitration phase (SIC operating mode) Figure 1 The bus signals CAN_H and CAN_L of the bus system;

[0038] Figure 6 Shown in the arbitration phase (SIC working mode) based on Figure 5 The time variation curve of the bus signals CAN_H and CAN_L sent to the bus when they switch between the recessive bus state and the dominant bus state and return to the recessive bus state;

[0039] Figure 7 An example of the time profile of a digital transmission signal, which should be converted into a Figure 1 The bus signals CAN_H and CAN_L of the bus system;

[0040] Figure 8 Shown in the data stage based on Figure 7 The time variation curve of the bus signals CAN_H and CAN_L sent to the bus by the sending signal;

[0041] Figure 9 A circuit diagram showing a transmission module of a user station of a bus system according to a first embodiment;

[0042] Figure 10 A timing diagram is shown, which is used to illustrate Figure 9 switching on different current levels of a transmitting stage of a first specific example of a transmitting module;

[0043] Figure 11 Show Figure 9 Send level details of a second specific example of a send module;

[0044] Figure 12 A circuit diagram showing a transmission module of a subscriber station of a bus system according to a second embodiment;

[0045] Figure 13 A circuit diagram showing a transmission module of a subscriber station of a bus system according to a third embodiment; and

[0046] Figure 14 A circuit diagram of a transmit module of a subscriber station of a bus system according to a fourth exemplary embodiment is shown.

[0047] In the figures, identical or functionally identical elements are provided with the same reference symbols unless stated otherwise. DETAILED DESCRIPTION

[0048] Figure 1 A bus system 1 is shown, which may for example be at least partially a CAN bus system, a CAN-FD bus system etc. The bus system 1 may be used in vehicles, in particular motor vehicles, aircraft etc., or in hospitals etc.

[0049] exist Figure 1 In FIG, bus system 1 has a plurality of subscriber stations 10, 20, and 30, which are connected to a bus 40 or bus line using a first bus core 41 and a second bus core 42, respectively. For signals on bus 40, bus cores 41 and 42 may also be referred to as CAN_H and CAN_L. Messages 45, 46, and 47 can be transmitted in the form of signals between the individual subscriber stations 10, 20, and 30 via bus 40. Subscriber stations 10, 20, and 30 may be, for example, control units or display devices of a motor vehicle.

[0050] like Figure 1 As shown in FIG, each of the user stations 10 and 30 includes a communication control device 11 and a transmitting / receiving device 12. The transmitting / receiving device 12 includes a transmitting module 121 and a receiving module 122.

[0051] The user station 20 includes a communication control device 21 and a transmitting / receiving device 22 . The transmitting / receiving device 22 includes a transmitting module 221 and a receiving module 222 .

[0052] The transmitting / receiving devices 12 of the subscriber stations 10, 30 and the transmitting / receiving device 22 of the subscriber station 20 are each directly connected to the bus 40, although this is not the case. Figure 1 Not shown in the figure.

[0053] The communication control devices 11 , 21 are each used to control communication between the corresponding subscriber station 10 , 20 , 30 and at least one other subscriber station among the subscriber stations 10 , 20 , 30 connected to the bus 40 via the bus 40 .

[0054] The communication control device 11 creates and reads first messages 45 and 47, which are, for example, modified CAN messages 45 and 47. In this case, the modified CAN messages 45 and 47 are constructed, for example, based on the CAN SIC format or the CAN XL format. The transmitting / receiving device 12 is used to transmit and receive messages 45 and 47 from the bus. The transmitting module 121 receives the digital transmit signal TxD created by the communication control device 11 for one of the messages 45 and 47 and converts it into a signal on the bus 40. The receiving module 121 receives the signal corresponding to the message 45 to 47 transmitted on the bus 40 and generates a digital receive signal RxD therefrom. The receiving module 122 transmits the receive signal RxD to the communication control device 11.

[0055] The communication control device 21 can be implemented as a conventional CAN controller according to ISO 11898-1:2015, that is, as a classic CAN controller or a CAN FD-compatible CAN controller. The communication control device 21 creates and reads a second message 46, for example, a CAN FD message 46. The transmit / receive device 22 is used to transmit and receive message 46 from the bus 40. The transmit module 221 receives the digital transmit signal TxD created by the communication control device 21 and converts it into a signal representing message 46, which is transmitted on the bus 40. The receive module 221 receives the signals corresponding to messages 45 to 47 transmitted on the bus 40 and generates a digital receive signal RxD therefrom. Otherwise, the transmit / receive device 22 can be implemented as a conventional CAN transceiver.

[0056] To transmit messages 45 and 47 using CAN XL or CAN SIC, proven features are used that ensure the robustness and user-friendliness of CAN and CAN FD, in particular the frame structure with identifiers and arbitration according to the known CSMA / CR method. The CSMA / CR method requires so-called recessive states on the bus 40, which can be overwritten by other subscriber stations 10, 20, 30 on the bus 40 with dominant levels or dominant states.

[0057] With the two subscriber stations 10 , 30 , messages 45 in various CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, can be formed and then transmitted, as well as such messages 45 can be received, as described in more detail below.

[0058] Figure 2For message 45, a frame 450 is shown, which is in particular a CAN XL frame, as provided by communication control device 11 to transceiver device 12 for transmission onto bus 40. In this embodiment, communication control device 11 creates a CAN FD-compatible frame 450. Alternatively, frame 450 may be CAN SIC-compatible.

[0059] according to Figure 2 Frame 450 used for CAN communication on bus 40 is divided into different communication phases 451 and 452, namely, arbitration phase 451 (first communication phase) and data phase 452 (second communication phase). After the start bit SOF, frame 450 has an arbitration field 453, a control field 454, a first handoff field 455, a data field 456, a checksum field 457, a second handoff field 458, and a frame termination field 459. Checksum field 457, second handoff field 458, and frame termination field 459 constitute the frame termination phases 457, 458, and 459 of frame 450.

[0060] In arbitration phase 451, using identifiers (IDs) in arbitration field 453, a bit-by-bit negotiation is carried out between user stations 10, 20, 30 as to which user station 10, 20, 30 wishes to send message 45, 46 with the highest priority and thereby obtain exclusive access to bus 40 of bus system 1 for transmission in the subsequent data phase 452. In arbitration phase 451, a physical layer, as in CAN and CAN-FD, is used. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model 1).

[0061] The key point during phase 451 is to use the known CSMA / CR method, which allows user stations 10, 20, 30 to access bus 40 simultaneously without disrupting higher-priority messages 45, 46. This makes it relatively easy to add further bus user stations 10, 20, 30 to bus system 1, which is very advantageous.

[0062] The CSMA / CR method requires so-called recessive states on bus 40, which can be overwritten by other user stations 10, 20, 30 on bus 40 with dominant levels or dominant states. In the recessive state, a high impedance state is present at each user station 10, 20, 30, which, combined with the parasitic effects of the bus wiring, results in longer time constants. This limits the maximum bit rate of the current CAN FD physical layer to approximately 2 megabits per second in practical vehicle use.

[0063] At the end of the arbitration phase 451 , a switch is made to the data phase 452 by means of a first switch field 455 .

[0064] In data phase 452, in addition to a portion of first switching field 455, payload data of CAN-XL frame 450 or message 45 from data field 456 as well as checksum field 457 and a portion of second switching field 458 are transmitted. At the end of data phase 452, a switch is made back to arbitration phase 451 using second switching field 458.

[0065] At least one acknowledge bit may be included in the end field of the end-of-frame field 459. In addition, a sequence of 11 identical bits may be present, indicating the end of the CAN XL frame 450. The at least one acknowledge bit may be used to inform the receiver whether an error was found in the received CAN XL frame 450 or message 45.

[0066] Only when the sending subscriber station 10 wins the arbitration and thus has exclusive access to the bus 40 of the bus system 1 for transmission does the sender of the message 45 start sending the bits of the data phase 452 onto the bus 40 .

[0067] Thus, in arbitration phase 451, the first communication phase, user stations 10, 30 partially use the format known from CAN / CAN-FD according to ISO 11898-1:2015, in particular up to and including the FDF bit. However, in data phase 452, the second communication phase, the net data transmission rate can be increased compared to CAN or CAN FD, in particular reaching over 10 megabits per second. The size of the payload data per frame can also be increased, in particular to approximately 2 kilobytes or any other value.

[0068] like Figure 3 As shown in FIG, in the arbitration phase 451, the transmitting / receiving device 12 uses the physical layer 451_P to transmit the transmission signal TxD ( Figure 1 ) are sent as signals CAN_H, CAN_L to the bus 40. The same applies to the transmitting / receiving device 22. In contrast, the transmitting / receiving device 12 can use a physical layer 452_P different from the physical layer 451_P in the data phase 452 to transmit the transmission signal TxD ( Figure 1 ) are sent as signals CAN_H, CAN_L onto the bus 40, as described above. There are two operating modes for the 452_P physical layer, namely FAST_TX and FAST RX, as described in more detail below.

[0069] Figure 3As shown on the left, in arbitration phase 451, subscriber stations 10, 20, and 30 each transmit signals CAN_H and CAN_L to bus 40 during time t, with a first bit duration t_bt1. Signals CAN_H and CAN_L are serial signals and alternately have at least one dominant state 401, where VCAN_H = 3.5V and VCAN_L = 1.5V, or at least one recessive state 402, where VCAN_H = VCAN_L = 2.5V. In phase 451, when TXD = 0 or L (low), dominant state 401 is driven when NRZ encoding is performed on transmit signal TXD. In phase 451, when TXD = 1 or H (high), recessive state 402 is generated or occurs when NRZ encoding is performed on transmit signal TXD. After arbitration in arbitration phase 451, one of subscriber stations 10, 20, and 30 is determined as the winner.

[0070] If the user station 10, 20, 30 recognizes Figure 3 If a signaling signal is received in the first switching field 455 of the data link 451 for switching from the first communication phase 451 to the second communication phase 452, the corresponding transmitting / receiving device 12 switches its physical layer 451_P from the first operating mode (SLOW) (which can also be implemented as an SIC operating mode) to the physical layer 452_P of the data phase 452 at the end of the arbitration phase 451. To this end, the operating mode of the data phase 452 is switched on.

[0071] For example, if the first user station 10 wins the arbitration, the transmitting / receiving device 12 of the user station 10, in particular based on Figure 2 Signaling in the first switching field 455 of the - at the end of the arbitration phase 451, its physical layer 451_P is switched from the first operating mode (SLOW) to the physical layer 452_P of the data phase 452 for the second operating mode (FAST_TX) of the transmitting / receiving device 12, since the subscriber station 10 is the sender of the message 45 in the data phase 452. Figure 3 As shown in FIG, transmit module 121 then uses physical layer 452_P to generate the state L0 or L1 for signals CAN_H, CAN_L on bus 40 in data phase 452 or in second operating mode (FAST_TX) in accordance with transmit signal TxD in sequence and thus serially. Conversely, for example, transmit / receive device 12 of subscriber station 30 switches its physical layer 451_P from the first operating mode (SLOW or SIC) to physical layer 452_P of data phase 452 of transmit / receive device 12's third operating mode (FAST_RX) at the end of arbitration phase 451, since subscriber station 30 is only a receiver of frame 450 in data phase 452, i.e., not a transmitter.

[0072] In the data phase 452, the frequency of the signals CAN_H, CAN_L may be increased. Figure 3 In the example of FIG. 4 , the bit time or bit duration t_bt2 in the data phase 452 is shorter or smaller than the bit time or bit duration t_bt1 in the arbitration phase 451 . Figure 3 In the example of FIG. 4 , the net data transfer rate in the data phase 452 is increased.

[0073] If the transmitting / receiving device 12 (especially using Figure 2 If a switch from data phase 452 back to arbitration phase 451 is identified (by the signaling in second switch field 458 of ), then the transceiver 12 switches from transmitting (operating mode FAST_TX) or receiving (operating mode FAST_RX) signals using physical layer 452_P to transmitting and / or receiving signals using physical layer 451_P. Consequently, after the end of data phase 452, all transceiver 12 switches their operating mode to the first operating mode (SLOW or SIC). Consequently, all transceiver 12 can switch not only between bit durations t_bt1 and t_bt2 but also their physical layer, as previously described.

[0074] according to Figure 4 In the arbitration phase 451 , ideally, over time t, a differential signal VDIFF=CAN_H−CAN_L is formed on the bus 40 , which has a value of VDIFF=2V for the dominant state 401 and a value of VDIFF=0V for the recessive state 402 . Figure 4 The left side shows the variation curve of VDIFF in phase 451. In contrast, in data phase 452, a corresponding VDIFF is formed on bus 40 as time t increases. Figure 4 The differential signal VDIFF of state L0 and L1 is VDIFF = CAN_H-CAN_L, as shown in Figure 4 As shown on the right, state L0 has a value of VDIFF=1V. State L1 has a value of VDIFF=-1V.

[0075] The receiving module 122 can use two of the receiving thresholds T1, T2, and T3 to distinguish between the states 401 and 402, wherein the receiving thresholds T1, T2, and T3 are within the range of TH_T1, TH_T2, and TH_T3. Figure 3 or Figure 4 The signal is sampled, as in Figure 4To evaluate the sampling result, the receiving module 122 uses a receiving threshold T1 of, for example, 0.7 V and a receiving threshold T2 of, for example, -0.35 V in the arbitration phase 451. In contrast, in the data phase 452, the receiving module 122 uses only the signal evaluated using the receiving threshold T3. Figure 3 When switching between the first to third operating modes (SLOW or SIC, FAST_TX, FAST_RX) described above, the receiving module 122 switches the receiving thresholds T2 and T3 respectively.

[0076] The reception threshold T2 is used to identify whether the bus 40 is idle when the user station 12 newly accesses the communication at the bus 40 and attempts to integrate itself into the communication at the bus 40.

[0077] When receiving a corresponding signal from the bus 40, each transmitting / receiving device 12 generates a corresponding receiving signal RxD, such as Figure 1 As shown in . Ideally, there is no time offset between the received signal RxD and the transmitted signal TxD.

[0078] Figure 5 An example of a portion of a digital transmission signal TxD is shown, which the transmission module 121 receives from the communication control device 11 in the arbitration phase 451 and generates the signals CAN_H, CAN_L for the bus 40 based on it. Figure 5 In the state LW (low=Low), the transmission signal TxD changes from the state LW (low=Low) to the state HI (high=High), and changes back to the state LW (low=Low).

[0079] like Figure 6 As shown in more detail in FIG, the sending module 121 is for Figure 5 The transmit signal TxD generates the signals CAN_H, CAN_L of the bus cores 41, 42, so that the state 403 (sic) is also present. The state 403 (sic) can be of different lengths, as shown by the state 403_0 (sic) at the transition from the state 402 (rec) to the state 401 (dom) and the state 403_1 (sic) at the transition from the state 401 (dom) to the state 402 (rec). The state 403_0 (sic) is shorter in time than the state 403_1 (sic). In order to generate the state 403 (sic) according to Figure 6 signal, switches the sending module 121 to the SIC operation mode (SIC mode).

[0080] In CiA610-3, the short sic state 403_0 does not need to be traversed and the state depends on the implementation. For CAN-SIC and for the SIC operating mode in the case of CAN-XL, the duration of the "long" state 403_1 (sic) is specified as t_sic < 530ns. Figure 5 The transmission starts with the rising edge of the transmission signal TxD.

[0081] In the "long" state 403_1 (sic), transmit module 121 should adapt the impedance between bus cores 41 (CANH) and 42 (CANL) as closely as possible to the characteristic wave impedance Zw of the bus line being used. Here, Zw = 100 ohms or 120 ohms. This adaptation prevents reflections and thus allows operation at higher bit rates. For simplicity, this will be referred to below as state 403 (sic) or sic state 403.

[0082] The transmitting module 121 may be configured to generate the following CAN-type signals for the bus 40 : CAN-FD, CAN-SIC, and CAN-XL.

[0083]

[0084] Table 1: CAN_Type for Transmitter Module 121

[0085] Therefore, the send module status sic can be generated not only in the case of CAN-SIC or CAN-XL (x1_sic), but also in the case of CAN-FD. However, in CAN-FD, the time for sending the module status sic can be shorter than in the case of CAN-SIC or CAN-XL.

[0086] Figure 7 An example of another part of the digital transmission signal TxD is shown, which the transmission module 121 receives from the communication control device 11 in the data phase 452 and generates the signals CAN_H, CAN_L for the bus 40 based on it. Figure 7 In FIG. 1 , the transmission signal TxD changes from the state HI (high) to the state LW (low) and then to the state HI (high), and so on many times.

[0087] like Figure 8 As shown in more detail in FIG, the sending module 121 is for Figure 7 The transmit signal TxD generates signals CAN_H and CAN_L for the bus cores 41 and 42, so that the state L0 is formed for the state LW (low=Low) and the state L1 is formed for the state HI (high=High).

[0088] Figure 9The basic structure of the sending module 121 for one of the user stations 10, 30 is shown. The sending module 121 can generate Figure 3 Signals CAN_H, CAN_L with states 401, 402, 403 and states L0, L1. Alternatively, the sending module 121 may generate signals according to Figure 6 Signals CAN_H, CAN_L with states 401, 402, 403 and according to Figure 8 The signals CAN_H and CAN_L have states L0 and L1. The transmitting module 121 has a regulating circuit 15 for balancing the common mode voltage V of the low impedance recessive state sic. CM .

[0089] Transmitter module 121 has four transmit stages: a first transmit stage 121A, a second transmit stage 121B, a third transmit stage 121C, and a fourth transmit stage 121D. Transmitter stages 121A through 121D are connected to form an H-bridge or a full-bridge. The components of transmit stages 121A through 121D, described in more detail below, are controlled by at least one control device 124. At least one control device 124 sends at least one signal to a control terminal 125 to which the components of transmit stages 121A through 121D are connected.

[0090] The transmission module 121 is connected to the bus 40 , more precisely via a terminal CANH of a first bus core 41 for CAN_H and via a terminal CANL of a second bus core 42 for CAN_L. Each of the transmission stages 121A to 121D is connected to the bus 40 .

[0091] A voltage supply is provided via at least one terminal 43 of the transmission module 121 for supplying electrical energy to the terminals CANH, CANL of the first and second bus wires 41 , 42 , in particular the CAN supply voltage, typically 5 V. A connection to ground or CAN_GND is provided via terminal 44 .

[0092] The first and second bus cores 41, 42 are terminated with a terminating resistor 49. The terminating resistor 49 is connected as an external load resistor in the full bridge. The resistor 49 is connected between the terminals of the bus cores 41, 42 in the bridge branches.

[0093] The regulating circuit 15 is connected to the transmission stages 121A to 121D. The regulating circuit 15 is not directly connected to the bus 40 but is connected to the bus 40 via the transmission stages 121A to 121D.

[0094] Figure 9 The regulating circuit 15 regulates the low impedance recessive state sic, and uses the regulating common mode voltage V CM The exact same value is always maintained on bus 40, regardless of the bus signal or e.g. Figure 4 This can reduce the interference caused by the transmitting module 121, which may be caused by the common mode voltage V CM This makes it possible to meet the CAN specifications (ISO 11898-2:2016, CiA601-4, CiA610-3) and EMV standards (IEC 62228-3).

[0095] For this purpose, the regulating circuit 15 comprises a differential amplifier 151, a replica 152 of the output stage of the transmission stage 121 and a regulating transistor MN CTRL .according to Figure 9 , replica 152 has a transistor MP R 、Diode MN DIOPR , transistor MP CASPR 、Diode MN DIONR , transistor MP CASNR and transistor MN R The replica 152 is a replica of the output stage of the transmission stage 121, which has a transistor MP0, a diode MN DIOPH , transistor MP CASPH 、Diode MN DIONH , transistor MP CASNH The above-mentioned components of the output stage of the transmitting stage 121 are also components of the transmitting stages 121A and 121D, which will be described in more detail below.

[0096] according to Figure 9 , the differential amplifier 151 implements the common mode voltage V CM With the rated common mode voltage V REF The common mode voltage V CM is tapped at the common mode point or tap point 157 of the replica 152. Therefore, a comparison voltage ΔV=V is present at the input of the differential amplifier 151. REF -V CM Current I CTRL and I BIAS The required equalization voltage is derived from the comparison voltage ΔV. In particular, V REF =2.5V=5V / 2=CAN_SUPPLY / 2.

[0097] In order to keep the current consumption in the replica 152 of the regulating circuit 15 low, all components in the replica 152, namely the transistors MP R 、Diode MN DIOPR , transistor MP CASPR 、Diode MN DIONR , transistor MP CASNR and transistor MN R- should be or should have scaled dimensions of the components of the output stage of the transmission stage 121. In particular, the dimensions of the components in the replica 152 are one hundred times smaller than the dimensions of the components of the output stage of the transmission stage 121. Of course, other factors can be selected. What is important here is that the replica 152 consists of the same component type as used in the output stage of the transmission stage 121. Furthermore, the replica 152 should match the output stage of the transmission stage 121 in terms of thermal properties and alignment. The term "alignment", which can also be referred to as orientation, is understood here to mean spatial alignment in the layout on the chip in which or with which the transmission stage 121 is constructed. Factors such as temperature or piezoelectric effects that cause elastic deformations may require that the control circuit 15 should be in the same alignment as the output stage of the transmission stage 121. In particular, the replica 152 and the output stage of the transmission stage 121 have the same temperature and the same alignment or orientation. Control transistor MN CTRL The size and alignment or orientation may be selected to result in an equalization current or bias current I BIAS The transistor MN MIR Same. Transistor MN MIR Also called bias current I BIAS The mother transistor MN MIR .

[0098] exist Figure 9 Therefore, the common mode point or tap point 157 of the replica 152 obtained by the adjustment circuit 15 is located at the common mode voltage at the output of the transmitting stage 121A, 121D, that is, the common mode voltage V CM on, and can be compared with the reference voltage V REF For example, the common mode voltage V CM is the common mode voltage V cm =(VCAN_H+VCAN_L) / 2. Regulation transistor MN CTRL - which can be selected in terms of size and alignment or orientation to be compatible with the bias current I BIAS The mother transistor MN MIR The same gate voltage then results in a regulated bias current I on the CANH side. CTRK =I BIAS +gΔV, where g is the gain of the differential amplifier 151 .

[0099] The bandwidth of the regulation loop of the regulation circuit 15, in particular the bandwidth of the differential amplifier 151, is selected so that Figure 3 During the bit duration t_bt1 or t_bt2 shown in FIG, the common mode voltage V CM Perform balance.

[0100] The (undisturbed) common mode voltage V can be determined using replica 152.CM , which together reflects the process and temperature dependencies of the output of the transmitting stage 121 .

[0101] use Figure 9 The common mode voltage V CM By balancing the current I on the CANH side (also called the high side) CTRL and the current I on the CANL side (also called the low side) BIAS Especially in the low impedance recessive state (SIC state), the current I CTRL , I BIAS The precise balance (matching) of the current I is required to take into account the leakage current with respect to temperature and process fluctuations. CTRL and I BIAS Very fine and possibly even temperature-dependent adjustments are made. These adjustments can be derived from temperature sensors and stored adjustment data.

[0102] This eliminates the need to determine the common-mode voltage V by tapping the bus 40 . CM However, this interception has the disadvantage that the interception must again meet the requirements for overvoltage and current at the interception point. However, meeting these requirements is very difficult because the actual common mode (V_CANH+V_CANL) / 2 can have a considerable amplitude (up to + / - 60V) in the presence of irradiation (DPI) on the bus 40.

[0103] To send according to Figure 3 The signals CAN_H, CAN_L or according to Figure 6 or according to Figure 8 According to the signals CAN_H and CAN_L, the transmitting stages 121A, 121B, 121C, and 121D are constructed as follows.

[0104] Figure 9 The first transmitting stage 121A has n current level switches, which can be switched between a first position 0 and a second position 1 and are connected to the transistor MP MIR 、MP R , MP0, MP1, MP2 to MP n The drain terminal of n is a natural number greater than 1. These n current level switches can be switched at a frequency f MAIN Switching. These n current level switches can be connected to the polarity reversing diode MN in its position 1. DIOPH The anode of transistor MP is connected. CASPH The source terminal is connected to the polarity reversal diode MN DIOPH The cathode of transistor MP CASPHThe drain terminal of transistor MP is connected to terminal CANH of bus core line 41. CASPH The gate terminal is connected to the control terminal 125, to which the control device 124 can apply a control voltage V PCAS . Transistor MP MIR 、MP R The current mirrors of the first to nth current stages S1 to Sn are formed, and these current stages provide currents I1 to In through the n current stage switches of the first transmitting stage 121A, as shown in FIG. Figure 10 In addition, there is a control circuit T_A, which controls the transmission signal TxD ( Figure 1 The control circuit T_A controls the n current level switches according to the transmission signal TxD and the set operating modes SIC and FAST_TX of the transmission module 121.

[0105] Transistor MP MIR 、MP R , MP0, MP1, MP2 to MP n It can be a CMOS transistor, especially a PMOS transistor. Figure 1 In the example, transistor MP MIR 、MP R , MP0, MP1, MP2 to MP n It is a normally off P-channel transistor. Transistor MP CASPH It can be a CMOS transistor, especially a PMOS transistor. CASPH In particular, a common-source and common-gate structure is used to meet feedback strength requirements in the event of overvoltage or undervoltage at the CANH terminal. The abbreviation "CMOS" refers to a semiconductor device that uses P-channel and N-channel MOSFETs on a common substrate. The abbreviation CMOS stands for "Complementary Metal-Oxide-Semiconductor." The abbreviation "MOSFET" stands for Metal Oxide Field-Effect Transistor.

[0106] Figure 9 The second transmitting stage 121B has n current level switches, which can be switched between a first position 0 and a second position 1 and are connected to the transistor MP MIR 、MP R , MP0, MP1, MP2 to MP n The drain terminal of n is a natural number greater than 1. n current level switches can be switched at a frequency f COMPL Switching. n current level switches can be in their position 1 with transistor MN CASNH The source terminal of transistor MN is connected.CASNH The drain terminal is connected to the polarity reversal diode MN DIONH The terminal CANH of the bus core line 41 is connected to the polarity reversal diode MN DIONH Anode of transistor MN CASNH The gate terminal is connected to the control terminal 125, to which the control device 124 can apply a control voltage V NCAS . Transistor MN MIR and MN R The first to nth current stages S1 to Sn are formed into current mirrors, which provide currents I1 to In via the n current stage switches of the second sending stage 121B, as described in more detail according to Figure 10 Furthermore, there is a control circuit T_B which controls the output of the transmission signal TxD ( Figure 1 ) controls n current level switches. The control circuit T_B controls the n current level switches according to the transmission signal TxD and the set working modes SIC and FAST_TX of the transmission module 121.

[0107] Transistor MP MIR 、MP R , MP0, MP1, MP2 to MP n It can be a CMOS transistor, especially an NMOS transistor. Figure 1 In the example, transistor MP MIR 、MP R , MP0, MP1, MP2 to MP n It is a normally off N-channel transistor. Transistor MN CASNH It can be a CMOS transistor, especially an NMOS transistor. Transistor MN CASNH In particular, a common-source common-gate structure is provided to meet the feedback strength requirement when the terminal CANH is overvoltage or undervoltage.

[0108] Figure 9 The third transmitting stage 121C has n current level switches which can be switched between a first position 0 and a second position 1 and are connected to the transistor MP MIR 、MP R , MP0, MP1, MP2 to MP n The drain terminal of the n current level switches can be switched at a frequency f COMPL Switching. These n current level switches can be connected to the polarity reversing diode MN in its position 1. DIOPH The anode of transistor MP is connected. CASPH The source terminal is connected to the polarity reversal diode MN DIOPH The cathode of transistor MP CASPLThe drain terminal of transistor MP is connected to terminal CANL of bus core line 42. CASPL The gate terminal is connected to the control terminal 125, to which the control device 124 can apply a control voltage V PCAS . Transistor MP MIR 、MP R The current mirrors of the first to nth current stages S1 to Sn are formed, and these current stages provide currents I1 to In through the n current stage switches of the third sending stage 121C, as shown in FIG. Figure 10 Furthermore, there is a control circuit T_C which controls the output of the transmission signal TxD ( Figure 1 The control circuit T_C controls the n current level switches according to the transmission signal TxD and the set operating modes SIC and FAST_TX of the transmission module 121.

[0109] Transistor MP CASPL It can be a CMOS transistor, especially a PMOS transistor. Transistor MN CASNL In particular, a common-source common-gate structure is provided to meet the feedback strength requirement when the terminal CANL is overvoltage or undervoltage.

[0110] Figure 9 The fourth transmitting stage 121D has n current level switches, which can be switched between a first position 0 and a second position 1 and are connected to the transistor MP MIR 、MP R , MP0, MP1, MP2 to MP n The drain terminal of n is a natural number greater than 1. These n current level switches can be switched at a frequency f MAIN Switching. These n current level switches can be connected to transistor MN in their position 1. CASNL The source terminal of transistor MP is connected. CASPL The drain terminal is connected to the polarity reversal diode MN DIOPL The terminal CANL of the bus core line 42 is connected to the polarity reversal diode MN DIOPL Anode of transistor MP CASNL The gate terminal is connected to the control terminal 125, to which the control device 124 can apply a control voltage V NCAS . Transistor MP MIR 、MP R The current mirrors of the first to nth current stages S1 to Sn are formed, and these current stages provide currents I1 to In through the n current stage switches of the fourth transmitting stage 121D, as shown in FIG. Figure 10 In addition, there is a control circuit T_D, which controls the transmission signal TxD ( Figure 1 The control circuit T_B controls the n current level switches according to the transmission signal TxD and the set operating modes SIC and FAST_TX of the transmission module 121.

[0111] Transistor MP CASNL It can be a CMOS transistor, especially an NMOS transistor. Transistor MN CASNL In particular, a common-source common-gate structure is provided to meet the feedback strength requirement when the terminal CANL is overvoltage or undervoltage.

[0112] The number n can be selected arbitrarily. In particular, the number n and therefore the number of stages or current stage switches can be selected between 1 and 60. Alternatively, however, a number greater than 60 or less than 60, in particular 30, can be selected for n.

[0113] The resistor R_H is connected between the transmitting stages 121A and 121C. One end of the resistor R_H is connected to the polarity reversing diode MN. DIOPH The anode of the transistor MP can be connected through the current level switch of the sending stage 121A. MIR 、MP R , MP0, MP1, MP2 to MP n The other end of the resistor R_H is connected to the polarity reversal diode MN DIOPL The anode of the transistors MP0, MP1, MP2 to MP1 can be connected through the current level switch of the sending stage 121C. n Drain terminal connection.

[0114] The resistor R_L is connected between the transmitting stages 121D and 121B. One end of the resistor R_L is connected to the transistor MN. CASNH The source terminal of the transistor MP can be connected to the switch of the fourth transmission stage 121D. R , MP0, MP1, MP2 to MP n The other end of the resistor R_L is connected to the drain terminal of the transistor MN. CASNL The source terminal of the transistor MN can be connected to the current level switch of the second sending stage 121B. R MP0, MP1, MP2 to MP n Drain terminal connection.

[0115] Polarity reversal diode MN DIOPH MN DIONL MN DIOPK and MN DIONHEach of the polarity reversing diodes MN protects the associated transmitting stage 121A, 121B, 121C, 121D from positive feedback to terminal 43 (CAN power) and negative feedback to terminal 44 (CAN_GND). DIOPH MN DIONL MN DIOPL and MN DIONH Each of them can also be called a blocking diode.

[0116] Each of the transmit stages 121A, 121B, 121C, and 121D, more specifically its current level switches and associated control circuits T_A, T_B, T_C, and T_D, sets a transmit current value for the associated transmit stage 121A, 121B, 121C, and 121D based on the transmit signal TxD and the operating mode of the arbitration phase 451 or the data phase 452 of the transmit module 121. This is also described in Table 1 above. Thus, the transmit current value of each transmit stage 121A, 121B, 121C, and 121D can be set based on the transmit signal TxD and the operating mode of the transmit module 121, such as the arbitration phase (SLOW or SIC) or the data phase (FAST_TX or FAST_RX). Therefore, each of the transmission stages 121A to 121D is configured to set the value of the current IA1 to Ian, etc. output from the transmission stage 121A to 121D when the transmission module 121 is in operation at the output end of the current mirror, which is present in the corresponding transmission stage 121A to 121D. The currents IA1 to IAn, etc. may also be referred to as I1 to In for short. The setting of the transmission current value is still described below according to Figure 10 and Figure 11 The currents I1 to In of each stage of the circuits 121A1 , 121B1 , 121C1 , and 121D1 and Table 2 are described in more detail.

[0117] Transistor MN CASPH MN CASNL MN CASPL and MN CASNH Each of them can also be called a high voltage isolation (HV-Standoff) device. Transistor MN CASPH MN CASPL Each of the CMOS transistors MP in the current mirror of the protection transmission stage 121A, 121C MIR 、MP R , MP0, MP1, MP2 and MP n , in such a way that transistor MN CASPH MN CASPL Absorbs high voltage drops. Transistor MN CASNH and MN CASNLEach of the CMOS transistors MP in the current mirror of the protection transmission stage 121D, 121B MIR 、MP R , MP0, MP1, MP2 and MP n , in such a way that transistor MN CASPH and MN CASPL Absorbs high voltage drop. HV cascode structure or transistor MN CASPH MN CASNL MN CASPL MN CASNH This enables adherence to limit values ​​(maximum rated parameters), such as the voltages -27 V to +40 V at CANH and CANL.

[0118] In transmit module 121, transmit stage 121A is connected between terminal 43 for power supply and terminal 41 (CANH) for signal CAN_H. Transmit stage 121C is connected between terminal 43 for power supply and terminal 42 (CANL). Transmit stage 121D is connected between terminal 41 (CANH) for signal CAN_H and terminal 44 (CAN_GND) for ground. Transmit stage 121B is connected between terminal 42 (CANL) for signal CAN_L and terminal 44 (CAN_GND) for ground. Thus, in transmit module 121, transmit stage 121A is connected to the CANH path. Transmit stage 121D is connected to the CANH path. Transmit stage 121C is connected to the CANL path. Transmit stage 121B is connected to the CANL path.

[0119] Therefore, the transmission module 121 connects a specific number of switchable currents of the transmission stages 121A, 121B, 121C, and 121D in parallel in the CANH path and in the CANL path, respectively. The current values ​​of the transmission stages 121A, 121B, 121C, and 121D are determined by the number of current stage switches of the transmission stages 121A, 121B, 121C, and 121D that are switched to position 1.

[0120] Figure 10 As an example, the configuration of the first to nth current level switches S1 to Sn of the transmission stage 121D is shown. Thus, the first current level switch S1 includes a current source IrefD1. The second current level switch S2 includes a current source IrefD2. The nth current level switch Sn includes a current source IrefDn. Optionally, at least one of the current sources IrefD1 to IrefDn is a current sink.

[0121] The current level switches of the transmission stages 121A, 121B, and 121C are constructed in the same manner.

[0122] Figure 9 The circuit (which has Figure 10 The functional mode of the circuit (of the embodiment shown in FIG. 1 ) is described in Table 2 below, depending on the operating mode of transmit module 121 and bus states 401 (dom), 403 (sic), 402 (rec) in SIC operating mode (arbitration phase 451), as well as bus states L0 and L1 in data phase 452. Table 2 shows the required impedances and the impedances of transmit stages 121A / 121B and 121C / 121D, depending on the state of transmit module 121 and the operating mode of transmit module 121 in phases 451 and 452. Furthermore, the drive currents of transmit stages 121A / 121B and 121C / 121D are shown, depending on the state of transmit module 121 and the operating mode of transmit module 121 in phases 451 and 452. The drive currents of transmit stages 121A / 121B and 121C / 121D are provided by the associated current stage switches S1 to Sn.

[0123]

[0124]

[0125] Table 2: Required impedance and drive current according to transmit state

[0126] If the impedance is “infinite”, the transmission module 121 or the corresponding transmission stages 121A, 121B, 121C, 121D are switched off or non-conductive.

[0127] In the transmission stage 121, resistors R_H and R_L are used to adjust the differential resistance between terminals CANH and CANL during the transmission module state (SIC state). For example, resistors R_H and R_L each have a value of 240 ohms. The goal is to set the impedance to 120 ohms based on the wave resistance Zw of the bus cores 41 and 42. In contrast, the impedance of the current mirrors of all four transmission stages 121A, 121B, 121C, and 121D can be selected to be much higher than 240 ohms. This results in two 240 ohm resistors being connected in parallel and thus resulting in a matched impedance of 120 ohms.

[0128] Furthermore, even in state 401 (dom), a differential resistance can be set between terminals CANH, CANL using transmitter stage 121, which is matched to the wave resistance of bus conductors 41, 42, typically 120 ohms each. This prevents reflections in state 401 (dom).

[0129] This configuration of transmission stage 121 prevents the possibility of requiring a supply voltage greater than 5 V at terminal 43, which is not possible due to system requirements or the specifications of the CAN specification. However, this would be necessary if the previously described advantageous behavior were to be achieved using the resistor concept solution in transmission stages 121A, 121B, 121C, 121D.

[0130] An additional advantage of the configuration of the transmitting stage 121 is that the currents flowing in the two paths of the transmitting stages 121A / D and 121B / C during state 403 (sic) can be adjusted arbitrarily or “freely” as shown in Table 1.

[0131] Will Figure 9 The division of each transmitting stage 121A, 121B, 121C, 121D into n parts or n current stages of the current stage switch allows for a time-staggered and controlled switching process between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 in the data phase 452. In particular, as with Figure 11 In the specific example shown, the current values ​​of n current levels of the current level switch can be set.

[0132] Figure 11 An example of the current level of each switching stage or current level switch S1 to S12 is shown. Thus, in the example shown, twelve of the current level or current level switches S1, S2 to S6 to S12 are used for each of the transmitting stages 121A, 121B, 121C, 121D. Figure 9 The associated transistor MP of the current mirror of the transmission stage 121A, 121C MIR 、MP R , MP0, MP1, MP2 to MP n or Figure 9 The associated transistor MN of the current mirror of the transmitting stage 121D, 121B MIR MN R , MN0, MN1, MN2 to MN n To turn on or off the current stage or current stage switches S1, S2 to S6 to S12. Figure 11 In the example, n=12.

[0133] Current I( Figure 11 The values ​​of I1, I2, I6, I12, etc. are set by selecting the values ​​of the currents of the corresponding current levels or current level switches S1 to S12. Therefore, the current levels or current level switches S1 to S12 ( Figure 12 ) has current sources IrefD1, IrefD2 to IrefDn, which provide currents with different current values.

[0134] To generate bus states 401, 402, 403 in arbitration phase 451 or bus states L0, L1 in data phase 452 according to Table 2, the individual current stages S1 to S12 are switched on or off in a time-shifted manner using control circuits T_A, T_B, T_C, T_D of transmit stages 121A, 121B, 121C, 121D. As a result, the corresponding current I flows in the CANH path or CANL path to which transmit stages 121A, 121B, 121C, 121D are connected.

[0135] Generally speaking, it is advantageous to design the staggering (interleaving) of each switching stage or current stage S1 to S12 such that the shape of the difference signal VDIFF follows a Gaussian error function, thereby resulting in the lowest possible emissions in terms of analysis.

[0136] For example, for the transition from state 402 (implicit) to state 401 (explicit) (which corresponds to Figure 4 The rising edge of the differential voltage VDIFF) is used to gradually increase the current in the CANH path and the CANL path by staggering the current levels of the transmitting stages 121A, 121B, 121C, and 121D in time to generate a dominant level at the bus 40. The transition from state 401 (dominant) to state 402 (recessive) (which corresponds to Figure 4 The falling edge of the differential voltage VDIFF is correspondingly achieved by switching off the current stages of transmission stages 121A, 121B, 121C, and 121D in a staggered manner, thereby gradually reducing the current in the CANH and CANL paths. During state 401 (dominant), the total current resulting from the currents I1 to I12 or I1 to In of all current stages S1 to Sn flows. In this case, all current stages S1 to Sn of transmission stages 121A, 121B, 121C, and 121D are turned on, and the total current used to generate the dominant level of nominal VDIFF = 2 V flows through the bus resistor or termination resistor 49.

[0137] By time control, you can Figure 6 The signal shapes of CAN_H and CAN_L are equalized as required. The signal changes of CAN_H and CAN_L can be shaped in a targeted manner. In general, the bus states 401, 402 and 403 in the arbitration phase 451 or the bus states L0 and L1 in the data phase 452 can be shaped according to the preset.

[0138] The currents of the individual current stages S1 to Sn of the transmission stages 121A, 121B, 121C and therefore their respective shares in the total current can be selected in various ways to achieve the lowest possible emissions, in particular low emissions of the transmission module 121. For low emissions, it is advantageous to switch on or off a small amount of current at the beginning and end of a switching process between bus states 401, 402 and to switch on or off a large amount of current in the middle of the switching process. Figure 11 The setting of the currents I1 , I2 to I1 of the current stages S1 to S12 shown in FIG. 1 is very advantageous.

[0139] Compared with the implementation of the current stages S1 to Sn of the transmitting stages 121A, 121B, and 121C having the same current source, Figures 9 to 11 The configuration avoids a current increase during the switch-off period, during the transition from state 401 (dominant) to state 402 (recessive).

[0140] The granularity of the temporal staggering (interleaving) for switching on or off the individual current stages S1 to S12 lies in the range of approximately 2 nanoseconds. Such small steps or steps of temporal staggering cause little common-mode interference and have a minimal negative impact on emissions. The current steps set by the current stages S1, S2 to S6 to S12 remain constant, while the temporal staggering is varied to achieve the smoothest possible behavior during the switching process (according to the Gaussian error function). Varying the temporal steps or temporal steps also prevents the appearance of narrowband frequency lines in the emission spectrum.

[0141] Alternatively, the staggered steps (interleaved steps) can be implemented with a fixed time step and a varying current step.

[0142] The illustrated structure of the transmit module 121 enables the bus signals CAN_H and CAN_L (CAN_L) to be implemented with sharp switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 in the data phase 452. Figure 6 ) symmetric switching.

[0143] On the one hand, due to the use of fast CMOS switches or CMOS transistors, the illustrated structure of transmit module 121 enables steeper switching edges between bus states 401, 402, 403 in arbitration phase (SIC operating mode) 451 or bus states L0, L1 in data phase 452. On the other hand, during the switching process, the symmetry of the temporal profiles of bus signals CAN_H and CAN_L is achieved, which is required to comply with transmission limits. The characteristic curves are equalized (matched) by the selection or use of current sources in stage circuits 121A1, 121B1, 121C1, and 121D1. Consequently, the characteristic curves are less dependent on the parameters of the transistors used in stage circuits 121A1, 121B1, 121C1, and 121D1.

[0144] The linearity state 401 (dom) is determined by equalizing (matching) stage circuit 121A1 with stage circuit 121B1. Here and below, the term "equalization" may refer to an active fine-tuning step. According to another possibility, "equalization" means that the values ​​of the current sources of stage circuits 121A1 and 121B1 match as closely as possible, which is done as standard without an equalization step or a fine-tuning step.

[0145] The Sic state (sic) is determined by equalizing (matching) the stage circuit 121A1 with the stage circuit 121C1 and equalizing (matching) the stage circuit 121D1 with the stage circuit 121B1.

[0146] In the operating mode XL-Fast, state L0 is determined by balancing (matching) stage circuit 121A1 with stage circuit 121B1. State L1 is determined by balancing (matching) stage circuit (121C1) with stage circuit (121D1).

[0147] Table 3 below shows examples of values ​​a, b, c, d, z that can be used for Figure 9 The transmission module 121 of the first transmission stage 121B is selected to generate the corresponding transmission module state. The value a indicates how many current level switches in the first transmission stage 121B are switched on. The value b indicates how many current level switches in the second transmission stage 121B are switched on. The value c indicates how many current level switches in the third transmission stage 121C are switched on. The value d indicates how many current level switches in the fourth transmission stage 121D are switched on. The value z indicates how many current level switches in the transistors MP1 to MP2 are switched on. n How many transistors are there and how many transistors are there in total? nTherefore, Table 3 shows an example of how many parallel current level switches in each transmission stage 121A, 121B, 121C, and 121D are turned on to set the corresponding state (transmitter state) of the transmission module 121. For example, it can be seen from Table 3 that in the arbitration phase, to drive state 401 (dom), 60 transistors MP and 60 transistors MN, as well as 60 current level switches of the first transmission stage 121A and 60 current level switches of the second transmission stage 121B, are turned on.

[0148]

[0149] Table 3: Required number of parallel switching transistors of the transmitting stages 121A, 121B, 121C, 121D depending on the state of the transmitting module 121 (transmitter state).

[0150] Transmitter module 121 implements a time-staggered and controlled switching process by dividing its four transmit stages 121A, 121B, 121C, and 121D into n parts. Switching can be performed according to a Gaussian error function. This allows for a smooth behavior during the switching process. Furthermore, the possible variation of the time stages during switching prevents the appearance of narrowband frequency lines in the transmit spectrum.

[0151] Alternatively, staggered and controlled switching processes can be implemented with fixed time steps and variable voltage steps using the transmission module 121. This also allows the transmission behavior of the transmission module 121 to be influenced so that predefined limit values ​​are adhered to.

[0152] Furthermore, the transmit module 121 can reduce effects caused by asymmetric behavior of transmit stages 121A, 121B, 121C, and 121D, which can occur in the transmit states dom, sic, and rec and degrade transmission performance. Transmit module 121 prevents uneven behavior of components in transmit stages 121A and 121B of the full bridge (Effect 1), thereby minimizing or preventing variations in the common-mode voltage in the dom state compared to the rec state. Furthermore, transmit module 121 prevents uneven behavior of components in transmit stages 121A / 121D and 121C / 121B of the full bridge (Effect 2), thereby minimizing or preventing variations in the common-mode voltage in the sic state compared to the rec state. This is particularly advantageous because adequate transmission results can only be achieved if the common-mode levels in the dom and sic states match the common-mode level in the rec state, starting from the common-mode level in the rec state. However, the causes of the behavior leading to Effect 1 may differ from those leading to Effect 2.

[0153] All previously described implementation variants of the transmission module 121 can also be used with a modified circuit topology of the full bridge. For example, the diode can be arranged at another location in the path to terminal 43. This allows the cascode structure to be omitted, and more voltage-resistant current-level switches can be used in the transmission stages 121A, 121B, 121C, and 121D.

[0154] Figure 12 The basic configuration of a transmission module 1210 according to a second embodiment is shown, which can be used in one of the user stations 10, 30 to replace the transmission module 121 in the previous embodiment. The transmission module 1210 according to this embodiment is configured similarly to the transmission module 121 in the previous embodiment except for the following differences.

[0155] The transmitting module 1210 has a regulating circuit 15A for balancing the common mode voltage V in the bus state where VDIFF is not equal to 0V. CM Such bus states are, for example, the state VDIFF=2V (which corresponds to the state 401(dom)) or the state VDIFF=1V (which corresponds to the state level 0 or L0) or the state VDIFF=-1V (which corresponds to the state level 1 or L1), as previously described with reference to Figure 3 and Figure 4 as well as Figure 6 and Figure 8 described.

[0156] The regulating circuit 15A has a replica 153 in which a circuit having two resistors R DL1 and R DL2 Scaled bus load 1531 is provided. Scaled bus load 1531 has a scaled size of the terminating resistor 49 of bus 40. The size of scaled bus load 1531 is, in particular, one hundredth the size of terminating resistor 49 or another multiple smaller than the size of terminating resistor 49. In particular, scaled bus load 1531 is an adjustable resistor.

[0157] The resistor R DL1 、R DL2 Between, replica 153 has a center tap point that is equal to the common mode point or tap point 157. Resistor R DL1 、R DL2 have the same dimensions, or more precisely, the same resistance value.

[0158] Otherwise, the copy 153 is designed as described above for the copy 152 of the sending module 121 of the previous exemplary embodiment.

[0159] The bandwidth of the regulation loop of the regulation circuit 15A, in particular the bandwidth of the differential amplifier 151, is selected so that Figure 3The common mode voltage V is applied to the bus state where VDIFF is not equal to 0 V during the bit duration t_bt1 or t_bt2 shown in FIG. CM balance.

[0160] The (undisturbed) common mode voltage V can be determined using replica 153. CM , which reflects the process and temperature dependence of the output of the transmitting stage 1210 .

[0161] according to Figure 12 In a first modification of the transmitting module 1210, at least two copies 153 or at least two copies 152, 153 are connected in parallel in the regulating circuit 15. In this way, for at least two of the possible bus states, in particular Figures 3 and 4 or Figure 6 and Figure 8 In order to balance all possible bus states 401 (dom), 402 (rec), 403 (sic), L0, L1, multiple copies can be used. In particular, another copy 152 can be used for each bus state to be balanced.

[0162] according to Figure 12 In a second modification of the transmission module, at least two copies are connected in parallel in the control circuit 15, wherein the copies are not only the output stages of the transmission stages 121A, 121D, but also copies of the entire full bridge. Such copies are the output stages of the transmission stages 121A, 121B, 121C, 121D connected in an H-bridge (full bridge). In this way, for at least two of the possible bus states, in particular Figures 3 and 4 or Figure 6 and Figure 8 Multiple copies may be used for all possible bus states 401 (dom), 402 (rec), 403 (sic), L0, L1.

[0163] Figure 13 The basic structure of a transmission module 1211 according to a third embodiment is shown, which can be used in one of the user stations 10 and 30 to replace the transmission modules 121 and 1210 of the previous embodiments. The transmission module 1211 according to this embodiment is constructed similarly to the transmission module 1210 of the previous embodiment except for the following differences.

[0164] Transmitting module 1211 includes a control circuit 15B, which includes a switchable bus load 1531 in a replica 153A. For this purpose, replica 153A includes a switching unit 1532 and a terminal 1533, to which a control signal sic can be input for actuating switching unit 1532. The control signal sic can be output, for example, by control device 124.

[0165] In the state of bus voltage VDIFF = 0V, this corresponds to Figure 6 In the SIC state 403, the logic signal sic=1 is switched to the terminal 1534. This short-circuits the scaling bus load 1531.

[0166] In this implementation, it is important to have a smooth switch between the regulation states, in particular at the signal sic at the terminal 1534. This smooth switch can be achieved, for example, by having less steep edges in the sic signal. Additionally or alternatively, the smooth switch can be caused by a corresponding bandwidth of the differential amplifier 151.

[0167] Otherwise, copy 153A is constructed like copy 153 of send module 121 described above for the previous exemplary embodiment.

[0168] Therefore, the regulating circuit 15B can be used to equalize the common mode voltage V of the bus state where VDIFF is equal to 0V or not equal to 0V. CM Such bus states are, for example, the sic state (VDIFF=0 V) or the state VDIFF=2 V (which corresponds to the state 401 (dom)) or the state VDIFF=1 V (which corresponds to the state level 0 or L0) or the state VDIFF=-1 V (which corresponds to the state level 1 or L1), as previously described with reference to Figure 3 and Figure 4 as well as Figure 6 and Figure 8 described.

[0169] The (undisturbed) common-mode voltage V can be determined using replica 153A. CM , which together reflects the process and temperature dependencies of the output of the transmitting stage 1211. This applies to all previously mentioned bus states where VDIFF is equal to or not equal to 0V.

[0170] There may also be multiple copies 152 , 153 , 153A in the sending stage 1211 , as described above with respect to the sending stage 1210 .

[0171] Figure 14 The basic configuration of a transmission module 1212 according to a fourth embodiment is shown, which can be used in one of the user stations 10, 30 to replace the transmission modules 121, 1210, 1211 of the aforementioned embodiments. The transmission module 1212 according to this embodiment is configured similarly to the transmission module 121 of the first embodiment except for the following differences.

[0172] The transmission module 1212 has transmission stages 121A1, 121B1, 121C1, 121D1, which are each designed as a resistive transmission stage. CURR and MN CURRHowever, the control circuit 15 is designed as described above with respect to the transmission module 121 .

[0173] Transistor MP CURR Caused by, from transistor MP CURR The current I flowing into the full bridge to the sending stage 121A, 121C HS Less than a predetermined value. In particular, I HS <115mA. Transistor MN CURR Caused by, from the full bridge from the sending stage 121D, 121B into the transistor MN CURR The current I LS Less than a predetermined value. In particular, I HS <115mA.

[0174] like Figure 14 As shown in FIG, the first transmission stage 121A1 includes resistors R_M_HS, each of which is connected to a current level switch of the transmission stage 121A1. The second transmission stage 121B1 includes resistors R_M_LS, each of which is connected to a current level switch of the transmission stage 121B1. The third transmission stage 121C1 includes resistors R_C_LS, each of which is connected to a current level switch of the transmission stage 121C1. The fourth transmission stage 121D1 includes resistors R_C_HS, each of which is connected to a current level switch of the transmission stage 121D1.

[0175] Otherwise, the structure and function of the sending module 1212 for generating the bus status are the same as those of the reference Figures 3 to 8 Same as described.

[0176] In the transmitting module 1212 using a resistive H-bridge (full bridge) structure, the common mode voltage V CM It is mainly determined by adjusting (matching) the resistance of the transmission stages 121A1, 121B1, 121C1, and 121D1. Therefore, in the transmission module 1212, the common mode voltage V CM According to the configuration of the transmission stages 121A1, 121B1, 121C1, 121D1, it can be concluded that the current limiter, in particular the transistor M1, can be adjusted to be small. PCURR MN NCURR The channel resistors limit the current (I_CTRL and I_BIAS) to adjust the common-mode voltage V CM .

[0177] There may also be multiple copies 152 , 153 , 153A in the sending stage 1212 , as previously described with respect to the sending stages 1210 , 1211 .

[0178] Therefore, the common mode voltage V can be realized by using the aforementioned sending modules 121, 1210, 1211, 1212 and the regulating circuits 15, 15A, 15B. CM The equilibrium makes it possible even if Figure 3 、 Figure 6 and Figure 8 Emissions can also be minimized during the switching process between the different bus states 401 , 402 , 403 , L1 , L0 .

[0179] All of the aforementioned embodiments of the transmission modules 121, 1210, 1211, 1212, the transmission / reception devices 12, 22, the control circuits 15, 15A, 15B of the subscriber stations 10, 20, 30, the bus system 1, and the methods implemented therein according to the first and second exemplary embodiments and their modifications may be used individually or in all possible combinations. In addition, the following modifications are particularly conceivable.

[0180] The bus system 1 according to the first and second embodiments has been described above as a bus system based on the CAN protocol. However, the bus system 1 according to the first and / or second embodiments may alternatively be another type of communication network in which signals are transmitted as differential signals. Advantageously, however, it is not mandatory in bus system 1 to ensure exclusive, conflict-free access to bus 40 for user stations 10, 20, 30, at least for a specific period of time.

[0181] The bus system 1 according to the first and / or second embodiment and its modifications is in particular a CAN bus system, a CANHS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system. However, the bus system 1 may be another communication network in which signals are transmitted serially as differential signals via the bus.

[0182] Thus, the functionality of the previously described embodiments can be employed, for example, in a transceiver 12 , 22 which can be operated in a CAN bus system, a CAN-HS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system.

[0183] In the bus system 1 there may be subscriber stations 10, 30, at least one of which uses a Figure 9 The sending module 121, and at least one user station uses Figure 12 The sending module 1210 or according to Figure 13 The sending module 1211 or according to Figure 14 Sending module 1212.

[0184] The number and arrangement of user stations 10, 20, 30 in the bus system 1 according to the first to fourth embodiments and their modifications are arbitrary. In particular, only user station 10 or only user station 30 may exist in the bus system 1 of the first or second embodiment.

Claims

1. A transmitting module (121; 1210; 1211; 1212) for transmitting a differential signal in a serial bus system (1), comprising: a first transmission stage (121A; 121A1) for generating a transmission current (I1 to In) for a first signal (CAN_H) to be transmitted on a bus (40) of a bus system (1); a second transmitting stage (121B; 121B1) for generating a transmitting current (I1 to In) for a second signal (CAN_L) to be transmitted on a bus (40) as a differential signal of the first signal (CAN_H); a third transmitting stage (121C; 121C1) for generating a transmitting current (I1 to In) for a first signal (CAN_H); a fourth transmitting stage (121D; 121D1) for generating a transmitting current (11 to In) for a second signal (CAN_L); and A regulating circuit (15; 15A; 15B) for equalizing the common mode voltage (V CM ), wherein the first to fourth transmission stages (121A to 121D; 121A1 to 121D1) are connected in a full bridge, wherein the first and fourth transmission stages (121A, 121D; 121A1, 121D1) are connected in series, and the third and second transmission stages (121C, 121B; 121C1, 121B1) are connected in series, wherein the regulating circuit (15; 15A; 15B) has a copy (152; 153; 153A) of the output stage of the transmitting module (121; 1210; 1211; 1212), and The replica (152; 153; 153A) is connected to the output stage of the sending module (121; 1210; 1211; 1212).

2. The transmission module (121; 1210; 1211; 1212) according to claim 1, wherein the common mode point (157) of the replica (152; 153; 153A) is located at the common mode voltage (V CM ).

3. The delivery module (121; 1210; 1211; 1212) according to claim 2, wherein the regulating circuit (15; 15A; 15B) further comprises: a differential amplifier (151) having an input connected to a common mode point (157) of the replicas (152; 153; 153A); and Regulation transistor (MN CTRL ), used to convert the common-mode voltage (V CM ) is adjusted to a predetermined value (ΔV), The common mode voltage (V CM ) is applied at the common mode point (157) of the replicas (152; 153; 153A).

4. The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, The replica (152; 153; 153A) has a series circuit comprising transistors (MP R ), diode (MN DIOPR ), transistor (MP CASPR ), diode (MN DIONR ), transistor (MP CASNR ) and transistors (MN R ),and The size of the components of the series circuit is smaller than the size of the components at the output ends of the first and fourth transmission stages (121A, 121D; 121A1, 121D1) by a predetermined number of times.

5. The transmitting module (121; 1210; 1211; 1212) according to claim 4, wherein the transistor (MP CASPR ) and transistors (MP CASNR ) are respectively constructed as a common source and common gate structure.

6. The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, wherein the output terminals (41, 42) of the full bridge are arranged to be connected to a terminal resistor (49) of a bus (40), and The replica (153; 153A) in the series circuit has a bus load (1531) which is a replica of the terminating resistor (49) of the bus (40).

7. The transmitting module (121; 1210; 1211; 1212) according to claim 6, wherein the bus load (1531) has two resistors (R DL1 、R DL2 ), which are all connected to the common mode point (157) of the replica (152; 153; 153A).

8. The sending module (121; 1210; 1211; 1212) according to claim 6 or 7, wherein the replica (153A) has a switching unit (1532) for switching the bus load (1531) on or off.

9. A transmitting module (121; 1210; 1211; 1212) according to any of the preceding claims, wherein each transmitting stage (121A to 121D; 121A1 to 121D1) is designed to set the value of the current (I1 to In) output from the transmitting stage (121A to 121D; 121A1 to 121D1) when the transmitting module (121) is in operation using a current mirror at the input of the transmitting stage (121A to 121D; 121A1 to 121D1).

10. The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, The current mirror at the input of each transmitting stage (121A to 121D; 121A1 to 121D1) has two CMOS transistors. The CMOS transistor of the current mirror at the input end of the first transmitting stage (121A; 121A1) is a PMOS transistor. The CMOS transistor of the current mirror at the input end of the second transmitting stage (121B; 121B1) is an NMOS transistor. The CMOS transistor of the current mirror at the input end of the third transmitting stage (121C; 121C1) is a PMOS transistor. The CMOS transistor of the current mirror at the input end of the fourth transmitting stage (121D; 121D1) is an NMOS transistor.

11. The transmission module (121; 1210; 1211; 1212) as claimed in claim 1, wherein each transmission stage (121A to 121D; 121A1 to 121D1) comprises at least two current stages (S1 to Sn) connected in parallel with one another.

12. The transmission module (121; 1210; 1211; 1212) according to claim 11, wherein the at least two current stages (S1 to Sn) have at least one current sink.

13. The transmitting module (121; 1210; 1211; 1212) according to claim 11 or 12, wherein for each of the first to fourth transmitting stages (121A to 121D; 121A1 to 121D1), the number n of at least two current stages (S1 to Sn) is the same, wherein n is a natural number greater than 1.

14. The transmission module (121; 1210; 1211; 1212) according to any one of the preceding claims, further comprising: a first resistor (R_H) having one end connected to the first transmission stage (121A; 121A1) and the other end connected to the third transmission stage (121C; 121C1); and A second resistor (R_L) has one end connected to the second transmission stage (121B; 121B1) and the other end connected to the fourth transmission stage (121D; 121D1).

15. The transmitting module (121; 1210; 1211; 1212) according to claim 1 further comprises a control circuit (T_A; T_B; T_C; T_D) for controlling the switchable components of the first to fourth transmitting stages (121A to 121D; 121A1 to 121D1) as a function of the digital transmitting signal (TxD) and the operating mode (SIC; FAST_TX) set for the transmitting module (121; 1210; 1211; 1212).

16. A transmitting module (121; 1210) according to claim 15, wherein the control circuit (T_A; T_B; T_C; T_D) is designed to perform time-staggered and controlled switching of the currents of at least two current stage switches (S1 to Sn) of the first to fourth transmitting stages (121A to 121D; 1210A to 1210D).

17. A transmitting / receiving device (12; 22) for a user station (20) of a serial bus system (1), comprising: The sending module (121; 1210; 1211; 1212) according to any one of the preceding claims, and A receiving module (122) is provided for receiving a signal from a bus (40).

18. A user station (10; 20; 30) for a serial bus system (1), comprising: The transmitting / receiving device (12; 22) according to claim 17, and A communication control device (11; 21) is provided for controlling communication in a bus system (1) and generating a digital transmission signal (TxD) for actuating a first to a fourth transmission stage (121A to 121D; 121A1 to 121D1).

19. A user station (10; 20; 30) according to claim 18, wherein the user station (10; 20; 30) is designed to communicate in a bus system (1), wherein the user station (10, 20, 30) is ensured to have at least temporary exclusive, conflict-free access to a bus (40) of the bus system (1).

20. A method for transmitting a differential signal in a serial bus system (1), wherein the method is implemented using a transmission module (121; 1210; 1211; 1212) having first to fourth transmission stages (121A to 121D; 1210A to 1210D) and a regulating circuit (15; 15A; 15B), wherein the method comprises the following steps: generating a transmission current (I1 to In) for a first signal (CAN_H) to be transmitted on a bus (40) of a bus system (1) using a first transmission stage (121A; 121A1), generating a transmission current (I1 to In) for a second signal (CAN_L) to be transmitted as a differential signal of the first signal (CAN_H) onto a bus (40) by means of a second transmission stage (121B; 121B1), generating a transmission current (I1 to In) for a first signal (CAN_H) using a third transmission stage (121C; 121C1), and generating a transmission current (I1 to In) for a second signal (CAN_L) by means of a fourth transmission stage (121D; 121D1), The common mode voltage (V CM ), wherein the first to fourth transmission stages (121A to 121D; 121A1 to 121D1) are connected in a full bridge, wherein the first and fourth transmission stages (121A, 121D; 121A1, 121D1) are connected in series, and the third and second transmission stages (121C, 121B; 121C1, 121B1) are connected in series, wherein the regulating circuit (15; 15A; 15B) has a copy (152; 153; 153A) of the output stage of the transmitting module (121; 1210; 1211; 1212), and The replica (152; 153; 153A) is connected to the output stage of the sending module (121; 1210; 1211; 1212).

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