Semiconductor device

Abstract

A semiconductor device includes: a semiconductor chip having a first main surface and a second main surface on an opposite side to the first main surface; and a trench-type IGBT structure formed on the first main surface of the semiconductor chip, the IGBT structure having: a trench formed on the first main surface of the semiconductor chip and extending in a plurality of directions; an insulating film formed on a side surface of the trench; an embedded conductor embedded inside the trench via the insulating film; and an intersection portion formed by grooves extending in the plurality of directions, the curvature index of the corner portion of the intersection portion being 1.5 [mu] m or more.

Description

Related Application

[0001] This application corresponds to Japanese Patent Application No. 2023-036384 filed with the Japan Patent Office on March 9, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device having a trench-type IGBT structure. Background Art

[0003] Patent Document 1 discloses an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) as an example of a semiconductor device.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2020 / 080476 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] One embodiment of the present disclosure provides a semiconductor device capable of improving dielectric breakdown resistance.

[0009] Solutions to Problems

[0010] One embodiment of the present disclosure provides a semiconductor device, comprising: a semiconductor chip having a first main surface and a second main surface on the opposite side thereof; and a trench-type IGBT structure formed on the first main surface of the semiconductor chip, the IGBT structure having: a groove formed on the first main surface of the semiconductor chip and extending in multiple directions; an insulating film formed on the side of the groove; an embedded conductor embedded in the inner side of the groove through the insulating film; and an intersection portion composed of grooves extending in the multiple directions, the curvature index of the corner of the intersection portion being greater than 1.5 μm.

[0011] Effects of the Invention

[0012] According to one embodiment of the present disclosure, a semiconductor device capable of improving dielectric breakdown resistance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic top view of a semiconductor device according to one embodiment of the present disclosure.

[0014] Figure 2 It is a plan view showing a layout example of a plurality of IGBT regions, boundary regions, gate electrodes, and emitter electrodes.

[0015] Figure 3 It is a plan view showing a layout example of a gate wiring, a boundary well region, and a peripheral well region.

[0016] Figure 4 yes Figure 2 An enlarged view of the portion surrounded by the single-dot chain line IV.

[0017] Figure 5 yes Figure 4 An enlarged view of the portion surrounded by a single-dot chain line V.

[0018] Figure 6 It is along Figure 4 A cross-sectional view taken along line VI-VI is shown.

[0019] Figure 7 It is along Figure 4 A cross-sectional view taken along line VII-VII is shown.

[0020] Figure 8 yes Figure 7 An enlarged view of the portion surrounded by the single-dot chain line VIII.

[0021] Figure 9 It is along Figure 5 A cross-sectional view taken along line IX-IX is shown.

[0022] Figure 10 yes Figure 6 An enlarged view of the portion surrounded by a single-dot chain line X.

[0023] Figure 11 yes Figure 2 An enlarged view of the portion surrounded by the single-dot chain line XI.

[0024] Figure 12A It is along Figure 11 A cross-sectional view taken along line XIIA-XIIA is shown.

[0025] Figure 12B yes Figure 11 An enlarged view of the portion surrounded by the single-dot chain line XIIB.

[0026] Figure 13 It is a schematic cross-sectional view for explaining the curvature index.

[0027] Figure 14A as well as Figure 14B A diagram showing a part of the manufacturing process of a semiconductor device according to one embodiment of the present disclosure.

[0028] Figure 15A as well as Figure 15B They are respectively Figure 14A as well as Figure 14B The diagram of the next process.

[0029] Figure 16A as well as Figure 16B They are respectively Figure 15A as well as Figure 15B The diagram of the next process.

[0030] Figure 17A as well as Figure 17B They are respectively Figure 16A as well as Figure 16B The diagram of the next process.

[0031] Figure 18A as well as Figure 18B They are respectively Figure 17A as well as Figure 17B The diagram of the next process.

[0032] Figure 19A as well as Figure 19B They are respectively Figure 18A as well as Figure 18B The diagram of the next process.

[0033] Figure 20A as well as Figure 20B They are respectively Figure 19A as well as Figure 19B The diagram of the next process.

[0034] Figure 21A as well as Figure 21B They are respectively Figure 20A as well as Figure 20B The diagram of the next process.

[0035] Figure 22A as well as Figure 22B They are respectively Figure 21A as well as Figure 21B The diagram of the next process.

[0036] Figure 23 This is a diagram for explaining a patterning mask.

[0037] Figure 24 This is a graph showing the relationship between the chamfer width and the curvature index of a patterning mask.

[0038] Figure 25 Graphs showing test results of an electrostatic discharge withstand test (ESD withstand test) conducted on Example 1, Example 2, and Reference Examples 1 to 4.

[0039] Figures 26A to 26CEach of the graphs shows the test results of a zero-time dielectric breakdown withstand test (TZBD withstand test) performed on Reference Examples 1 to 3.

[0040] Figures 27A to 27C These are graphs showing the test results of the electrostatic breakdown tolerance test performed on Reference Example 4, Example 1, and Example 2, respectively.

[0041] Figure 28 This is a graph showing the relationship between TCE treatment time and the amount of side etching of the trench.

[0042] Figures 29A to 29C Graphs showing test results of a zero-time dielectric breakdown withstand test (TZBD withstand test, 78 V) conducted on Reference Example 5, Example 3, and Example 4.

[0043] Figure 30A as well as Figure 30B Graphs showing test results of a zero-time dielectric breakdown withstand test (TZBD withstand test, 84 V) conducted on Reference Example 5, Example 3, and Example 4.

[0044] Figure 31A as well as Figure 31B Graphs showing test results of a zero-time dielectric breakdown withstand test (TZBD withstand test, 86 V) conducted on Reference Example 5, Example 3, and Example 4.

[0045] Figure 32 is with Figure 5 The corresponding drawings are cross-sectional views for explaining modified examples of the present disclosure. DETAILED DESCRIPTION

[0046] Figure 1 1 is a plan view showing a semiconductor device 1 according to one embodiment of the present disclosure. Figure 2 It is a plan view showing a layout example of a plurality of IGBT regions 6 , boundary regions 7 , gate electrodes 71 , and emitter electrodes 75 . Figure 3 1 is a plan view showing a layout example of the gate wiring 40 , the boundary well region 50 , and the peripheral well region 56 . Figure 4 yes Figure 2 An enlarged view of the portion surrounded by the single-dot chain line IV. Figure 5 yes Figure 4 An enlarged view of the portion surrounded by a single-dot chain line V. Figure 6 It is along Figure 4 A cross-sectional view taken along line VI-VI is shown. Figure 7 It is along Figure 4 A cross-sectional view taken along line VII-VII is shown. Figure 8 yes Figure 6 An enlarged view of the portion surrounded by the single-dot chain line VIII. Figure 9It is along Figure 5 A cross-sectional view taken along line IX-IX is shown. Figure 10 yes Figure 7 An enlarged view of the portion surrounded by a single-dot chain line X. Figure 11 yes Figure 2 An enlarged view of the portion surrounded by the single-dot chain line XI. Figure 12A It is along Figure 11 A cross-sectional view taken along line XIIA-XIIA is shown. Figure 12B yes Figure 11 An enlarged view of the portion surrounded by the single-dot chain line XIIB. Figure 13 It is a schematic plan view for explaining the curvature index CI.

[0047] The semiconductor device 1 is an IGBT (Insulated Gate Bipolar Transistor) semiconductor device including an IGBT.

[0048] like Figures 1 to 3 As shown, semiconductor device 1 includes a rectangular parallelepiped semiconductor chip 2. Semiconductor chip 2 has a first principal surface 3 on one side, a second principal surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting first principal surface 3 and second principal surface 4. First principal surface 3 and second principal surface 4 are formed into a quadrilateral when viewed from above (hereinafter referred to as "top view") as viewed from a normal direction Z. Normal direction Z also corresponds to the thickness direction of semiconductor chip 2.

[0049] The first side surface 5A and the second side surface 5B extend in a first direction X along the first principal surface 3 and oppose each other in a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and oppose each other in the first direction X. The semiconductor chip 2 has a single-layer structure formed of a single crystal silicon substrate.

[0050] The semiconductor chip 2 is, for example, square in plan view. The size of the semiconductor chip 2 is, for example, not less than 0.5 mm square and not more than 20 mm square. A chip size of "X mm square" may mean that the length of one side of the square semiconductor chip 2 is X mm.

[0051] like Figure 2 as well as Figure 3 As shown, semiconductor device 1 includes a plurality of IGBT regions 6 formed on first main surface 3 at intervals in a second direction Y. Each IGBT region 6 includes a trench-type IGBT structure (transistor structure) Tr. IGBT region 6 may also be referred to as an "active region." The plurality of IGBT regions 6 include a first IGBT region 6A and a second IGBT region 6B.

[0052] like Figure 2 as well as Figure 3 As shown, the first IGBT region 6A is formed in a region on the first side face 5A side relative to a straight line passing through the center of the first main surface 3 in the first direction X. The second IGBT region 6B is formed in a region on the second side face 5B side relative to a straight line passing through the center of the first main surface 3 in the first direction X. In this embodiment, the plurality of IGBT regions 6 are each formed in a quadrilateral annular shape having four sides parallel to the first to fourth side faces 5A to 5D in a plan view.

[0053] like Figure 2 as well as Figure 3 As shown, the semiconductor device 1 further includes a boundary region 7 formed between the plurality of IGBT regions 6. Specifically, the boundary region 7 is provided in a strip shape extending in the first direction X in the region between the first IGBT region 6A and the second IGBT region 6B. Figure 2 as well as Figure 3 In the example shown in FIG. 5 , the boundary region 7 is located on a straight line that passes through the center of the first main surface 3 in the first direction X.

[0054] like Figure 2 as well as Figure 3 As shown, the boundary region 7 includes a first boundary region 8 having a relatively large width in the second direction Y and a second boundary region 9 having a smaller width than the first boundary region 8 in the second direction Y. The first boundary region 8 is provided on one side (on the third side surface 5C side) in the first direction X as a portion supporting the terminal electrode. The first boundary region 8 may also be referred to as a "pad region," a "wide region," or a "terminal support region."

[0055] In this embodiment, the first boundary region 8 is located on a straight line that passes through the center of the first principal surface 3 in the first direction X when viewed from above, and is provided in a quadrilateral shape near the center of the third side surface 5C. The width of the first boundary region 8 can be greater than 100 μm and less than 800 μm. The width of the first boundary region 8 is preferably greater than 200 μm and less than 600 μm. In this embodiment, the width of the first boundary region 8 is set to be within the range of greater than 350 μm and less than 450 μm.

[0056] Second boundary region 9, serving as a portion supporting the wiring, is formed on the other side of first boundary region 8 in the first direction X (on the fourth side surface 5D side). Second boundary region 9 is located on a straight line that passes through the center of first principal surface 3 in the first direction X, extending in a stripe from first boundary region 8 toward the center of fourth side surface 5D. Second boundary region 9 may also be referred to as a "street," "narrow area," or "wiring support area."

[0057] like Figure 2 as well as Figure 3As shown, semiconductor device 1 further includes a peripheral region 10. Peripheral region 10 surrounds multiple IGBT regions 6. Peripheral region 10 is a square ring extending along first to fourth side surfaces 5A to 5D. Peripheral region 10, together with boundary region 7, forms an inactive region. In this embodiment, the IGBT structure Tr, described below, is not formed in boundary region 7 or peripheral region 10.

[0058] like Figure 6 、 Figure 7 as well as Figure 12A As shown, semiconductor device 1 includes an n-type (first conductivity type) drift region 11. Drift region 11 is formed throughout the interior of semiconductor chip 2. In this embodiment, semiconductor chip 2 is formed of an n-type semiconductor substrate, and drift region 11 is formed using this semiconductor substrate.

[0059] like Figure 6 、 Figure 7 as well as Figure 12A As shown, semiconductor device 1 further includes an n-type buffer region 12 formed on the surface portion of second main surface 4. In this embodiment, buffer region 12 is formed as a layer extending along the entire second main surface 4. Buffer region 12 has a higher n-type impurity concentration than drift region 11. The presence or absence of buffer region 12 is optional, and a configuration without buffer region 12 is also possible.

[0060] like Figure 6 、 Figure 7 as well as Figure 12A As shown, semiconductor device 1 includes a p-type (second conductivity type) collector region 13 formed on the surface of second principal surface 4. In this embodiment, collector region 13 is formed on the surface of buffer region 12 on the second principal surface 4 side. In this embodiment, collector region 13 is formed as a layer extending along the entire second principal surface 4. Collector region 13 is exposed from second principal surface 4 and portions of first to fourth side faces 5A to 5D.

[0061] like Figure 2 as well as Figure 4 As shown, the semiconductor device 1 further includes a plurality of trench isolation structures 20 formed on the first main surface 3 to partition the plurality of IGBT regions 6. A gate potential is applied to the plurality of trench isolation structures 20. The trench isolation structures 20 may also be referred to as "trench gate isolation structures," "trench gate connection structures," or the like. The plurality of trench isolation structures 20 include a first trench isolation structure 20A and a second trench isolation structure 20B.

[0062] like Figure 2 as well as Figure 4As shown, the first trench isolation structure 20A surrounds the first IGBT region 6A and demarcates the first IGBT region 6A from the boundary region 7 and the peripheral region 10. In this embodiment, the first trench isolation structure 20A is formed into a polygonal ring shape having four sides parallel to the periphery of the semiconductor chip 2 when viewed from above. The first trench isolation structure 20A has a portion that curves to demarcate the first boundary region 8 and the second boundary region 9 of the boundary region 7 when viewed from above.

[0063] like Figure 2 as well as Figure 4 As shown, the second trench isolation structure 20B surrounds the second IGBT region 6B and demarcates the second IGBT region 6B from the boundary region 7 and the peripheral region 10. In this embodiment, the second trench isolation structure 20B is formed into a polygonal ring shape having four sides parallel to the periphery of the semiconductor chip 2 when viewed from above. The second trench isolation structure 20B has a portion that curves to demarcate the first boundary region 8 and the second boundary region 9 of the boundary region 7 when viewed from above.

[0064] like Figure 2 、 Figure 4 as well as Figure 11 As shown, each trench isolation structure 20A, 20B includes at least two first-directional portions 20X extending along a first direction X and at least two second-directional portions 20Y extending along a second direction Y. The ends of the first-directional portions 20X and the second-directional portions 20Y are mechanically and electrically connected. The ends of the first-directional portions 20X and the second-directional portions 20Y intersect in an L-shape, forming a polygonal corner of the trench isolation structures 20A, 20B.

[0065] Hereinafter, the structure of a trench isolation structure 20 will be described. In the description of the trench isolation structure 20, Figure 8 as well as Figure 9 Both represent cross sections of the trench isolation structure 20 . Figure 8 is a cross section in a direction perpendicular to the length direction of the trench isolation structure 20, Figure 9 This is a cross section taken in a direction crossing a T-shaped intersection 91P (described later) of the trench isolation structure 20 .

[0066] like Figures 7 to 9 As shown, the trench isolation structure 20 includes a separation trench 21 (first trench), a separation insulating film 22, and a separation buried electrode (buried conductor) 23. The separation trench 21 is dug from the first main surface 3 toward the second main surface 4 to define the wall surface of the trench isolation structure 20.

[0067] Separation trench 21 is formed on first main surface 3. Separation trench 21 is formed vertically in cross-section. Separation trench 21 includes a pair of opposing side surfaces 21a and 21b and a bottom surface 21c connecting the pair of side surfaces 21a and 21b. Bottom surface 21c has a circular shape that bulges toward second main surface 4 in cross-section.

[0068] like Figure 8 As shown, the separation trench 21 has a first width W1. The first width W1 is the width (maximum value) in a direction perpendicular to the direction in which the separation trench 21 extends. The first width W1 is preferably smaller than the width of the second boundary region 9. The first width W1 is preferably not less than 0.5 μm and not more than 2.0 μm. More specifically, the first width W1 may be 1.0 μm.

[0069] The separation trench 21 has a first depth D1. The first depth D1 may be greater than or equal to 1 μm and less than or equal to 30 μm. The first depth D1 is preferably greater than or equal to 4 μm and less than or equal to 15 μm. The first depth D1 is particularly preferably greater than or equal to 6 μm and less than or equal to 10 μm. The separation trench 21 may also be formed into a tapered shape whose width decreases toward the second main surface 4 in a cross-sectional view. The bottom surface 21 c may also be a flat surface parallel to the first main surface 3 .

[0070] like Figure 8 as well as Figure 9 As shown, a first recess 96 is formed at the open ends 21d and 21e of the separation trench 21, recessed toward the side surfaces 21a and 21b of the separation trench 21. The cross-sectional shape of the first recess 96 is an arcuate shape recessed toward the side surfaces 21a and 21b of the separation trench 21. The first recess 96 has a third width W3. The third width W3 is the width in the second direction Y between the point where the extension of the side surfaces 21a and 21b intersects the first main surface 3 and the end of the first recess 96. The third width W3 is greater than 1350 Å and less than 2000 Å. The first recess 96 has a third depth D3. The third depth D3 is greater than the third width W3. The third depth D3 is greater than 1850 Å. The ratio of the third width W3 of the separation trench 21 to the first width W1 (W3 / W1) is greater than 0.14 and less than 0.2.

[0071] like Figures 7 to 9 As shown, the isolation insulating film 22 is formed in a film shape along the side surfaces 21a and 21b of the isolation trench 21. The isolation insulating film 22 defines a recessed space within the isolation trench 21. The isolation insulating film 22 may also include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The isolation insulating film 22 preferably has a single-layer structure consisting of a single insulating film. The isolation insulating film 22 particularly preferably includes a silicon oxide film formed from the oxide of the semiconductor chip 2.

[0072] like Figures 7 to 9As shown, the isolation buried electrode 23 is buried in the isolation trench 21 via the isolation insulating film 22. In this embodiment, the isolation buried electrode 23 is made of conductive polysilicon. A gate potential is applied to the isolation buried electrode 23.

[0073] The following describes the structures within the multiple IGBT regions 6. The structure on the second IGBT region 6B side is substantially the same as the structure on the first IGBT region 6A side. Specifically, the structure on the second IGBT region 6B side is line-symmetrical with the structure on the first IGBT region 6A side with respect to the boundary region 7. The following describes the structure on the first IGBT region 6A side. The description of the structure on the second IGBT region 6B side applies to the description of the structure on the first IGBT region 6A side, and will be omitted.

[0074] like Figure 6 as well as Figure 7 As shown, the semiconductor device 1 includes a p-type base region 25 formed in the surface portion of the first main surface 3 within the first IGBT region 6A. The base region 25 may also be referred to as a "body region" or "channel region." The base region 25 is formed at a shallower depth than the trench isolation structure 20 and has a bottom portion located closer to the first main surface 3 than the bottom wall of the trench isolation structure 20. The base region 25 extends in a layered manner along the first main surface 3 and is connected to the inner peripheral wall of the trench isolation structure 20.

[0075] like Figure 2 as well as Figure 4 As shown, the semiconductor device 1 includes a plurality of trench structures 30. A gate potential is applied to the plurality of trench structures 30. The plurality of trench structures 30 penetrate the base region 25 and reach the drift region 11. The plurality of trench structures 30 are arranged at intervals in a first direction X in a plan view and are each formed into a stripe shape extending in a second direction Y. In other words, the plurality of trench structures 30 are arranged in a stripe shape extending in the second direction Y.

[0076] like Figure 4 as well as Figure 11 As shown, the plurality of trench structures 30 each have a first end 30A on the side of the boundary region 7 and a second end 30B on the side of the peripheral region 10 in the longitudinal direction (second direction Y). The first end 30A and the second end 30B are mechanically and electrically connected to the trench isolation structure 20. That is, the plurality of trench structures 30, together with the trench isolation structure 20, form a ladder-shaped trench gate structure. The connection between the trench structures 30 and the trench isolation structure 20 can be considered part of either the trench isolation structure 20 or the trench structure 30.

[0077] Hereinafter, the structure of one trench structure 30 will be described.

[0078] like Figure 6 as well as Figure 10 As shown, the trench structure 30 includes a gate trench 31 (second trench), a gate insulating film 32, and a gate buried electrode (buried conductor) 33. The gate trench 31 is dug from the first main surface 3 toward the second main surface 4, defining the wall surface of the trench structure 30.

[0079] The gate trench 31 is formed on the first main surface 3. The gate trench 31 is formed into a vertical shape when viewed in cross section. The gate trench 31 includes a pair of opposing side surfaces 31a and 31b and a bottom surface 31c connecting the pair of side surfaces 31a and 31b. The bottom surface 31c has a circular shape that bulges toward the second main surface 4 when viewed in cross section. In this embodiment, the gate trench 31 is connected to the separation trench 21 at both ends (the first end 30A and the second end 30B) in the second direction Y. Specifically, the sidewalls of the gate trench 31 are connected to the sidewalls of the separation trench 21, and the bottom wall of the gate trench 31 is connected to the bottom wall of the separation trench 21.

[0080] like Figure 6 As shown, the plurality of gate trenches 31 are arranged at a constant pitch P in the first direction X. The pitch P of the plurality of gate trenches 31 is preferably smaller than the width of the second boundary region 9 of the boundary region 7. The pitch P of the plurality of gate trenches 31 may also be greater than or equal to 5 μm and less than or equal to 30 μm. The pitch P of the plurality of gate trenches 31 is preferably greater than or equal to 10 μm and less than or equal to 20 μm. The pitch P of the plurality of gate trenches 31 is preferably 15 μm.

[0081] like Figure 10 As shown, gate trench 31 has a second width W2. Second width W2 is the width (maximum value) in a direction perpendicular to the direction in which gate trench 31 extends. Second width W2 is preferably greater than or equal to 0.5 μm and less than or equal to 2.0 μm. More specifically, second width W2 may be 1.0 μm. Second width W2 may also be substantially equal to first width W1.

[0082] like Figure 10 As shown, the gate trench 31 has a second depth D2. The second depth D2 can be greater than 1 μm and less than 30 μm. The second depth D2 is preferably greater than 4 μm and less than 15 μm. The second depth D2 is particularly preferably greater than 6 μm and less than 10 μm. The second depth D2 is preferably approximately equal to the first depth D1. The gate trench 31 can also be formed into a tapered shape whose width decreases toward the second main surface 4 when viewed in cross section. The bottom surface 31 c can also be a flat surface parallel to the first main surface 3.

[0083] like Figure 10As shown, a second recess 97 is formed at the open ends 31d and 31e of the gate trench 31, recessed toward the side surfaces 31a and 31b of the gate trench 31. The cross-sectional shape of the second recess 97 is an arcuate shape recessed toward the side surfaces 31a and 31b of the gate trench 31. The second recess 97 has a fourth width W4. The fourth width W4 is the width in the first direction X between the point where the extension of the side surfaces 31a and 31b intersects the first principal surface 3 and the end of the second recess 97. The fourth width W4 is greater than 1350 Å and less than 2000 Å. The second recess 97 has a fourth depth D4. The fourth depth D4 is greater than the fourth width W4. The fourth depth D4 is greater than 1850 Å. The ratio of the fourth width W4 to the second width W2 of the gate trench 31 (W4 / W2) is greater than 0.14 and less than 0.2. The ratio (W4 / P) of the fourth width W4 to the pitch P (described later) of the plurality of gate trenches 31 is 0.009 or more and 0.0133 or less. The ratio (W4 / W5) of the fourth width W4 to the fifth width W5 (described later) of the mesa portion 90 (described later) is 0.011 or more and 0.017 or less.

[0084] like Figure 6 as well as Figure 10 As shown, the gate insulating film 32 is formed in a film shape along the wall surface of the gate trench 31. The gate insulating film 32 defines a recessed space in the gate trench 31. The thickness of the gate insulating film 32 is, for example, not less than 50 nm and not more than 200 nm.

[0085] The gate insulating film 32 may also include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The gate insulating film 32 preferably has a single-layer structure consisting of a single insulating film. The gate insulating film 32 particularly preferably includes a silicon oxide film formed from the oxide of the semiconductor chip 2. In this embodiment, the gate insulating film 32 is formed of the same insulating film as the isolation insulating film 22. The gate insulating film 32 is connected to the isolation insulating film 22 at the connection between the isolation trench 21 and the gate trench 31.

[0086] like Figure 6 as well as Figure 10 As shown, a gate buried electrode 33 is embedded in the gate trench 31 via a gate insulating film 32. In this embodiment, the gate buried electrode 33 is made of conductive polysilicon. A gate potential is applied to the gate buried electrode 33. The gate buried electrode 33 is connected to the isolation buried electrode 23 in the connecting portion between the isolation trench 21 and the gate trench 31.

[0087] like Figure 4 as well as Figure 6As shown, semiconductor device 1 further includes multiple n-type emitter regions 35 formed on the surface portion of base region 25. Each of the multiple emitter regions 35 has a higher n-type impurity concentration than the drift region 11. The multiple emitter regions 35 are formed on both sides of the multiple trench structures 30. When viewed from above, the multiple emitter regions 35 are formed in a strip shape extending along the multiple trench structures 30. Of course, the multiple emitter regions 35 can also be formed at intervals along the multiple trench structures 30 when viewed from above.

[0088] like Figure 6 As shown, semiconductor device 1 further includes multiple n-type carrier storage regions 36 formed in the region directly below base region 25 within semiconductor chip 2. Multiple carrier storage regions 36 suppress the discharge of carriers (holes) into base region 25 and promote the accumulation of carriers (holes) in the region directly below trench structures 30. In other words, multiple carrier storage regions 36 contribute to lower on-resistance and lower on-voltage from within semiconductor chip 2.

[0089] Multiple carrier storage regions 36 are arranged on both sides of the multiple trench structures 30 and are each formed into a strip shape extending along the multiple trench structures 30 when viewed from above. The multiple carrier storage regions 36 are formed in the region between the bottom of the base region 25 and the bottom wall of the trench structure 30 in the thickness direction of the semiconductor chip 2. The multiple carrier storage regions 36 are preferably separated from the bottom wall of the trench structure 30 toward the base region 25. The bottom of the multiple carrier storage regions 36 is preferably located closer to the bottom wall of the trench structure 30 than the middle portion of the trench structure 30. The multiple carrier storage regions 36 have a higher n-type impurity concentration than the drift region 11. The n-type impurity concentration of the multiple carrier storage regions 36 is preferably lower than that of the emitter region 35. The presence or absence of carrier storage regions 36 is optional. Therefore, a configuration without carrier storage regions 36 is also possible.

[0090] like Figure 6 As shown, the semiconductor device 1 includes a plurality of contact holes 37 formed on the first main surface 3 so as to expose the emitter region 35. The plurality of contact holes 37 are formed on both sides of the plurality of trench structures 30 at intervals in the first direction X. Figure 6 As shown, the plurality of contact holes 37 may each be formed in a tapered shape in which the opening width becomes narrower from the opening toward the bottom wall.

[0091] like Figure 6As shown, the plurality of contact holes 37 may be separated from the bottom of the emitter region 35 toward the first main surface 3 so as not to reach the base region 25. Of course, the plurality of contact holes 37 may also penetrate the emitter region 35 so as to reach the base region 25. In a plan view, the plurality of contact holes 37 are formed in a strip shape extending along the plurality of trench structures 30. In the longitudinal direction (second direction Y), the plurality of contact holes 37 are shorter than the plurality of trench structures 30.

[0092] like Figure 6 As shown, semiconductor device 1 includes multiple p-type contact regions 38 formed in a surface portion of base region 25 in a region separate from multiple emitter regions 35. Each of multiple contact regions 38 is formed in a strip shape extending along a corresponding contact hole 37 in a plan view. The bottoms of each of multiple contact regions 38 are formed in a region between the bottom wall of the corresponding contact hole 37 and the bottom of base region 25. Multiple contact regions 38 have a higher p-type impurity concentration than base region 25.

[0093] Thus, the base region 25, the plurality of trench structures 30, the plurality of emitter regions 35, the plurality of carrier storage regions 36, the plurality of contact holes 37, and the plurality of contact regions 38 are included in the IGBT structure Tr (refer to FIG. Figure 2 as well as Figure 4 )middle.

[0094] like Figure 4 As shown, the semiconductor device 1 includes a plurality of mesa portions 90 defined within the first IGBT region 6A. The plurality of mesa portions 90 are defined by gate trenches 31. Each mesa portion 90 is defined within the region between a pair of adjacent gate trenches 31 in the first direction X. The mesa portion 90 comprises a portion of the semiconductor chip 2. The plurality of mesa portions 90 each extend in a stripe shape extending in the second direction Y and are defined at intervals in the first direction X. In other words, the plurality of mesa portions 90 are formed in a stripe shape extending in the second direction Y.

[0095] like Figure 4 As shown, mesa portion 90 has a fifth width W5. Fifth width W5 is the width (maximum value) in a direction perpendicular to the direction in which mesa portion 90 extends. Fifth width W5 is preferably smaller than the width of second boundary region 9. Fifth width W5 may be greater than 11 μm and less than 21 μm. Preferably, it is greater than 11 μm and less than 16 μm. Fifth width W5 is preferably 14 μm.

[0096] like Figure 3 as well as Figure 4As shown, semiconductor device 1 includes a p-type boundary well region 50 formed in the surface portion of first main surface 3 within boundary region 7. In this embodiment, boundary well region 50 has a higher p-type impurity concentration than the plurality of base regions 25. Alternatively, boundary well region 50 may have a lower p-type impurity concentration than the plurality of base regions 25. Boundary well region 50 is formed in a region sandwiched between first trench isolation structure 20A and second trench isolation structure 20B. Boundary well region 50 extends in a first direction X along boundary region 7 when viewed from above.

[0097] like Figure 3 As shown, the boundary well region 50 includes a first boundary well region 51 formed in the first boundary region 8 of the boundary region 7, and a second boundary well region 52 formed in the second boundary region 9 of the boundary region 7. The first boundary well region 51 has a relatively large region width in the second direction Y. The first boundary well region 51 is formed in a quadrilateral shape when viewed from above. The first boundary well region 51 is preferably formed in the entire region of the first boundary region 8.

[0098] like Figure 3 as well as Figure 4 As shown, the second boundary well region 52 has a smaller width in the second direction Y than the first boundary well region 51, and extends in a stripe shape from the first boundary well region 51 toward the second boundary region 9. In this embodiment, the second boundary well region 52 is located on a straight line that passes through the center of the first main surface 3 in the first direction X.

[0099] like Figure 7 As shown, the boundary well region 50 is formed deeper than the base region 25. The boundary well region 50 is preferably formed deeper than the plurality of trench isolation structures 20. Figure 4 As shown, in this embodiment, the boundary well region 50 has a width in the second direction Y greater than that of the boundary region 7 , and is led out from the boundary region 7 into the plurality of IGBT regions 6 .

[0100] like Figure 7 As shown, the boundary well region 50 is connected to a plurality of trench isolation structures 20 adjacent to each other in the second direction Y. The boundary well region 50 has portions covering the bottom walls of the plurality of trench isolation structures 20. The boundary well region 50 has portions crossing the plurality of trench isolation structures 20 and covering the bottom walls of the plurality of trench structures 30.

[0101] like Figure 7 As shown, the boundary well region 50 covers the sidewalls of the trench isolation structure 20 in each IGBT region 6. Although not shown in the figure, the boundary well region 50 covers the sidewalls of the plurality of trench structures 30 in each IGBT region 6. Figure 4 as well as Figure 7As shown, the boundary well region 50 is connected to each base region 25 at the surface portion of the first main surface 3 .

[0102] like Figure 3 as well as Figure 11 As shown, semiconductor device 1 includes a p-type peripheral well region 56 formed in the surface portion of first main surface 3 in peripheral region 10. In this embodiment, peripheral well region 56 has a higher p-type impurity concentration than the plurality of base regions 25. Of course, peripheral well region 56 may also have a lower p-type impurity concentration than the plurality of base regions 25. The p-type impurity concentration of peripheral well region 56 is preferably substantially equal to the p-type impurity concentration of boundary well region 50.

[0103] like Figure 3 as well as Figure 12A As shown, the peripheral well region 56 is formed as a layer extending along the first main surface 3 and exposed from the first main surface 3. The peripheral well region 56 is formed at intervals inward from the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D). The peripheral well region 56 is formed in a band shape extending along the multiple IGBT regions 6 when viewed from above. In this embodiment, the peripheral well region 56 is formed in a ring shape that surrounds the multiple IGBT regions 6 when viewed from above. Specifically, the peripheral well region 56 is formed in a four-sided ring shape with four sides parallel to the periphery of the first main surface 3.

[0104] like Figure 12A As shown, the peripheral well region 56 is formed deeper than the plurality of base regions 25. It is particularly preferred that the peripheral well region 56 be formed deeper than the plurality of trench isolation structures 20 (the plurality of trench structures 30). In this embodiment, the peripheral well region 56 has a depth substantially equal to that of the boundary well region 50.

[0105] like Figure 12A As shown, the peripheral well region 56 is connected to the plurality of trench isolation structures 20. The peripheral well region 56 has a portion covering the bottom wall of the plurality of trench isolation structures 20. The peripheral well region 56 is led out from the peripheral region 10 to each IGBT region 6 (see Figure 3 The peripheral well region 56 has a portion that crosses the plurality of trench isolation structures 20 and covers the bottom walls of the plurality of trench structures 30 .

[0106] like Figure 4 as well as Figure 11 As shown, the IGBT structure Tr includes a plurality of T-shaped intersections 91P formed on the connection portion between the trench separation structure 20 and the trench structure 30. The plurality of T-shaped intersections 91P include: a plurality of first T-shaped intersections 91PA ( Figure 4 ), which is formed at the connection portion between the first end portion 30A of the trench structure 30 and the first direction portion 20X on the side of the boundary region 7 of the trench isolation structure 20; and a plurality of second T-shaped intersection portions 91PB ( Figure 11 ), which is formed at the connection portion between the second end portion 30B of the trench structure 30 and the first direction portion 20X on the outer peripheral region 10 side of the trench isolation structure 20 .

[0107] like Figure 4 As shown, the plurality of first T-shaped intersections 91PA are opposed to the boundary wiring 42 and the boundary well region 50 (second boundary well region 52) in the thickness direction of the semiconductor chip 2. Figure 11 As shown, the plurality of second T-shaped intersections 91PB are opposed to the first peripheral wiring 43 and the peripheral well region 56 in the thickness direction of the semiconductor chip 2 .

[0108] like Figure 5 As shown, the T-shaped intersection 91P has two corners 92P. The curvature index CI of each corner 92P is P 1.5 μm or more and 2.4 μm or less. Curvature index CI P is the curvature index CI of the corner 92P (refer to Figure 13 ).

[0109] like Figure 13 As shown, curvature index CI is an index used to define the curvature of corners (corners 92P and 92Q). Corners (corners 92P and 92Q) are formed by first side 93 and second side 94. Specifically, curvature index CI is the shortest distance between intersection point P1, which is formed by extension line E1 of first side 93 and extends perpendicularly to extension line E1 and extends to second side 94, which also extends to corners (corners 92P and 92Q), and corners (corners 92P and 92Q). In other words, it is the shortest distance between intersection point P1 and a tangent line TL to the corners (corners 92P and 92Q), which intersects extension line E1 and extension line E2 at 45 degrees.

[0110] In the T-shaped intersection 91P, the curvature index CI of the corner 92P is P The ratio of the first width W1 of the separation trench 21 (CI P / W1) is 1.5 or more and 2.4 or less. In the T-shaped intersection 91P, the curvature index CI of the corner 92P is P The ratio of the second width W2 of the plurality of gate trenches 31 (CI P / W2) is 1.5 or more and 2.4 or less. In the T-shaped intersection 91P, the curvature index CI of the corner 92P is P The ratio of the pitch P of the plurality of gate trenches 31 (CI P / P) is 0.1 or more and 0.16 or less. In the T-shaped intersection 91P, the curvature index CI of the corner 92P is PThe ratio of the fifth width W5 of the mesa portion 90 (CI P / W5) is 0.11 or more and 0.17 or less.

[0111] like Figure 11 As shown, the IGBT structure Tr includes a plurality of L-shaped intersections 91Q formed at the connection between the first directional portion 20X and the second directional portion 20Y of the trench isolation structure 20. The plurality of L-shaped intersections 91Q include a plurality of first L-shaped intersections 91 (not shown) formed at the connection between the first directional portion 20X and the second directional portion 20Y on the boundary region 7 side of the trench isolation structure 20; and a plurality of second L-shaped intersections 91QB formed at the connection between the first directional portion 20X and the second directional portion 20Y on the peripheral region 10 side of the trench isolation structure 20.

[0112] A plurality of first L-shaped intersections 91 (not shown) face the boundary wiring 42 and the boundary well region 50 (second boundary well region 52) in the thickness direction of the semiconductor chip 2. A plurality of second L-shaped intersections 91QB face the first peripheral wiring 43 and the peripheral well region 56 in the thickness direction of the semiconductor chip 2.

[0113] like Figure 12B As shown, the L-shaped intersection portion 91Q has a corner portion 92Q. The curvature index of the corner portion 92Q is 1.5 μm or more and 2.4 μm or less. P is the curvature index CI of the corner 92Q (refer to Figure 13 ).

[0114] In the L-shaped intersection 91Q, the curvature index CI of the corner 92Q is Q The ratio of the first width W1 of the separation trench 21 (CI Q / W1) is 1.5 or more and 2.4 or less. In the L-shaped intersection portion 91Q, the curvature index CI of the corner portion 92Q is Q The ratio of the second width W2 of the plurality of gate trenches 31 (CI Q / W2) is 1.5 or more and 2.4 or less. In the L-shaped intersection 91Q, the curvature index CI of the corner 92P is Q The ratio of the pitch P of the plurality of gate trenches 31 (CI Q / P) is 0.1 or more and 0.16 or less. In the L-shaped intersection portion 91Q, the curvature index CI of the corner portion 92Q is Q The ratio of the fifth width W5 of the mesa portion 90 (CI Q / W5) is 0.11 or more and 0.17 or less.

[0115] like Figure 6 、 Figure 7as well as Figure 12A As shown, the semiconductor device 1 includes a main surface insulating film 39 covering the first main surface 3. The thickness of the main surface insulating film 39 is, for example, not less than 50 nm and not more than 200 nm.

[0116] The main surface insulating film 39 may also include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The main surface insulating film 39 preferably has a single-layer structure composed of a single insulating film. The main surface insulating film 39 particularly preferably includes a silicon oxide film composed of an oxide of the semiconductor chip 2. In this embodiment, the main surface insulating film 39 is composed of the same insulating film as the gate insulating film 32.

[0117] like Figure 6 、 Figure 7 as well as Figure 12A As shown, the main surface insulating film 39 extends in a film-like manner along the first main surface 3 to cover the plurality of IGBT regions 6, the boundary region 7, and the peripheral region 10. The main surface insulating film 39 may be continuous with the periphery (the first to fourth side surfaces 5A to 5D) of the semiconductor chip 2.

[0118] like Figure 6 as well as Figure 7 As shown, the main surface insulating film 39 covers the first main surface 3 so as to expose the plurality of trench isolation structures 20 and the plurality of trench structures 30. Specifically, the main surface insulating film 39 is connected to the isolation insulating film 22 and the gate insulating film 32, exposing the isolation buried electrode 23 and the gate buried electrode 33.

[0119] like Figure 7 As shown, semiconductor device 1 includes gate wiring 40 disposed on first main surface 3 of semiconductor chip 2. Specifically, gate wiring 40 is disposed in a film shape on main surface insulating film 39. In this embodiment, gate wiring 40 is formed of a conductive polysilicon film.

[0120] like Figure 3 As shown, the gate wiring 40 is routed to at least the boundary region 7. In this embodiment, the gate wiring 40 is routed to the boundary region 7 and the peripheral region 10 in an arbitrary layout. Specifically, the gate wiring 40 includes a pad wiring 41, a boundary wiring 42, a first peripheral wiring 43, and a second peripheral wiring 44. The pad wiring 41 is arranged on the first boundary region 8 of the boundary region 7 and has a relatively large first wiring width in the second direction Y. In this embodiment, the pad wiring 41 is formed into a quadrilateral shape when viewed from above. The pad wiring 41 has a width in the second direction Y that is larger than the width of the boundary region 7 (the width of the first boundary region 8). The pad wiring 41 is led out from the boundary region 7 to a plurality of trench separation structures 20 adjacent to each other in the second direction Y.

[0121] like Figure 3As shown, in this embodiment, the pad wiring 41 is extended from the boundary region 7 to the multiple IGBT regions 6. As a result, the pad wiring 41 is mechanically and electrically connected to the isolation embedded electrode 23 and the multiple gate embedded electrodes 33, thereby transmitting the gate potential to the isolation embedded electrode 23 and the multiple gate embedded electrodes 33. In this embodiment, the pad wiring 41 is formed integrally with the isolation embedded electrode 23 and the multiple gate embedded electrodes 33.

[0122] like Figure 3 as well as Figure 4 As shown, a boundary wire 42 extends from a pad wire 41 to a second boundary region 9 of a boundary region 7 and has a second width in the second direction Y that is smaller than the first width of the pad wire 41. The boundary wire 42 is formed in a strip shape extending along the first direction X. In this embodiment, the boundary wire 42 crosses the center of the semiconductor chip 2. The boundary wire 42 has a width in the second direction Y that is greater than the width of the boundary region 7 (the width of the second boundary region 9). The boundary wire 42 extends from the boundary region 7 to a plurality of trench isolation structures 20 adjacent to each other in the second direction Y.

[0123] like Figure 4 As shown, in this embodiment, the boundary wiring 42 extends from the boundary region 7 to the multiple IGBT regions 6 in a manner that covers the first end portions 30A of the multiple trench structures 30. Thus, the boundary wiring 42 is mechanically and electrically connected to the isolation buried electrode 23 and the multiple gate buried electrodes 33, thereby transmitting the gate potential to the isolation buried electrode 23 and the multiple gate buried electrodes 33. In this embodiment, the boundary wiring 42 is formed integrally with the isolation buried electrode 23 and the multiple gate buried electrodes 33.

[0124] like Figure 3 As shown, the first peripheral wiring 43 is led out from the pad wiring 41 to the peripheral region 10 and is formed into a strip extending along the first side surface 5A and the third side surface 5C. The first peripheral wiring 43 may also have a portion extending in a strip along the fourth side surface 5D. The first peripheral wiring 43 has a portion extending from the peripheral region 10 to the first trench isolation structure 20A in the portion extending along the first side surface 5A. Figure 11 As shown, in this embodiment, the first peripheral wiring 43 also covers the second end portions 30B of the plurality of trench structures 30 in the first IGBT region 6A.

[0125] Thus, the first peripheral wiring 43 is mechanically and electrically connected to the isolation buried electrode 23 and the plurality of gate buried electrodes 33. In this embodiment, the first peripheral wiring 43 is formed integrally with the isolation buried electrode 23 and the plurality of gate buried electrodes 33. The first peripheral wiring 43 transmits the gate potential from the peripheral region 10 side to the isolation buried electrode 23 and the gate buried electrode 33.

[0126] like Figure 3 As shown, the second peripheral wiring 44 extends from the pad wiring 41 to the peripheral region 10, forming a strip-like shape extending along the second side surface 5B and the third side surface 5C. The second peripheral wiring 44 may also include a strip-like portion extending along the fourth side surface 5D. The portion of the second peripheral wiring 44 extending along the second side surface 5B includes a portion extending from the peripheral region 10 to the second trench isolation structure 20B. Although not shown in the figure, in this embodiment, the second peripheral wiring 44 also covers the second end portions 30B of the plurality of trench structures 30 in the second IGBT region 6B.

[0127] Thus, the second peripheral wiring 44 is mechanically and electrically connected to the isolation buried electrode 23 and the plurality of gate buried electrodes 33. In this embodiment, the second peripheral wiring 44 is formed integrally with the isolation buried electrode 23 and the plurality of gate buried electrodes 33. The second peripheral wiring 44 transmits the gate potential from the peripheral region 10 side to the isolation buried electrode 23 and the gate buried electrode 33.

[0128] Semiconductor device 1 further includes an interlayer insulating film 60 covering main surface insulating film 39. Interlayer insulating film 60 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. Interlayer insulating film 60 may also include at least one of an NSG (non-doped silicate glass) film, a PSG (phosphor silicate glass) film, and a BPSG (boron phosphor silicate glass) film, which are examples of silicon oxide films. Interlayer insulating film 60 may have a single-layer structure consisting of a single insulating film, or a stacked structure consisting of multiple insulating films. Interlayer insulating film 60 has a thickness exceeding that of main surface insulating film 39. For example, the thickness of interlayer insulating film 60 is not less than 1.0 μm and not more than 2.5 μm.

[0129] like Figure 6 、 Figure 7 as well as Figure 12A As shown, the interlayer insulating film 60 may also extend in a layered manner along the first main surface 3 and be connected to the periphery (first to fourth side surfaces 5A to 5D) of the semiconductor chip 2. The interlayer insulating film 60 selectively covers the multiple IGBT regions 6, the boundary region 7, and the peripheral region 10. In each IGBT region 6, the interlayer insulating film 60 covers the main surface insulating film 39, the multiple trench isolation structures 20, and the multiple trench structures 30. In the boundary region 7 and the peripheral region 10, the interlayer insulating film 60 covers the main surface insulating film 39 and the gate wiring 40.

[0130] like Figure 6As shown, the interlayer insulating film 60 has a plurality of contact openings 61 in each IGBT region 6, exposing the plurality of emitter regions 35. In this embodiment, the plurality of contact openings 61 are formed in a one-to-one correspondence with the plurality of contact holes 37, and are connected to the corresponding contact holes 37. The plurality of contact openings 61 are each formed in a strip shape extending along the corresponding contact hole 37 in a plan view.

[0131] The interlayer insulating film 60 includes at least one gate opening for selectively exposing the gate wiring 40 in the boundary region 7 and / or the peripheral region 10. In this embodiment, the gate opening may also expose the boundary wiring 42, the first peripheral wiring 43, and the second peripheral wiring 44. Figure 12A In FIG. 4 , only the gate opening 62 that exposes the first peripheral wiring 43 is shown.

[0132] like Figure 12A As shown, the interlayer insulating film 60 includes at least one (in this embodiment, a plurality of) first well openings 63 that selectively expose the inner edge of the peripheral well region 56 in the peripheral region 10. Specifically, the plurality of first well openings 63 expose the inner edge of the peripheral well region 56 in the region between the plurality of trench isolation structures 20 and the gate wiring 40.

[0133] like Figure 12A As shown, the interlayer insulating film 60 includes at least one (in this embodiment, one) second well opening 64 that selectively exposes the outer edge of the peripheral well region 56 in the peripheral region 10. Specifically, the second well opening 64 exposes the outer edge of the peripheral well region 56 in a region closer to the periphery of the first main surface 3 than the gate wiring 40. The second well opening 64 is formed in a strip shape extending along the plurality of IGBT regions 6. In this embodiment, the second well opening 64 is formed in a quadrilateral ring shape surrounding the plurality of IGBT regions 6.

[0134] like Figure 7 As shown, the interlayer insulating film 60 includes at least one (two in this embodiment) boundary gate opening 81 (also referred to as FIG. 8 ) for exposing the boundary wiring 42 of the gate wiring 40. Figure 4 In this embodiment, the plurality of boundary gate openings 81 are each formed in a strip shape extending in the first direction X and spaced apart in the second direction Y. The planar shape of the boundary gate openings 81 is arbitrary. The boundary gate openings 81 may also be formed in a circular, elliptical, quadrilateral, or polygonal shape when viewed from above. The plurality of boundary gate openings 81 may also be arranged spaced apart in the first direction X. Furthermore, the number of boundary gate openings 81 is arbitrary.

[0135] like Figure 4 、 Figure 6 as well as Figure 12AAs shown, the semiconductor device 1 includes a plurality of via electrodes 70 embedded in the interlayer insulating film 60 so as to be electrically connected to the plurality of emitter regions 35. Specifically, the plurality of via electrodes 70 are embedded in the plurality of contact openings 61 of the interlayer insulating film 60. The plurality of via electrodes 70 include portions that contact the semiconductor chip 2 and portions that contact the interlayer insulating film 60. The portions of the plurality of via electrodes 70 that contact the semiconductor chip 2 are electrically connected to the emitter region 35 and the contact region 38.

[0136] Each through-hole electrode 70 may also include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. The Ti-based metal may include at least one of a pure Ti film (a Ti film with a purity of 99% or greater) and a Ti alloy film. The Ti alloy film may also be a TiN film. The W-based metal may include at least one of a pure W film (a W film with a purity of 99% or greater) and a W alloy film. The Al-based metal may include at least one of a pure Al film (an Al film with a purity of 99% or greater) and an Al alloy film. The Al alloy film may also include at least one of an AlCu alloy, an AlSi alloy, and an AlSiCu alloy. The Cu-based metal may include at least one of a pure Cu film (a Cu film with a purity of 99% or greater) and a Cu alloy film. Each through-hole electrode 70 may also have a stacked structure including a Ti-based metal film and a W-based metal film.

[0137] like Figure 7 As shown, the semiconductor device 1 includes a plurality of gate via electrodes 82 embedded in a plurality of boundary gate openings 81, mechanically and electrically connected to the boundary wiring 42. Each gate via electrode 82 may also include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. Like the via electrode 70, each gate via electrode 82 may also have a stacked structure including a Ti-based metal film and a W-based metal film. The plurality of gate via electrodes 82 preferably face the gate wiring 40 (boundary wiring 42) and the boundary well region 50 (second boundary well region 52) in the thickness direction of the semiconductor chip 2.

[0138] like Figure 1 as well as Figure 2 As shown, the semiconductor device 1 includes a gate electrode 71 disposed on the interlayer insulating film 60 so as to be electrically connected to the gate wiring 40. The gate electrode 71 is made of a conductive material different from that of the gate wiring 40. In this embodiment, the gate electrode 71 is made of a metal film and has a lower resistance than the gate wiring 40. The gate electrode 71 may also be referred to as "gate metal." The gate electrode 71 may also include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. The gate electrode 71 may also have a stacked structure including a Ti-based metal film and an Al-based metal film.

[0139] like Figure 1 as well as Figure 3 As shown, the gate electrode 71 is arranged directly above the gate wiring 40. The gate electrode 71 can be routed to any region of the multiple IGBT regions 6, the boundary region 7, and the peripheral region 10 in an arbitrary layout according to the layout of the gate wiring 40. In this embodiment, the gate electrode 71 includes a gate pad electrode 72, a first gate finger electrode 73, a second gate finger electrode 74, and a boundary gate finger electrode 83.

[0140] For example, a capacitor is formed by the gate electrode 71 and the IGBT structure Tr facing the gate electrode 71 via the interlayer insulating film 60. The capacitance of the capacitor as a whole gate (gate capacitance) is 300 pF or less.

[0141] like Figure 1 as well as Figure 3 As shown, gate pad electrode 72 is arranged directly above pad wiring 41 of gate wiring 40. Gate pad electrode 72 extends from above interlayer insulating film 60 into a gate opening (not shown) and is electrically connected to pad wiring 41. In this embodiment, gate pad electrode 72 is formed into a quadrilateral shape in plan view.

[0142] like Figure 1 as well as Figure 3 As shown, the gate pad electrode 72 is opposed to the first boundary well region 51 of the boundary well region 50 in the thickness direction of the semiconductor chip 2. The gate pad electrode 72 is preferably formed spaced apart from the trench isolation structure 20 and the plurality of trench structures 30 in a plan view. The gate pad electrode 72 preferably has a planar area smaller than the planar area of ​​the first boundary well region 51 of the boundary well region 50. The gate pad electrode 72 particularly preferably has a planar area smaller than the planar area of ​​the pad wiring 41.

[0143] like Figure 1 as well as Figure 3 As shown, the first gate finger electrode 73 extends from the gate pad electrode 72 to directly above the first peripheral wiring 43. The first gate finger electrode 73 is formed in a strip shape extending along the first peripheral wiring 43. In this embodiment, the first gate finger electrode 73 extends in a strip shape along the first side surface 5A and the third side surface 5C.

[0144] like Figure 12A As shown, the first gate finger electrode 73 extends from the interlayer insulating film 60 into the gate opening 62 and is electrically connected to the first peripheral wiring 43. The first gate finger electrode 73 is opposed to the peripheral well region 56 in the thickness direction of the semiconductor chip 2. The first gate finger electrode 73 is preferably formed at intervals from the trench isolation structure 20 and the plurality of trench structures 30 in a plan view.

[0145] like Figure 1 as well as Figure 3 As shown, the second gate finger electrode 74 extends from the gate pad electrode 72 to directly above the second peripheral wiring 44. The second gate finger electrode 74 is formed in a strip shape extending along the second peripheral wiring 44. In this embodiment, the second gate finger electrode 74 extends in a strip shape along the second side surface 5B and the third side surface 5C.

[0146] The second gate finger electrode 74 is electrically connected to the second peripheral wiring 44 through the gate opening (not shown) from above the interlayer insulating film 60. If a via electrode similar to the via electrode 70 is embedded in the gate opening, the second gate finger electrode 74 can also be electrically connected to the second peripheral wiring 44 through the via electrode.

[0147] The second gate finger electrode 74 faces the peripheral well region 56 in the thickness direction of the semiconductor chip 2. The second gate finger electrode 74 is preferably formed spaced apart from the trench isolation structure 20 and the plurality of trench structures 30 in a plan view.

[0148] like Figure 1 as well as Figure 3 As shown, the boundary gate finger electrode 83 is drawn from the gate pad electrode 72 to directly above the boundary wiring 42. The boundary gate finger electrode 83 is formed in a strip shape extending along the boundary wiring 42 so as to cover the plurality of gate via electrodes 82.

[0149] like Figure 7 As shown, boundary gate finger electrodes 83 are electrically connected to boundary wiring 42 via multiple gate via electrodes 82. Boundary gate finger electrodes 83 face gate wiring 40 (boundary wiring 42) and boundary well region 50 (second boundary well region 52) in the thickness direction of semiconductor chip 2.

[0150] like Figure 4 as well as Figure 7 As shown, in the second direction Y, the boundary gate finger electrode 83 has a width smaller than the width of the boundary well region 50 and has a peripheral edge located closer to the boundary region 7 than the peripheral edge of the boundary well region 50. Specifically, the boundary gate finger electrode 83 has a width smaller than the width of the boundary wiring 42 and has a peripheral edge located closer to the boundary region 7 than the peripheral edge of the boundary wiring 42. In this embodiment, the boundary gate finger electrode 83 has a width smaller than the width of the boundary region 7 and has a peripheral edge located on the inner side of the peripheral edge of the boundary region 7.

[0151] like Figure 4As shown, the boundary gate finger electrodes 83 are disposed only directly above the boundary region 7 in a plan view and are not disposed on each IGBT region 6. Specifically, the boundary gate finger electrodes 83 are disposed on the boundary region 7 at intervals from the plurality of trench structures 30 of the first IGBT region 6A and the plurality of trench structures 30 of the second IGBT region 6B in a plan view. The boundary gate finger electrodes 83 are disposed on the boundary region 7 at intervals from the first trench isolation structure 20A and the second trench isolation structure 20B in a plan view.

[0152] Reference Figure 1 The semiconductor device 1 includes an emitter electrode 75 disposed on the interlayer insulating film 60 at a distance from the gate wiring 40. The emitter electrode 75 is formed of a conductive material different from that of the gate wiring 40. In this embodiment, the emitter electrode 75 is formed of a metal film. The emitter electrode 75 may also be referred to as "emitter metal." The emitter electrode 75 may also include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. The emitter electrode 75 may also have a stacked structure including a Ti-based metal film and an Al-based metal film.

[0153] like Figure 6 、 Figure 7 as well as Figure 12A As shown, the emitter electrode 75 is arranged on the interlayer insulating film 60 so as to cover the multiple IGBT regions 6. The emitter electrode 75 also covers the multiple via electrodes 70 and is electrically connected to the multiple emitter regions 35 via the multiple via electrodes 70. In this embodiment, the emitter electrode 75 includes a portion that covers the boundary wiring 42 of the gate wiring 40 through the interlayer insulating film 60. In other words, the emitter electrode 75 includes a portion that faces the gate wiring 40 (boundary wiring 42) and the boundary well region 50 in the thickness direction of the semiconductor chip 2.

[0154] like Figure 1 as well as Figure 2 As shown, in this embodiment, the emitter electrode 75 includes an emitter pad electrode 76 and an emitter finger electrode 77 . The emitter pad electrode 76 covers the plurality of IGBT regions 6 and the boundary region 7 .

[0155] like Figure 6 As shown, the emitter pad electrode 76 faces the gate wiring 40 via the interlayer insulating film 60 and is electrically connected to the plurality of emitter regions 35 via the plurality of via electrodes 70. Figure 12A As shown, emitter pad electrode 76 extends from above interlayer insulating film 60 into first well opening 63. Emitter pad electrode 76 is electrically connected to the inner edge of peripheral well region 56 within first well opening 63.

[0156] like Figure 1 as well as Figure 2As shown, the emitter finger electrode 77 is led out from the emitter pad electrode 76 to the area between the periphery of the first main surface 3 and the gate electrode 71, and extends in a strip shape along the gate electrode 71. In this embodiment, the emitter finger electrode 77 is formed into a quadrilateral ring shape surrounding the gate electrode 71 and the emitter pad electrode 76. Figure 11 As shown in A, the emitter finger electrode 77 extends from above the interlayer insulating film 60 into the second well opening 64. The emitter finger electrode 77 is electrically connected to the outer edge portion of the second well opening 64.

[0157] like Figure 1 as well as Figure 4 As shown, in this embodiment, the emitter electrode 75 has a notch portion 84 that extends in a strip shape along the boundary gate finger electrode 83 in a plan view. The notch portion 84 defines a slit 85 that extends in a strip shape along the boundary gate finger electrode 83 between the notch portion 84 and the boundary gate finger electrode 83. The slit 85 is formed directly above the boundary well region 50 in a plan view. The slit 85 is preferably formed directly above the boundary region 7 in a plan view.

[0158] like Figure 4 As shown, in this embodiment, the slits 85 are formed in the boundary region 7 at intervals from the plurality of trench structures 30 in the first IGBT region 6A and the plurality of trench structures 30 in the second IGBT region 6B. Furthermore, the slits 85 are formed in the boundary region 7 at intervals from the first trench isolation structure 20A and the second trench isolation structure 20B in a plan view. The slits 85 may also be opposed to the boundary well region 50 (second boundary well region 52) in the thickness direction of the semiconductor chip 2.

[0159] like Figure 6 、 Figure 7 as well as Figure 12A As shown, semiconductor device 1 includes a collector electrode 80 covering second main surface 4. Collector electrode 80 is electrically connected to collector region 13 exposed from second main surface 4. Collector electrode 80 forms an ohmic contact with collector region 13. Collector electrode 80 may also cover the entire area of ​​second main surface 4 so as to be in contact with the periphery (first to fourth side surfaces 5A to 5D) of semiconductor chip 2.

[0160] The collector 80 may also include at least one of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film. The collector 80 may also have a single film structure including a Ti film, a Ni film, an Au film, an Ag film, or an Al film. The collector 80 may also have a stacked structure in which at least two of the Ti film, the Ni film, the Pd film, the Au film, the Ag film, and the Al film are stacked in any manner. The collector 80 preferably includes a Ti film that directly covers at least the second main surface 4. The collector 80 may have, for example, a stacked structure including a Ti film, a Ni film, a Pd film, and an Au film stacked in sequence from the second main surface 4 side.

[0161] Figures 14A to 22A as well as Figures 14B to 22B The diagram shows a part of the manufacturing process of the semiconductor device 1 in order of the process steps. Figure 23 It is a figure for demonstrating the patterning mask PM. Figures 14A to 22A is with Figure 8 Longitudinal cross-sectional view of the corresponding part. Figures 14B to 22B is with Figure 9 The longitudinal section view of the corresponding part. Figures 14A to 22A as well as Figures 14B to 22B in Figure 8 as well as Figure 9 Among the reference numerals shown, only those necessary for describing the manufacturing process of the semiconductor device 1 are indicated, and other reference numerals are omitted.

[0162] like Figure 14A as well as Figure 14B As shown, when manufacturing the semiconductor device 1, first, an n-type semiconductor wafer 101 is prepared. The semiconductor wafer 101 has a first wafer main surface 103. The first wafer main surface 103 of the semiconductor wafer 101 corresponds to the first main surface 3 of the semiconductor chip 2.

[0163] Then, if Figure 14A as well as Figure 14B As shown, a p-type boundary well region 50 is formed on the first wafer main surface 103. A p-type peripheral well region 56 (refer to Figure 11 ) is formed simultaneously with the boundary well region 50.

[0164] Then, if Figure 15A 、 Figure 15B 、 Figure 16A as well as Figure 16B As shown in FIG. 1 , a separation trench 21 and a gate trench 31 are formed on the first wafer main surface 103. In this process, first, as shown in FIG. Figure 15A as well as Figure 15B As shown, a resist 104 is applied on a first wafer main surface 103 of a semiconductor wafer 101, and a patterning mask (virtual pattern) PM is arranged on the resist 104. The patterning mask PM has a predetermined opening pattern OP.

[0165] like Figure 23 As shown, the opening pattern OP of the patterning mask PM includes a first straight portion 98 and a second straight portion 99 that are orthogonal to each other, and a chamfered portion 100 that is inclined at an angle of 45° relative to the first straight portion 98 and the second straight portion 99. The chamfered portion 100 has a predetermined chamfer width W. F .

[0166] The straight portion 98 and the first side 93 (see Figure 13 ) corresponds to the straight portion 99 and the second side 94 (refer to Figure 13 )correspond.

[0167] Chamfer width W of patterning mask PM F The curvature index CI (curvature index CI) of the corners (92P, 92Q) formed using the patterning mask PM P , curvature index CI Q ) there is a correlation between them.

[0168] For example, the chamfer width W F =0.4μm corresponds to the curvature index CI=1.45μm, the chamfer width W F = 0.5 μm corresponds to the curvature index CI = 1.73 μm, the chamfer width W F =0.7 μm corresponds to the curvature index CI=2.44 μm.

[0169] By irradiating the resist 104 with light (eg, ultraviolet rays) through the patterning mask PM, the resist 104 is exposed, and the portion of the resist 104 exposed through the opening pattern OP is removed. Figure 16A as well as Figure 16B As shown, a second resist mask 105 having openings 105a having the same pattern as the opening pattern OP of the patterning mask PM is formed. The openings 105a of the second resist mask 105 are openings that expose the regions where the separation trenches 21 and the gate trenches 31 are to be formed. After the resist 104 is removed, the patterning mask PM is retracted from the first wafer main surface 103 of the semiconductor wafer 101.

[0170] Then, if Figure 17A as well as Figure 17B As shown, unnecessary portions of the semiconductor wafer 101 are removed by etching through the second resist mask 105. The etching method may also be wet etching. Thus, the separation trench 21 and the gate trench 31 are formed in the semiconductor wafer 101. Thereafter, the second resist mask 105 is removed.

[0171] Then, if Figure 18A as well as Figure 18BAs shown, first recesses 96 and second recesses 97 are formed at the opening ends 21d and 21e of the separation trench 21 and at the opening ends 31d and 31e of the gate trench 31, respectively. In this process, a third resist mask 106 having a predetermined pattern is first formed on the first wafer main surface 103. The third resist mask 106 has a plurality of openings 106a that expose the regions where the first recesses 96 and the second recesses 97 are to be formed.

[0172] Next, unnecessary portions of the semiconductor wafer 101 are removed by etching through the third resist mask 106 (TCE treatment (Top Corner Etching, top corner etching treatment). The etching method may also be a dry etching method. By the TCE treatment, a first recess 96 and a second recess 97 are formed in the separation trench 21 and the gate trench 31, respectively. The TCE treatment time is preferably 30 minutes or longer. The TCE treatment time is set to the third width W3 (refer to FIG. 1 ) of the first recess 96 of the separation trench 21. Figure 8 ) and the fourth width W4 of the gate trench 31 and the second recess 97 (refer to Figure 10 After the TCE treatment is completed, the third resist mask 106 is removed.

[0173] Next, if Figure 19A as well as Figure 19B As shown, a p-type boundary well region 50 is diffused in the semiconductor wafer 101. The boundary well region 50 is diffused to a depth position covering the bottom wall of the separation trench 21.

[0174] Then, if Figure 19A as well as Figure 19B As shown, an isolation insulating film 22, a gate insulating film 32, and a main surface insulating film 39 are formed on the first wafer main surface 103. The isolation insulating film 22, the gate insulating film 32, and the main surface insulating film 39 can also be formed by CVD (Chemical Vapor Deposition) or an oxidation treatment method (for example, thermal oxidation treatment).

[0175] Next, if Figure 19A 、 Figure 19B 、 Figure 20A as well as Figure 20B As shown, the isolation buried electrode 23, the boundary wiring 42, and the gate buried electrode 33 are formed. First, the base electrode layer 107 is deposited on the first wafer main surface 103. The base electrode layer 107 includes conductive polysilicon. The base electrode layer 107 can also be formed by CVD.

[0176] Next, if Figure 20A as well as Figure 20BAs shown, unnecessary portions of the base electrode layer 107 are removed. In this process, a resist mask (not shown) having a predetermined pattern is first applied to the areas where the boundary wiring 42 and the embedded gate electrode 33 are to be formed. The resist mask has openings that expose areas outside these areas. Next, the unnecessary portions of the base electrode layer 107 are removed by etching through the resist mask. The etching method may also be wet etching. This forms the boundary wiring 42 and the embedded gate electrode 33.

[0177] Then, if Figure 21A as well as Figure 21B As shown, n-type impurities are introduced into the semiconductor wafer 101 through the ion introduction mask, thereby forming a plurality of carrier storage regions 36 on the surface of the semiconductor wafer 101. Then, the ion introduction mask is removed. Next, p-type impurities are introduced into the first wafer main surface 103 of the semiconductor wafer 101 through the ion introduction mask. Thus, a plurality of base regions 25 are formed on the surface of the semiconductor wafer 101. Then, the ion introduction mask is removed. Next, n-type impurities are introduced into the first wafer main surface 103 of the semiconductor wafer 101 through the ion introduction mask. Thus, a plurality of emitter regions 35 are formed on the surface of the semiconductor wafer 101. Then, the ion introduction mask is removed.

[0178] Then, if Figure 22A as well as Figure 22B As shown, an interlayer insulating film 60 is formed on the first wafer main surface 103. Thereafter, a gate electrode 71, an emitter electrode 75, etc. are formed on the first wafer main surface 103. The semiconductor device 1 is obtained by including the above steps.

[0179] Next, the first destructive test will be described. As the semiconductor device 1 to be tested in the first destructive test, the following Examples 1 and 2 and Reference Examples 1 to 4 are used.

[0180] <Examples 1 and 2>

[0181] pass Figures 14A to 22A as well as Figures 14B to 22B The manufacturing shown is produced Figures 1 to 3 The semiconductor device 1 shown in the embodiment 1 and 2 is formed by cutting the corner 92P (refer to Figure 5 ) and the corner 92Q of the L-shaped intersection 91Q (see Figure 12B ) is used in the production of the patterning mask PM chamfer width W F The chamfer width W is set to 0.4 μm (Example 1) and 0.5 μm (Example 2). F When the curvature index CI is 0.4μm (refer to Figure 13 ) is 1.45μm. FWhen the curvature index is 0.5 μm, the curvature index CI is 1.73 μm.

[0182] In Examples 1 and 2, the first width W1 of the separation trench 21 (see Figure 8 ) is 1.0 μm, and the second width W2 of the gate trench 31 (refer to Figure 10 ) is 1.0 μm. No first recess 96 is formed at the opening ends 21 d and 21 e of the separation trench 21 (see Figure 8 The second recess 97 is not formed at the opening ends 31 d and 31 e of the gate trench 31 (see Figure 10 ).

[0183] <Reference Examples 1~4>

[0184] In Reference Examples 1 to 4, the chamfer width W of the patterning mask PM used in fabricating the semiconductor device 1 is set to F The chamfer width W is 0.0 μm (reference example 1), 0.1 μm (reference example 2), 0.2 μm (reference example 3), and 0.3 μm (reference example 4). F When the chamfer width W is 0.0 μm, the patterning mask PM is not chamfered. F When the curvature index CI is 0.0μm (refer to Figure 13 ) is 0.76 μm. That is, even if the patterning mask PM is not chamfered, the corners (corners 92P and 92Q) of the T-shaped intersections 91P and 91Q (see Figure 5 as well as Figure 12B ) is also rounded. If the patterning mask PM is chamfered, the curvature of the corners (corner 92P, corner 92Q) becomes gentle. F When the chamfer width W is 0.1 μm, the curvature index CI is 0.86 μm. F When the chamfer width W is 0.2 μm, the curvature index CI is 1.02 μm. F When the curvature index CI is 0.3 μm, it is 1.20 μm.

[0185] Based on the above, the chamfer width W of the patterning mask PM is F The relationship between the curvature index CI and the Figure 23 From the curve graph. Figure 23 It can be seen that by making the chamfer width W of the patterning mask PM F Increases, and with this increase, the curvature index CI also increases in a quadratic function. That is, by appropriately adjusting the chamfer width W of the patterning mask PM F , the curvature index CI of the corner portion 92P of the T-shaped intersection portion 91P and the corner portion 92Q of the L-shaped intersection portion 91Q can be freely changed.

[0186] Next, for Examples 1 and 2 and Reference Examples 1 to 4, an electrostatic discharge withstand test (ESD test) for measuring electrostatic discharge withstand (ESD withstand) and a zero-time dielectric breakdown test (TZDB test) for measuring zero-time dielectric breakdown withstand were performed as first breakdown tests.

[0187] In the electrostatic breakdown withstand test (ESD test), three samples corresponding to Examples 1 and 2 and Reference Examples 1 to 4 were prepared, and the breakdown voltage (BV) of each sample was measured. The breakdown voltage (BV) is the voltage at which semiconductor device 1 breaks down. It is measured by increasing the collector voltage from 0V to the voltage at which semiconductor device 1 breaks down, with the emitter voltage and gate voltage at 0V. In this embodiment, the electrostatic breakdown withstand test is an HBM (Human Body Model) test. The electrostatic breakdown withstand of the semiconductor device 1 sample is measured when a charged human body comes into contact with the device.

[0188] The test results of the electrostatic breakdown resistance test are shown in Figure 25 .exist Figure 25 In the example, the breakdown voltage is expressed as a relative value when the reference voltage is set to 1. Figure 25 In the example, samples 1 to 3 correspond to reference example 1, samples 4 to 6 correspond to reference example 2, samples 7 to 9 correspond to reference example 3, and samples 10 to 12 correspond to reference example 4. Figure 25 , Samples 13 to 15 correspond to Example 1, and Samples 16 to 18 correspond to Example 2.

[0189] according to Figure 25 The test results shown in the figure show that the breakdown voltage values ​​of Examples 1 and 2 are higher than those of Reference Examples 1 to 4. In other words, it is known that the electrostatic breakdown resistance of Examples 1 and 2 is high. Figure 13 ) is 1.5 μm or more, the electrostatic breakdown resistance of the semiconductor device 1 becomes high.

[0190] In the zero-time dielectric breakdown test (TZDB test), semiconductor devices 1 arranged at various locations within the surface of a circular wafer W are measured. The applied voltage (V ge ) is 80 V. The semiconductors to be measured are Example 1, Example 2, and Reference Examples 1 to 4.

[0191] The test results of the zero-time insulation breakdown test are shown in Figures 26A to 26C as well as Figures 27A to 27C .exist Figures 26A to 26C as well as Figures 27A to 27CIn the diagram, the black rectangles represent the portion of wafer W where chips with a leakage current greater than the reference value flow (the damaged region), while the white rectangles represent the portion of the wafer where chips with a leakage current less than the reference value flow (the non-damaged region). Chips present in the black rectangles are believed to cause dielectric breakdown in the semiconductor device during the zero-time dielectric breakdown test.

[0192] Depend on Figures 26A and 26B as well as Figures 27A to 27C The test results shown show that the dielectric breakdown resistance is high in Example 1 and Example 2. This shows that the dielectric breakdown resistance increases when the curvature index CI of the semiconductor device 1 is 1.5 μm or more.

[0193] Next, the second destruction test will be described. As the semiconductor devices 1 to be tested in the second destruction test, the following Examples 3 and 4 and Reference Example 5 were used.

[0194] <Examples 3, 4>

[0195] pass Figures 14A to 22A as well as Figures 14B to 22B The manufacturing process shown below produces Figures 1 to 3 The semiconductor device 1 shown in FIG. In Examples 1 and 2, the TCE treatment time was set to 30 seconds (Example 3) and 45 seconds (Example 4), respectively. When the TCE treatment time was 30 seconds, the third width W3 of the first recess 96 (see FIG. Figure 8 ) and the fourth width W4 of the second recess 97 (refer to Figure 10 ) is 1368 Å.

[0196] At this time, the third depth D3 (refer to Figure 8 ) and the fourth depth D4 (refer to Figure 10 ) is 1838 Å. When the TCE treatment time is 45 seconds, the third width W3 and the fourth width W4 are 2176 Å. At this time, the third depth D3 and the fourth depth D4 are 2849 Å.

[0197] Based on the above, the relationship between the processing time of TCE processing and the side etching amount of the trench is obtained. Figure 28 From Figure 28 It can be seen that by increasing the TCE treatment time, the side etching amount and depth of the recess at the trench opening end also increase proportionally. In other words, by appropriately adjusting the TCE treatment time, the third width W3 and third depth D3 of the first recess 96, as well as the fourth width W4 and fourth depth D4 of the second recess 97, can be freely changed.

[0198] In the third and fourth embodiments, the first width W1 of the separation trench 21 (see Figure 8 ) is 1.0 μm, and the second width W2 of the gate trench 31 (refer to Figure 10 ) is 1.0μm. Pitch P (refer to Figure 6 ) is 15 μm. The width W5 of the mesa portion 90 (refer to Figure 4 ) is 10 μm. The curvature index CI of the corners (corner 92P, corner 92Q) (refer to Figure 13 ) is 0.76μm (equivalent to the chamfer width W F =0.0μm).

[0199] <Reference Example 5>

[0200] In Reference Example 5, the processing time of the TCE treatment is set to 15 seconds. When the processing time of the TCE treatment is 15 seconds, the third width W3 of the first concave portion 96 (refer to Figure 8 ) and the fourth width W4 of the second recess 97 (refer to Figure 10 ) is 532Å. At this time, the third depth D3 (refer to Figure 8 ) and the fourth depth D4 (refer to Figure 10 ) is 828 Å.

[0201] Next, for Examples 3, 4, and Reference Example 5, a zero-time dielectric breakdown test (TZDB test) was performed as a second breakdown test to measure the zero-time dielectric breakdown withstand. ge ) starts from 78V and gradually increases. Reference Example 5 applies voltage V ge Since the battery starts to break down at 80V, no measurement is performed at voltages above this voltage.

[0202] The test results of the zero-time dielectric breakdown test (TZDB test) are shown in Figures 29A to 29C 、 Figure 30A 、 Figure 30B 、 Figure 31A as well as Figure 31B .

[0203] Figures 29A to 29C Indicates the applied voltage V ge The test results are shown below at 80V. Figure 30A to Figure 3 0C means the applied voltage V ge The test results are shown below: Figure 31A to Figure 3 1C means applied voltage V ge The test results are shown below:

[0204] exist Figures 29A to 29C 、 Figure 30A 、 Figure 30B 、 Figure 31A as well as Figure 31BIn the diagram, the black rectangles represent the portion of wafer W where chips with a leakage current greater than the reference value flow (the damaged region), while the white rectangles represent the portion of the wafer where chips with a leakage current less than the reference value flow (the non-damaged region). Chips present in the black rectangles are believed to cause dielectric breakdown in the semiconductor device during the zero-time dielectric breakdown test.

[0205] From the test results shown in FIG29 to FIG31, it can be seen that the dielectric breakdown resistance of Examples 3 and 4 is high. Figure 8 ) and the fourth width W4 (refer to Figure 10 ) is 1350Å or more, the dielectric breakdown resistance is high.

[0206] The IGBT structure Tr includes multiple T-shaped intersections 91P. Electric fields tend to concentrate at these intersections. As a result, the semiconductor chip 2 may be damaged, possibly starting at these intersections. Therefore, the semiconductor device 1 is required to have a high electrostatic discharge (ESD) tolerance.

[0207] Generally speaking, as the chip size of semiconductor chip 2 increases or as gate capacitance increases, the electrostatic breakdown resistance tends to increase. However, regardless of the chip size and gate capacitance of semiconductor chip 2, semiconductor device 1 is required to have high electrostatic breakdown resistance. Furthermore, semiconductor device 1 is required to have not only high electrostatic breakdown resistance but also high dielectric breakdown resistance.

[0208] According to the present embodiment, the curvature index CI of the corner portion 92P of the T-shaped intersection portion 91P is P The thickness is 1.5 μm or more. Therefore, the electric field concentration at the corner 92P of the T-shaped intersection 91P can be alleviated, and the current concentration at the corner 92P of the T-shaped intersection 91P can be suppressed. Thus, the occurrence of damage at the T-shaped intersection 91P can be suppressed.

[0209] In addition, the curvature index CI of the corner portion 92P of the T-shaped intersection portion 91P is P The thickness is 2.4 μm or less. Therefore, the embedding properties of the isolation buried electrode 23 in the isolation trench 21 and the embedding properties of the gate buried electrode 33 in the gate trench 31 are not impaired. In other words, the occurrence of damage in the T-shaped intersection 91P can be suppressed without impairing the embedding properties of the buried electrodes 23 and 33.

[0210] In addition, the curvature index CI of the corner portion 92Q of the L-shaped intersection portion 91Q is QThe thickness is 1.5 μm or greater. Therefore, the electric field concentration at the corner 92Q of the L-shaped intersection 91Q can be alleviated. Therefore, the current concentration at the corner 92Q of the L-shaped intersection 91Q can be suppressed. Thus, the occurrence of damage at the L-shaped intersection 91Q can be suppressed.

[0211] In addition, the curvature index CI of the corner portion 92Q of the L-shaped intersection portion 91Q is Q The thickness is 2.4 μm or less. Therefore, the embedding property of the isolation buried electrode 23 in the isolation trench 21 is not impaired. That is, the occurrence of damage in the L-shaped intersection 91Q can be suppressed without impairing the embedding property of the isolation buried electrode 23.

[0212] Therefore, it is possible to improve the electrostatic breakdown resistance and dielectric breakdown resistance of the semiconductor device 1. As a countermeasure against dielectric breakdown, it is possible to avoid increasing the thickness of the gate insulating film 32, the main surface insulating film 39, and the interlayer insulating film 60. As a result, the gate capacitance of the semiconductor device 1 can be reduced.

[0213] Furthermore, according to this embodiment, first recesses 96 are formed at the open ends 21d and 21e of the separation trench 21. Since the third width W3 of the first recesses 96 is greater than 1350 Å, the generation of electric field concentration at the open ends 21d and 21e of the separation trench 21 can be mitigated. Consequently, current concentration at the open ends 21d and 21e of the separation trench 21 can be suppressed. Consequently, the occurrence of damage in the separation trench 21 can be suppressed.

[0214] Furthermore, since the third width W3 of the first recess 96 is less than or equal to 2000 Å, there is no adverse effect on the function of the separation trench 21. In other words, the function of the separation trench 21 is not adversely affected, and the occurrence of damage in the separation trench 21 can be suppressed.

[0215] Furthermore, a second recess 97 is formed at the open ends 31d and 31e of the gate trench 31. Since the fourth width W4 of the second recess 97 is greater than or equal to 1350 Å, the generation of electric field concentration at the open ends 31d and 31e of the gate trench 31 can be mitigated. Consequently, current concentration at the open ends 31d and 31e of the gate trench 31 can be suppressed. Consequently, the generation of damage at the open ends 31d and 31e of the gate trench 31 can be suppressed.

[0216] Furthermore, since the fourth width W4 of the second recess 97 is 2000 Å or less, it does not adversely affect the function of the gate trench 31. That is, it does not adversely affect the function of the gate trench 31, and the occurrence of damage in the gate trench 31 can be suppressed.

[0217] Therefore, the electrostatic breakdown resistance and dielectric breakdown resistance of the semiconductor device 1 can be further improved.

[0218] As mentioned above, although embodiment of this disclosure was described, the semiconductor device 1 of this disclosure can be implemented in other forms.

[0219] For example, in the above embodiment, the semiconductor device 1 is an IGBT discrete type having an IGBT mounted alone as a functional element, but may be an RC-IGBT (Reverse-Conducting Insulated Gate Bipolar Transistor) having an IGBT and a diode mounted in combination.

[0220] In addition, if Figure 32 As shown in the semiconductor device 201, the IGBT structure Tr may also include a cross-shaped intersection 91R where two trenches 202 and 203 intersect in a cross shape as an intersection. The cross-shaped intersection 91R has four corners 92R. The curvature index CI of each corner 92R is R The thickness may be 1.5 μm or more and 2.4 μm or less.

[0221] In each of the aforementioned embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be employed. That is, a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0222] The following features can be extracted from the description of this specification and the drawings.

[0223] [Note 1-1]

[0224] A semiconductor device 1, 201, comprising:

[0225] a semiconductor chip 2 having a first main surface 3 and a second main surface 4 opposite thereto; and

[0226] A trench-type IGBT structure Tr is formed on the first main surface 3 of the semiconductor chip 2.

[0227] The IGBT structure Tr has:

[0228] Trenches 21 , 31 formed on the first main surface 3 of the semiconductor chip 2 and extending in multiple directions;

[0229] Insulating films 22 and 32 formed on side surfaces 21 a, 21 b, 31 a and 31 b of the trenches 21 and 31;

[0230] embedded conductors 23 and 33 embedded in the inner sides of the trenches 21 and 31 via the insulating films 22 and 32; and

[0231] The intersections 91P, 91Q, and 91R are formed by grooves 21 and 31 extending in the plurality of directions.

[0232] The curvature index CI of the corners 92P, 92Q of the intersections 91P, 91Q, 91R is P 、CI Q 1.5 μm or more.

[0233] According to this structure, the curvature index CI of the corners 92P, 92Q of the intersections 91P, 91Q, 91R of the grooves 21, 31 is P 、CI Q The thickness is 1.5 μm or greater, thereby alleviating the occurrence of electric field concentration at the corners 92P and 92Q of the trenches 21 and 31. This reduces the concentration of current at the corners 92P and 92Q of the trenches 21 and 31. This also reduces the occurrence of damage in the trenches 21 and 31, thereby improving dielectric breakdown resistance.

[0234] [Notes 1-2]

[0235] The semiconductor device 1 or 201 according to Supplementary Note 1-1, wherein the chamfer width W of the imaginary figure formed by the extension lines E1 and E2 of both sides of the corners 92P and 92Q forming the intersections 91P, 91Q and 91R is F It is 0.4μm or more.

[0236] [Notes 1-3]

[0237] The semiconductor device 1 or 201 according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q and 91R is P 、CI Q It is less than 2.4μm.

[0238] [Appendix 1-4]

[0239] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-3, wherein the curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q and 91R is P 、CI Q The ratios CI / W1 and CI / W2 of the widths W1 and W2 of the grooves 21 and 31 are equal to or greater than 1.5.

[0240] [Appendix 1-5]

[0241] The semiconductor device 1 or 201 according to Supplementary Notes 1 to 4, wherein the curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q and 91R is P、CI Q The ratios CI / W1 and CI / W2 to the widths W1 and W2 of the grooves 21 and 31 are 2.4 or less.

[0242] [Appendix 1-6]

[0243] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-5, wherein the trenches 21 or 31 extending in the plurality of directions include: a first trench 21; and a plurality of second trenches 31 intersecting the first trench 21 at the intersections 91P, 91Q, and 91R and arranged in a stripe shape at intervals.

[0244] The curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q, and 91R P 、CI Q The ratio CI of the pitch P of the plurality of second trenches 31 is P / P、CI Q / P is 0.1 or more.

[0245] [Appendix 1-7]

[0246] The semiconductor device 1 or 201 according to Supplementary Notes 1 to 6, wherein the curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q and 91R is P 、CI Q The ratio CI relative to the pitch P of the plurality of second trenches 31 is P / P、CI Q / P is less than 0.16.

[0247] [Notes 1-8]

[0248] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-7, wherein the trenches 21 or 31 extending in the plurality of directions include: a first trench 21; and a plurality of second trenches 31 intersecting the first trench 21 at the intersections 91P, 91Q, and 91R and arranged in a stripe shape at intervals.

[0249] The curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q, and 91R P 、CI Q The ratio CI to the width W5 of the mesa portion 90 defined between the plurality of second trenches 31 is P / W5、CI Q / W5 is 0.11 or more.

[0250] [Notes 1-9]

[0251] The semiconductor device 1 or 201 according to Supplementary Notes 1 to 8, wherein the curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q and 91R is P 、CI Q The ratio CI relative to the width W5 of the mesa portion 90 is P / W5、CI Q / W5 is 0.17 or less.

[0252] [Notes 1-10]

[0253] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-9, wherein:

[0254] The embedded conductors 23 and 33 include a gate embedded electrode 33 for controlling the channel of the IGBT structure Tr.

[0255] The lead portion 40 is integrally led out from the embedded gate electrode 33 to the first main surface 3 and covers the corner portions 92P and 92Q of the intersection portions 91P, 91Q, and 91R.

[0256] [Notes 1-11]

[0257] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-3, wherein:

[0258] The grooves 21, 31 extending in the plurality of directions include: a plurality of gate grooves (31) arranged in a stripe shape at intervals along the first direction and extending in the second direction respectively; and a connecting groove 21 extending in the first direction, connecting the ends of the plurality of gate grooves 31 in the second direction to each other, forming the T-shaped intersections 91P, 91Q, 91R at the connection parts with the respective gate grooves 31,

[0259] The embedded conductors 23 and 33 are integrally embedded in the gate trench 31 and the connection trench 21.

[0260] The lead portion 40 is led out from the embedded conductors 23 and 33 to the first main surface 3 and covers the corner portions 92P and 92Q of the intersection portions 91P, 91Q and 91R.

[0261] [Notes 1-12]

[0262] The semiconductor device 1 or 201 according to Supplement 1-11, wherein:

[0263] The gate trench 31 and the connection trench 21 have the same width.

[0264] The curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q, and 91R P 、CI Q The ratio of the width of the gate trench 31 to the width of the connection trench 21 is greater than or equal to 1.5 and less than or equal to 2.4.

[0265] [Notes 1-13]

[0266] The semiconductor device 1 or 201 according to Supplementary Note 1-11 or Supplementary Note 1-12, wherein the curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q and 91R is P 、CI Q The ratio of the pitch P to the plurality of gate trenches 31 is greater than or equal to 0.1 and less than or equal to 0.16.

[0267] [Notes 1-14]

[0268] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-11 to 1-13, wherein the curvature index CI of the corners 92P and 92Q of the intersections 91P, 91Q and 91R is P 、CI Q The ratio of the width of the mesa portion 90 defined between the plurality of gate trenches 31 is greater than or equal to 0.11 and less than or equal to 0.17.

[0269] [Notes 1-15]

[0270] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-11 to 1-14 includes a gate finger electrode 83 , wherein a region of the gate finger electrode on the connection trench 21 extends along the second direction and is connected to the lead portion 40 .

[0271] [Notes 1-16]

[0272] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-15, wherein the size of the semiconductor chip 2 is not less than 0.5 mm square and not more than 20 mm square.

[0273] [Appendix 1-17]

[0274] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-16, wherein a gate capacitance value of the semiconductor chip 2 is 300 pF or less.

[0275] [Notes 1-18]

[0276] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-9, wherein the intersections 91P, 91Q, and 91R include a T-shaped intersection 91P where the trenches 21 and 31 extending in the plurality of directions intersect in a T-shape.

[0277] [Notes 1-19]

[0278] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-10, wherein the intersections 91P, 91Q, and 91R include an L-shaped intersection 91Q where the trenches 21 and 31 extending in the plurality of directions intersect in an L shape.

[0279] [Note 1-20]

[0280] The semiconductor device 1 or 201 according to any one of Supplementary Notes 1-1 to 1-10, wherein the intersections 91P, 91Q, and 91R include a cross-shaped intersection 91R where the trenches 21 and 31 extending in the plurality of directions intersect in a cross shape.

[0281] [Note 2-1]

[0282] A semiconductor device 1, 201, comprising:

[0283] a semiconductor chip 2 having a first main surface 3 and a second main surface 4 opposite thereto; and

[0284] A trench-type IGBT structure Tr is formed on the first main surface 3 of the semiconductor chip 2.

[0285] The IGBT structure Tr has:

[0286] Trenches 21 , 31 formed in the first main surface 3 of the semiconductor chip 2 ;

[0287] Insulating films 22 and 32 formed on side surfaces 21 a, 21 b, 31 a and 31 b of the trenches 21 and 31; and

[0288] The buried conductors 23 and 33 are buried inside the trenches 21 and 31 via the insulating films 22 and 32.

[0289] The opening ends 21d, 21e, 31d, 31e of the grooves 21, 31 are formed with recessed portions 96, 97 that are recessed toward the side surfaces 21a, 21b, 31a, 31b of the grooves 21, 31.

[0290] The widths W3 and W4 of the recesses 96 and 97 are greater than 1350Å.

[0291] According to this structure, recesses 96 and 97 are formed at the open ends 21d, 21e, 31d, and 31e of the trenches 21 and 31. Since the widths W3 and W4 of the recesses 96 and 97 are greater than 1350Å, the electric field concentration at the open ends 21d, 21e, 31d, and 31e of the trenches 21 and 31 can be mitigated. Consequently, current concentration at the open ends 21d, 21e, 31d, and 31e of the trenches 21 and 31 can be suppressed. Consequently, the occurrence of damage in the trenches 21 and 31 can be suppressed, thereby improving dielectric breakdown resistance.

[0292] [Note 2-2]

[0293] The semiconductor device 1 or 201 according to Supplementary Note 2-1, wherein the depths D3 and D4 of the recesses 96 and 97 are greater than or equal to 1850 Å.

[0294] [Note 2-3]

[0295] The semiconductor device 1 or 201 according to Supplement 2-1 or Supplement 2-2, wherein the widths W3 and W4 of the recesses 96 and 97 are 2000Å or less.

[0296] [Notes 2-4]

[0297] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-1 to 2-3, wherein the ratios W3 / W1 and W4 / W2 of the widths W3 and W4 of the recesses 96 and 97 to the widths W1 and W2 of the trenches 21 and 31 are equal to or greater than 0.14.

[0298] [Notes 2-5]

[0299] The semiconductor device 1 or 201 according to Supplementary Note 2-4, wherein the ratios W3 / W1 or W4 / W2 of the widths W3 or W4 of the recesses 96 or 97 to the widths W1 or W2 of the trenches 21 or 31 are equal to or smaller than 0.2.

[0300] [Appendix 2-6]

[0301] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-1 to 2-5, wherein:

[0302] The plurality of grooves 31 are arranged in stripes at intervals.

[0303] A ratio W4 / P of the width W4 of the recess 97 to the pitch P of the plurality of grooves 31 is equal to or greater than 0.009.

[0304] [Appendix 2-7]

[0305] The semiconductor device 1 or 201 according to Supplementary Note 2-6, wherein the ratio W4 / P of the width W4 of the recess 97 to the pitch P of the plurality of trenches 31 is 0.0133 or less.

[0306] [Note 2-8]

[0307] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-1 to 2-7, wherein:

[0308] The plurality of grooves 31 are arranged in stripes at intervals.

[0309] A ratio W4 / W5 of the width W4 of the recessed portion 97 to the width W5 of the mesa portion 90 defined between the plurality of grooves 31 is equal to or greater than 0.011.

[0310] [Note 2-9]

[0311] The semiconductor device 1 or 201 according to Supplementary Note 2-8, wherein the ratio W4 / W5 of the width W4 of the recess 97 to the width W5 of the mesa portion 90 is 0.017 or less.

[0312] [Note 2-10]

[0313] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-1 to 2-9, wherein:

[0314] The embedded conductors 23 and 33 include a gate embedded electrode 33 for controlling the channel of the IGBT structure Tr.

[0315] The lead portion 40 is integrally led out from the embedded gate electrode 33 to the first main surface 3 and covers the recessed portions 96 and 97 .

[0316] [Note 2-11]

[0317] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-1 to 2-3, wherein:

[0318] The trenches 21 and 31 are formed by a plurality of gate trenches 31 and a connecting trench 21. The plurality of gate trenches are arranged in a stripe shape at intervals in the first direction and extend in the second direction respectively. The connecting trench extends in the first direction and connects the ends of the plurality of gate trenches 31 in the second direction to each other, forming T-shaped intersections 91P, 91Q, and 91R at the connection portions with the respective gate trenches 31.

[0319] The recesses 96 and 97 are formed at the intersections 91P, 91Q, and 91R of the grooves 21 and 31.

[0320] The embedded conductors 23 and 33 are integrally embedded in the gate trench 31 and the connection trench 21.

[0321] The lead portion 40 is led out from the embedded conductors 23 and 33 to the first main surface 3 and covers the recessed portions 96 and 97 of the intersection portions 91P, 91Q, and 91R.

[0322] [Note 2-12]

[0323] The semiconductor device 1 or 201 according to Supplement 2-11, wherein:

[0324] The gate trench 31 and the connection trench 21 have the same width.

[0325] The ratio of the width of the recesses 96 and 97 to the width of the gate trench 31 and the connection trench 21 is greater than or equal to 0.14 and less than or equal to 0.2.

[0326] [Note 2-13]

[0327] The semiconductor device 1 or 201 according to Supplementary Note 2-11 or Supplementary Note 2-12, wherein a ratio of the width of the recesses 96 or 97 to the pitch P of the plurality of gate trenches 31 is greater than or equal to 0.009 and less than or equal to 0.0133.

[0328] [Note 2-14]

[0329] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-11 to 2-13, wherein a ratio of a width of the recesses 96 or 97 to a width W5 of the mesa portion 90 defined between the plurality of gate trenches 31 is greater than or equal to 0.011 and less than or equal to 0.017.

[0330] [Note 2-15]

[0331] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-11 to 2-14 includes a gate finger electrode 83 , wherein a region of the gate finger electrode on the connection trench 21 extends along the second direction and is connected to the lead portion 40 .

[0332] [Note 2-16]

[0333] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-1 to 2-15, wherein the cross-sectional shape of the recessed portion 96 or 97 is an arc shape that is recessed toward the side surface 21 a , 21 b , 31 a , 31 b of the trench 21 or 31 .

[0334] [Note 2-17]

[0335] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-1 to 2-16, wherein the depths D3 and D4 of the recesses 96 and 97 are greater than the widths W3 and W4 of the recesses 96 and 97 .

[0336] [Note 2-18]

[0337] The semiconductor device 1 or 201 according to Supplement 2-17, wherein ratios W3 / D3 and W4 / D4 of the widths W3 and W4 of the recesses 96 and 97 to the depths D3 and D4 of the recesses 96 and 97 are not less than 0.6 and less than 0.9.

[0338] [Note 2-19]

[0339] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-1 to 2-18, wherein the size of the semiconductor chip 2 is not less than 0.5 mm square and not more than 20 mm square.

[0340] [Note 2-20]

[0341] The semiconductor device 1 or 201 according to any one of Supplementary Notes 2-1 to 2-19, wherein a gate capacitance value of the semiconductor chip 2 is 300 pF or less.

[0342] Explanation of symbols

[0343] 1—semiconductor device; 2—semiconductor chip; 3—first main surface; 4—second main surface; 5A—first side surface; 5B—second side surface; 5C—third side surface; 5D—fourth side surface; 6—IGBT region; 6A—first IGBT region; 6B—second IGBT region; 7—boundary region; 8—first boundary region; 9—second boundary region; 10—peripheral region; 11—drift region; 12—buffer region; 13—collector region; 20—trench separation structure; 20A—first trench separation structure; 20B—second trench separation structure; 20X—first direction portion; 20Y—second direction portion; 21—separation trench; 21a—side surface; 21b—side surface; 21c—bottom Surface; 21d—open end; 21e—open end; 22—separation insulating film; 23—separation buried electrode; 25—base region; 30—trench structure; 30A—first end; 30B—second end; 31—gate trench; 31a—side; 31b—side; 31c—bottom; 31d—open end; 31e—open end; 32—gate insulating film; 33—gate buried electrode; 35—emitter region; 36—carrier storage region; 37—contact hole; 38—contact region; 39—main surface insulating film; 40—gate wiring; 41—pad wiring; 42—boundary wiring; 43—first peripheral wiring; 44—second peripheral wiring; 50—boundary well region; 51—first Boundary well region; 52—second boundary well region; 56—peripheral well region; 60—interlayer insulating film; 61—contact opening; 62—gate opening; 63—first well opening; 64—second well opening; 70—through hole electrode; 71—gate electrode; 72—gate pad electrode; 73—first gate finger electrode; 74—second gate finger electrode; 75—emitter electrode; 76—emitter pad electrode; 77—emitter finger electrode; 80—collector; 81—boundary gate opening; 82—gate through hole electrode; 83—boundary gate finger electrode; 84—notch portion; 85—slit; 90—table portion; 91—first L-shaped intersection portion; 91P—T-shaped intersection portion; 91PA—first T-shaped shaped intersection; 91PB—second T-shaped intersection; 91Q—L-shaped intersection; 91QB—second L-shaped intersection; 91R—cross-shaped intersection; 92P—corner; 92Q—corner; 92R—corner; 93—first side; 94—second side; 96—first concave portion; 97—second concave portion; 98—first straight portion; 99—second straight portion; 100—chamfered portion; 101—semiconductor wafer; 103—first wafer main surface; 104—resist; 105—second resist mask; 105a—opening; 106—third resist mask; 106a—opening; 107—base electrode layer; 201—semiconductor device; 202—trench; 203—trench; CI P —Curvature index; CI Q—Curvature index; D1—first depth; D2—second depth; D3—third depth; D4—fourth depth; E1—extension line; E2—extension line; OP—opening pattern; P—pitch; P1—intersection; PM—patterning mask; TL—tangent line; Tr—IGBT structure; W1—first width; W2—second width; W3—third width; W4—fourth width; W5—fifth width; X—first direction; Y—second direction; Z—normal direction.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor chip having a first main surface and a second main surface opposite thereto; as well as A trench-type IGBT structure is formed on the first main surface of the semiconductor chip. The IGBT structure has: a trench formed on the first main surface of the semiconductor chip and extending in multiple directions; an insulating film formed on a side surface of the trench; a buried conductor embedded in the inner side of the trench via the insulating film; as well as an intersection portion consisting of grooves extending in the plurality of directions, The curvature index of the corner of the intersection is 1.5 μm or more.

2. The semiconductor device according to claim 1, wherein The chamfer width of an imaginary figure formed by extension lines of both sides of the corner portion forming the intersection is 0.4 μm or more.

3. The semiconductor device according to claim 1 or 2, wherein: The curvature index of the corner portion of the intersection portion is 2.4 μm or less.

4. The semiconductor device according to any one of claims 1 to 3, wherein A ratio of the curvature index of the corner portion of the intersection portion to the width of the groove is 1.5 or greater.

5. The semiconductor device according to claim 4, wherein The ratio of the curvature index of the corner portion of the intersection portion to the width of the groove is 2.4 or less.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The grooves extending in the plurality of directions include: a first groove; and a plurality of second grooves intersecting the first groove at the intersection portion and arranged in a stripe shape with intervals therebetween. A ratio of the curvature index of the corner portion of the intersection portion to the pitch of the plurality of second grooves is greater than or equal to 0.

1.

7. The semiconductor device according to claim 6, wherein: The ratio of the curvature index of the corner portion of the intersection portion to the pitch of the plurality of second grooves is 0.16 or less.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The grooves extending in the plurality of directions include: a first groove; and a plurality of second grooves intersecting the first groove at the intersection portion and arranged in a stripe shape with intervals therebetween. A ratio of the curvature index of the corner portion of the intersection portion to the width of the land portion defined between the plurality of second grooves is 0.11 or greater.

9. The semiconductor device according to claim 8, wherein The ratio of the curvature index of the corner portion of the intersection portion to the width of the land portion is 0.17 or less.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The buried conductor includes a gate buried electrode that controls a channel of the IGBT structure. A lead portion is included, the lead portion being integrally led out from the embedded gate electrode to the first main surface and covering the corner portion of the intersection portion.

11. The semiconductor device according to any one of claims 1 to 3, wherein: The trenches extending in the plurality of directions include: a plurality of gate trenches arranged in a stripe shape at intervals in the first direction and extending in the second direction; and a connecting trench extending in the first direction, connecting the ends of the plurality of gate trenches in the second direction to each other, and forming the T-shaped intersection portion at the connection portion with each of the gate trenches. The buried conductor is integrally buried in the gate trench and the connection trench, A lead portion is included, the lead portion being led out from the embedded conductor to the first main surface and covering the corner portion of the intersection portion.

12. The semiconductor device according to claim 11, wherein The gate trench and the connection trench have the same width, A ratio of the curvature index of the corner portion of the intersection portion to the width of the gate trench and the connection trench is greater than or equal to 1.5 and less than or equal to 2.

4.

13. The semiconductor device according to claim 11 or 12, wherein: A ratio of the curvature index of the corner portion of the intersection portion to the pitch of the plurality of gate trenches is greater than or equal to 0.1 and less than or equal to 0.

16.

14. The semiconductor device according to any one of claims 11 to 13, wherein: A ratio of the curvature index of the corner portion of the intersection portion to the width of the mesa portion defined between the plurality of gate trenches is greater than or equal to 0.11 and less than or equal to 0.

17.

15. The semiconductor device according to any one of claims 11 to 14, wherein: A gate finger electrode is included, wherein the gate finger electrode extends along the second direction in a region on the connection trench and is connected to the lead-out portion.

16. The semiconductor device according to any one of claims 1 to 15, wherein: The size of the semiconductor chip is not less than 0.5 mm square and not more than 20 mm square.

17. The semiconductor device according to any one of claims 1 to 16, wherein: The gate capacitance of the semiconductor chip is less than 300 pF.

18. The semiconductor device according to any one of claims 1 to 9, wherein: The intersection portion includes a T-shaped intersection portion where the grooves extending in the plurality of directions intersect in a T-shape.

19. The semiconductor device according to any one of claims 1 to 10, wherein: The intersection portion includes an L-shaped intersection portion where the grooves extending in the plurality of directions intersect in an L shape.

20. The semiconductor device according to any one of claims 1 to 10, wherein The intersection portion includes a cross-shaped intersection portion where grooves extending in the plurality of directions intersect in a cross shape.

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